From 1463562afd8c66c9fe60e14db8e9a48064ea474e Mon Sep 17 00:00:00 2001 From: Niklas Hauser Date: Sun, 6 Oct 2024 21:40:19 +0200 Subject: [PATCH] [ext] Update CMSIS Core to v6.1.0 --- .gitmodules | 2 +- ext/arm/cmsis | 2 +- ext/arm/core.lb | 7 ++++--- src/modm/platform/core/cortex/delay.cpp.in | 6 ++++-- src/modm/platform/uart/cortex/itm.cpp.in | 16 +++++++--------- 5 files changed, 17 insertions(+), 16 deletions(-) diff --git a/.gitmodules b/.gitmodules index 8658da233d..72de297697 100644 --- a/.gitmodules +++ b/.gitmodules @@ -9,7 +9,7 @@ url = https://github.com/modm-io/ros-lib [submodule "ext/arm/cmsis"] path = ext/arm/cmsis - url = https://github.com/modm-ext/cmsis-5-partial.git + url = https://github.com/modm-ext/cmsis-core-partial.git [submodule "ext/gcc/libstdc++"] path = ext/gcc/libstdc++ url = https://github.com/modm-io/avr-libstdcpp.git diff --git a/ext/arm/cmsis b/ext/arm/cmsis index 5211ec1798..c77dd09e5f 160000 --- a/ext/arm/cmsis +++ b/ext/arm/cmsis @@ -1 +1 @@ -Subproject commit 5211ec1798bb2e237ad4706d164a7b5c59363af1 +Subproject commit c77dd09e5f345131564a816b2e92278fa5101b0c diff --git a/ext/arm/core.lb b/ext/arm/core.lb index 26e441a724..1b0cb373fc 100644 --- a/ext/arm/core.lb +++ b/ext/arm/core.lb @@ -27,11 +27,12 @@ def build(env): env.copy("cmsis/CMSIS/Core/Include/cmsis_version.h", "cmsis_version.h") env.copy("cmsis/CMSIS/Core/Include/cmsis_compiler.h", "cmsis_compiler.h") env.copy("cmsis/CMSIS/Core/Include/cmsis_gcc.h", "cmsis_gcc.h") + env.copy("cmsis/CMSIS/Core/Include/m-profile/cmsis_gcc_m.h", "m-profile/cmsis_gcc_m.h") if "33" in core: - env.copy("cmsis/CMSIS/Core/Include/mpu_armv8.h", "mpu_armv8.h") + env.copy("cmsis/CMSIS/Core/Include/m-profile/armv8m_mpu.h", "m-profile/armv8m_mpu.h") elif core != "0": # 0+ has MPU support though! - env.copy("cmsis/CMSIS/Core/Include/mpu_armv7.h", "mpu_armv7.h") + env.copy("cmsis/CMSIS/Core/Include/m-profile/armv7m_mpu.h", "m-profile/armv7m_mpu.h") if core == "7": - env.copy("cmsis/CMSIS/Core/Include/cachel1_armv7.h", "cachel1_armv7.h") + env.copy("cmsis/CMSIS/Core/Include/m-profile/armv7m_cachel1.h", "m-profile/armv7m_cachel1.h") env.collect(":build:path.include", "modm/ext/cmsis/core") diff --git a/src/modm/platform/core/cortex/delay.cpp.in b/src/modm/platform/core/cortex/delay.cpp.in index 5e5fab5ea8..0e5dc5fa17 100644 --- a/src/modm/platform/core/cortex/delay.cpp.in +++ b/src/modm/platform/core/cortex/delay.cpp.in @@ -43,9 +43,11 @@ modm_dwt_enable(void) { // Enable Tracing Debug Unit CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + __DSB(); %% if core.startswith("cortex-m7") - // Unlock key - DWT->LAR = 0xC5ACCE55; + // Unlock key in LAR register + *(uint32_t*)(DWT_BASE+0xFB0) = 0xC5ACCE55; + __DSB(); %% endif // Reset counter to 0 DWT->CYCCNT = 0; diff --git a/src/modm/platform/uart/cortex/itm.cpp.in b/src/modm/platform/uart/cortex/itm.cpp.in index 084ef22325..3f83a9cc3c 100644 --- a/src/modm/platform/uart/cortex/itm.cpp.in +++ b/src/modm/platform/uart/cortex/itm.cpp.in @@ -37,35 +37,33 @@ Itm::initialize() DBGMCU->CR |= DBGMCU_CR_TRACE_IOEN; %% endif %% endif + __DSB(); } void Itm::enable(uint8_t prescaler) { // Trace Port Interface Selected Pin Protocol Register - TPI->ACPR = prescaler; + TPIU->ACPR = prescaler; // Trace Port Interface Selected Pin Protocol Register - TPI->SPPR = (0b10 << TPI_SPPR_TXMODE_Pos); + TPIU->SPPR = (0b10 << TPIU_SPPR_TXMODE_Pos); // Trace Port Interface Formatter and Flush Control Register - TPI->FFCR = (1 << TPI_FFCR_TrigIn_Pos); + TPIU->FFCR = (1 << TPIU_FFCR_TrigIn_Pos); // Trace Port Interface Current Parallel Port Size Register - TPI->CSPSR = 0b1; + TPIU->CSPSR = 0b1; // Enable write access to ITM registers - ITM->LAR = 0xC5ACCE55; + *(uint32_t*)(ITM_BASE+0xFB0) = 0xC5ACCE55; + __DSB(); // Trace Privilege Register ITM->TPR = 0; // Trace Control Register -%% if target.platform == "stm32" and target.family in ["l5", "u5"] ITM->TCR = (1 << ITM_TCR_TRACEBUSID_Pos) | -%% else - ITM->TCR = (1 << ITM_TCR_TraceBusID_Pos) | -%% endif (1 << ITM_TCR_DWTENA_Pos) | (1 << ITM_TCR_ITMENA_Pos);