From e6b78f920c0cfdde80c3f5587bd6bfa6ed2fae8f Mon Sep 17 00:00:00 2001 From: Kaelin Laundry Date: Sun, 17 Nov 2024 18:36:29 -0800 Subject: [PATCH] [stm32] Disable MASRX in STM32H7 SPI Follow-up to 678fd9a0e0cdd342b2c2d8e9627ec3331f66bf9c and #1223. It seems that once the RX FIFO has been cleared and emptied, the next transmitted byte always enters SUSP mode. It is unclear why this happens. When MASRX is not set, neither SUSP nor OVR are seen for the same transmit sequence. --- src/modm/platform/spi/stm32h7/spi_hal_impl.hpp.in | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/modm/platform/spi/stm32h7/spi_hal_impl.hpp.in b/src/modm/platform/spi/stm32h7/spi_hal_impl.hpp.in index 77770cf4bd..958dba720b 100644 --- a/src/modm/platform/spi/stm32h7/spi_hal_impl.hpp.in +++ b/src/modm/platform/spi/stm32h7/spi_hal_impl.hpp.in @@ -56,8 +56,7 @@ SpiHal{{ id }}::initialize(Prescaler prescaler, // initialize with unlimited transfer size setTransferSize(0); - // Pause master transfer if RX FIFO is full - SPI{{ id }}->CR1 = SPI_CR1_MASRX; + SPI{{ id }}->CR1 = 0; SPI{{ id }}->CFG2 = static_cast(dataMode) | static_cast(dataOrder)