[cortex-m7] Enable I/D-Cache optionally

Author: salkinium

src/modm/platform/core/cortex/module.lb

@@ -219,7 +219,20 @@ def prepare(module, options):
             maximum="64Ki",
             default="3Ki"))
 
-    if "f" in options[":target"].get_driver("core")["type"]:
+    core = options[":target"].get_driver("core")["type"]
+    if "m7" in core:
+        module.add_option(
+            BooleanOption(
+                name="enable_icache",
+                description="Enable Instruction-Cache",
+                default=True))
+        module.add_option(
+            BooleanOption(
+                name="enable_dcache",
+                description="Enable Data-Cache",
+                default=True))
+
+    if "f" in core:
         module.add_option(
             EnumerationOption(
                 name="float-abi",
@@ -331,8 +344,7 @@ def validate(env):
 def build(env):
     env.substitutions = env.query("vector_table")
     core = env.substitutions["core"]
-    with_icache = "m7" in core
-    with_dcache = with_icache and not (env.has_module(":platform:dma") or env.has_module(":platform:bdma"))
+    enable_dcache = env.get("enable_dcache", False) and not (env.has_module(":platform:dma") or env.has_module(":platform:bdma"))
     env.substitutions.update({
         "target": env[":target"].identifier,
         "with_fault_storage": env.has_module(":platform:fault"),
@@ -341,12 +353,14 @@ def build(env):
         "with_fpu": env.get("float-abi", "soft") != "soft",
         "with_multicore": env.has_module(":platform:multicore"),
         "with_msplim": sum(c.isnumeric() for c in core) == 2,
-        "with_icache": with_icache,
-        "with_dcache": with_dcache,
+        "enable_icache": env.get("enable_icache", False),
+        "enable_dcache": enable_dcache,
+        "has_icache": env.has_option("enable_icache"),
+        "has_dcache": env.has_option("enable_dcache"),
     })
     env.outbasepath = "modm/src/modm/platform/core"
 
-    if env.substitutions["with_icache"] and not env.substitutions["with_dcache"]:
+    if env.get("enable_dcache", False) and not enable_dcache:
         env.log.warning("Cortex-M7 D-Cache is disabled due to using DMA!")
 
     # startup script

src/modm/platform/core/cortex/startup.c.in

@@ -95,20 +95,18 @@ table_zero(const uint32_t *const start, const uint32_t *const end)
 // Called by Reset_Handler in reset_handler.s
 void __modm_startup(void)
 {
-	// Copy and zero all internal memory
-	table_copy(__table_copy_intern_start, __table_copy_intern_end);
-	table_zero(__table_zero_intern_start, __table_zero_intern_end);
-%#
-%% if with_icache
-	// Enable instruction cache
-	SCB_EnableICache();
+%% if has_icache and not enable_icache
+	SCB_DisableICache();
 	SCB_InvalidateICache();
 %% endif
-%% if with_dcache
-	// Enable data cache with default WBWA policy
-	SCB_EnableDCache();
+%% if has_dcache and not enable_dcache
+	SCB_DisableDCache();
 	SCB_CleanInvalidateDCache();
 %% endif
+%#
+	// Copy and zero all internal memory
+	table_copy(__table_copy_intern_start, __table_copy_intern_end);
+	table_zero(__table_zero_intern_start, __table_zero_intern_end);
 %#
 %% if core != "cortex-m0"
 	// Set the vector table location
@@ -119,6 +117,17 @@ void __modm_startup(void)
 	// Enable trapping of divide by zero for UDIV/SDIV instructions.
 	SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk;
 %% endif
+%#
+%% if enable_icache
+	// Enable instruction cache
+	SCB_EnableICache();
+	SCB_InvalidateICache();
+%% endif
+%% if enable_dcache
+	// Enable data cache with default WBWA policy
+	SCB_EnableDCache();
+	SCB_CleanInvalidateDCache();
+%% endif
 %#
 	// Call all hardware initialize hooks
 	table_call(__hardware_init_start, __hardware_init_end);