diff --git a/source/locale/es/LC_MESSAGES/SpinalHDL/Simulation/simulator_specifics.po b/source/locale/es/LC_MESSAGES/SpinalHDL/Simulation/simulator_specifics.po new file mode 100644 index 00000000000..15c26fcbc27 --- /dev/null +++ b/source/locale/es/LC_MESSAGES/SpinalHDL/Simulation/simulator_specifics.po @@ -0,0 +1,175 @@ +# SOME DESCRIPTIVE TITLE. +# Copyright (C) 2018 - 2024, SpinalHDL +# This file is distributed under the same license as the SpinalHDL package. +# FIRST AUTHOR , YEAR. +# +msgid "" +msgstr "" +"Project-Id-Version: SpinalHDL\n" +"Report-Msgid-Bugs-To: \n" +"POT-Creation-Date: 2024-01-02 16:09+0000\n" +"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" +"Last-Translator: Automatically generated\n" +"Language-Team: none\n" +"Language: es\n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=UTF-8\n" +"Content-Transfer-Encoding: 8bit\n" + +#: ../../SpinalHDL/Simulation/simulator_specifics.rst:3 +msgid "Simulator specific details" +msgstr "" + +#: ../../SpinalHDL/Simulation/simulator_specifics.rst:6 +msgid "How SpinalHDL simulates the hardware with Verilator backend" +msgstr "" + +#: ../../SpinalHDL/Simulation/simulator_specifics.rst:8 +msgid "Behind the scenes, SpinalHDL generates a Verilog equivalent hardware model of the DUT and then uses Verilator to convert it to a C++ cycle-accurate model." +msgstr "" + +#: ../../SpinalHDL/Simulation/simulator_specifics.rst:9 +msgid "The C++ model is compiled into a shared object (.so), which is bound to Scala via JNI-FFI." +msgstr "" + +#: ../../SpinalHDL/Simulation/simulator_specifics.rst:10 +msgid "The native Verilator API is abstracted by providing a simulation multi-threaded API." +msgstr "" + +#: ../../SpinalHDL/Simulation/simulator_specifics.rst:12 +#: ../../SpinalHDL/Simulation/simulator_specifics.rst:29 +#: ../../SpinalHDL/Simulation/simulator_specifics.rst:49 +#: ../../SpinalHDL/Simulation/simulator_specifics.rst:69 +msgid "**Advantages:**" +msgstr "" + +#: ../../SpinalHDL/Simulation/simulator_specifics.rst:14 +msgid "Since the Verilator backend uses a compiled C++ simulation model, the simulation speed is fast compared to most of the other commercial and free simulators." +msgstr "" + +#: ../../SpinalHDL/Simulation/simulator_specifics.rst:16 +#: ../../SpinalHDL/Simulation/simulator_specifics.rst:34 +#: ../../SpinalHDL/Simulation/simulator_specifics.rst:56 +#: ../../SpinalHDL/Simulation/simulator_specifics.rst:73 +msgid "**Limitations:**" +msgstr "" + +#: ../../SpinalHDL/Simulation/simulator_specifics.rst:18 +msgid "Verilator accepts only synthesizable Verilog/System Verilog code. Therefore special care has to be taken when simulating Verilog blackbox components that may have non-synthesizable statements." +msgstr "" + +#: ../../SpinalHDL/Simulation/simulator_specifics.rst:19 +msgid "VHDL blackboxes cannot be simulated." +msgstr "" + +#: ../../SpinalHDL/Simulation/simulator_specifics.rst:20 +msgid "The simulation boot process is slow due to the necessity to compile and link the generated C++ model. Some support to incrementally compile and link exists which can provide speedups for subsequent simulations after building the first." +msgstr "" + +#: ../../SpinalHDL/Simulation/simulator_specifics.rst:23 +msgid "How SpinalHDL simulates the hardware with GHDL/Icarus Verilog backend" +msgstr "" + +#: ../../SpinalHDL/Simulation/simulator_specifics.rst:25 +msgid "Depending on the chosen simulator, SpinalHDL generates a Verilog or VHDL hardware model of the DUT." +msgstr "" + +#: ../../SpinalHDL/Simulation/simulator_specifics.rst:26 +#: ../../SpinalHDL/Simulation/simulator_specifics.rst:46 +#: ../../SpinalHDL/Simulation/simulator_specifics.rst:66 +msgid "The HDL model is loaded in the simulator." +msgstr "" + +#: ../../SpinalHDL/Simulation/simulator_specifics.rst:27 +#: ../../SpinalHDL/Simulation/simulator_specifics.rst:47 +msgid "The communication between the simulation and the JVM is established through shared memory. The commands are issued to the simulator using `VPI `_." +msgstr "" + +#: ../../SpinalHDL/Simulation/simulator_specifics.rst:31 +msgid "Both GHDL and Icarus Verilog can accept non-synthesizable HDL code." +msgstr "" + +#: ../../SpinalHDL/Simulation/simulator_specifics.rst:32 +msgid "The simulation boot process is quite faster compared to Verilator." +msgstr "" + +#: ../../SpinalHDL/Simulation/simulator_specifics.rst:36 +msgid "GHDL accepts VHDL code only. Therefore only VHDL blackboxes can be used with this simulator." +msgstr "" + +#: ../../SpinalHDL/Simulation/simulator_specifics.rst:37 +msgid "Icarus Verilog accepts Verilog code only. Therefore only Verilog blackboxes can be used with this simulator." +msgstr "" + +#: ../../SpinalHDL/Simulation/simulator_specifics.rst:38 +msgid "The simulation speed is around one order of magnitude slower compared to Verilator." +msgstr "" + +#: ../../SpinalHDL/Simulation/simulator_specifics.rst:40 +msgid "Finally, as the native Verilator API is rather crude, SpinalHDL abstracts over it by providing both single and multi-threaded simulation APIs to help the user construct testbench implementations." +msgstr "" + +#: ../../SpinalHDL/Simulation/simulator_specifics.rst:43 +msgid "How SpinalHDL simulates the hardware with Synopsys VCS backend" +msgstr "" + +#: ../../SpinalHDL/Simulation/simulator_specifics.rst:45 +#: ../../SpinalHDL/Simulation/simulator_specifics.rst:65 +msgid "SpinalHDL generates a Verilog/VHDL (depended on your choice) hardware model of the DUT." +msgstr "" + +#: ../../SpinalHDL/Simulation/simulator_specifics.rst:51 +msgid "Support all language features of SystemVerilog/Verilog/VHDL." +msgstr "" + +#: ../../SpinalHDL/Simulation/simulator_specifics.rst:52 +msgid "Support encrypted IP." +msgstr "" + +#: ../../SpinalHDL/Simulation/simulator_specifics.rst:53 +msgid "Support FSDB wave format dump." +msgstr "" + +#: ../../SpinalHDL/Simulation/simulator_specifics.rst:54 +msgid "High Performance of both compilation and simulation." +msgstr "" + +#: ../../SpinalHDL/Simulation/simulator_specifics.rst:58 +msgid "Synopsys VCS is a **commercial** simulation tool. It is close source and not free. You have to own the licenses to **legally** use it." +msgstr "" + +#: ../../SpinalHDL/Simulation/simulator_specifics.rst:60 +msgid "Before using VCS as the simulation backend, make sure that you have checked your system environment as :ref:`VCS environment`." +msgstr "" + +#: ../../SpinalHDL/Simulation/simulator_specifics.rst:63 +msgid "How SpinalHDL simulates the hardware with Xilinx XSim backend" +msgstr "" + +#: ../../SpinalHDL/Simulation/simulator_specifics.rst:67 +msgid "The communication between the simulation and the JVM is established through shared memory. The commands are issued to the simulator using XSI." +msgstr "" + +#: ../../SpinalHDL/Simulation/simulator_specifics.rst:71 +msgid "Support Xilinx built-in primitives and cores." +msgstr "" + +#: ../../SpinalHDL/Simulation/simulator_specifics.rst:75 +msgid "Xilinx XSim is a **commercial** tool installed with Vivado. It is closed source and subject to licensing terms to use. You have to own the licenses to **legally** use it." +msgstr "" + +#: ../../SpinalHDL/Simulation/simulator_specifics.rst:76 +msgid "Vivado versions prior to 2019.1 do not work properly." +msgstr "" + +#: ../../SpinalHDL/Simulation/simulator_specifics.rst:78 +msgid "Before using XSim as the simulation backend, make sure that you have done following steps. 1. Define VIVADO_HOME environment variable to specify where your vivado located. ex `export VIVADO_HOME=/d/Xilinx/Vivado/2022.1` (under MSYS2). 2. Make sure two vivado path is inside the PATH. For Windows MSYS2 user, run shell command like `export PATH=$PATH:$VIVADO_HOME/bin:$VIVADO_HOME/lib/win64.o`. For Linux user just source the Vivado's settings64.sh file located at `VIVADO_HOME`." +msgstr "" + +#: ../../SpinalHDL/Simulation/simulator_specifics.rst:83 +msgid "Performance" +msgstr "" + +#: ../../SpinalHDL/Simulation/simulator_specifics.rst:85 +msgid "When a high-performance simulation is required, Verilator should be used as a backend. On a little SoC like `Murax `_, an Intel® Core™ i7-4720HQ is capable of simulating 1.2 million clock cycles per second. However, when the DUT is simple and a maximum of few thousands clock cycles have to be simulated, using GHDL or Icarus Verilog could yield a better result, due to their lower simulation loading overhead." +msgstr ""