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+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-26 16:21+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: Automatically generated\n"
+"Language-Team: none\n"
+"Language: es\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:4
+msgid "Clock domains"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:7
+msgid "Introduction"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:9
+msgid "In SpinalHDL, clock and reset signals can be combined to create a **clock domain**. Clock domains can be applied to some areas of the design and then all synchronous elements instantiated into those areas will then **implicitly** use this clock domain."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:11
+msgid "Clock domain application works like a stack, which means that if you are in a given clock domain you can still apply another clock domain locally."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:13
+msgid "Please note that a register captures its clock domain when the register is created, not when it is assigned. So please make sure to create them inside the desired ``ClockingArea``."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:18
+msgid "Instantiation"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:20
+msgid "The syntax to define a clock domain is as follows (using EBNF syntax):"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:33
+msgid "This definition takes five parameters:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:39
+#: ../../SpinalHDL/Structuring/clock_domain.rst:196
+msgid "Argument"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:40
+#: ../../SpinalHDL/Structuring/clock_domain.rst:197
+#: ../../SpinalHDL/Structuring/clock_domain.rst:338
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:41
+#: ../../SpinalHDL/Structuring/clock_domain.rst:198
+msgid "Default"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:42
+msgid "``clock``"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:43
+msgid "Clock signal that defines the domain"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:45
+msgid "``reset``"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:46
+msgid "Reset signal. If a register exists which needs a reset and the clock domain doesn't provide one, an error message will be displayed"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:47
+#: ../../SpinalHDL/Structuring/clock_domain.rst:50
+#: ../../SpinalHDL/Structuring/clock_domain.rst:53
+msgid "null"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:48
+msgid "``softReset``"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:49
+msgid "Reset which infers an additional synchronous reset"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:51
+msgid "``clockEnable``"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:52
+msgid "The goal of this signal is to disable the clock on the whole clock domain without having to manually implement that on each synchronous element"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:54
+#: ../../SpinalHDL/Structuring/clock_domain.rst:214
+msgid "``frequency``"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:55
+msgid "Allows you to specify the frequency of the given clock domain and later read it in your design. This parameter does not generate and PLL or other hardware to control the frequency"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:57
+#: ../../SpinalHDL/Structuring/clock_domain.rst:216
+msgid "UnknownFrequency"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:58
+#: ../../SpinalHDL/Structuring/clock_domain.rst:202
+msgid "``config``"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:59
+msgid "Specify the polarity of signals and the nature of the reset"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:60
+#: ../../SpinalHDL/Structuring/clock_domain.rst:204
+msgid "Current config"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:63
+msgid "An applied example to define a specific clock domain within the design is as follows:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:78
+msgid "When an `Area` is not needed, it is also possible to apply the clock domain directly. Two syntaxes exist:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:105
+msgid "Configuration"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:107
+msgid "In addition to :ref:`constructor parameters <clock_domain_instantiation>`\\ , the following elements of each clock domain are configurable via a ``ClockDomainConfig``\\ class:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:113
+msgid "Property"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:114
+msgid "Valid values"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:115
+msgid "``clockEdge``"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:116
+msgid "``RISING``\\ , ``FALLING``"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:117
+msgid "``resetKind``"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:118
+msgid "``ASYNC``\\ , ``SYNC``\\ , and ``BOOT`` which is supported by some FPGAs (where FF values are loaded by the bitstream)"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:119
+msgid "``resetActiveLevel``"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:120
+#: ../../SpinalHDL/Structuring/clock_domain.rst:122
+#: ../../SpinalHDL/Structuring/clock_domain.rst:124
+msgid "``HIGH``\\ , ``LOW``"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:121
+msgid "``softResetActiveLevel``"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:123
+msgid "``clockEnableActiveLevel``"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:157
+msgid "By default, a ``ClockDomain`` is applied to the whole design. The configuration of this default domain is:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:160
+msgid "Clock : rising edge"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:161
+msgid "Reset : asynchronous, active high"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:162
+msgid "No clock enable"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:164
+msgid "This corresponds to the following ``ClockDomainConfig``:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:175
+msgid "Internal clock"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:177
+msgid "An alternative syntax to create a clock domain is the following:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:190
+msgid "This definition takes six parameters:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:199
+msgid "``name``"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:200
+msgid "Name of `clk` and `reset` signal"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:203
+msgid "Specify polarity of signals and the nature of the reset"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:205
+msgid "``withReset``"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:206
+msgid "Add a reset signal"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:207
+msgid "true"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:208
+msgid "``withSoftReset``"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:209
+msgid "Add a soft reset signal"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:210
+#: ../../SpinalHDL/Structuring/clock_domain.rst:213
+msgid "false"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:211
+msgid "``withClockEnable``"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:212
+msgid "Add a clock enable"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:215
+msgid "Frequency of the clock domain"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:219
+msgid "The advantage of this approach is to create clock and reset signals with a known/specified name instead of an inherited one."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:221
+msgid "Once created, you have to assign the ``ClockDomain``'s signals, as shown in the example below:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:253
+msgid "In other components then the one you created the ClockDomain in, you must not use ``.clock`` and ``.reset``, but ``.readClockWire`` and ``.readResetWire`` as listed below. For the global ClockDomain you must always use those ``.readXXX`` functions."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:259
+msgid "External clock"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:261
+msgid "You can define a clock domain which is driven by the outside anywhere in your source. It will then automatically add clock and reset wires from the top level inputs to all synchronous elements."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:274
+msgid "The arguments to the ``ClockDomain.external`` function are exactly the same as in the ``ClockDomain.internal`` function. Below is an example of a design using ``ClockDomain.external``:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:296
+msgid "Signal priorities in HDL generation"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:298
+msgid "In the current version, reset and clock enable signals have different priorities. Their order is : ``asyncReset``, ``clockEnable``, ``syncReset`` and ``softReset``."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:300
+msgid "Please be careful that clockEnable has a higher priority than syncReset. If you do a sync reset when the clockEnable is disabled (especially at the beginning of a simulation), the gated registers will not be reseted."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:302
+msgid "Here is an example:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:310
+msgid "It will generate VerilogHDL codes like:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:324
+msgid "If that behaviour is problematic, one workaround is to use a when statement as a clock enable instead of using the ClockDomain.enable feature. This is open for future improvements."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:327
+msgid "Context"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:329
+msgid "You can retrieve in which clock domain you are by calling ``ClockDomain.current`` anywhere."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:331
+msgid "The returned ``ClockDomain`` instance has the following functions that can be called:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:337
+msgid "name"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:339
+msgid "Return"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:340
+msgid "frequency.getValue"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:0
+msgid "Return the frequency of the clock domain."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:0
+msgid "This being the arbitrary value you configured the domain with."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:343
+msgid "Double"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:344
+msgid "hasReset"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:345
+msgid "Return if the clock domain has a reset signal"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:346
+#: ../../SpinalHDL/Structuring/clock_domain.rst:349
+#: ../../SpinalHDL/Structuring/clock_domain.rst:352
+msgid "Boolean"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:347
+msgid "hasSoftReset"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:348
+msgid "Return if the clock domain has a soft reset signal"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:350
+msgid "hasClockEnable"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:351
+msgid "Return if the clock domain has a clock enable signal"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:353
+msgid "readClockWire"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:354
+msgid "Return a signal derived from the clock signal"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:355
+#: ../../SpinalHDL/Structuring/clock_domain.rst:358
+#: ../../SpinalHDL/Structuring/clock_domain.rst:361
+#: ../../SpinalHDL/Structuring/clock_domain.rst:364
+#: ../../SpinalHDL/Structuring/clock_domain.rst:367
+#: ../../SpinalHDL/Structuring/clock_domain.rst:370
+#: ../../SpinalHDL/Structuring/clock_domain.rst:373
+msgid "Bool"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:356
+msgid "readResetWire"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:357
+msgid "Return a signal derived from the reset signal"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:359
+msgid "readSoftResetWire"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:360
+msgid "Return a signal derived from the soft reset signal"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:362
+msgid "readClockEnableWire"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:363
+msgid "Return a signal derived from the clock enable signal"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:365
+msgid "isResetActive"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:366
+msgid "Return True when the reset is active"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:368
+msgid "isSoftResetActive"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:369
+msgid "Return True when the soft reset is active"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:371
+msgid "isClockEnableActive"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:372
+msgid "Return True when the clock enable is active"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:375
+msgid "An example is included below where a UART controller uses the frequency specification to set its clock divider:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:387
+msgid "Clock domain crossing"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:389
+msgid "SpinalHDL checks at compile time that there are no unwanted/unspecified cross clock domain signal reads. If you want to read a signal that is emitted by another ``ClockDomain`` area, you should add the ``crossClockDomain`` tag to the destination signal as depicted in the following example:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:451
+msgid "In general, you can use 2 or more flip-flop driven by the destination clock domain to prevent metastability. The ``BufferCC(input: T, init: T = null, bufferDepth: Int = 2)`` function provided in ``spinal.lib._`` will instantiate the necessary flip-flops (the number of flip-flops will depends on the ``bufferDepth`` parameter) to mitigate the phenomena."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:475
+msgid "The ``BufferCC`` function is only for signals of type ``Bit``, or ``Bits`` operating as Gray-coded counters (only 1 bit-flip per clock cycle), and can not used for multi-bit cross-domain processes. For multi-bit cases, it is recommended to use ``StreamFifoCC`` for high bandwidth requirements, or use ``StreamCCByToggle`` to reduce resource usage in cases where bandwidth is not critical."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:478
+msgid "Special clocking Areas"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:481
+msgid "Slow Area"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:483
+msgid "A ``SlowArea`` is used to create a new clock domain area which is slower than the current one:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:512
+msgid "The clock signal used in a SlowArea is the same as the parent one. The SlowArea add instead a clock-enable signal that will slow down the sampling rate inside it. In other words, ``ClockDomain.current.readClockWire`` will return the fast (parent domain) clock. To obtain the clock enable, use ``ClockDomain.current.readClockEnableWire``"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:517
+msgid "BootReset"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:519
+msgid "`clockDomain.withBootReset()` could specify register's resetKind as BOOT. `clockDomain.withSyncReset()` could specify register's resetKind as SYNC (sync-reset)."
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:537
+msgid "ResetArea"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:539
+msgid "A ``ResetArea`` is used to create a new clock domain area where a special reset signal is combined with the current clock domain reset:"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:559
+msgid "ClockEnableArea"
+msgstr ""
+
+#: ../../SpinalHDL/Structuring/clock_domain.rst:561
+msgid "A ``ClockEnableArea`` is used to add an additional clock enable in the current clock domain:"
+msgstr ""