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container.prj
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container.prj
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verilog work "ipcore_dir/ipcore_dir/ddr/user_design/rtl/phy/mig_7series_v1_9_ddr_of_pre_fifo.v"
verilog work "ipcore_dir/ipcore_dir/ddr/user_design/rtl/phy/mig_7series_v1_9_ddr_if_post_fifo.v"
verilog work "ipcore_dir/ipcore_dir/ddr/user_design/rtl/phy/mig_7series_v1_9_ddr_byte_group_io.v"
verilog work "ipcore_dir/ipcore_dir/ddr/user_design/rtl/phy/mig_7series_v1_9_ddr_byte_lane.v"
verilog work "ipcore_dir/ipcore_dir/ddr/user_design/rtl/controller/mig_7series_v1_9_round_robin_arb.v"
verilog work "ipcore_dir/ipcore_dir/ddr/user_design/rtl/phy/mig_7series_v1_9_ddr_phy_4lanes.v"
verilog work "ipcore_dir/ipcore_dir/ddr/user_design/rtl/controller/mig_7series_v1_9_bank_state.v"
verilog work "ipcore_dir/ipcore_dir/ddr/user_design/rtl/controller/mig_7series_v1_9_bank_queue.v"
verilog work "ipcore_dir/ipcore_dir/ddr/user_design/rtl/controller/mig_7series_v1_9_bank_compare.v"
verilog work "ipcore_dir/ipcore_dir/ddr/user_design/rtl/controller/mig_7series_v1_9_arb_select.v"
verilog work "ipcore_dir/ipcore_dir/ddr/user_design/rtl/controller/mig_7series_v1_9_arb_row_col.v"
verilog work "ipcore_dir/ipcore_dir/ddr/user_design/rtl/phy/mig_7series_v1_9_ddr_prbs_gen.v"
verilog work "ipcore_dir/ipcore_dir/ddr/user_design/rtl/phy/mig_7series_v1_9_ddr_phy_wrlvl_off_delay.v"
verilog work "ipcore_dir/ipcore_dir/ddr/user_design/rtl/phy/mig_7series_v1_9_ddr_phy_wrcal.v"
verilog work "ipcore_dir/ipcore_dir/ddr/user_design/rtl/phy/mig_7series_v1_9_ddr_phy_tempmon.v"
verilog work "ipcore_dir/ipcore_dir/ddr/user_design/rtl/phy/mig_7series_v1_9_ddr_phy_rdlvl.v"
verilog work "ipcore_dir/ipcore_dir/ddr/user_design/rtl/phy/mig_7series_v1_9_ddr_phy_prbs_rdlvl.v"
verilog work "ipcore_dir/ipcore_dir/ddr/user_design/rtl/phy/mig_7series_v1_9_ddr_phy_oclkdelay_cal.v"
verilog work "ipcore_dir/ipcore_dir/ddr/user_design/rtl/phy/mig_7series_v1_9_ddr_phy_init.v"
verilog work "ipcore_dir/ipcore_dir/ddr/user_design/rtl/phy/mig_7series_v1_9_ddr_phy_dqs_found_cal_hr.v"
verilog work "ipcore_dir/ipcore_dir/ddr/user_design/rtl/phy/mig_7series_v1_9_ddr_phy_dqs_found_cal.v"
verilog work "ipcore_dir/ipcore_dir/ddr/user_design/rtl/phy/mig_7series_v1_9_ddr_mc_phy.v"
verilog work "ipcore_dir/ipcore_dir/ddr/user_design/rtl/controller/mig_7series_v1_9_rank_common.v"
verilog work "ipcore_dir/ipcore_dir/ddr/user_design/rtl/controller/mig_7series_v1_9_rank_cntrl.v"
verilog work "ipcore_dir/ipcore_dir/ddr/user_design/rtl/controller/mig_7series_v1_9_bank_common.v"
verilog work "ipcore_dir/ipcore_dir/ddr/user_design/rtl/controller/mig_7series_v1_9_bank_cntrl.v"
verilog work "ipcore_dir/ipcore_dir/ddr/user_design/rtl/controller/mig_7series_v1_9_arb_mux.v"
verilog work "ipcore_dir/ipcore_dir/ddr/user_design/rtl/phy/mig_7series_v1_9_ddr_mc_phy_wrapper.v"
verilog work "ipcore_dir/ipcore_dir/ddr/user_design/rtl/phy/mig_7series_v1_9_ddr_calib_top.v"
verilog work "ipcore_dir/ipcore_dir/ddr/user_design/rtl/ecc/mig_7series_v1_9_ecc_merge_enc.v"
verilog work "ipcore_dir/ipcore_dir/ddr/user_design/rtl/ecc/mig_7series_v1_9_ecc_gen.v"
verilog work "ipcore_dir/ipcore_dir/ddr/user_design/rtl/ecc/mig_7series_v1_9_ecc_dec_fix.v"
verilog work "ipcore_dir/ipcore_dir/ddr/user_design/rtl/ecc/mig_7series_v1_9_ecc_buf.v"
verilog work "ipcore_dir/ipcore_dir/ddr/user_design/rtl/controller/mig_7series_v1_9_rank_mach.v"
verilog work "ipcore_dir/ipcore_dir/ddr/user_design/rtl/controller/mig_7series_v1_9_col_mach.v"
verilog work "ipcore_dir/ipcore_dir/ddr/user_design/rtl/controller/mig_7series_v1_9_bank_mach.v"
vhdl work "debugtools.vhdl"
vhdl work "cputypes.vhdl"
vhdl work "sid_coeffs.vhd"
verilog work "ipcore_dir/ipcore_dir/ddr/user_design/rtl/ui/mig_7series_v1_9_ui_wr_data.v"
verilog work "ipcore_dir/ipcore_dir/ddr/user_design/rtl/ui/mig_7series_v1_9_ui_rd_data.v"
verilog work "ipcore_dir/ipcore_dir/ddr/user_design/rtl/ui/mig_7series_v1_9_ui_cmd.v"
vhdl work "ipcore_dir/ipcore_dir/ddr/user_design/rtl/phy/mig_7series_v1_9_ddr_phy_top.vhd"
verilog work "ipcore_dir/ipcore_dir/ddr/user_design/rtl/controller/mig_7series_v1_9_mc.v"
vhdl work "ghdl_ram9x4k.vhdl"
vhdl work "bitplane.vhdl"
vhdl work "sprite.vhdl"
vhdl work "sid_voice.vhd"
vhdl work "sid_filters.vhd"
vhdl work "sd.vhdl"
verilog work "ipcore_dir/ipcore_dir/ddr/user_design/rtl/ui/mig_7series_v1_9_ui_top.v"
verilog work "ipcore_dir/ipcore_dir/ddr/user_design/rtl/ip_top/mig_7series_v1_9_mem_intfc.v"
vhdl work "ghdl_videobuffer.vhdl"
vhdl work "ghdl_ram8x512.vhdl"
vhdl work "ghdl_ram8x4096.vhdl"
vhdl work "crc.vhdl"
vhdl work "bitplanes.vhdl"
vhdl work "vicii_sprites.vhdl"
vhdl work "version.vhdl"
vhdl work "UART_TX_CTRL.vhd"
vhdl work "uart_rx.vhdl"
vhdl work "sid_6581.vhd"
vhdl work "shadowram.vhdl"
vhdl work "sdcardio.vhdl"
vhdl work "ram8x32k.vhd"
vhdl work "ram32x1024.vhd"
vhdl work "microcode.vhdl"
vhdl work "kickstart.vhdl"
vhdl work "keymapper.vhdl"
verilog work "ipcore_dir/ipcore_dir/ddr/user_design/rtl/ip_top/mig_7series_v1_9_memc_ui_top_std.v"
verilog work "ipcore_dir/ipcore_dir/ddr/user_design/rtl/clocking/mig_7series_v1_9_tempmon.v"
verilog work "ipcore_dir/ipcore_dir/ddr/user_design/rtl/clocking/mig_7series_v1_9_iodelay_ctrl.v"
verilog work "ipcore_dir/ipcore_dir/ddr/user_design/rtl/clocking/mig_7series_v1_9_infrastructure.v"
verilog work "ipcore_dir/ipcore_dir/ddr/user_design/rtl/clocking/mig_7series_v1_9_clk_ibuf.v"
vhdl work "ghdl_screen_ram_buffer.vhdl"
vhdl work "ghdl_ram18x2k.vhdl"
vhdl work "ghdl_ram128x1k.vhdl"
vhdl work "ghdl_farstack.vhdl"
vhdl work "ghdl_chipram8bit.vhdl"
vhdl work "ghdl_alpha_blend.vhdl"
vhdl work "framepacker.vhdl"
vhdl work "ethernet.vhdl"
vhdl work "cia6526.vhdl"
vhdl work "charrom.vhdl"
vhdl work "c65uart.vhdl"
vhdl work "viciv.vhdl"
vhdl work "uart_monitor.vhdl"
vhdl work "LocalRst.vhd"
vhdl work "ipcore_dir/ipcore_dir/ddr/user_design/rtl/ddr.vhd"
vhdl work "iomapper.vhdl"
vhdl work "gs4510.vhdl"
vhdl work "ghdl_ram151x512.vhdl"
vhdl work "machine.vhdl"
vhdl work "FPGAMonitor.vhd"
vhdl work "dotclock.vhd"
vhdl work "ddrwrapper.vhdl"
vhdl work "container.vhd"