Husky: potentially incorrect ADC sampling rate phase when using external clock

[jpcrypt]

When scope.clock.clkgen_src = 'extclk', then when setting scope.clock.clkgen_freq = X, we calculate Husky's PLL parameters to generate an ADC sampling clock as close as possible to scope.clock.adc_mul times the observed (measured by Husky) external clock frequency (let's call that X'), instead of scope.clock.adc_mul times the specified external clock frequency X.

If X' is not exactly X (which is possible and commonly occurs), then potentially there will not be a constant adc_mul samples per target clock cycle: once in a while there will be one extra or one less ADC sample in one clock cycle; also the phase relationship between the target and ADC clocks will not be constant: it will be slowly shifting forwards or backwards.

Usually, even if X' is not exactly X, then the "as close as possible" part mentioned above means we actually end up getting an ADC sampling clock of exactly adc_mul times the target clock (i.e. there is no problem).

But in theory that's not always the case, and exceptions have been observed: they are rare, but possible. They are more likely to occur with large adc_mul values.

A fix is forthcoming as part of wider fixes and improvements to the Husky clock management code. In the meantime, if:
1 / scope.clock.pll.get_input_div() * scope.clock.pll.get_pll_mul() * 5 / scope.clock.pll.get_prescale() / scope.clock.pll.get_outdiv(1) == 1

then you're ok. If not, you can try a different adc_mul.