From 3103106d3d63811aa460d53344e3cd35768e3418 Mon Sep 17 00:00:00 2001 From: Joo Liang Cheah Date: Wed, 5 Feb 2025 14:48:33 +0800 Subject: [PATCH 1/2] try pipeline test --- examples/analog_in/voltage_acq_int_clk.py | 3 ++- examples/analog_in/voltage_acq_int_clk_plot_data.py | 7 +++++-- examples/digital_in/read_dig_lines.py | 2 +- examples/digital_out/write_dig_lines.py | 2 +- 4 files changed, 9 insertions(+), 5 deletions(-) diff --git a/examples/analog_in/voltage_acq_int_clk.py b/examples/analog_in/voltage_acq_int_clk.py index 3debb6ef3..f073ccc75 100644 --- a/examples/analog_in/voltage_acq_int_clk.py +++ b/examples/analog_in/voltage_acq_int_clk.py @@ -8,8 +8,9 @@ from nidaqmx.constants import AcquisitionType, READ_ALL_AVAILABLE with nidaqmx.Task() as task: - task.ai_channels.add_ai_voltage_chan("Dev1/ai0") + task.ai_channels.add_ai_voltage_chan("Dev11/ai0") task.timing.cfg_samp_clk_timing(1000.0, sample_mode=AcquisitionType.FINITE, samps_per_chan=50) data = task.read(READ_ALL_AVAILABLE) print("Acquired data: [" + ", ".join(f"{value:f}" for value in data) + "]") + diff --git a/examples/analog_in/voltage_acq_int_clk_plot_data.py b/examples/analog_in/voltage_acq_int_clk_plot_data.py index f495efe6c..b9127ad6d 100644 --- a/examples/analog_in/voltage_acq_int_clk_plot_data.py +++ b/examples/analog_in/voltage_acq_int_clk_plot_data.py @@ -10,8 +10,10 @@ import nidaqmx from nidaqmx.constants import READ_ALL_AVAILABLE, AcquisitionType -with nidaqmx.Task() as task: - task.ai_channels.add_ai_voltage_chan("Dev1/ai0") +with nidaqmx.Task("ni") as task: + # task.ai_channels.add_ai_voltage_chan("Dev11/ai0") + # create_ai_microphone_chan + task.ai_channels.add_ai_microphone_chan("Dev11/ai1") task.timing.cfg_samp_clk_timing(1000.0, sample_mode=AcquisitionType.FINITE, samps_per_chan=50) data = task.read(READ_ALL_AVAILABLE) @@ -20,3 +22,4 @@ plot.ylabel("Amplitude") plot.title("Waveform") plot.show() + diff --git a/examples/digital_in/read_dig_lines.py b/examples/digital_in/read_dig_lines.py index 7370fc98e..a8bc8233a 100644 --- a/examples/digital_in/read_dig_lines.py +++ b/examples/digital_in/read_dig_lines.py @@ -9,7 +9,7 @@ with nidaqmx.Task() as task: - task.di_channels.add_di_chan("Dev1/port0/line0:3", line_grouping=LineGrouping.CHAN_PER_LINE) + task.di_channels.add_di_chan("Dev11/port0/line0:3", line_grouping=LineGrouping.CHAN_PER_LINE) data = task.read() print(f"Acquired data: {data}") diff --git a/examples/digital_out/write_dig_lines.py b/examples/digital_out/write_dig_lines.py index cf6e39b66..03f93a3dd 100644 --- a/examples/digital_out/write_dig_lines.py +++ b/examples/digital_out/write_dig_lines.py @@ -10,7 +10,7 @@ with nidaqmx.Task() as task: data = [True, False, True, False] - task.do_channels.add_do_chan("Dev1/port0/line0:3", line_grouping=LineGrouping.CHAN_PER_LINE) + task.do_channels.add_do_chan("Dev11/port0/line0:3", line_grouping=LineGrouping.CHAN_PER_LINE) task.start() task.write(data) task.stop() From 1aa4405fc550a4f1e81d93d2ece161a99c8358c9 Mon Sep 17 00:00:00 2001 From: Joo Liang Cheah Date: Wed, 5 Feb 2025 14:53:19 +0800 Subject: [PATCH 2/2] fixed style errors --- examples/analog_in/voltage_acq_int_clk.py | 1 - examples/analog_in/voltage_acq_int_clk_plot_data.py | 1 - 2 files changed, 2 deletions(-) diff --git a/examples/analog_in/voltage_acq_int_clk.py b/examples/analog_in/voltage_acq_int_clk.py index f073ccc75..f2b6bd847 100644 --- a/examples/analog_in/voltage_acq_int_clk.py +++ b/examples/analog_in/voltage_acq_int_clk.py @@ -13,4 +13,3 @@ data = task.read(READ_ALL_AVAILABLE) print("Acquired data: [" + ", ".join(f"{value:f}" for value in data) + "]") - diff --git a/examples/analog_in/voltage_acq_int_clk_plot_data.py b/examples/analog_in/voltage_acq_int_clk_plot_data.py index b9127ad6d..3695b92e7 100644 --- a/examples/analog_in/voltage_acq_int_clk_plot_data.py +++ b/examples/analog_in/voltage_acq_int_clk_plot_data.py @@ -22,4 +22,3 @@ plot.ylabel("Amplitude") plot.title("Waveform") plot.show() -