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mips32.sql
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PRAGMA foreign_keys=OFF;
BEGIN TRANSACTION;
CREATE TABLE instructions (platform TEXT, mnem TEXT, description TEXT);
INSERT INTO "instructions" VALUES('MIPS32','ABS.fmt','
Floating Point Absolute Value ABS.fmt
31 26 25 21 20 16 15 11 10 6 5 0
COP1 0 ABS
fmt fs fd
010001 00000 000101
6 5 5 5 5 6
Format: ABS.S fd, fs MIPS32 (MIPS I)
ABS.D fd, fs MIPS32 (MIPS I)
Purpose:
To compute the absolute value of an FP value
Description: fd <- abs(fs)
The absolute value of the value in FPR fs is placed in FPR fd. The operand and result are values in format fmt. Cause
bits are ORed into the Flag bits if no exception is taken.
This operation is arithmetic; a NaN operand signals invalid operation.
Restrictions:
The fields fs and fd must specify FPRs valid for operands of type fmt. If they are not valid, the result is UNPRE-
DICTABLE.
The operand must be a value in format fmt; if it is not, the result is UNPREDICTABLE and the value of the operand
FPR becomes UNPREDICTABLE.
Operation:
StoreFPR(fd, fmt, AbsoluteValue(ValueFPR(fs, fmt)))
Exceptions:
Coprocessor Unusable, Reserved Instruction
Floating Point Exceptions:
Unimplemented Operation, Invalid Operation');
INSERT INTO "instructions" VALUES('MIPS32','ADD','
Add Word ADD
31 26 25 21 20 16 15 11 10 6 5 0
SPECIAL 0 ADD
rs rt rd
000000 00000 100000
6 5 5 5 5 6
Format: ADD rd, rs, rt MIPS32 (MIPS I)
Purpose:
To add 32-bit integers. If an overflow occurs, then trap.
Description: rd <- rs + rt
The 32-bit word value in GPR rt is added to the 32-bit value in GPR rs to produce a 32-bit result.
. If the addition results in 32-bit 2''s complement arithmetic overflow, the destination register is not modified and
an Integer Overflow exception occurs.
. If the addition does not overflow, the 32-bit result is placed into GPR rd.
Restrictions:
None
Operation:
temp <- (GPR[rs]31||GPR[rs]31..0) + (GPR[rt]31||GPR[rt]31..0)
if temp
32 != temp31 then
SignalException(IntegerOverflow)
else
GPR[rd] <- temp
endif
Exceptions:
Integer Overflow
Programming Notes:
ADDU performs the same arithmetic operation but does not trap on overflow.');
INSERT INTO "instructions" VALUES('MIPS32','ADD.fmt','
Floating Point Add ADD.fmt
31 26 25 21 20 16 15 11 10 6 5 0
COP1 ADD
fmt ft fs fd
010001 000000
6 5 5 5 5 6
Format: ADD.S fd, fs, ft MIPS32 (MIPS I)
ADD.D fd, fs, ft MIPS32 (MIPS I)
Purpose:
To add floating point values
Description: fd <- fs + ft
The value in FPR ft is added to the value in FPR fs. The result is calculated to infinite precision, rounded by using to
the current rounding mode in FCSR, and placed into FPR fd. The operands and result are values in format fmt. Cause
bits are ORed into the Flag bits if no exception is taken.
Restrictions:
The fields fs, ft, and fd must specify FPRs valid for operands of type fmt. If they are not valid, the result is UNPRE-
DICTABLE.
The operands must be values in format fmt; if they are not, the result is UNPREDICTABLE and the value of the
operand FPRs becomes UNPREDICTABLE.
Operation:
StoreFPR (fd, fmt, ValueFPR(fs, fmt) +fmt ValueFPR(ft, fmt))
Exceptions:
Coprocessor Unusable, Reserved Instruction
Floating Point Exceptions:
Unimplemented Operation, Invalid Operation, Inexact, Overflow, Underflow');
INSERT INTO "instructions" VALUES('MIPS32','ADDI','
Add Immediate Word ADDI
31 26 25 21 20 16 15 0
ADDI
rs rt immediate
001000
6 5 5 16
Format: ADDI rt, rs, immediate MIPS32 (MIPS I)
Purpose:
To add a constant to a 32-bit integer. If overflow occurs, then trap.
Description: rt <- rs + immediate
The 16-bit signed immediate is added to the 32-bit value in GPR rs to produce a 32-bit result.
. If the addition results in 32-bit 2''s complement arithmetic overflow, the destination register is not modified and
an Integer Overflow exception occurs.
. If the addition does not overflow, the 32-bit result is placed into GPR rt.
Restrictions:
None
Operation:
temp <- (GPR[rs]31||GPR[rs]31..0) + sign_extend(immediate)
if temp
32 != temp31 then
SignalException(IntegerOverflow)
else
GPR[rt] <- temp
endif
Exceptions:
Integer Overflow
Programming Notes:
ADDIU performs the same arithmetic operation but does not trap on overflow.');
INSERT INTO "instructions" VALUES('MIPS32','ADDIU','
Add Immediate Unsigned Word ADDIU
31 26 25 21 20 16 15 0
ADDIU
rs rt immediate
001001
6 5 5 16
Format: ADDIU rt, rs, immediate MIPS32 (MIPS I)
Purpose:
To add a constant to a 32-bit integer
Description: rt <- rs + immediate
The 16-bit signed immediate is added to the 32-bit value in GPR rs and the 32-bit arithmetic result is placed into
GPR rt.
No Integer Overflow exception occurs under any circumstances.
Restrictions:
None
Operation:
temp <- GPR[rs] + sign_extend(immediate)
GPR[rt]<- temp
Exceptions:
None
Programming Notes:
The term !=unsigned!= in the instruction name is a misnomer; this operation is 32-bit modulo arithmetic that does not
trap on overflow. This instruction is appropriate for unsigned arithmetic, such as address arithmetic, or integer arith-
metic environments that ignore overflow, such as C language arithmetic.');
INSERT INTO "instructions" VALUES('MIPS32','ADDU','
Add Unsigned Word ADDU
31 26 25 21 20 16 15 11 10 6 5 0
SPECIAL 0 ADDU
rs rt rd
000000 00000 100001
6 5 5 5 5 6
Format: ADDU rd, rs, rt MIPS32 (MIPS I)
Purpose:
To add 32-bit integers
Description: rd <- rs + rt
The 32-bit word value in GPR rt is added to the 32-bit value in GPR rs and the 32-bit arithmetic result is placed into
GPR rd.
No Integer Overflow exception occurs under any circumstances.
Restrictions:
None
Operation:
temp <- GPR[rs] + GPR[rt]
GPR[rd] <- temp
Exceptions:
None
Programming Notes:
The term !=unsigned!= in the instruction name is a misnomer; this operation is 32-bit modulo arithmetic that does not
trap on overflow. This instruction is appropriate for unsigned arithmetic, such as address arithmetic, or integer arith-
metic environments that ignore overflow, such as C language arithmetic.');
INSERT INTO "instructions" VALUES('MIPS32','AND','
And AND
31 26 25 21 20 16 15 11 10 6 5 0
SPECIAL 0 AND
rs rt rd
000000 00000 100100
6 5 5 5 5 6
Format: AND rd, rs, rt MIPS32 (MIPS I)
Purpose:
To do a bitwise logical AND
Description: rd <- rs AND rt
The contents of GPR rs are combined with the contents of GPR rt in a bitwise logical AND operation. The result is
placed into GPR rd.
Restrictions:
None
Operation:
GPR[rd] <- GPR[rs] and GPR[rt]
Exceptions:
None');
INSERT INTO "instructions" VALUES('MIPS32','ANDI','
And Immediate ANDI
31 26 25 21 20 16 15 0
ANDI
rs rt immediate
001100
6 5 5 16
Format: ANDI rt, rs, immediate MIPS32 (MIPS I)
Purpose:
To do a bitwise logical AND with a constant
Description: rt <- rs AND immediate
The 16-bit immediate is zero-extended to the left and combined with the contents of GPR rs in a bitwise logical AND
operation. The result is placed into GPR rt.
Restrictions:
None
Operation:
GPR[rt] <- GPR[rs] and zero_extend(immediate)
Exceptions:
None');
INSERT INTO "instructions" VALUES('MIPS32','B','
Unconditional Branch B
31 26 25 21 20 16 15 0
BEQ 0 0
offset
000100 00000 00000
6 5 5 16
Format: B offset Assembly Idiom
Purpose:
To do an unconditional branch
Description: branch
B offset is the assembly idiom used to denote an unconditional branch. The actual instruction is interpreted by the
hardware as BEQ r0, r0, offset.
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following
the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the
delay slot of a branch or jump.
Operation:
I: target_offset <- sign_extend(offset || 0 ) 2
I+1: PC <- PC + target_offset
Exceptions:
None
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is +- 128 Kbytes. Use jump (J) or jump register
(JR) instructions to branch to addresses outside this range.');
INSERT INTO "instructions" VALUES('MIPS32','BAL','
Branch and Link BAL
31 26 25 21 20 16 15 0
REGIMM 0 BGEZAL
offset
000001 00000 10001
6 5 5 16
Format: BAL rs, offset Assembly Idiom
Purpose:
To do an unconditional PC-relative procedure call
Description: procedure_call
BAL offset is the assembly idiom used to denote an unconditional branch. The actual instruction is iterpreted by the
hardware as BGEZAL r0, offset.
Place the return address link in GPR 31. The return link is the address of the second instruction following the branch,
where execution continues after a procedure call.
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following
the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the
delay slot of a branch or jump.
GPR 31 must not be used for the source register rs, because such an instruction does not have the same effect when
reexecuted. The result of executing such an instruction is UNPREDICTABLE. This restriction permits an exception
handler to resume execution by reexecuting the branch when an exception occurs in the branch delay slot.
Operation:
I: target_offset <- sign_extend(offset || 0 ) 2
GPR[31] <- PC + 8
I+1: PC <- PC + target_offset
Exceptions:
None
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is +- 128 KBytes. Use jump and link (JAL) or
jump and link register (JALR) instructions for procedure calls to addresses outside this range.');
INSERT INTO "instructions" VALUES('MIPS32','BC1F','
Branch on FP False BC1F
31 26 25 21 20 18 17 16 15 0
COP1 BC nd tf
cc offset
010001 01000 0 0
6 5 3 1 1 16
Format: BC1F offset (cc = 0 implied) MIPS32 (MIPS I)
BC1F cc, offset MIPS32 (MIPS IV)
Purpose:
To test an FP condition code and do a PC-relative conditional branch
Description: if cc = 0 then branch
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following
the branch (not the branch itself) in the branch delay slot to form a PC-relative effective target address. If the FP con-
dition code bit CC is false (0), the program branches to the effective target address after the instruction in the delay
slot is executed. An FP condition code is set by the FP compare instruction, C.cond.fmt.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the
delay slot of a branch or jump.
Operation:
This operation specification is for the general Branch On Condition operation with the tf (true/false) and nd (nullify
delay slot) fields as variables. The individual instructions BC1F, BC1FL, BC1T, and BC1TL have specific values for
tf and nd.
I: condition <- FPConditionCode(cc) = 0
target_offset <- (offset15) GPRLEN-(16+2) || offset || 0 2
I+1: if condition then
PC <- PC + target_offset
endif
Exceptions:
Coprocessor Unusable, Reserved Instruction
Floating Point Exceptions:
Unimplemented Operation
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is +- 128 KBytes. Use jump (J) or jump register
(JR) instructions to branch to addresses outside this range
Historical Information:
The MIPS I architecture defines a single floating point condition code, implemented as the coprocessor 1 condition
signal (Cp1Cond) and the C bit in the FP Control/Status register. MIPS I, II, and III architectures must have the CC
field set to 0, which is implied by the first format in the !=Format!= section.
The MIPS IV and MIPS32 architectures add seven more Condition Code bits to the original condition code 0. FP
compare and conditional branch instructions specify the Condition Code bit to set or test. Both assembler formats are
valid for MIPS IV and MIPS32.
In the MIPS I, II, and III architectures there must be at least one instruction between the compare instruction that sets
the condition code and the branch instruction that tests it. Hardware does not detect a violation of this restriction.');
INSERT INTO "instructions" VALUES('MIPS32','BC1FL','
Branch on FP False Likely BC1FL
31 26 25 21 20 18 17 16 15 0
COP1 BC nd tf
cc offset
010001 01000 1 0
6 5 3 1 1 16
Format: BC1FL offset (cc = 0 implied) MIPS32 (MIPS II)
BC1FL cc, offset MIPS32 (MIPS IV)
Purpose:
To test an FP condition code and make a PC-relative conditional branch; execute the instruction in the delay slot only
if the branch is taken.
Description: if cc = 0 then branch_likely
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following
the branch (not the branch itself) in the branch delay slot to form a PC-relative effective target address. If the FP Con-
dition Code bit CC is false (0), the program branches to the effective target address after the instruction in the delay
slot is executed. If the branch is not taken, the instruction in the delay slot is not executed.
An FP condition code is set by the FP compare instruction, C.cond.fmt.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the
delay slot of a branch or jump.
Operation:
This operation specification is for the general Branch On Condition operation with the tf (true/false) and nd (nullify
delay slot) fields as variables. The individual instructions BC1F, BC1FL, BC1T, and BC1TL have specific values for
tf and nd.
I: condition <- FPConditionCode(cc) = 0
target_offset <- (offset15) GPRLEN-(16+2) || offset || 0 2
I+1: if condition then
PC <- PC + target_offset
else
NullifyCurrentInstruction()
endif
Exceptions:
Coprocessor Unusable, Reserved Instruction
Floating Point Exceptions:
Unimplemented Operation
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is +- 128 KBytes. Use jump (J) or jump register
(JR) instructions to branch to addresses outside this range.
Software is strongly encouraged to avoid the use of the Branch Likely instructions, as they will be removed from a
future revision of the MIPS Architecture.
Some implementations always predict the branch will be taken, so there is a significant penalty if the branch is not
taken. Software should only use this instruction when there is a very high probability (98% or more) that the branch
will be taken. If the branch is not likely to be taken or if the probability of a taken branch is unknown, software is
encouraged to use the BC1F instruction instead.
Historical Information:
The MIPS I architecture defines a single floating point condition code, implemented as the coprocessor 1 condition
signal (Cp1Cond) and the C bit in the FP Control/Status register. MIPS I, II, and III architectures must have the CC
field set to 0, which is implied by the first format in the !=Format!= section.
The MIPS IV and MIPS32 architectures add seven more Condition Code bits to the original condition code 0. FP
compare and conditional branch instructions specify the Condition Code bit to set or test. Both assembler formats are
valid for MIPS IV and MIPS32.
In the MIPS II andIII architectionrs there must be at least one instruction between the compare instruction that
sets a condition code and the branch instruction that tests it. Hardware does not detect a violation of this restriction.');
INSERT INTO "instructions" VALUES('MIPS32','BC1T','
Branch on FP True BC1T
31 26 25 21 20 18 17 16 15 0
COP1 BC nd tf
cc offset
010001 01000 0 1
6 5 3 1 1 16
Format: BC1T offset (cc = 0 implied) MIPS32 (MIPS I)
BC1T cc, offset MIPS32 (MIPS IV)
Purpose:
To test an FP condition code and do a PC-relative conditional branch
Description: if cc = 1 then branch
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following
the branch (not the branch itself) in the branch delay slot to form a PC-relative effective target address. If the FP con-
dition code bit CC is true (1), the program branches to the effective target address after the instruction in the delay slot
is executed. An FP condition code is set by the FP compare instruction, C.cond.fmt.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the
delay slot of a branch or jump.
Operation:
This operation specification is for the general Branch On Condition operation with the tf (true/false) and nd (nullify
delay slot) fields as variables. The individual instructions BC1F, BC1FL, BC1T, and BC1TL have specific values for
tf and nd.
I: condition <- FPConditionCode(cc) = 1
target_offset <- (offset15) GPRLEN-(16+2) || offset || 0 2
I+1: if condition then
PC <- PC + target_offset
endif
Exceptions:
Coprocessor Unusable, Reserved Instruction
Floating Point Exceptions:
Unimplemented Operation
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is +- 128 KBytes. Use jump (J) or jump register
(JR) instructions to branch to addresses outside this range.
Historical Information:
The MIPS I architecture defines a single floating point condition code, implemented as the coprocessor 1 condition
signal (Cp1Cond) and the C bit in the FP Control/Status register. MIPS I, II, and III architectures must have the CC
field set to 0, which is implied by the first format in the !=Format!= section.
The MIPS IV and MIPS32 architectures add seven more Condition Code bits to the original condition code 0. FP
compare and conditional branch instructions specify the Condition Code bit to set or test. Both assembler formats are
valid for MIPS IV and MIPS32.
In the MIPS I, II, and III architectures there must be at least one instruction between the compare instruction that sets
the condition code and the branch instruction that tests it. Hardware does not detect a violation of this restriction.');
INSERT INTO "instructions" VALUES('MIPS32','BC1TL','
Branch on FP True Likely BC1TL
31 26 25 21 20 18 17 16 15 0
COP1 BC nd tf
cc offset
010001 01000 1 1
6 5 3 1 1 16
Format: BC1TL offset (cc = 0 implied) MIPS32 (MIPS II)
BC1TL cc, offset MIPS32 (MIPS IV)
Purpose:
To test an FP condition code and do a PC-relative conditional branch; execute the instruction in the delay slot only if
the branch is taken.
Description: if cc = 1 then branch_likely
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following
the branch (not the branch itself) in the branch delay slot to form a PC-relative effective target address. If the FP Con-
dition Code bit CC is true (1), the program branches to the effective target address after the instruction in the delay
slot is executed. If the branch is not taken, the instruction in the delay slot is not executed.
An FP condition code is set by the FP compare instruction, C.cond.fmt.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the
delay slot of a branch or jump.
Operation:
This operation specification is for the general Branch On Condition operation with the tf (true/false) and nd (nullify
delay slot) fields as variables. The individual instructions BC1F, BC1FL, BC1T, and BC1TL have specific values for
tf and nd.
I: condition <- FPConditionCode(cc) = 1
target_offset <- (offset15) GPRLEN-(16+2) || offset || 0 2
I+1: if condition then
PC <- PC + target_offset
else
NullifyCurrentInstruction()
endif
Exceptions:
Coprocessor Unusable, Reserved Instruction
Floating Point Exceptions:
Unimplemented Operation
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is +- 128 KBytes. Use jump (J) or jump register
(JR) instructions to branch to addresses outside this range.
Software is strongly encouraged to avoid the use of the Branch Likely instructions, as they will be removed from a
future revision of the MIPS Architecture.
Some implementations always predict the branch will be taken, so there is a significant penalty if the branch is not
taken. Software should only use this instruction when there is a very high probability (98% or more) that the branch
will be taken. If the branch is not likely to be taken or if the probability of a taken branch is unknown, software is
encouraged to use the BC1T instruction instead.
Historical Information:
The MIPS I architecture defines a single floating point condition code, implemented as the coprocessor 1 condition
signal (Cp1Cond) and the C bit in the FP Control/Status register. MIPS I, II, and III architectures must have the CC
field set to 0, which is implied by the first format in the !=Format!= section.
The MIPS IV and MIPS32 architectures add seven more Condition Code bits to the original condition code 0. FP
compare and conditional branch instructions specify the Condition Code bit to set or test. Both assembler formats are
valid for MIPS IV and MIPS32.
In the MIPS II andIII architectionrs there must be at least one instruction between the compare instruction that
sets a condition code and the branch instruction that tests it. Hardware does not detect a violation of this restriction.');
INSERT INTO "instructions" VALUES('MIPS32','BC2F','
Branch on COP2 False BC2F
31 26 25 21 20 18 17 16 15 0
COP2 BC nd tf
cc offset
010010 01000 0 0
6 5 3 1 1 16
Format: BC2F offset (cc = 0 implied) MIPS32 (MIPS I)
BC2F cc, offset MIPS32 (MIPS IV)
Purpose:
To test a COP2 condition code and do a PC-relative conditional branch
Description: if cc = 0 then branch
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following
the branch (not the branch itself) in the branch delay slot to form a PC-relative effective target address. If the COP2
condition specified by CC is false (0), the program branches to the effective target address after the instruction in the
delay slot is executed.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the
delay slot of a branch or jump.
Operation:
This operation specification is for the general Branch On Condition operation with the tf (true/false) and nd (nullify
delay slot) fields as variables. The individual instructions BC2F, BC2FL, BC2T, and BC2TL have specific values for
tf and nd.
I: condition <- COP2Condition(cc) = 0
target_offset <- (offset15) GPRLEN-(16+2) || offset || 0 2
I+1: if condition then
PC <- PC + target_offset
endif
Exceptions:
Coprocessor Unusable, Reserved Instruction
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is +- 128 KBytes. Use jump (J) or jump register
(JR) instructions to branch to addresses outside this range.');
INSERT INTO "instructions" VALUES('MIPS32','BC2FL','
Branch on COP2 False Likely BC2FL
31 26 25 21 20 18 17 16 15 0
COP2 BC nd tf
cc offset
010010 01000 1 0
6 5 3 1 1 16
Format: BC2FL offset (cc = 0 implied) MIPS32 (MIPS II)
BC2FL cc, offset MIPS32 (MIPS IV)
Purpose:
To test a COP2 condition code and make a PC-relative conditional branch; execute the instruction in the delay slot
only if the branch is taken.
Description: if cc = 0 then branch_likely
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following
the branch (not the branch itself) in the branch delay slot to form a PC-relative effective target address. If the COP2
condition specified by CC is false (0), the program branches to the effective target address after the instruction in the
delay slot is executed. If the branch is not taken, the instruction in the delay slot is not executed.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the
delay slot of a branch or jump.
Operation:
This operation specification is for the general Branch On Condition operation with the tf (true/false) and nd (nullify
delay slot) fields as variables. The individual instructions BC2F, BC2FL, BC2T, and BC2TL have specific values for
tf and nd.
I: condition <- COP2Condition(cc) = 0
target_offset <- (offset15) GPRLEN-(16+2) || offset || 0 2
I+1: if condition then
PC <- PC + target_offset
else
NullifyCurrentInstruction()
endif
Exceptions:
Coprocessor Unusable, Reserved Instruction
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is +- 128 KBytes. Use jump (J) or jump register
(JR) instructions to branch to addresses outside this range.
Software is strongly encouraged to avoid the use of the Branch Likely instructions, as they will be removed from a
future revision of the MIPS Architecture.
Some implementations always predict the branch will be taken, so there is a significant penalty if the branch is not
taken. Software should only use this instruction when there is a very high probability (98% or more) that the branch
will be taken. If the branch is not likely to be taken or if the probability of a taken branch is unknown, software is
encouraged to use the BC2F instruction instead.');
INSERT INTO "instructions" VALUES('MIPS32','BC2T','
Branch on COP2 True BC2T
31 26 25 21 20 18 17 16 15 0
COP2 BC nd tf
cc offset
010010 01000 0 1
6 5 3 1 1 16
Format: BC2T offset (cc = 0 implied) MIPS32 (MIPS I)
BC2T cc, offset MIPS32 (MIPS IV)
Purpose:
To test a COP2 condition code and do a PC-relative conditional branch
Description: if cc = 1 then branch
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following
the branch (not the branch itself) in the branch delay slot to form a PC-relative effective target address. If the COP2
condition specified by CC is true (1), the program branches to the effective target address after the instruction in the
delay slot is executed.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the
delay slot of a branch or jump.
Operation:
This operation specification is for the general Branch On Condition operation with the tf (true/false) and nd (nullify
delay slot) fields as variables. The individual instructions BC2F, BC2FL, BC2T, and BC2TL have specific values for
tf and nd.
I: condition <- COP2Condition(cc) = 1
target_offset <- (offset15) GPRLEN-(16+2) || offset || 0 2
I+1: if condition then
PC <- PC + target_offset
endif
Exceptions:
Coprocessor Unusable, Reserved Instruction
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is +- 128 KBytes. Use jump (J) or jump register
(JR) instructions to branch to addresses outside this range.');
INSERT INTO "instructions" VALUES('MIPS32','BC2TL','
Branch on COP2 True Likely BC2TL
31 26 25 21 20 18 17 16 15 0
COP2 BC nd tf
cc offset
010010 01000 1 1
6 5 3 1 1 16
Format: BC2TL offset (cc = 0 implied) MIPS32 (MIPS II)
BC2TL cc, offset MIPS32 (MIPS IV)
Purpose:
To test a COP2 condition code and do a PC-relative conditional branch; execute the instruction in the delay slot only
if the branch is taken.
Description: if cc = 1 then branch_likely
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following
the branch (not the branch itself) in the branch delay slot to form a PC-relative effective target address. If the COP2
condition specified by CC is true (1), the program branches to the effective target address after the instruction in the
delay slot is executed. If the branch is not taken, the instruction in the delay slot is not executed.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the
delay slot of a branch or jump.
Operation:
This operation specification is for the general Branch On Condition operation with the tf (true/false) and nd (nullify
delay slot) fields as variables. The individual instructions BC2F, BC2FL, BC2T, and BC2TL have specific values for
tf and nd.
I: condition <- COP2Condition(cc) = 1
target_offset <- (offset15) GPRLEN-(16+2) || offset || 0 2
I+1: if condition then
PC <- PC + target_offset
else
NullifyCurrentInstruction()
endif
Exceptions:
Coprocessor Unusable, Reserved Instruction