[tobe fromlist] platform: nordic: Update the nrf-pinctrl.h

platform/ext/target/nordic_nrf/common/core/cmsis_drivers/Driver_USART.c

@@ -22,7 +22,7 @@
 #include <nrfx_uarte.h>
 #include <string.h>
 #include <stdint.h>
-#include <nrf-pinctrl.h>
+#include <tfm-pinctrl.h>
 
 #ifndef ARRAY_SIZE
 #define ARRAY_SIZE(arr) (sizeof(arr)/sizeof(arr[0]))

platform/ext/target/nordic_nrf/common/core/common/nrf-pinctrl.h

@@ -3,33 +3,57 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef NRF_INCLUDE_NRF_PINCTRL_H
-#define NRF_INCLUDE_NRF_PINCTRL_H
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NRF_PINCTRL_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NRF_PINCTRL_H_
 
 /*
  * The whole nRF pin configuration information is encoded in a 32-bit bitfield
  * organized as follows:
  *
- * - 31..16: Pin function.
- * - 15:     Reserved.
- * - 14:     Pin inversion mode.
- * - 13:     Pin low power mode.
- * - 12..9:  Pin output drive configuration.
- * - 8..7:   Pin pull configuration.
- * - 6..0:   Pin number (combination of port and pin).
+ * - 31..24: Pin function.
+ * - 19-23:  Reserved.
+ * - 18:     Associated peripheral belongs to GD FAST ACTIVE1 (nRF54H only)
+ * - 17:     Clockpin enable.
+ * - 16:     Pin inversion mode.
+ * - 15:     Pin low power mode.
+ * - 14..11: Pin output drive configuration.
+ * - 10..9:  Pin pull configuration.
+ * - 8..0:   Pin number (combination of port and pin).
  */
 
-/* NOTE: Keep in sync with Zephyr's nrf-pinctrl.h */
-
 /**
  * @name nRF pin configuration bit field positions and masks.
  * @{
  */
 
 /** Position of the function field. */
-#define NRF_FUN_POS 17U
+#define NRF_FUN_POS 24U
 /** Mask for the function field. */
-#define NRF_FUN_MSK 0x7FFFU
+#define NRF_FUN_MSK 0xFFU
+/** Position of the GPD FAST ACTIVE1 */
+#define NRF_GPD_FAST_ACTIVE1_POS 18U
+/** Mask for the GPD FAST ACTIVE1 */
+#define NRF_GPD_FAST_ACTIVE1_MSK 0x1U
+/** Position of the clockpin enable field. */
+#define NRF_CLOCKPIN_ENABLE_POS 17U
+/** Mask for the clockpin enable field. */
+#define NRF_CLOCKPIN_ENABLE_MSK 0x1U
+/** Position of the invert field. */
+#define NRF_INVERT_POS 16U
+/** Mask for the invert field. */
+#define NRF_INVERT_MSK 0x1U
+/** Position of the low power field. */
+#define NRF_LP_POS 15U
+/** Mask for the low power field. */
+#define NRF_LP_MSK 0x1U
+/** Position of the drive configuration field. */
+#define NRF_DRIVE_POS 11U
+/** Mask for the drive configuration field. */
+#define NRF_DRIVE_MSK 0xFU
+/** Position of the pull configuration field. */
+#define NRF_PULL_POS 9U
+/** Mask for the pull configuration field. */
+#define NRF_PULL_MSK 0x3U
 /** Position of the pin field. */
 #define NRF_PIN_POS 0U
 /** Mask for the pin field. */
@@ -50,6 +74,246 @@
 #define NRF_FUN_UART_RTS 2U
 /** UART CTS */
 #define NRF_FUN_UART_CTS 3U
+/** SPI master SCK */
+#define NRF_FUN_SPIM_SCK 4U
+/** SPI master MOSI */
+#define NRF_FUN_SPIM_MOSI 5U
+/** SPI master MISO */
+#define NRF_FUN_SPIM_MISO 6U
+/** SPI slave SCK */
+#define NRF_FUN_SPIS_SCK 7U
+/** SPI slave MOSI */
+#define NRF_FUN_SPIS_MOSI 8U
+/** SPI slave MISO */
+#define NRF_FUN_SPIS_MISO 9U
+/** SPI slave CSN */
+#define NRF_FUN_SPIS_CSN 10U
+/** TWI master SCL */
+#define NRF_FUN_TWIM_SCL 11U
+/** TWI master SDA */
+#define NRF_FUN_TWIM_SDA 12U
+/** I2S SCK in master mode */
+#define NRF_FUN_I2S_SCK_M 13U
+/** I2S SCK in slave mode */
+#define NRF_FUN_I2S_SCK_S 14U
+/** I2S LRCK in master mode */
+#define NRF_FUN_I2S_LRCK_M 15U
+/** I2S LRCK in slave mode */
+#define NRF_FUN_I2S_LRCK_S 16U
+/** I2S SDIN */
+#define NRF_FUN_I2S_SDIN 17U
+/** I2S SDOUT */
+#define NRF_FUN_I2S_SDOUT 18U
+/** I2S MCK */
+#define NRF_FUN_I2S_MCK 19U
+/** PDM CLK */
+#define NRF_FUN_PDM_CLK 20U
+/** PDM DIN */
+#define NRF_FUN_PDM_DIN 21U
+/** PWM OUT0 */
+#define NRF_FUN_PWM_OUT0 22U
+/** PWM OUT1 */
+#define NRF_FUN_PWM_OUT1 23U
+/** PWM OUT2 */
+#define NRF_FUN_PWM_OUT2 24U
+/** PWM OUT3 */
+#define NRF_FUN_PWM_OUT3 25U
+/** QDEC A */
+#define NRF_FUN_QDEC_A 26U
+/** QDEC B */
+#define NRF_FUN_QDEC_B 27U
+/** QDEC LED */
+#define NRF_FUN_QDEC_LED 28U
+/** QSPI SCK */
+#define NRF_FUN_QSPI_SCK 29U
+/** QSPI CSN */
+#define NRF_FUN_QSPI_CSN 30U
+/** QSPI IO0 */
+#define NRF_FUN_QSPI_IO0 31U
+/** QSPI IO1 */
+#define NRF_FUN_QSPI_IO1 32U
+/** QSPI IO2 */
+#define NRF_FUN_QSPI_IO2 33U
+/** QSPI IO3 */
+#define NRF_FUN_QSPI_IO3 34U
+/** EXMIF CK */
+#define NRF_FUN_EXMIF_CK 35U
+/** EXMIF DQ0 */
+#define NRF_FUN_EXMIF_DQ0 36U
+/** EXMIF DQ1 */
+#define NRF_FUN_EXMIF_DQ1 37U
+/** EXMIF DQ2 */
+#define NRF_FUN_EXMIF_DQ2 38U
+/** EXMIF DQ3 */
+#define NRF_FUN_EXMIF_DQ3 39U
+/** EXMIF DQ4 */
+#define NRF_FUN_EXMIF_DQ4 40U
+/** EXMIF DQ5 */
+#define NRF_FUN_EXMIF_DQ5 41U
+/** EXMIF DQ6 */
+#define NRF_FUN_EXMIF_DQ6 42U
+/** EXMIF DQ7 */
+#define NRF_FUN_EXMIF_DQ7 43U
+/** EXMIF CS0 */
+#define NRF_FUN_EXMIF_CS0 44U
+/** EXMIF CS1 */
+#define NRF_FUN_EXMIF_CS1 45U
+/** CAN TX */
+#define NRF_FUN_CAN_TX 46U
+/** CAN RX */
+#define NRF_FUN_CAN_RX 47U
+/** TWIS SCL */
+#define NRF_FUN_TWIS_SCL 48U
+/** TWIS SDA */
+#define NRF_FUN_TWIS_SDA 49U
+/** EXMIF RWDS */
+#define NRF_FUN_EXMIF_RWDS 50U
+/** GRTC fast clock output */
+#define NRF_FUN_GRTC_CLKOUT_FAST 55U
+/** GRTC slow clock output */
+#define NRF_FUN_GRTC_CLKOUT_32K  56U
+/** SDP_MSPI clock pin */
+#define NRF_FUN_SDP_MSPI_SCK 57U
+/** SDP_MSPI data pin 0 */
+#define NRF_FUN_SDP_MSPI_DQ0 58U
+/** SDP_MSPI data pin 1 */
+#define NRF_FUN_SDP_MSPI_DQ1 59U
+/** SDP_MSPI data pin 2 */
+#define NRF_FUN_SDP_MSPI_DQ2 60U
+/** SDP_MSPI data pin 3 */
+#define NRF_FUN_SDP_MSPI_DQ3 61U
+/** SDP_MSPI data pin 4 */
+#define NRF_FUN_SDP_MSPI_DQ4 62U
+/** SDP_MSPI data pin 5 */
+#define NRF_FUN_SDP_MSPI_DQ5 63U
+/** SDP_MSPI data pin 6 */
+#define NRF_FUN_SDP_MSPI_DQ6 64U
+/** SDP_MSPI data pin 7 */
+#define NRF_FUN_SDP_MSPI_DQ7 65U
+/** SDP_MSPI chip select 0 */
+#define NRF_FUN_SDP_MSPI_CS0 66U
+/** SDP_MSPI chip select 1 */
+#define NRF_FUN_SDP_MSPI_CS1 67U
+/** SDP_MSPI chip select 2 */
+#define NRF_FUN_SDP_MSPI_CS2 68U
+/** SDP_MSPI chip select 3 */
+#define NRF_FUN_SDP_MSPI_CS3 69U
+/** SDP_MSPI chip select 4 */
+#define NRF_FUN_SDP_MSPI_CS4 70U
+/** High-Performance Framework MSPI clock pin */
+#define NRF_FUN_HPF_MSPI_SCK NRF_FUN_SDP_MSPI_SCK
+/** High-Performance Framework MSPI data pin 0 */
+#define NRF_FUN_HPF_MSPI_DQ0 NRF_FUN_SDP_MSPI_DQ0
+/** High-Performance Framework MSPI data pin 1 */
+#define NRF_FUN_HPF_MSPI_DQ1 NRF_FUN_SDP_MSPI_DQ1
+/** High-Performance Framework MSPI data pin 2 */
+#define NRF_FUN_HPF_MSPI_DQ2 NRF_FUN_SDP_MSPI_DQ2
+/** High-Performance Framework MSPI data pin 3 */
+#define NRF_FUN_HPF_MSPI_DQ3 NRF_FUN_SDP_MSPI_DQ3
+/** High-Performance Framework MSPI data pin 4 */
+#define NRF_FUN_HPF_MSPI_DQ4 NRF_FUN_SDP_MSPI_DQ4
+/** High-Performance Framework MSPI data pin 5 */
+#define NRF_FUN_HPF_MSPI_DQ5 NRF_FUN_SDP_MSPI_DQ5
+/** High-Performance Framework MSPI data pin 6 */
+#define NRF_FUN_HPF_MSPI_DQ6 NRF_FUN_SDP_MSPI_DQ6
+/** High-Performance Framework MSPI data pin 7 */
+#define NRF_FUN_HPF_MSPI_DQ7 NRF_FUN_SDP_MSPI_DQ7
+/** High-Performance Framework MSPI chip select pin 0 */
+#define NRF_FUN_HPF_MSPI_CS0 NRF_FUN_SDP_MSPI_CS0
+/** High-Performance Framework MSPI chip select pin 1 */
+#define NRF_FUN_HPF_MSPI_CS1 NRF_FUN_SDP_MSPI_CS1
+/** High-Performance Framework MSPI chip select pin 2 */
+#define NRF_FUN_HPF_MSPI_CS2 NRF_FUN_SDP_MSPI_CS2
+/** High-Performance Framework MSPI chip select pin 3 */
+#define NRF_FUN_HPF_MSPI_CS3 NRF_FUN_SDP_MSPI_CS3
+/** High-Performance Framework MSPI chip select pin 4 */
+#define NRF_FUN_HPF_MSPI_CS4 NRF_FUN_SDP_MSPI_CS4
+/** TDM SCK in master mode */
+#define NRF_FUN_TDM_SCK_M        71U
+/** TDM SCK in slave mode */
+#define NRF_FUN_TDM_SCK_S        72U
+/** TDM LRCK in master mode */
+#define NRF_FUN_TDM_FSYNC_M      73U
+/** TDM LRCK in slave mode */
+#define NRF_FUN_TDM_FSYNC_S      74U
+/** TDM SDIN */
+#define NRF_FUN_TDM_SDIN         75U
+/** TDM SDOUT */
+#define NRF_FUN_TDM_SDOUT        76U
+/** TDM MCK */
+#define NRF_FUN_TDM_MCK          77U
+/** SPI master CSN */
+#define NRF_FUN_SPIM_CSN         78U
+/** TPIU CLOCK */
+#define NRF_FUN_TPIU_CLOCK       79U
+/** TPIU DATA0 */
+#define NRF_FUN_TPIU_DATA0       80U
+/** TPIU DATA1 */
+#define NRF_FUN_TPIU_DATA1       81U
+/** TPIU DATA2 */
+#define NRF_FUN_TPIU_DATA2       82U
+/** TPIU DATA3 */
+#define NRF_FUN_TPIU_DATA3       83U
+
+/** @} */
+
+/**
+ * @name nRF pinctrl output drive.
+ * @{
+ */
+
+/** Standard '0', standard '1'. */
+#define NRF_DRIVE_S0S1 0U
+/** High drive '0', standard '1'. */
+#define NRF_DRIVE_H0S1 1U
+/** Standard '0', high drive '1'. */
+#define NRF_DRIVE_S0H1 2U
+/** High drive '0', high drive '1'. */
+#define NRF_DRIVE_H0H1 3U
+/** Disconnect '0' standard '1'. */
+#define NRF_DRIVE_D0S1 4U
+/** Disconnect '0', high drive '1'. */
+#define NRF_DRIVE_D0H1 5U
+/** Standard '0', disconnect '1'. */
+#define NRF_DRIVE_S0D1 6U
+/** High drive '0', disconnect '1'. */
+#define NRF_DRIVE_H0D1 7U
+/** Extra high drive '0', extra high drive '1'. */
+#define NRF_DRIVE_E0E1 8U
+
+/** @} */
+
+/**
+ * @name nRF pinctrl pull-up/down.
+ * @note Values match nrf_gpio_pin_pull_t constants.
+ * @{
+ */
+
+/** Pull-up disabled. */
+#define NRF_PULL_NONE 0U
+/** Pull-down enabled. */
+#define NRF_PULL_DOWN 1U
+/** Pull-up enabled. */
+#define NRF_PULL_UP 3U
+
+/** @} */
+
+/**
+ * @name nRF pinctrl low power mode.
+ * @{
+ */
+
+/** Input. */
+#define NRF_LP_DISABLE 0U
+/** Output. */
+#define NRF_LP_ENABLE 1U
+
+/** @} */
+
+/**
+ * @name nRF pinctrl helpers to indicate disconnected pins.
+ * @{
+ */
 
 /** Indicates that a pin is disconnected */
 #define NRF_PIN_DISCONNECTED NRF_PIN_MSK
@@ -60,7 +324,7 @@
  * @brief Utility macro to build nRF psels property entry.
  *
  * @param fun Pin function configuration (see NRF_FUNC_{name} macros).
- * @param port Port (0 or 1).
+ * @param port Port (0 or 15).
  * @param pin Pin (0..31).
  */
 #define NRF_PSEL(fun, port, pin)						       \
@@ -79,19 +343,4 @@
 	(NRF_PIN_DISCONNECTED |							       \
 	 ((NRF_FUN_ ## fun & NRF_FUN_MSK) << NRF_FUN_POS))
 
-/**
- * @brief Utility macro to obtain pin function.
- *
- * @param pincfg Pin configuration bit field.
- */
-#define NRF_GET_FUN(pincfg) (((pincfg) >> NRF_FUN_POS) & NRF_FUN_MSK)
-
-
-/**
- * @brief Utility macro to obtain port and pin combination.
- *
- * @param pincfg Pin configuration bit field.
- */
-#define NRF_GET_PIN(pincfg) (((pincfg) >> NRF_PIN_POS) & NRF_PIN_MSK)
-
-#endif /* NRF_INCLUDE_NRF_PINCTRL_H */
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NRF_PINCTRL_H_ */

platform/ext/target/nordic_nrf/common/core/common/tfm-pinctrl.h

@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef TFM_INCLUDE_NRF_PINCTRL_H
+#define TFM_INCLUDE_NRF_PINCTRL_H
+
+/* The nrf-pinctrl.h is a copy of the header:
+ * include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h
+ * in Zephyr and it needs to be kept in sync.
+ */
+#include "nrf-pinctrl.h"
+
+/* Copied from the header soc/nordic/common/pinctrl_soc.h in Zephyr because they are
+ * used by the Driver_USART.c in TF-M.
+ */
+
+/**
+ * @brief Utility macro to obtain pin function.
+ *
+ * @param pincfg Pin configuration bit field.
+ */
+#define NRF_GET_FUN(pincfg) (((pincfg) >> NRF_FUN_POS) & NRF_FUN_MSK)
+
+/**
+ * @brief Utility macro to obtain port and pin combination.
+ *
+ * @param pincfg Pin configuration bit field.
+ */
+#define NRF_GET_PIN(pincfg) (((pincfg) >> NRF_PIN_POS) & NRF_PIN_MSK)
+
+#endif /* TFM_INCLUDE_NRF_PINCTRL_H */
+