diff --git a/README.md b/README.md
index dce22379..0817d97e 100644
--- a/README.md
+++ b/README.md
@@ -89,6 +89,7 @@ Note: support for specific languages is strictly community maintained and can br
   - [x] `typoscript`
   - [x] `usd`
   - [x] `verilog`
+  - [x] `vhdl`
   - [x] `vim`
   - [x] `vue`
   - [x] `xml`
diff --git a/queries/vhdl/context.scm b/queries/vhdl/context.scm
new file mode 100644
index 00000000..21331b0f
--- /dev/null
+++ b/queries/vhdl/context.scm
@@ -0,0 +1,54 @@
+[
+    (block_comment)
+    (architecture_definition)
+    (architecture_head)
+    (concurrent_block)
+    (configuration_declaration)
+    (component_instantiation_statement)
+    (generic_map_aspect)
+    (port_map_aspect)
+    (process_statement)
+    (process_head)
+    (sequential_block)
+    (block_configuration)
+    (block_statement)
+    (block_head)
+    (component_declaration)
+    (component_configuration)
+    (generic_clause)
+    (port_clause)
+    (entity_declaration)
+    (entity_head)
+    (entity_body)
+    (package_declaration)
+    (package_definition)
+    (function_specification)
+    (subprogram_declaration)
+    (subprogram_definition)
+    (subprogram_head)
+    (procedure_specification
+      (identifier) @context.end)
+    (sequential_block)
+    (loop_statement)
+    (if_statement_block)
+    (if_statement)
+    (elsif_statement)
+    (else_statement)
+    (case_statement)
+    (case_statement_alternative)
+    (for_generate_statement)
+    (if_generate_statement)
+    (if_generate)
+    (elsif_generate)
+    (else_generate)
+    (case_generate_statement)
+    (case_generate_alternative)
+    (type_declaration)
+] @context
+
+; A nice to have, unfortunately, treesitter-context does not support the make-range function
+; https://github.com/nvim-treesitter/nvim-treesitter-context/issues/454
+; (_
+;   (if_conditional_analysis) @_start @context.start @context.end
+;   (end_conditional_analysis) @_end
+;   (#make-range! "context" @_start @_end))
diff --git a/test/lang/test.vhd b/test/lang/test.vhd
new file mode 100644
index 00000000..c42867fa
--- /dev/null
+++ b/test/lang/test.vhd
@@ -0,0 +1,99 @@
+--+-------------------------------
+--| Block Comment
+--+-------------------------------
+
+-- (architecture_definition)
+architecture Behavioral of MyEntity is
+    -- (architecture_head)
+    signal clk: std_logic;
+begin
+    -- (concurrent_block)
+    clk_process: process(clk)
+    begin
+        clk <= not clk after 10 ns;
+        wait for 10 ns;
+    end process clk_process;
+
+    -- -- (case_statement)
+    -- case state is
+    --     when Idle => state <= Active;
+    --     when Active => state <= Waiting;
+    --     when others => state <= Idle;
+    -- end case;
+
+    -- (for_generate_statement)
+    g_GENERATE_FOR: for i in 0 to 3 generate
+        comp_inst: MyComponent
+        port map (
+            a => data(i)
+        );
+    end generate g_GENERATE_FOR;
+
+    -- (if_generate_statement)
+    g_GENERATE_IF: if clk = '1' generate
+        comp_inst: MyComponent port map (a => clk);
+    end generate g_GENERATE_IF;
+
+    U1: MyComponent
+        generic map (
+            WIDTH => 8
+        )
+        port map (
+            a => data(0)
+        );
+
+end Behavioral;
+
+-- (configuration_declaration)
+configuration Config of MyEntity is
+    for Behavioral
+    end for;
+end configuration Config;
+
+-- (process_statement)
+process (clk)
+begin
+    if rising_edge(clk) then
+        -- (sequential_block)
+        if_statement_block: if enable = '1' then
+            -- (loop_statement)
+            for i in 0 to 7 loop
+                -- (if_statement)
+                if data(i) = '1' then
+                    -- (elsif_statement)
+                elsif data(i) = '0' then
+                    -- (else_statement)
+                else
+                    data(i) <= 'X';
+                end if;
+            end loop;
+        end if;
+    end if;
+end process;
+
+-- (type_declaration)
+type State_Type is (Idle, Active, Waiting);
+-- (entity_declaration)
+entity MyEntity is
+    -- (entity_head)
+    port (
+        clk: in std_logic;
+        reset: in std_logic;
+        data: out std_logic_vector(7 downto 0)
+    );
+end MyEntity;
+
+-- (package_declaration)
+package MyPackage is
+    -- (package_definition)
+    function Add (a, b: integer) return integer;
+end MyPackage;
+
+-- (subprogram_declaration)
+function Add (a, b: integer) return integer is
+begin
+    -- (subprogram_head)
+    return a + b;
+end Add;
+
+