From 0878f9588d86ccb8127cff6b08e12009a71a1c58 Mon Sep 17 00:00:00 2001 From: "mcu_sdk.ci" Date: Mon, 22 Apr 2024 04:16:45 +0000 Subject: [PATCH] Apply release update from MCUXpresso SDK 2.15.100 release Signed-off-by: mcu_sdk.ci --- README.md | 40 +- SW-Content-Register.txt | 684 ++++++++---------- boards/evkbmimxrt1060/evkbmimxrt1060.png | Bin 28771 -> 28771 bytes components/edgefast_wifi/include/wpl.h | 14 +- components/edgefast_wifi/source/wpl_nxp.c | 304 ++++---- components/flash/mflash/lpc55s3x/mflash_drv.c | 10 +- .../mflash/lpc55s3x_flexspi/mflash_drv.c | 4 +- components/flash/mflash/lpc55xxx/mflash_drv.c | 10 +- .../fsl_adapter_flexspi_nor_flash.c | 18 + .../fsl_adapter_flexspi_nor_flash.c | 18 + .../fsl_adapter_flexspi_nor_flash.c | 18 + .../fsl_adapter_flexspi_nor_flash.c | 18 + .../fsl_adapter_flexspi_hyper_flash_config.c | 18 + .../fsl_adapter_flexspi_hyper_nor_flash.c | 18 + .../fsl_adapter_flexspi_nor_flash.c | 18 + .../fsl_adapter_flexspi_nor_flash.c | 18 + .../mem_manager/fsl_component_mem_manager.h | 4 +- .../fsl_component_mem_manager_light.c | 35 +- .../messaging/fsl_component_messaging.c | 2 +- components/osa/fsl_os_abstraction_free_rtos.c | 38 +- components/osa/fsl_os_abstraction_threadx.c | 20 +- components/pf5020/fsl_pf5020.c | 14 +- .../phy/device/phyrtl8201/fsl_phyrtl8201.c | 2 +- .../devices/MIMXRT1171/fsl_pm_device.c | 68 +- .../devices/MIMXRT1172/fsl_pm_device.c | 68 +- .../devices/MIMXRT1173/fsl_pm_device.c | 68 +- .../devices/MIMXRT1175/fsl_pm_device.c | 68 +- .../devices/MIMXRT1176/fsl_pm_device.c | 68 +- .../fsl_component_serial_manager.c | 85 ++- .../fsl_component_serial_manager.h | 45 +- .../fsl_component_serial_port_internal.h | 3 +- .../fsl_component_serial_port_usb.c | 30 +- .../wlan_txpwrlimit_cfg_murata_1XK_WW.h | 5 + .../wlan_txpwrlimit_cfg_murata_1ZM_WW.h | 5 + .../wlan_txpwrlimit_cfg_murata_2DS_WW.h | 5 + .../incl/wifi_bt_module_config.h | 5 + devices/MIMXRT1042/all_lib_device.cmake | 12 +- devices/MIMXRT1052/all_lib_device.cmake | 6 - devices/MIMXRT1062/all_lib_device.cmake | 366 +++++----- devices/MIMXRT1064/all_lib_device.cmake | 6 - devices/MIMXRT1166/all_lib_device.cmake | 6 - devices/MIMXRT1176/all_lib_device.cmake | 422 ++++++----- manifests/EVK-MIMXRT1020_manifest_v3_14.xml | 4 +- manifests/EVK-MIMXRT1060_manifest_v3_14.xml | 32 +- manifests/EVK-MIMXRT1064_manifest_v3_14.xml | 4 +- manifests/EVKB-IMXRT1050_manifest_v3_14.xml | 4 +- manifests/LPCXpresso55S06_manifest_v3_14.xml | 4 +- manifests/LPCXpresso55S16_manifest_v3_14.xml | 4 +- manifests/LPCXpresso55S28_manifest_v3_14.xml | 24 +- manifests/LPCXpresso55S36_manifest_v3_14.xml | 4 +- manifests/LPCXpresso55S69_manifest_v3_14.xml | 4 +- manifests/MIMXRT1040-EVK_manifest_v3_14.xml | 4 +- manifests/MIMXRT1060-EVKB_manifest_v3_14.xml | 32 +- manifests/MIMXRT1060-EVKC_manifest_v3_14.xml | 32 +- manifests/MIMXRT1160-EVK_manifest_v3_14.xml | 4 +- manifests/MIMXRT1170-EVKB_manifest_v3_14.xml | 46 +- manifests/MIMXRT1170-EVK_manifest_v3_14.xml | 46 +- ...re_nxp_mmcau_MIMXRT1166_manifest_v3_14.xml | 2 +- ...re_nxp_mmcau_MIMXRT1176_manifest_v3_14.xml | 2 +- middleware/mmcau/set_middleware_mmcau.cmake | 38 - utilities/debug_console/fsl_debug_console.c | 21 +- west.yml | 54 +- 62 files changed, 1591 insertions(+), 1440 deletions(-) diff --git a/README.md b/README.md index a230454ca..a38947989 100644 --- a/README.md +++ b/README.md @@ -7,9 +7,43 @@ Previously user should get MCUXpresso SDK via mcuxpresso.nxp.com or MCUXpresso I * Arm® CMSIS-CORE startup and device header files and CMSIS-DSP standard libraries * Open-source peripheral drivers that provide stateless, high-performance, easy-to-use APIs * Drivers for communication peripherals also include high-level transactional APIs for high-performance data transfers -* High-quality software: all drivers and startup code are MISRA-C: 2004 compliant and checked with Coverity® static analysis tools -* Software examples demonstrating the usage of peripheral drivers +* High-quality software: all drivers and startup code are MISRA-C: 2012 compliant and checked with Coverity® static analysis tools +**The project can work solely**, if you only want to get the fundamental support for SoC(s) or board(s), you just use the original Git way to clone and checkout the project. + +**The project is also the main repository to achieve the whole SDK delivery**, it contains the [west.yml](https://github.com/NXPmicro/mcux-sdk/blob/main/west.yml) which keeps description and revision for other projects in the overall MCUXpresso delivery. Currently available middleware sets are shown in below figure, user could click the middleware to navigate the middleware project repo. +[![MCUXSDK Graph](docs/sdk_graph.svg)](https://htmlpreview.github.io/?https://github.com/NXPmicro/mcux-sdk/blob/main/docs/sdk_graph.html) +You need to have both Git and West installed in order to get a new delivery of the whole SDK or update the existing SDK deliveries. You could follow below guide according to your scenario: +* Clone/check-out a new delivery of whole SDK + + Execute below commands to achieve the whole SDK delivery at revision ```${revision}``` and place it in a folder named ```mcuxsdk``` + ``` + west init -m https://github.com/NXPmicro/mcux-sdk --mr ${revision} mcuxsdk + cd mcuxsdk + west update + ``` + Replace ```${revision}``` with any SDK revision(branch/tag/commit SHA) you wish to achieve. This can be ```main``` if you want the latest state, or any commit SHA or tag. + +* Update existing west cloned SDK whole delivery + + Assume you have followed previous commands to clone/check-out whole SDK delivery to the west workspace mcuxsdk, then the main repository of SDK is located in mcuxsdk/core. If you would like to update/check-out to another revision, you need to first update the main repository to the expected revision, then update the west workspace: + + When you would like to update SDK full delivery in the latest branch of main repository, follow below commands: + + ``` + cd mcuxsdk/core + git fetch + git rebase + west update + ``` + + If the ```${revision}``` is different revision from that used in main repository, such as different branch, different tag or different commit SHA, you could follow below commands: + ``` + cd mcuxsdk/core + git fetch + git checkout ${revision} + west update + ``` Other features like RTOS support and middleware stacks currently are not demonstrated in this project. If you are interest in these features please go mcuxpresso.nxp.com to find full SDK support. # Releases @@ -32,4 +66,4 @@ See [Getting Start Guide](docs/Getting_Started.md) to start explore the project. Most of software in the project is open-source and licensed under BSD-3-Clause, see [COPYING_BSD-3](COPYING-BSD-3). Whole license information for the project could be found in [SW-Content-Register.txt](SW-Content-Register.txt) # Contribution -Currently we are not ready to accept contribution, you could create an issue to suggest a new idea or track a bug. Contribution will be open soon. \ No newline at end of file +Currently we are not ready to accept contribution, you could create an issue to suggest a new idea or track a bug. Contribution will be open soon. diff --git a/SW-Content-Register.txt b/SW-Content-Register.txt index 78edf31e6..d2df6c222 100644 --- a/SW-Content-Register.txt +++ b/SW-Content-Register.txt @@ -1,6 +1,6 @@ Release Name: MCUXpresso Software Development Kit (SDK) -Release Version: 2.15.0 -Package License: LA_OPT_NXP_Software_License.txt v49 September 2023- Additional Distribution License granted, license in Section 2.3 applies +Release Version: 2.15.100 +Package License: LA_OPT_NXP_Software_License v49 September 2023 - Additional Distribution License granted, license in Section 2.3 applies SDK_Peripheral_Driver Name: SDK Peripheral Driver Version: 2.x.x @@ -61,6 +61,29 @@ CMSIS Name: CMSIS https://github.com/ARM-software/CMSIS_5/releases/t ag/5.8.0 +wifi Name: NXP Wi-Fi driver + Version: 1.3.46 + Outgoing License: BSD-3-Clause + License File: COPYING-BSD-3 + Format: source code, header files, firmware + binaries + Description: NXP Wi-Fi driver and networking + utilities + Location: middleware/wifi_nxp + Origin: NXP (BSD-3-Clause) + +wpa_supplicant Name: wpa_supplicant-rtos + Version: 2.11.0 + Outgoing License: BSD-3-Clause + License File: + middleware/wireless/wpa_supplicant-rtos/wpa_suppli + cant/README + Format: source code + Description: WPA Supplicant & HOSTAPD + Location: middleware/wireless/wpa_supplicant-rtos + Origin: https://w1.fi/wpa_supplicant/ and + https://w1.fi/hostapd/ + fatfs Name: FatFs Version: R0.15 Outgoing License: FatFs License @@ -86,190 +109,6 @@ freertos-kernel Name: FreeRTOS kernel Origin: Amazon (MIT) Url: https://github.com/FreeRTOS/FreeRTOS-Kernel -multicore_mcmgr Name: MCMGR - Version: 4.1.4 - Outgoing License: BSD-3-Clause - License File: COPYING-BSD-3 - Format: source code - Description: Multicore manager - Location: middleware/multicore/mcmgr - Origin: NXP (BSD-3-Clause) - -multicore Name: Multicore SDK - Version: 2.15.0 - Outgoing License: BSD-3-Clause - License File: COPYING-BSD-3 - Format: source code - Description: NXP Multicore Software Development - Kit. - Location: middleware/multicore - Origin: NXP (BSD-3-Clause) - -multicore_rpmsg_lite Name: RPMsg-Lite - Version: 5.1.0 - Outgoing License: BSD-3-Clause - License File: COPYING-BSD-3 - Format: source code - Description: Open Asymmetric Multi Processing - (OpenAMP) framework project - Location: middleware/multicore/rpmsg_lite - Origin: Mentor Graphics Corporation & community - contributors - Url: https://github.com/NXPmicro/rpmsg-lite - -multicore_erpc Name: eRPC - Version: 1.12.0 - Outgoing License: BSD-3-Clause - License File: middleware/multicore/erpc/LICENSE - Format: source code - Description: Embedded Remote Procedure Call - Location: middleware/multicore/erpc - Origin: NXP & community contributors - Url: https://github.com/EmbeddedRPC/erpc - -multicore_erpc_the_bus_piraName: The Bus Pirate -te Version: NA - Outgoing License: Open Source - CC0 (Public Domain - Dedication License) - License File: - http://code.google.com/p/the-bus-pirate/ - Format: source code - Description: OS independent serial interface - Location: - middleware/multicore/erpc/erpc_c/port/erpc_serial. - h, - middleware/multicore/erpc/erpc_c/port/erpc_serial. - cpp - Origin: Community - Url: http://code.google.com/p/the-bus-pirate/ - -multicore_erpc_cpp_templateName: CPP Template - Version: NA - Outgoing License: Open Source - MIT - License File: - middleware/multicore/erpc/erpcgen/src/cpptemplate/ - LICENSE.txt - Format: source code - Description: CPP Template - Location: - middleware/multicore/erpc/erpcgen/src/cpptemplate - Origin: Ryan Ginstrom & Martinho Fernandes - -multicore_erpc_cpp_option_pName: C++ option-parser -arser Version: NA - Outgoing License: Brad Appleton's license - License File: - http://www.bradapp.com/ftp/src/libs/C++/Options.ta - r.gz , see README file - Format: Plain Text - Description: C++ option-parser - Location: - middleware/multicore/erpc/erpcgen/src/options.cpp - Origin: Brad Appleton bradapp@enteract.com - Url: - http://www.bradapp.com/ftp/src/libs/C++/Options.ht - ml - -sdmmc Name: SD MMC SDIO Card middleware - Version: 2.2.7 - Outgoing License: BSD-3-Clause - License File: COPYING-BSD-3 - Format: source code - Description: A software component support SD card, - eMMC card, SDIO card. - Location: middleware/sdmmc - Origin: NXP (BSD-3-Clause) - -sdmmc_sdspi Name: SD Card middleware - Version: 2.1.4 - Outgoing License: BSD-3-Clause - License File: COPYING-BSD-3 - Format: source code - Description: A software component support access - SD card through spi. - Location: middleware/sdmmc/sdspi - Origin: NXP (BSD-3-Clause) - -mbedtls Name: Mbed TLS - Version: 2.28.5 - Outgoing License: Apache-2.0 - License File: middleware/mbedtls/LICENSE - Format: source code - Description: Cryptographic and SSL/TLS Library - Location: middleware/mbedtls - Origin: ARM(Apache-2.0) - - https://github.com/Mbed-TLS/mbedtls/releases/tag/v - 2.28.3 - -usb Name: USB - Version: 2.9.1 - Outgoing License: BSD-3-Clause - License File: COPYING-BSD-3 - Format: source code - Description: NXP USB stack. This is a version of - the USB stack that has been integrated with the - MCUXpresso SDK. - Location: middleware/usb - Origin: NXP (BSD-3-Clause) - -osa Name: OSA - Version: 1.0.0 - Outgoing License: BSD-3-Clause - License File: COPYING-BSD-3 - Format: source code - Description: NXP USB stack. This is a version of - the USB stack that has been integrated with the - MCUXpresso SDK. - Origin: NXP (BSD-3-Clause) - Location: components/osa - -SDK_Examples Name: SDK examples - Version: NA - Outgoing License: BSD-3-Clause - License File: COPYING-BSD-3 - Format: source code, binary, project files, linker - files - Description: SDK out of box examples to show how - to use peripheral drivers and integrate - middleware. - Location: boards// - Origin: NXP (BSD-3-Clause) - -naturedsp_hifi4 Name: naturedsp - Version: 4.1.1 - Outgoing License: LA_OPT_NXP_Software_License.txt - v49 September 2023- No distribution permitted, - license in Section 2.2 applies. - License File: LA_OPT_NXP_Software_License.txt - Format: source code - Description: Digital Signal Processing for Xtensa - HiFi Audio Engines - Location: middleware/dsp/naturedsp/hifi4 - Origin: Cadence Design Systems (Proprietary) - -wifi Name: NXP Wi-Fi driver - Version: 1.3.46 - Outgoing License: BSD-3-Clause - License File: COPYING-BSD-3 - Format: source code, header files, firmware - binaries - Description: NXP Wi-Fi driver and networking - utilities - Location: middleware/wifi_nxp - Origin: NXP (BSD-3-Clause) - -wpa_supplicant Name: wpa_supplicant-rtos - Version: 2.11.0 - Outgoing License: BSD-3-Clause - License File: - middleware/wireless/wpa_supplicant-rtos/wpa_suppli - cant/README - Format: source code - Description: WPA Supplicant & HOSTAPD - Location: middleware/wireless/wpa_supplicant-rtos - Origin: https://w1.fi/wpa_supplicant/ and - https://w1.fi/hostapd/ - littlefs Name: LittleFS Version: 2.8.0 Outgoing License: BSD-3-Clause @@ -295,6 +134,23 @@ lwip Name: lwIP TCP/IP Stack Computer Science (BSD-3-Clause) - http://savannah.nongnu.org/projects/lwip +maestro_framework Name: Maestro Audio Framework + Version: 1.7.0 + Outgoing License: LA_OPT_NXP_Software_License v49 + September 2023 - Additional distribution license + granted, license in Section 2.3 applies + License File: LA_OPT_NXP_Software_License.txt + Format: Source + Description: Maestro MCU Audio Framework + Location: middleware/maestro + Origin: NXP (Proprietary) Flac (BSD 3-clause) Ogg + (BSD 3-clause) Opus (BSD 3-clause) Opusfile (BSD + 3-clause) + Url: https://github.com/xiph/flac + https://github.com/xiph/ogg + https://github.com/xiph/opus + https://github.com/xiph/opusfile + mcuboot Name: MCUBoot Version: 1.10.0 Outgoing License: Apache-2.0 @@ -307,42 +163,43 @@ mcuboot Name: MCUBoot Origin: MCUBoot https://www.mcuboot.com/ Url: https://github.com/mcu-tools/mcuboot -vit Name: VIT_v4.8.1 - Version: 4.8.1 - Outgoing License: LA_OPT_NXP_Software_License.txt - v49 September 2023- Additional Distribution - License granted, license in Section 2.3 applies - License File: LA_OPT_NXP_Software_License.txt - Format: Precompiled libraries, header files, - example application - Description: Voice Intelligent Technology library - Location: middleware/vit - Origin: NXP (Proprietary) +mbedtls Name: Mbed TLS + Version: 2.28.5 + Outgoing License: Apache-2.0 + License File: middleware/mbedtls/LICENSE + Format: source code + Description: Cryptographic and SSL/TLS Library + Location: middleware/mbedtls + Origin: ARM(Apache-2.0) - + https://github.com/Mbed-TLS/mbedtls/releases/tag/v + 2.28.3 -voice_seeker_hifi4 Name: VoiceSeeker (no AEC) - Version: 0.6.8 - Outgoing License: LA_OPT_NXP_Software_License.txt - v49 September 2023- Additional Distribution - License granted, license in Section 2.3 applies - License File: LA_OPT_NXP_Software_License.txt - Format: Precompiled libraries, header files, - example application - Description: VoiceSeeker is a multi-microphone - voice control audio front-end signal processing - solution. Acoustic Echo Cancellation (AEC) is not - enabled in this free version. - Location: middleware/voice_seeker/RT685_HiFi4 - Origin: NXP (Proprietary) Cadence Design Systems - (Proprietary) - Url: - https://www.nxp.com/design/software/embedded-softw - are/voiceseeker-audio-front-end:VOICESEEKER +sdmmc Name: SD MMC SDIO Card middleware + Version: 2.2.7 + Outgoing License: BSD-3-Clause + License File: COPYING-BSD-3 + Format: source code + Description: A software component support SD card, + eMMC card, SDIO card. + Location: middleware/sdmmc + Origin: NXP (BSD-3-Clause) + +usb Name: USB + Version: 2.9.1 + Outgoing License: BSD-3-Clause + License File: COPYING-BSD-3 + Format: source code + Description: NXP USB stack. This is a version of + the USB stack that has been integrated with the + MCUXpresso SDK. + Location: middleware/usb + Origin: NXP (BSD-3-Clause) voice_seeker_cm7 Name: VoiceSeeker (no AEC) Version: 0.6.8 - Outgoing License: LA_OPT_NXP_Software_License.txt - v49 September 2023- Additional Distribution - License granted, license in Section 2.3 applies + Outgoing License: LA_OPT_NXP_Software_License v49 + September 2023 - No distribution permitted, + license in Section 2.2 applies. License File: LA_OPT_NXP_Software_License.txt Format: Precompiled libraries, header files, example application @@ -357,43 +214,28 @@ voice_seeker_cm7 Name: VoiceSeeker (no AEC) are/voiceseeker-audio-front-end:VOICESEEKER https://github.com/ARM-software/CMSIS_5 -voice_seeker_cm4 Name: VoiceSeeker (no AEC) - Version: 0.6.8 - Outgoing License: LA_OPT_NXP_Software_License.txt - v49 September 2023- Additional Distribution - License granted, license in Section 2.3 applies +vit Name: VIT_v4.8.1 + Version: 4.8.1 + Outgoing License: LA_OPT_NXP_Software_License v49 + September 2023 - Additional distribution license + granted, license in Section 2.3 applies License File: LA_OPT_NXP_Software_License.txt Format: Precompiled libraries, header files, example application - Description: VoiceSeeker is a multi-microphone - voice control audio front-end signal processing - solution. Acoustic Echo Cancellation (AEC) is not - enabled in this free version. - Location: middleware/voice_seeker/ARM_CortexM4 - Origin: NXP (Proprietary) ARM (Apache-2.0) - Url: - https://www.nxp.com/design/software/embedded-softw - are/voiceseeker-audio-front-end:VOICESEEKER - https://github.com/ARM-software/CMSIS_5 + Description: Voice Intelligent Technology library + Location: middleware/vit + Origin: NXP (Proprietary) -voice_seeker_fusionf1 Name: VoiceSeeker (no AEC) - Version: 0.6.8 - Outgoing License: LA_OPT_NXP_Software_License.txt - v49 September 2023- Additional Distribution - License granted, license in Section 2.3 applies - License File: LA_OPT_NXP_Software_License.txt - Format: Precompiled libraries, header files, - example application - Description: VoiceSeeker is a multi-microphone - voice control audio front-end signal processing - solution. Acoustic Echo Cancellation (AEC) is not - enabled in this free version. - Location: middleware/voice_seeker/RT595_FusionF1 - Origin: NXP (Proprietary) Cadence Design Systems - (Proprietary) - Url: - https://www.nxp.com/design/software/embedded-softw - are/voiceseeker-audio-front-end:VOICESEEKER +osa Name: OSA + Version: 1.0.0 + Outgoing License: BSD-3-Clause + License File: COPYING-BSD-3 + Format: source code + Description: NXP USB stack. This is a version of + the USB stack that has been integrated with the + MCUXpresso SDK. + Origin: NXP (BSD-3-Clause) + Location: components/osa wifi_tx_pwr_limits Name: Wi-Fi module Tx power limits Version: 1.0.0 @@ -504,23 +346,6 @@ msis_nn Version: 23.08 (commit dc64e48) Origin: ARM Url: https://github.com/ARM-software/CMSIS-NN -eiq_tensorflow_lite_micro_xName: Cadence HiFi4 Neural Network (NN) Library -tensa_nn Version: 2.9.0 - Outgoing License: LA_OPT_NXP_Software_License.txt - v49 September 2023- Additional Distribution - License granted, license in Section 2.3 applies - License File: LA_OPT_NXP_Software_License.txt - Format: source code - Description: A neural network kernels library for - Xtensa cores from Cadence - Location: - middleware/eiq/tensorflow-lite/third_party/xa_nnli - b_hifi4, - middleware/eiq/tensorflow-lite/tensorflow/lite/mic - ro/kernels/xtensa_hifi - Origin: Cadence Design Systems, Inc. (proprietary) - Url: https://github.com/foss-xtensa/nnlib-hifi4 - Glow_Utils Name: Glow Utils Version: 1.0.0 Outgoing License: BSD-3-Clause @@ -533,8 +358,8 @@ Glow_Utils Name: Glow Utils DeepviewRT_Library Name: DeepviewRT Library Version: 2.4.20 - Outgoing License: LA_OPT_NXP_Software_License.txt - v49 September 2023- No distribution permitted, + Outgoing License: LA_OPT_NXP_Software_License v49 + September 2023 - No distribution permitted, license in Section 2.2 applies. License File: LA_OPT_NXP_Software_License.txt Format: machine learning library and header file @@ -546,9 +371,9 @@ DeepviewRT_Library Name: DeepviewRT Library DeepviewRT_Sample Name: DeepviewRT Sample Version: 1.0.0 - Outgoing License: LA_OPT_NXP_Software_License.txt - v49 September 2023- Additional Distribution - License granted, license in Section 2.3 applies + Outgoing License: LA_OPT_NXP_Software_License v49 + September 2023 - Additional distribution license + granted, license in Section 2.3 applies License File: LA_OPT_NXP_Software_License.txt Format: source code Description: Utilities and project examples for @@ -559,143 +384,223 @@ DeepviewRT_Sample Name: DeepviewRT Sample mpp Name: Multimedia Processing Pipelines (MPP) Version: 2.1.0 - Outgoing License: LA_OPT_NXP_Software_License.txt - v49 September 2023- Additional Distribution - License granted, license in Section 2.3 applies + Outgoing License: LA_OPT_NXP_Software_License v49 + September 2023 - Additional distribution license + granted, license in Section 2.3 applies License File: LA_OPT_NXP_Software_License.txt Format: source code, header files Description: Library to build vision pipelines Location: middleware/eiq/mpp Origin: NXP -edgefast_bluetooth Name: EdgeFast Protocol Abstraction Layer - Version: 1.5.0 - Outgoing License: BSD-3-Clause - License File: COPYING-BSD-3 - Format: source code, header files - Description: EdgeFast Bluetooth PAL - Location: middleware/edgefast_bluetooth - Origin: NXP (BSD-3-Clause) Zephyr BT/BLE Host - stack (Apache-2.0) - - https://github.com/zephyrproject-rtos/zephyr/tree/ - v2.6-branch/subsys/bluetooth - -CRC32-GS Name: CRC32 code - Version: NA - Outgoing License: Public domain - Format: source code - Description: CRC32 code written by Gary S. Brown - Location: - components/codec/tfa9xxx/vas_tfa_drv/tfa_container - _crc32.c - Origin: Gary S. Brown - -mmcau Name: mmCAU S/W Library - Version: 2.0.4 - Outgoing License: BSD-3-Clause - License File: middleware/mmcau/LICENSE - Format: source code - Description: S/W library that works with the - memory-mapped cryptographic acceleration unit - present on some MCUXpresso SoCs - Location: middleware/mmcau - Origin: NXP (BSD-3-Clause) - azure_rtos_threadx Name: Azure RTOS ThreadX - Version: 6.2.0 - Outgoing License: LA_OPT_NXP_Software_License.txt - v49 September 2023- Additional Distribution - License granted, license in Section 2.3 applies + Version: 6.4.1 + Outgoing License: LA_OPT_NXP_Software_License v49 + September 2023 - Additional distribution license + granted, license in Section 2.3 applies License File: LA_OPT_NXP_Software_License.txt Format: source code Description: RTOS kernel for microcontrollers Location: rtos/azure-rtos/threadx - Origin: Microsoft - Url: - https://azure.microsoft.com/en-us/services/rtos/ + Origin: Eclipse Foundation + Url: https://threadx.io/ azure_rtos_filex Name: Azure RTOS FileX - Version: 6.2.0 - Outgoing License: LA_OPT_NXP_Software_License.txt - v49 September 2023- Additional Distribution - License granted, license in Section 2.3 applies + Version: 6.4.1 + Outgoing License: LA_OPT_NXP_Software_License v49 + September 2023 - Additional distribution license + granted, license in Section 2.3 applies License File: LA_OPT_NXP_Software_License.txt Format: source code Description: file system Location: rtos/azure-rtos/filex - Origin: Microsoft - Url: - https://azure.microsoft.com/en-us/services/rtos/ + Origin: Eclipse Foundation + Url: https://threadx.io/ azure_rtos_levelx Name: Azure RTOS LevelX - Version: 6.2.0 - Outgoing License: LA_OPT_NXP_Software_License.txt - v49 September 2023- Additional Distribution - License granted, license in Section 2.3 applies + Version: 6.4.1 + Outgoing License: LA_OPT_NXP_Software_License v49 + September 2023 - Additional distribution license + granted, license in Section 2.3 applies License File: LA_OPT_NXP_Software_License.txt Format: source code Description: NAND and NOR flash wear leveling facilities for embedded applications Location: rtos/azure-rtos/levelx - Origin: Microsoft - Url: - https://azure.microsoft.com/en-us/services/rtos/ + Origin: Eclipse Foundation + Url: https://threadx.io/ azure_rtos_netxduo Name: Azure RTOS NetX Duo - Version: 6.2.0 - Outgoing License: LA_OPT_NXP_Software_License.txt - v49 September 2023- Additional Distribution - License granted, license in Section 2.3 applies + Version: 6.4.1 + Outgoing License: LA_OPT_NXP_Software_License v49 + September 2023 - Additional distribution license + granted, license in Section 2.3 applies License File: LA_OPT_NXP_Software_License.txt Format: source code Description: advanced, industrial-grade TCP/IP network stack Location: rtos/azure-rtos/netxduo - Origin: Microsoft - Url: - https://azure.microsoft.com/en-us/services/rtos/ + Origin: Eclipse Foundation + Url: https://threadx.io/ azure_rtos_guix Name: Azure RTOS GUIX - Version: 6.2.0 - Outgoing License: LA_OPT_NXP_Software_License.txt - v49 September 2023- Additional Distribution - License granted, license in Section 2.3 applies + Version: 6.4.1 + Outgoing License: LA_OPT_NXP_Software_License v49 + September 2023 - Additional distribution license + granted, license in Section 2.3 applies License File: LA_OPT_NXP_Software_License.txt Format: source code Description: advanced, industrial-grade GUI solution Location: rtos/azure-rtos/guix - Origin: Microsoft - Url: - https://azure.microsoft.com/en-us/services/rtos/ + Origin: Eclipse Foundation + Url: https://threadx.io/ azure_rtos_usbx Name: Azure RTOS USBX - Version: 6.2.0 - Outgoing License: LA_OPT_NXP_Software_License.txt - v49 September 2023- Additional Distribution - License granted, license in Section 2.3 applies + Version: 6.4.1 + Outgoing License: LA_OPT_NXP_Software_License v49 + September 2023 - Additional distribution license + granted, license in Section 2.3 applies License File: LA_OPT_NXP_Software_License.txt Format: source code Description: A high-performance USB host and device embedded stack Location: rtos/azure-rtos/usbx - Origin: Microsoft - Url: - https://azure.microsoft.com/en-us/services/rtos/ + Origin: Eclipse Foundation + Url: https://threadx.io/ segger_rtt Name: SEGGER Real Timer Transfer Version: 7.22 - Outgoing License: LA_OPT_NXP_Software_License.txt - v49 September 2023- Additional Distribution - License granted, license in Section 2.3 applies + Outgoing License: LA_OPT_NXP_Software_License v49 + September 2023 - Additional distribution license + granted, license in Section 2.3 applies License File: LA_OPT_NXP_Software_License.txt Format: source code Description: SEGGER Real Timer Transfer Location: components/rtt Origin: SEGGER Microcontroller (proprietary) +SDK_Examples Name: SDK examples + Version: NA + Outgoing License: BSD-3-Clause + License File: COPYING-BSD-3 + Format: source code, binary, project files, linker + files + Description: SDK out of box examples to show how + to use peripheral drivers and integrate + middleware. + Location: boards// + Origin: NXP (BSD-3-Clause) + +mmcau Name: mmCAU S/W Library + Version: 2.0.4 + Outgoing License: BSD-3-Clause + License File: middleware/mmcau/LICENSE + Format: source code + Description: S/W library that works with the + memory-mapped cryptographic acceleration unit + present on some MCUXpresso SoCs + Location: middleware/mmcau + Origin: NXP (BSD-3-Clause) + +multicore_mcmgr Name: MCMGR + Version: 4.1.4 + Outgoing License: BSD-3-Clause + License File: COPYING-BSD-3 + Format: source code + Description: Multicore manager + Location: middleware/multicore/mcmgr + Origin: NXP (BSD-3-Clause) + +multicore Name: Multicore SDK + Version: 2.15.0 + Outgoing License: BSD-3-Clause + License File: COPYING-BSD-3 + Format: source code + Description: NXP Multicore Software Development + Kit. + Location: middleware/multicore + Origin: NXP (BSD-3-Clause) + +multicore_rpmsg_lite Name: RPMsg-Lite + Version: 5.1.0 + Outgoing License: BSD-3-Clause + License File: COPYING-BSD-3 + Format: source code + Description: Open Asymmetric Multi Processing + (OpenAMP) framework project + Location: middleware/multicore/rpmsg_lite + Origin: Mentor Graphics Corporation & community + contributors + Url: https://github.com/NXPmicro/rpmsg-lite + +multicore_erpc Name: eRPC + Version: 1.12.0 + Outgoing License: BSD-3-Clause + License File: middleware/multicore/erpc/LICENSE + Format: source code + Description: Embedded Remote Procedure Call + Location: middleware/multicore/erpc + Origin: NXP & community contributors + Url: https://github.com/EmbeddedRPC/erpc + +multicore_erpc_the_bus_piraName: The Bus Pirate +te Version: NA + Outgoing License: Open Source - CC0 (Public Domain + Dedication License) + License File: + http://code.google.com/p/the-bus-pirate/ + Format: source code + Description: OS independent serial interface + Location: + middleware/multicore/erpc/erpc_c/port/erpc_serial. + h, + middleware/multicore/erpc/erpc_c/port/erpc_serial. + cpp + Origin: Community + Url: http://code.google.com/p/the-bus-pirate/ + +multicore_erpc_cpp_templateName: CPP Template + Version: NA + Outgoing License: Open Source - MIT + License File: + middleware/multicore/erpc/erpcgen/src/cpptemplate/ + LICENSE.txt + Format: source code + Description: CPP Template + Location: + middleware/multicore/erpc/erpcgen/src/cpptemplate + Origin: Ryan Ginstrom & Martinho Fernandes + +multicore_erpc_cpp_option_pName: C++ option-parser +arser Version: NA + Outgoing License: Brad Appleton's license + License File: + http://www.bradapp.com/ftp/src/libs/C++/Options.ta + r.gz , see README file + Format: Plain Text + Description: C++ option-parser + Location: + middleware/multicore/erpc/erpcgen/src/options.cpp + Origin: Brad Appleton bradapp@enteract.com + Url: + http://www.bradapp.com/ftp/src/libs/C++/Options.ht + ml + +edgefast_bluetooth Name: EdgeFast Protocol Abstraction Layer + Version: 1.5.0 + Outgoing License: BSD-3-Clause + License File: COPYING-BSD-3 + Format: source code, header files + Description: EdgeFast Bluetooth PAL + Location: middleware/edgefast_bluetooth + Origin: NXP (BSD-3-Clause) Zephyr BT/BLE Host + stack (Apache-2.0) - + https://github.com/zephyrproject-rtos/zephyr/tree/ + v2.6-branch/subsys/bluetooth + FWK Name: Connectivity Framework - Version: 6.2.0 + Version: 6.2.1 Outgoing License: BSD-3-Clause License File: COPYING-BSD-3 Format: source code & header files @@ -705,10 +610,10 @@ FWK Name: Connectivity Framework Origin: NXP (BSD-3-Clause) SecLib Name: Connectivity SecLib - Version: 6.2.0 - Outgoing License: LA_OPT_NXP_Software_License.txt - v49 September 2023- Additional Distribution - License granted, license in Section 2.3 applies + Version: 6.2.1 + Outgoing License: LA_OPT_NXP_Software_License v49 + September 2023 - Additional distribution license + granted, license in Section 2.3 applies License File: LA_OPT_NXP_Software_License.txt Format: Binary libraries Description: Connectivity Security Library @@ -717,50 +622,27 @@ SecLib Name: Connectivity SecLib a Origin: NXP -maestro_framework Name: Maestro Audio Framework - Version: 1.7.0 - Outgoing License: LA_OPT_NXP_Software_License.txt - v49 September 2023- Additional Distribution - License granted, license in Section 2.3 applies - License File: LA_OPT_NXP_Software_License.txt - Format: Source - Description: Maestro MCU Audio Framework - Location: middleware/maestro - Origin: NXP (Proprietary) Flac (BSD 3-clause) Ogg - (BSD 3-clause) Opus (BSD 3-clause) Opusfile (BSD - 3-clause) - Url: https://github.com/xiph/flac - https://github.com/xiph/ogg - https://github.com/xiph/opus - https://github.com/xiph/opusfile +NVS Name: Connectivity settings + Version: 6.2.1 + Outgoing License: Apache-2.0 + License File: + middleware/wireless/framework/NVS/LICENSE + Format: source code & header files + Description: Connectivity NVS module - Zephyr NVS + implementation over OSA + Location: middleware/wireless/framework/NVS + Origin: NXP and Zephyr (Apache-2.0) -naturedsp_fusionf1 Name: naturedsp - Version: 1.2.0 - Outgoing License: LA_OPT_NXP_Software_License.txt - v49 September 2023- No distribution permitted, - license in Section 2.2 applies. - License File: LA_OPT_NXP_Software_License.txt - Format: source code, precompiled library - Description: Digital Signal Processing for Xtensa - Fusion Audio Engines - Location: middleware/dsp/naturedsp/fusionf1 - Origin: Cadence Design Systems (Proprietary) - -segger_sysview Name: Segger SystemView Demo - Version: 3.30 - Outgoing License: BSD-1-Clause +settings Name: Connectivity settings + Version: 6.2.1 + Outgoing License: Apache-2.0 License File: - boards//freertos_examples/visualization/fre - ertos_segger_sysview/LICENSE - Format: source code - Description: Segger SystemView demo - Location: - boards//freertos_examples/visualization/fre - ertos_segger_sysview - Origin: Segger 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xEventGroupSetBits(s_wplSyncEvent, EVENT_BIT(reason)); + (void)xEventGroupSetBits(s_wplSyncEvent, EVENT_BIT((uint32_t)reason)); } switch (reason) @@ -219,9 +219,9 @@ wpl_ret_t WPL_Start(linkLostCb_t callbackFunction) if (status == WPLRET_SUCCESS) { - xEventGroupClearBits(s_wplSyncEvent, WPL_SYNC_INIT_GROUP); + (void)xEventGroupClearBits(s_wplSyncEvent, WPL_SYNC_INIT_GROUP); - ret = wlan_start(wlan_event_callback); + ret = wlan_start(&wlan_event_callback); if (ret != WM_SUCCESS) { status = WPLRET_FAIL; @@ -231,12 +231,12 @@ wpl_ret_t WPL_Start(linkLostCb_t callbackFunction) if (status == WPLRET_SUCCESS) { syncBit = xEventGroupWaitBits(s_wplSyncEvent, WPL_SYNC_INIT_GROUP, pdTRUE, pdFALSE, WPL_SYNC_TIMEOUT_MS); - if (syncBit & EVENT_BIT(WLAN_REASON_INITIALIZED)) + if ((syncBit & EVENT_BIT(WLAN_REASON_INITIALIZED)) != 0U) { s_linkLostCb = callbackFunction; status = WPLRET_SUCCESS; } - else if (syncBit & EVENT_BIT(WLAN_REASON_INITIALIZATION_FAILED)) + else if ((syncBit & EVENT_BIT(WLAN_REASON_INITIALIZATION_FAILED)) != 0U) { status = WPLRET_FAIL; } @@ -281,40 +281,41 @@ wpl_ret_t WPL_Stop(void) return status; } -wpl_ret_t WPL_Start_AP(char *ssid, char *password, int chan) +wpl_ret_t WPL_Start_AP(const char *ssid, const char *password, int chan) { wpl_ret_t status = WPLRET_SUCCESS; int ret; enum wlan_security_type security = WLAN_SECURITY_NONE; EventBits_t syncBit; struct wlan_network uap_network; + size_t ssid_len = strlen(ssid); + size_t password_len = strlen(password); if ((s_wplState != WPL_STARTED) || (s_wplUapActivated != false)) { status = WPLRET_NOT_READY; } - if (status == WPLRET_SUCCESS) + if ((ssid_len == 0U) || (ssid_len > IEEEtypes_SSID_SIZE)) { - if ((strlen(ssid) == 0) || (strlen(ssid) > IEEEtypes_SSID_SIZE)) - { - status = WPLRET_BAD_PARAM; - } + status = WPLRET_BAD_PARAM; + } + + if (((0U < password_len) && (password_len < WPL_WIFI_PASSWORD_MIN_LEN)) || + (password_len > WPL_WIFI_PASSWORD_LENGTH)) + { + status = WPLRET_BAD_PARAM; } if (status == WPLRET_SUCCESS) { - if (strlen(password) == 0) + if (password_len == 0U) { security = WLAN_SECURITY_NONE; } - else if ((strlen(password) >= WPL_WIFI_PASSWORD_MIN_LEN) && (strlen(password) <= WPL_WIFI_PASSWORD_LENGTH)) - { - security = WLAN_SECURITY_WPA2; - } else { - status = WPLRET_BAD_PARAM; + security = WLAN_SECURITY_WPA2; } } @@ -322,13 +323,13 @@ wpl_ret_t WPL_Start_AP(char *ssid, char *password, int chan) { wlan_initialize_uap_network(&uap_network); - memcpy(uap_network.ssid, ssid, strlen(ssid)); + (void)memcpy(uap_network.ssid, ssid, ssid_len); uap_network.ip.ipv4.address = ipaddr_addr(WPL_WIFI_AP_IP_ADDR); uap_network.ip.ipv4.gw = ipaddr_addr(WPL_WIFI_AP_IP_ADDR); - uap_network.channel = chan; + uap_network.channel = (unsigned int)chan; uap_network.security.type = security; - uap_network.security.psk_len = strlen(password); - strncpy(uap_network.security.psk, password, strlen(password)); + uap_network.security.psk_len = (uint8_t)password_len; + (void)strncpy(uap_network.security.psk, password, password_len); } if (status == WPLRET_SUCCESS) @@ -342,7 +343,7 @@ wpl_ret_t WPL_Start_AP(char *ssid, char *password, int chan) if (status == WPLRET_SUCCESS) { - xEventGroupClearBits(s_wplSyncEvent, WPL_SYNC_UAP_START_GROUP); + (void)xEventGroupClearBits(s_wplSyncEvent, WPL_SYNC_UAP_START_GROUP); ret = wlan_start_network(uap_network.name); if (ret != WM_SUCCESS) @@ -353,11 +354,11 @@ wpl_ret_t WPL_Start_AP(char *ssid, char *password, int chan) { syncBit = xEventGroupWaitBits(s_wplSyncEvent, WPL_SYNC_UAP_START_GROUP, pdTRUE, pdFALSE, WPL_SYNC_TIMEOUT_MS); - if (syncBit & EVENT_BIT(WLAN_REASON_UAP_SUCCESS)) + if ((syncBit & EVENT_BIT(WLAN_REASON_UAP_SUCCESS)) != 0U) { status = WPLRET_SUCCESS; } - else if (syncBit & EVENT_BIT(WLAN_REASON_UAP_START_FAILED)) + else if ((syncBit & EVENT_BIT(WLAN_REASON_UAP_START_FAILED)) != 0U) { status = WPLRET_FAIL; } @@ -407,7 +408,7 @@ wpl_ret_t WPL_Stop_AP(void) { dhcp_server_stop(); - xEventGroupClearBits(s_wplSyncEvent, WPL_SYNC_UAP_START_GROUP); + (void)xEventGroupClearBits(s_wplSyncEvent, WPL_SYNC_UAP_START_GROUP); ret = wlan_stop_network(UAP_NETWORK_NAME); if (ret != WM_SUCCESS) @@ -418,11 +419,11 @@ wpl_ret_t WPL_Stop_AP(void) { syncBit = xEventGroupWaitBits(s_wplSyncEvent, WPL_SYNC_UAP_STOP_GROUP, pdTRUE, pdFALSE, WPL_SYNC_TIMEOUT_MS); - if (syncBit & EVENT_BIT(WLAN_REASON_UAP_STOPPED)) + if ((syncBit & EVENT_BIT(WLAN_REASON_UAP_STOPPED)) != 0U) { status = WPLRET_SUCCESS; } - else if (syncBit & EVENT_BIT(WLAN_REASON_UAP_STOP_FAILED)) + else if ((syncBit & EVENT_BIT(WLAN_REASON_UAP_STOP_FAILED)) != 0U) { status = WPLRET_FAIL; } @@ -457,87 +458,89 @@ static int WLP_process_results(unsigned int count) uint32_t ssids_json_len = count * MAX_JSON_NETWORK_RECORD_LENGTH; /* Add length of "{"networks":[]}" */ - ssids_json_len += 15; + ssids_json_len += 15U; ssids_json = pvPortMalloc(ssids_json_len); if (ssids_json == NULL) { PRINTF("[!] Memory allocation failed\r\n"); - xEventGroupSetBits(s_wplSyncEvent, EVENT_BIT(EVENT_SCAN_DONE)); + (void)xEventGroupSetBits(s_wplSyncEvent, EVENT_BIT(EVENT_SCAN_DONE)); return WM_FAIL; } /* Start building JSON */ - strcpy(ssids_json, "{\"networks\":["); + (void)strcpy(ssids_json, "{\"networks\":["); uint32_t ssids_json_idx = strlen(ssids_json); - for (int i = 0; i < count; i++) + for (uint32_t i = 0; i < count; i++) { - wlan_get_scan_result(i, &scan_result); - - PRINTF("%s\r\n", scan_result.ssid); - PRINTF(" BSSID : %02X:%02X:%02X:%02X:%02X:%02X\r\n", (unsigned int)scan_result.bssid[0], - (unsigned int)scan_result.bssid[1], (unsigned int)scan_result.bssid[2], - (unsigned int)scan_result.bssid[3], (unsigned int)scan_result.bssid[4], - (unsigned int)scan_result.bssid[5]); - PRINTF(" RSSI : %ddBm\r\n", -(int)scan_result.rssi); - PRINTF(" Channel : %d\r\n", (int)scan_result.channel); + ret = wlan_get_scan_result(i, &scan_result); + if (ret == WM_SUCCESS) + { + PRINTF("%s\r\n", scan_result.ssid); + PRINTF(" BSSID : %02X:%02X:%02X:%02X:%02X:%02X\r\n", (unsigned int)scan_result.bssid[0], + (unsigned int)scan_result.bssid[1], (unsigned int)scan_result.bssid[2], + (unsigned int)scan_result.bssid[3], (unsigned int)scan_result.bssid[4], + (unsigned int)scan_result.bssid[5]); + PRINTF(" RSSI : %ddBm\r\n", -(int)scan_result.rssi); + PRINTF(" Channel : %d\r\n", (int)scan_result.channel); - char security[40]; - security[0] = '\0'; + char security[40]; + security[0] = '\0'; - if (scan_result.wpa2_entp) - { - strcat(security, "WPA2_ENTP "); - } - if (scan_result.wep) - { - strcat(security, "WEP "); - } - if (scan_result.wpa) - { - strcat(security, "WPA "); - } - if (scan_result.wpa2) - { - strcat(security, "WPA2 "); - } - if (scan_result.wpa3_sae) - { - strcat(security, "WPA3_SAE "); - } + if (scan_result.wpa2_entp == 1U) + { + (void)strcat(security, "WPA2_ENTP "); + } + if (scan_result.wep == 1U) + { + (void)strcat(security, "WEP "); + } + if (scan_result.wpa == 1U) + { + (void)strcat(security, "WPA "); + } + if (scan_result.wpa2 == 1U) + { + (void)strcat(security, "WPA2 "); + } + if (scan_result.wpa3_sae == 1U) + { + (void)strcat(security, "WPA3_SAE "); + } - if (i != 0) - { - /* Add ',' separator before next entry */ - ssids_json[ssids_json_idx++] = ','; - } + if (i != 0U) + { + /* Add ',' separator before next entry */ + ssids_json[ssids_json_idx++] = ','; + } - ret = snprintf( - ssids_json + ssids_json_idx, ssids_json_len - ssids_json_idx - 1, - "{\"ssid\":\"%s\",\"bssid\":\"%02X:%02X:%02X:%02X:%02X:%02X\",\"signal\":\"%ddBm\",\"channel\":%d," - "\"security\":\"%s\"}", - scan_result.ssid, (unsigned int)scan_result.bssid[0], (unsigned int)scan_result.bssid[1], - (unsigned int)scan_result.bssid[2], (unsigned int)scan_result.bssid[3], (unsigned int)scan_result.bssid[4], - (unsigned int)scan_result.bssid[5], -(int)scan_result.rssi, (int)scan_result.channel, security); - if (ret > 0) - { - ssids_json_idx += ret; - } - else - { - PRINTF("[!] JSON creation failed\r\n"); - vPortFree(ssids_json); - ssids_json = NULL; - xEventGroupSetBits(s_wplSyncEvent, EVENT_BIT(EVENT_SCAN_DONE)); - return WM_FAIL; + ret = snprintf( + ssids_json + ssids_json_idx, ssids_json_len - ssids_json_idx - 1U, + "{\"ssid\":\"%s\",\"bssid\":\"%02X:%02X:%02X:%02X:%02X:%02X\",\"signal\":\"%ddBm\",\"channel\":%d," + "\"security\":\"%s\"}", + scan_result.ssid, (unsigned int)scan_result.bssid[0], (unsigned int)scan_result.bssid[1], + (unsigned int)scan_result.bssid[2], (unsigned int)scan_result.bssid[3], (unsigned int)scan_result.bssid[4], + (unsigned int)scan_result.bssid[5], -(int)scan_result.rssi, (int)scan_result.channel, security); + if (ret > 0) + { + ssids_json_idx += (uint32_t)ret; + } + else + { + PRINTF("[!] JSON creation failed\r\n"); + vPortFree(ssids_json); + ssids_json = NULL; + (void)xEventGroupSetBits(s_wplSyncEvent, EVENT_BIT(EVENT_SCAN_DONE)); + return WM_FAIL; + } } } /* End of JSON "]}" */ - strcpy(ssids_json + ssids_json_idx, "]}"); + (void)strcpy(ssids_json + ssids_json_idx, "]}"); - xEventGroupSetBits(s_wplSyncEvent, EVENT_BIT(EVENT_SCAN_DONE)); + (void)xEventGroupSetBits(s_wplSyncEvent, EVENT_BIT(EVENT_SCAN_DONE)); return WM_SUCCESS; } @@ -554,7 +557,7 @@ char *WPL_Scan(void) if (status == WPLRET_SUCCESS) { - ret = wlan_scan(WLP_process_results); + ret = wlan_scan(&WLP_process_results); if (ret != WM_SUCCESS) { status = WPLRET_FAIL; @@ -564,7 +567,7 @@ char *WPL_Scan(void) if (status == WPLRET_SUCCESS) { syncBit = xEventGroupWaitBits(s_wplSyncEvent, WPL_SYNC_SCAN_GROUP, pdTRUE, pdFALSE, WPL_SYNC_TIMEOUT_MS); - if (syncBit & EVENT_BIT(EVENT_SCAN_DONE)) + if ((syncBit & EVENT_BIT(EVENT_SCAN_DONE)) != 0U) { status = WPLRET_SUCCESS; } @@ -582,43 +585,45 @@ char *WPL_Scan(void) return NULL; } -wpl_ret_t WPL_AddNetworkWithSecurity(char *ssid, char *password, char *label, wpl_security_t security) +wpl_ret_t WPL_AddNetworkWithSecurity(const char *ssid, const char *password, const char *label, wpl_security_t security) { wpl_ret_t status = WPLRET_SUCCESS; int ret; struct wlan_network sta_network; memset(&sta_network, 0, sizeof(struct wlan_network)); + size_t ssid_len = strlen(ssid); + size_t password_len = strlen(password); + size_t label_len = strlen(label); + if (s_wplState != WPL_STARTED) { status = WPLRET_NOT_READY; } - if (status == WPLRET_SUCCESS) + if ((label_len == 0U) || (label_len > WLAN_NETWORK_NAME_MAX_LENGTH)) { - if ((strlen(label) == 0) || (strlen(label) > (WLAN_NETWORK_NAME_MAX_LENGTH - 1))) - { - status = WPLRET_BAD_PARAM; - } + status = WPLRET_BAD_PARAM; } - if (status == WPLRET_SUCCESS) + if ((ssid_len == 0U) || (ssid_len > IEEEtypes_SSID_SIZE)) { - if ((strlen(ssid) == 0) || (strlen(ssid) > IEEEtypes_SSID_SIZE)) - { - status = WPLRET_BAD_PARAM; - } + status = WPLRET_BAD_PARAM; } - if (status == WPLRET_SUCCESS) + if (((0U < password_len) && (password_len < WPL_WIFI_PASSWORD_MIN_LEN)) || + (password_len > WPL_WIFI_PASSWORD_LENGTH)) { - size_t password_len = strlen(password); + status = WPLRET_BAD_PARAM; + } - if (password_len == 0) + if (status == WPLRET_SUCCESS) + { + if (password_len == 0U) { sta_network.security.type = WLAN_SECURITY_NONE; } - else if ((password_len >= WPL_WIFI_PASSWORD_MIN_LEN) && (password_len <= WPL_WIFI_PASSWORD_LENGTH)) + else { switch (security) { @@ -628,15 +633,15 @@ wpl_ret_t WPL_AddNetworkWithSecurity(char *ssid, char *password, char *label, wp sta_network.security.mfpr = true; sta_network.security.password_len = password_len; strncpy(sta_network.security.password, password, password_len); - sta_network.security.psk_len = password_len; + sta_network.security.psk_len = (uint8_t)password_len; strncpy(sta_network.security.psk, password, password_len); break; case WPL_SECURITY_WPA3_SAE: sta_network.security.type = WLAN_SECURITY_WPA3_SAE; sta_network.security.mfpc = true; sta_network.security.mfpr = true; - sta_network.security.password_len = strlen(password); - strncpy(sta_network.security.password, password, strlen(password)); + sta_network.security.password_len = password_len; + strncpy(sta_network.security.password, password, password_len); break; default: PRINTF("[!] Unimplemented security type (%d)\r\n", security); @@ -644,19 +649,15 @@ wpl_ret_t WPL_AddNetworkWithSecurity(char *ssid, char *password, char *label, wp break; } } - else - { - status = WPLRET_BAD_PARAM; - } } - strcpy(sta_network.name, label); - strcpy(sta_network.ssid, ssid); - sta_network.ip.ipv4.addr_type = ADDR_TYPE_DHCP; - sta_network.ssid_specific = 1; - if (status == WPLRET_SUCCESS) { + strncpy(sta_network.name, label, label_len); + strncpy(sta_network.ssid, ssid, ssid_len); + sta_network.ip.ipv4.addr_type = ADDR_TYPE_DHCP; + sta_network.ssid_specific = 1; + ret = wlan_add_network(&sta_network); if (ret != WM_SUCCESS) { @@ -667,27 +668,25 @@ wpl_ret_t WPL_AddNetworkWithSecurity(char *ssid, char *password, char *label, wp return status; } -wpl_ret_t WPL_AddNetwork(char *ssid, char *password, char *label) +wpl_ret_t WPL_AddNetwork(const char *ssid, const char *password, const char *label) { return WPL_AddNetworkWithSecurity(ssid, password, label, WPL_SECURITY_WILDCARD); } -wpl_ret_t WPL_RemoveNetwork(char *label) +wpl_ret_t WPL_RemoveNetwork(const char *label) { wpl_ret_t status = WPLRET_SUCCESS; int ret; + size_t label_len = strlen(label); if (s_wplState != WPL_STARTED) { status = WPLRET_NOT_READY; } - if (status == WPLRET_SUCCESS) + if ((label_len == 0U) || (label_len > WLAN_NETWORK_NAME_MAX_LENGTH)) { - if ((strlen(label) == 0) || (strlen(label) > (WLAN_NETWORK_NAME_MAX_LENGTH - 1))) - { - status = WPLRET_BAD_PARAM; - } + status = WPLRET_BAD_PARAM; } if (status == WPLRET_SUCCESS) @@ -707,23 +706,21 @@ wpl_ret_t WPL_Join(char *label) wpl_ret_t status = WPLRET_SUCCESS; int ret; EventBits_t syncBit; + size_t label_len = strlen(label); if ((s_wplState != WPL_STARTED) || (s_wplStaConnected != false)) { status = WPLRET_NOT_READY; } - if (status == WPLRET_SUCCESS) + if ((label_len == 0U) || (label_len > WLAN_NETWORK_NAME_MAX_LENGTH)) { - if ((strlen(label) == 0) || (strlen(label) > (WLAN_NETWORK_NAME_MAX_LENGTH - 1))) - { - status = WPLRET_BAD_PARAM; - } + status = WPLRET_BAD_PARAM; } if (status == WPLRET_SUCCESS) { - xEventGroupClearBits(s_wplSyncEvent, WPL_SYNC_CONNECT_GROUP); + (void)xEventGroupClearBits(s_wplSyncEvent, WPL_SYNC_CONNECT_GROUP); ret = wlan_connect(label); if (ret != WM_SUCCESS) @@ -735,23 +732,23 @@ wpl_ret_t WPL_Join(char *label) if (status == WPLRET_SUCCESS) { syncBit = xEventGroupWaitBits(s_wplSyncEvent, WPL_SYNC_CONNECT_GROUP, pdTRUE, pdFALSE, WPL_SYNC_TIMEOUT_MS); - if (syncBit & EVENT_BIT(WLAN_REASON_SUCCESS)) + if ((syncBit & EVENT_BIT(WLAN_REASON_SUCCESS)) != 0U) { status = WPLRET_SUCCESS; } - else if (syncBit & EVENT_BIT(WLAN_REASON_CONNECT_FAILED)) + else if ((syncBit & EVENT_BIT(WLAN_REASON_CONNECT_FAILED)) != 0U) { status = WPLRET_FAIL; } - else if (syncBit & EVENT_BIT(WLAN_REASON_NETWORK_NOT_FOUND)) + else if ((syncBit & EVENT_BIT(WLAN_REASON_NETWORK_NOT_FOUND)) != 0U) { status = WPLRET_NOT_FOUND; } - else if (syncBit & EVENT_BIT(WLAN_REASON_NETWORK_AUTH_FAILED)) + else if ((syncBit & EVENT_BIT(WLAN_REASON_NETWORK_AUTH_FAILED)) != 0U) { status = WPLRET_AUTH_FAILED; } - else if (syncBit & EVENT_BIT(WLAN_REASON_ADDRESS_FAILED)) + else if ((syncBit & EVENT_BIT(WLAN_REASON_ADDRESS_FAILED)) != 0U) { status = WPLRET_ADDR_FAILED; } @@ -763,7 +760,7 @@ wpl_ret_t WPL_Join(char *label) if (status != WPLRET_SUCCESS) { /* Abort the next connection attempt */ - WPL_Leave(); + (void)WPL_Leave(); } } @@ -787,16 +784,23 @@ wpl_ret_t WPL_Leave(void) } enum wlan_connection_state connection_state = WLAN_DISCONNECTED; - wlan_get_connection_state(&connection_state); - if (connection_state == WLAN_DISCONNECTED) + ret = wlan_get_connection_state(&connection_state); + if (ret != WM_SUCCESS) { - s_wplStaConnected = false; - return WPLRET_SUCCESS; + status = WPLRET_FAIL; + } + else + { + if (connection_state == WLAN_DISCONNECTED) + { + s_wplStaConnected = false; + return WPLRET_SUCCESS; + } } if (status == WPLRET_SUCCESS) { - xEventGroupClearBits(s_wplSyncEvent, WPL_SYNC_DISCONNECT_GROUP); + (void)xEventGroupClearBits(s_wplSyncEvent, WPL_SYNC_DISCONNECT_GROUP); ret = wlan_disconnect(); if (ret != WM_SUCCESS) @@ -808,7 +812,7 @@ wpl_ret_t WPL_Leave(void) if (status == WPLRET_SUCCESS) { syncBit = xEventGroupWaitBits(s_wplSyncEvent, WPL_SYNC_DISCONNECT_GROUP, pdTRUE, pdFALSE, WPL_SYNC_TIMEOUT_MS); - if (syncBit & EVENT_BIT(WLAN_REASON_USER_DISCONNECT)) + if ((syncBit & EVENT_BIT(WLAN_REASON_USER_DISCONNECT)) != 0U) { status = WPLRET_SUCCESS; } @@ -836,7 +840,7 @@ wpl_ret_t WPL_GetIP(char *ip, int client) if (status == WPLRET_SUCCESS) { - if (client) + if (client == 1) { ret = wlan_get_address(&addr); } diff --git a/components/flash/mflash/lpc55s3x/mflash_drv.c b/components/flash/mflash/lpc55s3x/mflash_drv.c index 39009812e..84cd18747 100644 --- a/components/flash/mflash/lpc55s3x/mflash_drv.c +++ b/components/flash/mflash/lpc55s3x/mflash_drv.c @@ -1,5 +1,5 @@ /* - * Copyright 2017-2020 NXP + * Copyright 2017-2020, 2024 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -55,7 +55,7 @@ int32_t mflash_drv_sector_erase(uint32_t sector_addr) if (0 == mflash_drv_is_sector_aligned(sector_addr)) return kStatus_InvalidArgument; - return FLASH_Erase(&g_flash_instance, sector_addr, MFLASH_SECTOR_SIZE, kFLASH_ApiEraseKey); + return FLASH_Erase(&g_flash_instance, sector_addr, MFLASH_SECTOR_SIZE, (uint32_t)kFLASH_ApiEraseKey); } /* API - Page program */ @@ -92,7 +92,7 @@ int32_t mflash_drv_is_readable(uint32_t addr) FLASH_READMODE_DMACC(g_flash_instance.modeConfig.readSingleWord.readDmaccWord); FLASH->CMD = 3; while ((FLASH->INTSTAT & FLASH_INTSTAT_DONE_MASK) == 0U) - ; + {} result = FLASH->INTSTAT; /* Report failure in case of errors */ @@ -108,11 +108,11 @@ int32_t mflash_drv_read(uint32_t addr, uint32_t *buffer, uint32_t len) { if (mflash_drv_is_readable(addr) != 0) { - memset(buffer, 0xFF, len); + (void)memset(buffer, 0xFF, len); } else { - memcpy(buffer, (void *)addr, len); + (void)memcpy(buffer, (void *)addr, len); } return kStatus_Success; diff --git a/components/flash/mflash/lpc55s3x_flexspi/mflash_drv.c b/components/flash/mflash/lpc55s3x_flexspi/mflash_drv.c index b1c8a736d..18b6be986 100644 --- a/components/flash/mflash/lpc55s3x_flexspi/mflash_drv.c +++ b/components/flash/mflash/lpc55s3x_flexspi/mflash_drv.c @@ -1,5 +1,5 @@ /* - * Copyright 2017-2020 NXP + * Copyright 2017-2020, 2024 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -60,7 +60,7 @@ int32_t mflash_drv_page_program(uint32_t page_addr, uint32_t *data) /* API - Read data */ int32_t mflash_drv_read(uint32_t addr, uint32_t *buffer, uint32_t len) { - memcpy(buffer, (void *)addr, len); + (void)memcpy(buffer, (void *)addr, len); return kStatus_Success; } diff --git a/components/flash/mflash/lpc55xxx/mflash_drv.c b/components/flash/mflash/lpc55xxx/mflash_drv.c index ce5d3601c..89ae77a66 100644 --- a/components/flash/mflash/lpc55xxx/mflash_drv.c +++ b/components/flash/mflash/lpc55xxx/mflash_drv.c @@ -1,5 +1,5 @@ /* - * Copyright 2017-2020 NXP + * Copyright 2017-2020, 2024 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -50,7 +50,7 @@ int32_t mflash_drv_sector_erase(uint32_t sector_addr) if (0 == mflash_drv_is_sector_aligned(sector_addr)) return kStatus_InvalidArgument; - return FLASH_Erase(&g_flash_instance, sector_addr, MFLASH_SECTOR_SIZE, kFLASH_ApiEraseKey); + return FLASH_Erase(&g_flash_instance, sector_addr, MFLASH_SECTOR_SIZE, (uint32_t)kFLASH_ApiEraseKey); } /* API - Page program */ @@ -86,13 +86,13 @@ int32_t mflash_drv_is_readable(uint32_t addr) FLASH_READMODE_MARGIN(g_flash_instance.modeConfig.readSingleWord.readMarginLevel) | FLASH_READMODE_DMACC(g_flash_instance.modeConfig.readSingleWord.readDmaccWord); FLASH->CMD = 3; - while (!(FLASH->INT_STATUS & FLASH_INT_STATUS_DONE_MASK)) + while ((FLASH->INT_STATUS & FLASH_INT_STATUS_DONE_MASK) == 0UL) ; result = FLASH->INT_STATUS; /* Report failure in case of errors */ result_mask = FLASH_INT_STATUS_FAIL_MASK | FLASH_INT_STATUS_ERR_MASK | FLASH_INT_STATUS_ECC_ERR_MASK; - if (result_mask & result) + if ((result_mask & result) != 0UL) return kStatus_Fail; return kStatus_Success; @@ -104,7 +104,7 @@ int32_t mflash_drv_read(uint32_t addr, uint32_t *buffer, uint32_t len) if (mflash_drv_is_readable(addr) != 0) return kStatus_Fail; - memcpy(buffer, (void *)addr, len); + (void)memcpy((void *)buffer, (void *)addr, len); return kStatus_Success; } diff --git a/components/internal_flash/evkbmimxrt1060/fsl_adapter_flexspi_nor_flash.c b/components/internal_flash/evkbmimxrt1060/fsl_adapter_flexspi_nor_flash.c index eec9e158f..5d7ed9e66 100644 --- a/components/internal_flash/evkbmimxrt1060/fsl_adapter_flexspi_nor_flash.c +++ b/components/internal_flash/evkbmimxrt1060/fsl_adapter_flexspi_nor_flash.c @@ -814,3 +814,21 @@ hal_flash_status_t HAL_FlashGetSecurityState(hal_flash_security_state_t *state) { return kStatus_HAL_Flash_Success; } + +/*! + * \brief Read data from FLASH with ECC Fault detection enabled. + * + * Note : BusFault is not raised, just SoC indication + * + * @param scr The address of the Flash location to be read + * @param size The number of bytes to be read + * @param pData Pointer to the data to be read from Flash + * + * @retval #kStatus_HAL_Flash_Success API was executed successfully. + * #kStatus_HAL_Flash_EccError if ECC Fault error got raised + * + */ +hal_flash_status_t HAL_FlashReadCheckEccFaults(uint32_t src, uint32_t size, uint8_t *pData) +{ + return kStatus_HAL_Flash_NotSupport; +} diff --git a/components/internal_flash/evkbmimxrt1170/fsl_adapter_flexspi_nor_flash.c b/components/internal_flash/evkbmimxrt1170/fsl_adapter_flexspi_nor_flash.c index 6c4f2c075..e1c9f5208 100644 --- a/components/internal_flash/evkbmimxrt1170/fsl_adapter_flexspi_nor_flash.c +++ b/components/internal_flash/evkbmimxrt1170/fsl_adapter_flexspi_nor_flash.c @@ -899,3 +899,21 @@ hal_flash_status_t HAL_FlashGetSecurityState(hal_flash_security_state_t *state) { return kStatus_HAL_Flash_Success; } + +/*! + * \brief Read data from FLASH with ECC Fault detection enabled. + * + * Note : BusFault is not raised, just SoC indication + * + * @param scr The address of the Flash location to be read + * @param size The number of bytes to be read + * @param pData Pointer to the data to be read from Flash + * + * @retval #kStatus_HAL_Flash_Success API was executed successfully. + * #kStatus_HAL_Flash_EccError if ECC Fault error got raised + * + */ +hal_flash_status_t HAL_FlashReadCheckEccFaults(uint32_t src, uint32_t size, uint8_t *pData) +{ + return kStatus_HAL_Flash_NotSupport; +} diff --git a/components/internal_flash/evkmimxrt1040/fsl_adapter_flexspi_nor_flash.c b/components/internal_flash/evkmimxrt1040/fsl_adapter_flexspi_nor_flash.c index 8d3ef6128..263b33405 100644 --- a/components/internal_flash/evkmimxrt1040/fsl_adapter_flexspi_nor_flash.c +++ b/components/internal_flash/evkmimxrt1040/fsl_adapter_flexspi_nor_flash.c @@ -765,3 +765,21 @@ hal_flash_status_t HAL_FlashGetSecurityState(hal_flash_security_state_t *state) { return kStatus_HAL_Flash_Success; } + +/*! + * \brief Read data from FLASH with ECC Fault detection enabled. + * + * Note : BusFault is not raised, just SoC indication + * + * @param scr The address of the Flash location to be read + * @param size The number of bytes to be read + * @param pData Pointer to the data to be read from Flash + * + * @retval #kStatus_HAL_Flash_Success API was executed successfully. + * #kStatus_HAL_Flash_EccError if ECC Fault error got raised + * + */ +hal_flash_status_t HAL_FlashReadCheckEccFaults(uint32_t src, uint32_t size, uint8_t *pData) +{ + return kStatus_HAL_Flash_NotSupport; +} diff --git a/components/internal_flash/fsl_adapter_flexspi_nor_flash.c b/components/internal_flash/fsl_adapter_flexspi_nor_flash.c index 2de36a53f..a12b994fb 100644 --- a/components/internal_flash/fsl_adapter_flexspi_nor_flash.c +++ b/components/internal_flash/fsl_adapter_flexspi_nor_flash.c @@ -814,3 +814,21 @@ hal_flash_status_t HAL_FlashGetSecurityState(hal_flash_security_state_t *state) { return kStatus_HAL_Flash_Success; } + +/*! + * \brief Read data from FLASH with ECC Fault detection enabled. + * + * Note : BusFault is not raised, just SoC indication + * + * @param scr The address of the Flash location to be read + * @param size The number of bytes to be read + * @param pData Pointer to the data to be read from Flash + * + * @retval #kStatus_HAL_Flash_Success API was executed successfully. + * #kStatus_HAL_Flash_EccError if ECC Fault error got raised + * + */ +hal_flash_status_t HAL_FlashReadCheckEccFaults(uint32_t src, uint32_t size, uint8_t *pData) +{ + return kStatus_HAL_Flash_NotSupport; +} diff --git a/components/internal_flash/hyper_flash/RT1050/fsl_adapter_flexspi_hyper_flash_config.c b/components/internal_flash/hyper_flash/RT1050/fsl_adapter_flexspi_hyper_flash_config.c index 7188836bf..ef46821e1 100644 --- a/components/internal_flash/hyper_flash/RT1050/fsl_adapter_flexspi_hyper_flash_config.c +++ b/components/internal_flash/hyper_flash/RT1050/fsl_adapter_flexspi_hyper_flash_config.c @@ -98,3 +98,21 @@ void flexspi_clock_init(void) CLOCK_SetMux(kCLOCK_FlexspiMux, 0x3); /* Choose PLL3 PFD0 clock as flexspi source clock. */ CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3); /* flexspi clock 83M, DDR mode, internal clock 42M. */ } + +/*! + * \brief Read data from FLASH with ECC Fault detection enabled. + * + * Note : BusFault is not raised, just SoC indication + * + * @param scr The address of the Flash location to be read + * @param size The number of bytes to be read + * @param pData Pointer to the data to be read from Flash + * + * @retval #kStatus_HAL_Flash_Success API was executed successfully. + * #kStatus_HAL_Flash_EccError if ECC Fault error got raised + * + */ +hal_flash_status_t HAL_FlashReadCheckEccFaults(uint32_t src, uint32_t size, uint8_t *pData) +{ + return kStatus_HAL_Flash_NotSupport; +} diff --git a/components/internal_flash/hyper_flash/fsl_adapter_flexspi_hyper_nor_flash.c b/components/internal_flash/hyper_flash/fsl_adapter_flexspi_hyper_nor_flash.c index 489dae37f..5300d1dee 100644 --- a/components/internal_flash/hyper_flash/fsl_adapter_flexspi_hyper_nor_flash.c +++ b/components/internal_flash/hyper_flash/fsl_adapter_flexspi_hyper_nor_flash.c @@ -1005,3 +1005,21 @@ hal_flash_status_t HAL_FlashGetSecurityState(hal_flash_security_state_t *state) { return kStatus_HAL_Flash_Success; } + +/*! + * \brief Read data from FLASH with ECC Fault detection enabled. + * + * Note : BusFault is not raised, just SoC indication + * + * @param scr The address of the Flash location to be read + * @param size The number of bytes to be read + * @param pData Pointer to the data to be read from Flash + * + * @retval #kStatus_HAL_Flash_Success API was executed successfully. + * #kStatus_HAL_Flash_EccError if ECC Fault error got raised + * + */ +hal_flash_status_t HAL_FlashReadCheckEccFaults(uint32_t src, uint32_t size, uint8_t *pData) +{ + return kStatus_HAL_Flash_NotSupport; +} diff --git a/components/internal_flash/mimxrt1160/fsl_adapter_flexspi_nor_flash.c b/components/internal_flash/mimxrt1160/fsl_adapter_flexspi_nor_flash.c index 4026cf5dc..844f8e3c2 100644 --- a/components/internal_flash/mimxrt1160/fsl_adapter_flexspi_nor_flash.c +++ b/components/internal_flash/mimxrt1160/fsl_adapter_flexspi_nor_flash.c @@ -914,3 +914,21 @@ hal_flash_status_t HAL_FlashGetSecurityState(hal_flash_security_state_t *state) { return kStatus_HAL_Flash_Success; } + +/*! + * \brief Read data from FLASH with ECC Fault detection enabled. + * + * Note : BusFault is not raised, just SoC indication + * + * @param scr The address of the Flash location to be read + * @param size The number of bytes to be read + * @param pData Pointer to the data to be read from Flash + * + * @retval #kStatus_HAL_Flash_Success API was executed successfully. + * #kStatus_HAL_Flash_EccError if ECC Fault error got raised + * + */ +hal_flash_status_t HAL_FlashReadCheckEccFaults(uint32_t src, uint32_t size, uint8_t *pData) +{ + return kStatus_HAL_Flash_NotSupport; +} diff --git a/components/internal_flash/mimxrt1170/fsl_adapter_flexspi_nor_flash.c b/components/internal_flash/mimxrt1170/fsl_adapter_flexspi_nor_flash.c index 4aa6b1e86..0c94ae593 100644 --- a/components/internal_flash/mimxrt1170/fsl_adapter_flexspi_nor_flash.c +++ b/components/internal_flash/mimxrt1170/fsl_adapter_flexspi_nor_flash.c @@ -912,3 +912,21 @@ hal_flash_status_t HAL_FlashGetSecurityState(hal_flash_security_state_t *state) { return kStatus_HAL_Flash_Success; } + +/*! + * \brief Read data from FLASH with ECC Fault detection enabled. + * + * Note : BusFault is not raised, just SoC indication + * + * @param scr The address of the Flash location to be read + * @param size The number of bytes to be read + * @param pData Pointer to the data to be read from Flash + * + * @retval #kStatus_HAL_Flash_Success API was executed successfully. + * #kStatus_HAL_Flash_EccError if ECC Fault error got raised + * + */ +hal_flash_status_t HAL_FlashReadCheckEccFaults(uint32_t src, uint32_t size, uint8_t *pData) +{ + return kStatus_HAL_Flash_NotSupport; +} diff --git a/components/mem_manager/fsl_component_mem_manager.h b/components/mem_manager/fsl_component_mem_manager.h index 78070a500..05f82b9fa 100644 --- a/components/mem_manager/fsl_component_mem_manager.h +++ b/components/mem_manager/fsl_component_mem_manager.h @@ -354,7 +354,7 @@ uint32_t MEM_GetHeapUpperLimit(void); * @retval UpperLimit Return the address after the last allocated block if MemManagerLight is used. * @retval 0 Return 0 in case of the legacy MemManager. */ -uint32_t MEM_GetHeapUpperLimitByAreaId(uint8_t id); +uint32_t MEM_GetHeapUpperLimitByAreaId(uint8_t area_id); #endif /*! @@ -471,7 +471,7 @@ void *MEM_CallocAlt(size_t len, size_t val); * @return kStatus_MemSuccess if success, kStatus_MemInitError otherwise. * */ -mem_status_t MEM_RegisterExtendedArea(memAreaCfg_t *area_desc, uint8_t *area_id, uint16_t flags); +mem_status_t MEM_RegisterExtendedArea(memAreaCfg_t *area_desc, uint8_t *p_area_id, uint16_t flags); /*! * @brief Function to unregister an extended area diff --git a/components/mem_manager/fsl_component_mem_manager_light.c b/components/mem_manager/fsl_component_mem_manager_light.c index 29e247a8c..c05125af6 100644 --- a/components/mem_manager/fsl_component_mem_manager_light.c +++ b/components/mem_manager/fsl_component_mem_manager_light.c @@ -437,7 +437,7 @@ static memAreaPrivDesc_t *MEM_GetAreaByAreaId(uint8_t area_id) memAreaPrivDesc_t *p_area = &heap_area_list; for (uint8_t i = 0u; i < area_id; i++) { - p_area = (memAreaPrivDesc_t *)p_area->next; + p_area = (memAreaPrivDesc_t *)(void *)p_area->next; } return p_area; } @@ -516,7 +516,7 @@ mem_status_t MEM_RegisterExtendedArea(memAreaCfg_t *area_desc, uint8_t *p_area_i { uint32_t area_sz; - memAreaPrivDesc_t *new_area_desc = (memAreaPrivDesc_t *)area_desc; + memAreaPrivDesc_t *new_area_desc = (memAreaPrivDesc_t *)(void *)area_desc; assert((flags & AREA_FLAGS_RFFU) == 0U); /* Registering an additional area : memHeap nust have been registered beforehand */ uint8_t id = 0; @@ -532,14 +532,15 @@ mem_status_t MEM_RegisterExtendedArea(memAreaCfg_t *area_desc, uint8_t *p_area_i break; } area_sz = new_area_desc->end_address.raw_address - new_area_desc->start_address.raw_address; - if (area_sz <= KB(1)) + if (area_sz <= (uint32_t)KB((uint32_t)1U)) { /* doesn't make sense to register an area smaller than 1024 bytes */ st = kStatus_MemInitError; break; } - for (p_area = &heap_area_list, id = 1; p_area->next != NULL; p_area = (memAreaPrivDesc_t *)p_area->next) + id = 1; + for (p_area = &heap_area_list; p_area->next != NULL; p_area = (memAreaPrivDesc_t *)(void *)p_area->next) { if (p_area == new_area_desc) { @@ -631,14 +632,14 @@ mem_status_t MEM_UnRegisterExtendedArea(uint8_t area_id) st = kStatus_MemFreeError; break; } - prev_area = MEM_GetAreaByAreaId(area_id - 1); /* Get previous area in list */ + prev_area = MEM_GetAreaByAreaId(area_id - 1U); /* Get previous area in list */ if (prev_area == NULL) { st = kStatus_MemFreeError; break; } - p_area_to_remove = (memAreaPrivDesc_t *)prev_area->next; + p_area_to_remove = (memAreaPrivDesc_t *)(void *)prev_area->next; if (p_area_to_remove == NULL) { st = kStatus_MemFreeError; @@ -759,17 +760,17 @@ static void *MEM_BufferAllocateFromArea(memAreaPrivDesc_t *p_area, uint8_t area_ int32_t remaining_bytes; /* Current allocation should never be greater than heap end */ - available_size = p_area->end_address.raw_address - current_footprint; + available_size = (int32_t)p_area->end_address.raw_address - (int32_t)current_footprint; assert(available_size >= 0); assert(FreeBlockHdr == p_area->ctx.FreeBlockHdrList.tail); total_size = (numBytes + BLOCK_HDR_SIZE); - remaining_bytes = (available_size - total_size); + remaining_bytes = available_size - (int32_t)total_size; if (remaining_bytes >= 0) /* need to keep the room for the next BlockHeader */ { - if (p_area->low_watermark > remaining_bytes) + if (p_area->low_watermark > (uint32_t)remaining_bytes) { - p_area->low_watermark = remaining_bytes; + p_area->low_watermark = (uint32_t)remaining_bytes; } /* Depending on the platform, some RAM banks could need some reinitialization after a low power * period, such as ECC RAM banks */ @@ -917,7 +918,7 @@ static void *MEM_BufferAllocate(uint32_t numBytes, uint8_t poolId) if (poolId == 0U) { area_id = 0U; - for (p_area = &heap_area_list; p_area != NULL; p_area = (memAreaPrivDesc_t *)p_area->next) + for (p_area = &heap_area_list; p_area != NULL; p_area = (memAreaPrivDesc_t *)(void *)p_area->next) { if ((p_area->flags & AREA_FLAGS_POOL_NOT_SHARED) == 0U) { @@ -985,7 +986,7 @@ static mem_status_t MEM_BufferFreeBackToArea(memAreaPrivDesc_t *p_area, void *bu /* when allocating a buffer, we always create a FreeBlockHdr at the end of the buffer, so the FreeBlockHdrList.tail should always be at a higher address than current BlockHdr */ - assert(BlockHdr < p_area->ctx.FreeBlockHdrList.tail); + assert((uint32_t)BlockHdr < (uint32_t)p_area->ctx.FreeBlockHdrList.tail); #if defined(gMemManagerLightGuardsCheckEnable) && (gMemManagerLightGuardsCheckEnable == 1) MEM_BlockHeaderCheck(BlockHdr->next); @@ -997,7 +998,7 @@ static mem_status_t MEM_BufferFreeBackToArea(memAreaPrivDesc_t *p_area, void *bu MEM_BufferFrees_memStatis(buffer); #endif /* MEM_STATISTICS_INTERNAL */ - if (BlockHdr < p_area->ctx.FreeBlockHdrList.head) + if ((uint32_t)BlockHdr < (uint32_t)p_area->ctx.FreeBlockHdrList.head) { /* BlockHdr is placed before FreeBlockHdrList.head so we can set it as the new head of the list */ @@ -1063,7 +1064,7 @@ mem_status_t MEM_BufferFree(void *buffer /* IN: Block of memory to free*/) } else { - assert(p_area != NULL); + assert(false); ret = kStatus_MemFreeError; } @@ -1250,7 +1251,7 @@ static uint32_t MEM_GetFreeHeapSpaceInArea(memAreaPrivDesc_t *p_area) } /* Add remaining free space in the heap */ - free_sz += p_area->end_address.raw_address - (uint32_t)p_area->ctx.FreeBlockHdrList.tail - BLOCK_HDR_SIZE + 1; + free_sz += p_area->end_address.raw_address - (uint32_t)p_area->ctx.FreeBlockHdrList.tail - BLOCK_HDR_SIZE + (uint32_t)1U; return free_sz; } @@ -1262,7 +1263,7 @@ uint32_t MEM_GetFreeHeapSizeByAreaId(uint8_t area_id) if (area_id == 0U) { /* Iterate through all registered areas */ - for (p_area = &heap_area_list; p_area != NULL; p_area = (memAreaPrivDesc_t *)p_area->next) + for (p_area = &heap_area_list; p_area != NULL; p_area = (memAreaPrivDesc_t *)(void *)p_area->next) { if ((p_area->flags & AREA_FLAGS_POOL_NOT_SHARED) == 0U) { @@ -1312,7 +1313,7 @@ void *MEM_CallocAlt(size_t len, size_t val) void *pData = MEM_BufferAllocate(blk_size, 0U); if (NULL != pData) { - (void)memset(pData, 0U, blk_size); + (void)memset(pData, 0, blk_size); } return pData; diff --git a/components/messaging/fsl_component_messaging.c b/components/messaging/fsl_component_messaging.c index 2b4bbcc9c..0ebf4e3ef 100644 --- a/components/messaging/fsl_component_messaging.c +++ b/components/messaging/fsl_component_messaging.c @@ -157,7 +157,7 @@ void *MSG_Alloc(uint32_t length) { ((list_element_t *)buffer)->list = NULL; buffer = (list_element_t *)buffer + 1; - memset(buffer, 0u, length); + (void)memset(buffer, 0, length); } return buffer; } diff --git a/components/osa/fsl_os_abstraction_free_rtos.c b/components/osa/fsl_os_abstraction_free_rtos.c index 074ca7cdd..c22a1c1bf 100644 --- a/components/osa/fsl_os_abstraction_free_rtos.c +++ b/components/osa/fsl_os_abstraction_free_rtos.c @@ -63,7 +63,7 @@ typedef struct osa_freertos_task typedef struct _osa_event_struct { - EventGroupHandle_t handle; /* The event handle */ + EventGroupHandle_t eventHandle; /* The event handle */ uint8_t autoClear; /*!< Auto clear or manual clear */ } osa_event_struct_t; @@ -717,11 +717,11 @@ osa_status_t OSA_EventCreate(osa_event_handle_t eventHandle, uint8_t autoClear) #if (defined(configSUPPORT_STATIC_ALLOCATION) && (configSUPPORT_STATIC_ALLOCATION > 0U)) && \ !((defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0U))) - pEventStruct->handle = xEventGroupCreateStatic((StaticEventGroup_t *)(void *)((uint8_t *)(eventHandle) + sizeof(osa_event_struct_t))); + pEventStruct->eventHandle = xEventGroupCreateStatic((StaticEventGroup_t *)(void *)((uint8_t *)(eventHandle) + sizeof(osa_event_struct_t))); #else - pEventStruct->handle = xEventGroupCreate(); + pEventStruct->eventHandle = xEventGroupCreate(); #endif - if (NULL != pEventStruct->handle) + if (NULL != pEventStruct->eventHandle) { pEventStruct->autoClear = autoClear; } @@ -746,16 +746,16 @@ osa_status_t OSA_EventSet(osa_event_handle_t eventHandle, osa_event_flags_t flag assert(NULL != eventHandle); osa_event_struct_t *pEventStruct = (osa_event_struct_t *)eventHandle; - if (NULL == pEventStruct->handle) + if (NULL == pEventStruct->eventHandle) { return KOSA_StatusError; } if (0U != __get_IPSR()) { #if (configUSE_TRACE_FACILITY == 1) - result = xEventGroupSetBitsFromISR(pEventStruct->handle, (event_flags_t)flagsToSet, &taskToWake); + result = xEventGroupSetBitsFromISR(pEventStruct->eventHandle, (event_flags_t)flagsToSet, &taskToWake); #else - result = xEventGroupSetBitsFromISR((void *)pEventStruct->handle, (event_flags_t)flagsToSet, &taskToWake); + result = xEventGroupSetBitsFromISR((void *)pEventStruct->eventHandle, (event_flags_t)flagsToSet, &taskToWake); #endif assert(pdPASS == result); (void)result; @@ -763,7 +763,7 @@ osa_status_t OSA_EventSet(osa_event_handle_t eventHandle, osa_event_flags_t flag } else { - (void)xEventGroupSetBits(pEventStruct->handle, (event_flags_t)flagsToSet); + (void)xEventGroupSetBits(pEventStruct->eventHandle, (event_flags_t)flagsToSet); } (void)result; @@ -782,7 +782,7 @@ osa_status_t OSA_EventClear(osa_event_handle_t eventHandle, osa_event_flags_t fl assert(NULL != eventHandle); osa_event_struct_t *pEventStruct = (osa_event_struct_t *)eventHandle; - if (NULL == pEventStruct->handle) + if (NULL == pEventStruct->eventHandle) { return KOSA_StatusError; } @@ -790,14 +790,14 @@ osa_status_t OSA_EventClear(osa_event_handle_t eventHandle, osa_event_flags_t fl if (0U != __get_IPSR()) { #if (configUSE_TRACE_FACILITY == 1) - (void)xEventGroupClearBitsFromISR(pEventStruct->handle, (event_flags_t)flagsToClear); + (void)xEventGroupClearBitsFromISR(pEventStruct->eventHandle, (event_flags_t)flagsToClear); #else - (void)xEventGroupClearBitsFromISR((void *)pEventStruct->handle, (event_flags_t)flagsToClear); + (void)xEventGroupClearBitsFromISR((void *)pEventStruct->eventHandle, (event_flags_t)flagsToClear); #endif } else { - (void)xEventGroupClearBits(pEventStruct->handle, (event_flags_t)flagsToClear); + (void)xEventGroupClearBits(pEventStruct->eventHandle, (event_flags_t)flagsToClear); } return KOSA_StatusSuccess; } @@ -817,7 +817,7 @@ osa_status_t OSA_EventGet(osa_event_handle_t eventHandle, osa_event_flags_t flag osa_event_struct_t *pEventStruct = (osa_event_struct_t *)eventHandle; EventBits_t eventFlags; - if (NULL == pEventStruct->handle) + if (NULL == pEventStruct->eventHandle) { return KOSA_StatusError; } @@ -829,11 +829,11 @@ osa_status_t OSA_EventGet(osa_event_handle_t eventHandle, osa_event_flags_t flag if (0U != __get_IPSR()) { - eventFlags = xEventGroupGetBitsFromISR(pEventStruct->handle); + eventFlags = xEventGroupGetBitsFromISR(pEventStruct->eventHandle); } else { - eventFlags = xEventGroupGetBits(pEventStruct->handle); + eventFlags = xEventGroupGetBits(pEventStruct->eventHandle); } *pFlagsOfEvent = (osa_event_flags_t)eventFlags & flagsMask; @@ -870,7 +870,7 @@ osa_status_t OSA_EventWait(osa_event_handle_t eventHandle, /* Clean FreeRTOS cotrol flags */ flagsToWait = flagsToWait & 0x00FFFFFFU; - if (NULL == pEventStruct->handle) + if (NULL == pEventStruct->eventHandle) { return KOSA_StatusError; } @@ -887,7 +887,7 @@ osa_status_t OSA_EventWait(osa_event_handle_t eventHandle, clearMode = (pEventStruct->autoClear != 0U) ? pdTRUE : pdFALSE; - flagsSave = xEventGroupWaitBits(pEventStruct->handle, (event_flags_t)flagsToWait, clearMode, (BaseType_t)waitAll, + flagsSave = xEventGroupWaitBits(pEventStruct->eventHandle, (event_flags_t)flagsToWait, clearMode, (BaseType_t)waitAll, timeoutTicks); flagsSave &= (event_flags_t)flagsToWait; @@ -919,11 +919,11 @@ osa_status_t OSA_EventDestroy(osa_event_handle_t eventHandle) assert(NULL != eventHandle); osa_event_struct_t *pEventStruct = (osa_event_struct_t *)eventHandle; - if (NULL == pEventStruct->handle) + if (NULL == pEventStruct->eventHandle) { return KOSA_StatusError; } - vEventGroupDelete(pEventStruct->handle); + vEventGroupDelete(pEventStruct->eventHandle); return KOSA_StatusSuccess; } diff --git a/components/osa/fsl_os_abstraction_threadx.c b/components/osa/fsl_os_abstraction_threadx.c index 575207d3a..c97ee0b43 100644 --- a/components/osa/fsl_os_abstraction_threadx.c +++ b/components/osa/fsl_os_abstraction_threadx.c @@ -66,7 +66,7 @@ typedef struct osa_thread_task typedef struct _osa_event_struct { - TX_EVENT_FLAGS_GROUP handle; /* The event handle */ + TX_EVENT_FLAGS_GROUP eventHandle; /* The event handle */ uint8_t autoClear; /*!< Auto clear or manual clear */ } osa_event_struct_t; @@ -151,7 +151,7 @@ void OSA_EnterCritical(uint32_t *sr) *END**************************************************************************/ void OSA_ExitCritical(uint32_t sr) { - tx_interrupt_control(sr); + (void)tx_interrupt_control(sr); } /*FUNCTION********************************************************************** @@ -649,7 +649,7 @@ osa_status_t OSA_EventCreate(osa_event_handle_t eventHandle, uint8_t autoClear) pEventStruct->autoClear = autoClear; - if (TX_SUCCESS != tx_event_flags_create(&pEventStruct->handle, NULL)) + if (TX_SUCCESS != tx_event_flags_create(&pEventStruct->eventHandle, NULL)) { status = KOSA_StatusError; } @@ -671,7 +671,7 @@ osa_status_t OSA_EventSet(osa_event_handle_t eventHandle, osa_event_flags_t flag assert(eventHandle != NULL); - if (TX_SUCCESS != tx_event_flags_set(&pEventStruct->handle, (ULONG)flagsToSet, TX_OR)) + if (TX_SUCCESS != tx_event_flags_set(&pEventStruct->eventHandle, (ULONG)flagsToSet, TX_OR)) { status = KOSA_StatusError; } @@ -693,7 +693,7 @@ osa_status_t OSA_EventClear(osa_event_handle_t eventHandle, osa_event_flags_t fl assert(eventHandle != NULL); - if (TX_SUCCESS != tx_event_flags_set(&pEventStruct->handle, (ULONG)~flagsToClear, TX_AND)) + if (TX_SUCCESS != tx_event_flags_set(&pEventStruct->eventHandle, (ULONG)~flagsToClear, TX_AND)) { status = KOSA_StatusError; } @@ -723,7 +723,7 @@ osa_status_t OSA_EventGet(osa_event_handle_t eventHandle, osa_event_flags_t flag return KOSA_StatusError; } - if (TX_SUCCESS != tx_event_flags_info_get(&pEventStruct->handle, NULL, &flags, NULL, NULL, NULL)) + if (TX_SUCCESS != tx_event_flags_info_get(&pEventStruct->eventHandle, NULL, &flags, NULL, NULL, NULL)) { status = KOSA_StatusError; } @@ -791,7 +791,7 @@ osa_status_t OSA_EventWait(osa_event_handle_t eventHandle, options |= TX_EVENT_FLAGS_AND_MASK; } - status = tx_event_flags_get(&pEventStruct->handle, flagsToWait, options, (ULONG *)&flagsSave, timeoutTicks); + status = tx_event_flags_get(&pEventStruct->eventHandle, flagsToWait, options, (ULONG *)&flagsSave, timeoutTicks); if (status != TX_SUCCESS && status != TX_NO_EVENTS) { return KOSA_StatusError; @@ -829,7 +829,7 @@ osa_status_t OSA_EventDestroy(osa_event_handle_t eventHandle) assert(eventHandle != NULL); - if (TX_SUCCESS != tx_event_flags_delete(&pEventStruct->handle)) + if (TX_SUCCESS != tx_event_flags_delete(&pEventStruct->eventHandle)) { status = KOSA_StatusError; } @@ -845,7 +845,7 @@ osa_status_t OSA_EventDestroy(osa_event_handle_t eventHandle) *END**************************************************************************/ void OSA_InterruptEnable(void) { - tx_interrupt_control(TX_INT_ENABLE); + (void)tx_interrupt_control(TX_INT_ENABLE); } /*FUNCTION********************************************************************** @@ -856,7 +856,7 @@ void OSA_InterruptEnable(void) *END**************************************************************************/ void OSA_InterruptDisable(void) { - tx_interrupt_control(TX_INT_DISABLE); + (void)tx_interrupt_control(TX_INT_DISABLE); } /*FUNCTION********************************************************************** diff --git a/components/pf5020/fsl_pf5020.c b/components/pf5020/fsl_pf5020.c index e6ca00743..7db10774f 100644 --- a/components/pf5020/fsl_pf5020.c +++ b/components/pf5020/fsl_pf5020.c @@ -1,5 +1,5 @@ /* - * Copyright 2021 ~ 2022 NXP + * Copyright 2021 ~ 2022, 2024 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -239,18 +239,18 @@ static status_t PF5020_MaskInterrupts(pf5020_handle_t *handle, uint64_t interrup { if ((tmp64 & (uint64_t)kPF5020_ILIM_Ldo1IlimInterrupt) != 0ULL) { - tmp64 &= (uint64_t)(~kPF5020_ILIM_Ldo1IlimInterrupt); + tmp64 &= (uint64_t)(~(uint64_t)kPF5020_ILIM_Ldo1IlimInterrupt); status = PF5020_WriteReg(handle, PF5020_LDO_ILIM_MASK, enableMask ? 0U : 1U); } if ((tmp64 & (uint64_t)kPF5020_UV_Ldo1UvInterrupt) != 0ULL) { - tmp64 &= (uint64_t)(~kPF5020_UV_Ldo1UvInterrupt); + tmp64 &= (uint64_t)(~(uint64_t)kPF5020_UV_Ldo1UvInterrupt); status = PF5020_WriteReg(handle, PF5020_LDO_UV_MASK, enableMask ? 0U : 1U); } if ((tmp64 & (uint64_t)kPF5020_OV_Ldo1OvInterrupt) != 0UL) { - tmp64 &= (uint64_t)(~kPF5020_OV_Ldo1OvInterrupt); + tmp64 &= (uint64_t)(~(uint64_t)kPF5020_OV_Ldo1OvInterrupt); status = PF5020_WriteReg(handle, PF5020_LDO_OV_MASK, enableMask ? 0U : 1U); } if (status == kStatus_Success) @@ -2029,19 +2029,19 @@ status_t PF5020_ClearInterruptStatus(pf5020_handle_t *handle, uint64_t interrupt if ((tmp64 & (uint64_t)kPF5020_ILIM_Ldo1IlimInterrupt) != 0ULL) { status = PF5020_WriteReg(handle, PF5020_LDO_ILIM_INT, 1U); - tmp64 &= (uint64_t)~kPF5020_ILIM_Ldo1IlimInterrupt; + tmp64 &= (uint64_t)(~(uint64_t)kPF5020_ILIM_Ldo1IlimInterrupt); } if ((tmp64 & (uint64_t)kPF5020_UV_Ldo1UvInterrupt) != 0ULL) { status = PF5020_WriteReg(handle, PF5020_LDO_UV_INT, 1U); - tmp64 &= (uint64_t)~kPF5020_UV_Ldo1UvInterrupt; + tmp64 &= (uint64_t)(~(uint64_t)kPF5020_UV_Ldo1UvInterrupt); } if ((tmp64 & (uint64_t)kPF5020_OV_Ldo1OvInterrupt) != 0ULL) { status = PF5020_WriteReg(handle, PF5020_LDO_OV_INT, 1U); - tmp64 &= (uint64_t)~kPF5020_OV_Ldo1OvInterrupt; + tmp64 &= (uint64_t)(~(uint64_t)kPF5020_OV_Ldo1OvInterrupt); } tmp8 = (uint8_t)(tmp64 >> (8ULL * i)) & (0xFFU); diff --git a/components/phy/device/phyrtl8201/fsl_phyrtl8201.c b/components/phy/device/phyrtl8201/fsl_phyrtl8201.c index 7a008f137..052859389 100644 --- a/components/phy/device/phyrtl8201/fsl_phyrtl8201.c +++ b/components/phy/device/phyrtl8201/fsl_phyrtl8201.c @@ -21,7 +21,7 @@ #define PHY_PAGE_INTR_ADDR (7U) #define PHY_INER_REG (19U) -#define PHY_INER_LINKSTATUS_CHANGE_MASK (1U << 13) +#define PHY_INER_LINKSTATUS_CHANGE_MASK ((uint16_t)1U << 13) /*! @brief Defines the timeout macro. */ #define PHY_READID_TIMEOUT_COUNT 1000U diff --git a/components/power_manager/devices/MIMXRT1171/fsl_pm_device.c b/components/power_manager/devices/MIMXRT1171/fsl_pm_device.c index b078092b1..4ce3c7b6e 100644 --- a/components/power_manager/devices/MIMXRT1171/fsl_pm_device.c +++ b/components/power_manager/devices/MIMXRT1171/fsl_pm_device.c @@ -1,5 +1,5 @@ /* - * Copyright 2023 NXP + * Copyright 2023~2024 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -98,23 +98,23 @@ #define PM_RT1170_LPSR_ANA_LDO_LP_MODE_SETPOINT_MAP \ (0xFFFFU) // LPSR_ANA_LDO lowpower mode is disabled for all setpoints. #define PM_RT1170_LPSR_ANA_LDO_TRACKING_EN_SETPOINT_MAP \ - (~PM_RT1170_LPSR_ANA_LDO_EN_SETPOINT_MAP) // LPSR_ANA_DO tracking is enabled + ((uint32_t)(~PM_RT1170_LPSR_ANA_LDO_EN_SETPOINT_MAP)) // LPSR_ANA_DO tracking is enabled // from setpoint 0 to setpoint 10. #define PM_RT1170_LPSR_ANA_LDO_BYPASS_EN_SETPOINT_MAP \ - (~PM_RT1170_LPSR_ANA_LDO_EN_SETPOINT_MAP) // LPSR_ANA_DO bypass is enabled from + ((uint32_t)(~PM_RT1170_LPSR_ANA_LDO_EN_SETPOINT_MAP)) // LPSR_ANA_DO bypass is enabled from // setpoint 0 to setpoint 10. #define PM_RT1170_LPSR_DIG_LDO_EN_SETPOINT_MAP \ - (0xF81C) // LPSR_DIG_DO is enabled from setpoint 2 to setpoint 4, + (0xF81CU) // LPSR_DIG_DO is enabled from setpoint 2 to setpoint 4, // and setpoint 11 to setpoint 15. #define PM_RT1170_LPSR_DIG_LDO_STANDBY_SETPOINT_MAP (0xFFFFU) // LPSR_DIG_DO standby mode is disabled for all setpoints. #define PM_RT1170_LPSR_DIG_LDO_LP_MODE_SETPOINT_MAP \ (0xFFFFU) // LPSR_DIG_DO lowpower mode is disabled for all setpoints. #define PM_RT1170_LPSR_DIG_LDO_TRACKING_EN_SETPOINT_MAP \ - (~PM_RT1170_LPSR_DIG_LDO_EN_SETPOINT_MAP) // LPSR_DIG_DO tracking is enabled + ((uint32_t)(~PM_RT1170_LPSR_DIG_LDO_EN_SETPOINT_MAP)) // LPSR_DIG_DO tracking is enabled // from setpoint 0 to setpoint 1, // and setpoint 5 to setpoint 10. #define PM_RT1170_LPSR_DIG_LDO_BYPASS_EN_SETPOINT_MAP \ - (~PM_RT1170_LPSR_DIG_LDO_EN_SETPOINT_MAP) // LPSR_DIG_DO bypass is enabled from + ((uint32_t)(~PM_RT1170_LPSR_DIG_LDO_EN_SETPOINT_MAP)) // LPSR_DIG_DO bypass is enabled from // setpoint 0 to setpoint 1, // and setpoint 5 to setpoint 10. @@ -212,6 +212,7 @@ static bool RT1170_IsWakeupSource(pm_wakeup_source_t *ws); ******************************************************************************/ #if __CORTEX_M == 7 +extern const uint16_t g_clockSourceSpMapping[29U]; const uint16_t g_clockSourceSpMapping[29U] = { 0xFFFFU, /*!< Clock Source OSCPLL0: 16MHz RC OSC output, turn on in all setpoints. */ 0x0000U, /*!< Clock Source OSCPLL1: 48MHz RC OSC output, turn off in all setpoints. */ @@ -831,17 +832,18 @@ const pm_device_option_t g_devicePMOption = { */ static inline uint8_t RT1170_FindOperateMode(uint32_t rescIndex, pm_resc_group_t *pSysRescGroup) { - uint8_t u8Tmp = (pSysRescGroup->groupSlice[rescIndex / 8UL] >> (4UL * (rescIndex % 8UL))) & 0xFUL; + uint32_t u32Tmp = (pSysRescGroup->groupSlice[rescIndex / 8UL] >> (4UL * (rescIndex % 8UL))) & 0xFUL; // Find first set, that is the operate mode to set. - u8Tmp |= (u8Tmp >> 1U); - u8Tmp |= (u8Tmp >> 2U); + u32Tmp |= (u32Tmp >> 1U); + u32Tmp |= (u32Tmp >> 2U); - return ((u8Tmp + 1U) >> 1U); + return (uint8_t)(uint32_t)((u32Tmp + 1UL) >> 1UL); } #if __CORTEX_M == 7 /*! + * @brief Configure setpoint mapping for CM7. */ static inline void RT1170_SetCore0PlatformSetpointMap(GPC_CPU_MODE_CTRL_Type *base) @@ -849,7 +851,7 @@ static inline void RT1170_SetCore0PlatformSetpointMap(GPC_CPU_MODE_CTRL_Type *ba uint8_t i, j; uint32_t u32Tmp; - uint8_t coreSetpointMap[17U][17U] = PM_RT1170_CM7_COMPATIBLE_SETPOINT_MAP; + uint32_t coreSetpointMap[17U][17U] = PM_RT1170_CM7_COMPATIBLE_SETPOINT_MAP; // Enable CPU sleep hold. GPC_CM_EnableCpuSleepHold(base, true); @@ -893,15 +895,15 @@ static inline void RT1170_SetClockSourcesControlBySetpoint(void) ANADIG_PLL->PLL_AUDIO_CTRL &= ~ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_MASK; ANADIG_PLL->PLL_VIDEO_CTRL &= ~ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_MASK; - clock_name_t clockSourceName = kCLOCK_OscRc16M; - for (clockSourceName = kCLOCK_OscRc16M; clockSourceName <= kCLOCK_VideoPllOut; clockSourceName++) + uint8_t clockSourceName = (uint8_t)kCLOCK_OscRc16M; + for (clockSourceName = (uint8_t)kCLOCK_OscRc16M; clockSourceName <= (uint8_t)kCLOCK_VideoPllOut; clockSourceName++) { if (!CLOCK_OSCPLL_IsSetPointImplemented((clock_name_t)clockSourceName)) { assert(0); } // keep clock source init state aligned with set point 0 state. - if ((g_clockSourceSpMapping[(uint8_t)clockSourceName] & 0x1) == 0) + if ((g_clockSourceSpMapping[(uint8_t)clockSourceName] & (uint16_t)0x1U) == (uint16_t)0U) { CCM->OSCPLL[(uint8_t)clockSourceName].DIRECT = 0; } @@ -910,12 +912,12 @@ static inline void RT1170_SetClockSourcesControlBySetpoint(void) CCM->OSCPLL[(uint8_t)clockSourceName].DIRECT = 1; } // All clock sources except OSC_RC 16M are turned off in standby mode. - uint32_t standbyValue = 0UL; - if (clockSourceName == kCLOCK_OscRc16M) + uint16_t standbyValue = 0U; + if ((clock_name_t)clockSourceName == kCLOCK_OscRc16M) { standbyValue = 0xFFFFU; } - CLOCK_OSCPLL_ControlBySetPointMode(clockSourceName, g_clockSourceSpMapping[(uint8_t)clockSourceName], + CLOCK_OSCPLL_ControlBySetPointMode((clock_name_t)clockSourceName, g_clockSourceSpMapping[(uint8_t)clockSourceName], standbyValue); } @@ -1000,7 +1002,7 @@ static inline void RT1170_SetPowerSupplyControlBySetpoint(void) PMU_GPCEnableLdoBypassMode(kPMU_LpsrDigLdo, PM_RT1170_LPSR_DIG_LDO_BYPASS_EN_SETPOINT_MAP); for (uint8_t i = 0U; i < 16U; i++) { - PMU_GPCSetLpsrDigLdoTargetVoltage(1U << i, g_lpsrDigLdoTargetVoltage[i]); + PMU_GPCSetLpsrDigLdoTargetVoltage(1UL << i, g_lpsrDigLdoTargetVoltage[i]); } PMU_SetLpsrDigLdoControlMode(ANADIG_LDO_SNVS, kPMU_GPCMode); @@ -1032,20 +1034,20 @@ static inline void RT1170_SetSRCControlMode(void) SRC_EnableSetPointTransferReset(SRC, kSRC_LpsrSlice, true); SRC_SetSliceSetPointConfig(SRC, kSRC_LpsrSlice, PM_RT1170_LPSRMIX_SETPOINT_MAP); // e. Reset slice corresponding to Cortex-M4 platform is controlled by entering of suspend mode. - SRC_SetAssignList(SRC, kSRC_M4CoreSlice, kSRC_CM4Core); - SRC_SetSliceDomainModeConfig(SRC, kSRC_M4CoreSlice, kSRC_Cpu1SuspendModeAssertReset); + SRC_SetAssignList(SRC, kSRC_M4CoreSlice, (uint32_t)kSRC_CM4Core); + SRC_SetSliceDomainModeConfig(SRC, kSRC_M4CoreSlice, (uint32_t)kSRC_Cpu1SuspendModeAssertReset); SRC_EnableDomainModeTransferReset(SRC, kSRC_M4CoreSlice, true); // f. Reset slice corresponding to Cortex-M7 platform is controlled by entering of suspend mode. - SRC_SetAssignList(SRC, kSRC_M7CoreSlice, kSRC_CM7Core); - SRC_SetSliceDomainModeConfig(SRC, kSRC_M7CoreSlice, kSRC_Cpu0SuspendModeAssertReset); + SRC_SetAssignList(SRC, kSRC_M7CoreSlice, (uint32_t)kSRC_CM7Core); + SRC_SetSliceDomainModeConfig(SRC, kSRC_M7CoreSlice, (uint32_t)kSRC_Cpu0SuspendModeAssertReset); SRC_EnableDomainModeTransferReset(SRC, kSRC_M7CoreSlice, true); // g. Reset slice corresponding to CM4 Debug is controlled by entering of suspend mode. - SRC_SetAssignList(SRC, kSRC_M4DebugSlice, kSRC_CM4Core); - SRC_SetSliceDomainModeConfig(SRC, kSRC_M4DebugSlice, kSRC_Cpu1SuspendModeAssertReset); + SRC_SetAssignList(SRC, kSRC_M4DebugSlice, (uint32_t)kSRC_CM4Core); + SRC_SetSliceDomainModeConfig(SRC, kSRC_M4DebugSlice, (uint32_t)kSRC_Cpu1SuspendModeAssertReset); SRC_EnableDomainModeTransferReset(SRC, kSRC_M4DebugSlice, true); // h. Reset slice corresponding to CM7 Debug is controlled by entering of suspend mode. - SRC_SetAssignList(SRC, kSRC_M7DebugSlice, kSRC_CM7Core); - SRC_SetSliceDomainModeConfig(SRC, kSRC_M7DebugSlice, kSRC_Cpu0SuspendModeAssertReset); + SRC_SetAssignList(SRC, kSRC_M7DebugSlice, (uint32_t)kSRC_CM7Core); + SRC_SetSliceDomainModeConfig(SRC, kSRC_M7DebugSlice, (uint32_t)kSRC_Cpu0SuspendModeAssertReset); SRC_EnableDomainModeTransferReset(SRC, kSRC_M7DebugSlice, true); // i. Reset slice corresponding to USBPHY1 and USBPHY2 is controlled by WAKEUP domain's setpoint request. SRC_EnableSetPointTransferReset(SRC, kSRC_Usbphy1Slice, true); @@ -1209,7 +1211,7 @@ static inline void RT1170_SetCore1PlatformSetpointMap(GPC_CPU_MODE_CTRL_Type *ba uint8_t i, j; uint32_t u32Tmp; - uint8_t coreSetpointMap[17U][17U] = PM_RT1170_CM4_COMPATIBLE_SETPOINT_MAP; + uint32_t coreSetpointMap[17U][17U] = PM_RT1170_CM4_COMPATIBLE_SETPOINT_MAP; // Enable CPU sleep hold. GPC_CM_EnableCpuSleepHold(base, true); @@ -1344,7 +1346,7 @@ static void RT1170_PreparePowerSetting(void) // 5. Control body bias via GPC, CM7 is responsible for this. /* Check if FBB need to be enabled in OverDrive(OD) mode. Note: FUSE could not be read out if OTP memory is powered off.*/ - if (((OCOTP->FUSEN[7].FUSE & 0x10U) >> 4U) != 1) + if (((OCOTP->FUSEN[7].FUSE & 0x10UL) >> 4UL) != 1UL) { PMU_GPCEnableBodyBias(kPMU_FBB_CM7, PM_RT1170_FBB_EN_SETPOINT_MAP); } @@ -1435,9 +1437,9 @@ static void RT1170_EnterPowerState(uint8_t stateIndex, pm_resc_mask_t *pSoftResc else { // 1. Get CPU mode to transit based on application request. - if (pSoftRescMask->rescMask[0] & (1UL << kResc_CPU_PLATFORM)) + if ((pSoftRescMask->rescMask[0] & (1UL << kResc_CPU_PLATFORM)) != 0UL) { - switch (RT1170_FindOperateMode(kResc_CPU_PLATFORM, pSysRescGroup)) + switch (RT1170_FindOperateMode((uint32_t)kResc_CPU_PLATFORM, pSysRescGroup)) { case PM_RESOURCE_FULL_ON: // In case of application request PM_RESC_CORE_DOMAIN_RUN. @@ -1495,7 +1497,7 @@ static void RT1170_EnterPowerState(uint8_t stateIndex, pm_resc_mask_t *pSoftResc GPC_CM_ClearStandbyModeRequest(CURRENT_GPC_INSTANCE, kGPC_StopMode); GPC_CM_ClearStandbyModeRequest(CURRENT_GPC_INSTANCE, kGPC_SuspendMode); - if (RT1170_FindOperateMode(kResc_STBY_REQ, pSysRescGroup) != PM_RESOURCE_FULL_ON) + if (RT1170_FindOperateMode((uint32_t)kResc_STBY_REQ, pSysRescGroup) != PM_RESOURCE_FULL_ON) { // If not request to de-assert standby request, assert standby request when CPU entering selected CPU // mode. @@ -1527,13 +1529,13 @@ static status_t RT1170_ManageWakeupSource(pm_wakeup_source_t *ws, bool enable) if (enable) { // Enabled selected wakeup source, including enable it in NVIC and GPC. - EnableIRQ((IRQn_Type)irqId); + (void)EnableIRQ((IRQn_Type)irqId); GPC_CM_EnableIrqWakeup(CURRENT_GPC_INSTANCE, irqId, true); } else { // Disable selected wakeup source, including disable it in NVIC and GPC. - DisableIRQ((IRQn_Type)irqId); + (void)DisableIRQ((IRQn_Type)irqId); GPC_CM_EnableIrqWakeup(CURRENT_GPC_INSTANCE, irqId, false); } diff --git a/components/power_manager/devices/MIMXRT1172/fsl_pm_device.c b/components/power_manager/devices/MIMXRT1172/fsl_pm_device.c index b078092b1..4ce3c7b6e 100644 --- a/components/power_manager/devices/MIMXRT1172/fsl_pm_device.c +++ b/components/power_manager/devices/MIMXRT1172/fsl_pm_device.c @@ -1,5 +1,5 @@ /* - * Copyright 2023 NXP + * Copyright 2023~2024 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -98,23 +98,23 @@ #define PM_RT1170_LPSR_ANA_LDO_LP_MODE_SETPOINT_MAP \ (0xFFFFU) // LPSR_ANA_LDO lowpower mode is disabled for all setpoints. #define PM_RT1170_LPSR_ANA_LDO_TRACKING_EN_SETPOINT_MAP \ - (~PM_RT1170_LPSR_ANA_LDO_EN_SETPOINT_MAP) // LPSR_ANA_DO tracking is enabled + ((uint32_t)(~PM_RT1170_LPSR_ANA_LDO_EN_SETPOINT_MAP)) // LPSR_ANA_DO tracking is enabled // from setpoint 0 to setpoint 10. #define PM_RT1170_LPSR_ANA_LDO_BYPASS_EN_SETPOINT_MAP \ - (~PM_RT1170_LPSR_ANA_LDO_EN_SETPOINT_MAP) // LPSR_ANA_DO bypass is enabled from + ((uint32_t)(~PM_RT1170_LPSR_ANA_LDO_EN_SETPOINT_MAP)) // LPSR_ANA_DO bypass is enabled from // setpoint 0 to setpoint 10. #define PM_RT1170_LPSR_DIG_LDO_EN_SETPOINT_MAP \ - (0xF81C) // LPSR_DIG_DO is enabled from setpoint 2 to setpoint 4, + (0xF81CU) // LPSR_DIG_DO is enabled from setpoint 2 to setpoint 4, // and setpoint 11 to setpoint 15. #define PM_RT1170_LPSR_DIG_LDO_STANDBY_SETPOINT_MAP (0xFFFFU) // LPSR_DIG_DO standby mode is disabled for all setpoints. #define PM_RT1170_LPSR_DIG_LDO_LP_MODE_SETPOINT_MAP \ (0xFFFFU) // LPSR_DIG_DO lowpower mode is disabled for all setpoints. #define PM_RT1170_LPSR_DIG_LDO_TRACKING_EN_SETPOINT_MAP \ - (~PM_RT1170_LPSR_DIG_LDO_EN_SETPOINT_MAP) // LPSR_DIG_DO tracking is enabled + ((uint32_t)(~PM_RT1170_LPSR_DIG_LDO_EN_SETPOINT_MAP)) // LPSR_DIG_DO tracking is enabled // from setpoint 0 to setpoint 1, // and setpoint 5 to setpoint 10. #define PM_RT1170_LPSR_DIG_LDO_BYPASS_EN_SETPOINT_MAP \ - (~PM_RT1170_LPSR_DIG_LDO_EN_SETPOINT_MAP) // LPSR_DIG_DO bypass is enabled from + ((uint32_t)(~PM_RT1170_LPSR_DIG_LDO_EN_SETPOINT_MAP)) // LPSR_DIG_DO bypass is enabled from // setpoint 0 to setpoint 1, // and setpoint 5 to setpoint 10. @@ -212,6 +212,7 @@ static bool RT1170_IsWakeupSource(pm_wakeup_source_t *ws); ******************************************************************************/ #if __CORTEX_M == 7 +extern const uint16_t g_clockSourceSpMapping[29U]; const uint16_t g_clockSourceSpMapping[29U] = { 0xFFFFU, /*!< Clock Source OSCPLL0: 16MHz RC OSC output, turn on in all setpoints. */ 0x0000U, /*!< Clock Source OSCPLL1: 48MHz RC OSC output, turn off in all setpoints. */ @@ -831,17 +832,18 @@ const pm_device_option_t g_devicePMOption = { */ static inline uint8_t RT1170_FindOperateMode(uint32_t rescIndex, pm_resc_group_t *pSysRescGroup) { - uint8_t u8Tmp = (pSysRescGroup->groupSlice[rescIndex / 8UL] >> (4UL * (rescIndex % 8UL))) & 0xFUL; + uint32_t u32Tmp = (pSysRescGroup->groupSlice[rescIndex / 8UL] >> (4UL * (rescIndex % 8UL))) & 0xFUL; // Find first set, that is the operate mode to set. - u8Tmp |= (u8Tmp >> 1U); - u8Tmp |= (u8Tmp >> 2U); + u32Tmp |= (u32Tmp >> 1U); + u32Tmp |= (u32Tmp >> 2U); - return ((u8Tmp + 1U) >> 1U); + return (uint8_t)(uint32_t)((u32Tmp + 1UL) >> 1UL); } #if __CORTEX_M == 7 /*! + * @brief Configure setpoint mapping for CM7. */ static inline void RT1170_SetCore0PlatformSetpointMap(GPC_CPU_MODE_CTRL_Type *base) @@ -849,7 +851,7 @@ static inline void RT1170_SetCore0PlatformSetpointMap(GPC_CPU_MODE_CTRL_Type *ba uint8_t i, j; uint32_t u32Tmp; - uint8_t coreSetpointMap[17U][17U] = PM_RT1170_CM7_COMPATIBLE_SETPOINT_MAP; + uint32_t coreSetpointMap[17U][17U] = PM_RT1170_CM7_COMPATIBLE_SETPOINT_MAP; // Enable CPU sleep hold. GPC_CM_EnableCpuSleepHold(base, true); @@ -893,15 +895,15 @@ static inline void RT1170_SetClockSourcesControlBySetpoint(void) ANADIG_PLL->PLL_AUDIO_CTRL &= ~ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_MASK; ANADIG_PLL->PLL_VIDEO_CTRL &= ~ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_MASK; - clock_name_t clockSourceName = kCLOCK_OscRc16M; - for (clockSourceName = kCLOCK_OscRc16M; clockSourceName <= kCLOCK_VideoPllOut; clockSourceName++) + uint8_t clockSourceName = (uint8_t)kCLOCK_OscRc16M; + for (clockSourceName = (uint8_t)kCLOCK_OscRc16M; clockSourceName <= (uint8_t)kCLOCK_VideoPllOut; clockSourceName++) { if (!CLOCK_OSCPLL_IsSetPointImplemented((clock_name_t)clockSourceName)) { assert(0); } // keep clock source init state aligned with set point 0 state. - if ((g_clockSourceSpMapping[(uint8_t)clockSourceName] & 0x1) == 0) + if ((g_clockSourceSpMapping[(uint8_t)clockSourceName] & (uint16_t)0x1U) == (uint16_t)0U) { CCM->OSCPLL[(uint8_t)clockSourceName].DIRECT = 0; } @@ -910,12 +912,12 @@ static inline void RT1170_SetClockSourcesControlBySetpoint(void) CCM->OSCPLL[(uint8_t)clockSourceName].DIRECT = 1; } // All clock sources except OSC_RC 16M are turned off in standby mode. - uint32_t standbyValue = 0UL; - if (clockSourceName == kCLOCK_OscRc16M) + uint16_t standbyValue = 0U; + if ((clock_name_t)clockSourceName == kCLOCK_OscRc16M) { standbyValue = 0xFFFFU; } - CLOCK_OSCPLL_ControlBySetPointMode(clockSourceName, g_clockSourceSpMapping[(uint8_t)clockSourceName], + CLOCK_OSCPLL_ControlBySetPointMode((clock_name_t)clockSourceName, g_clockSourceSpMapping[(uint8_t)clockSourceName], standbyValue); } @@ -1000,7 +1002,7 @@ static inline void RT1170_SetPowerSupplyControlBySetpoint(void) PMU_GPCEnableLdoBypassMode(kPMU_LpsrDigLdo, PM_RT1170_LPSR_DIG_LDO_BYPASS_EN_SETPOINT_MAP); for (uint8_t i = 0U; i < 16U; i++) { - PMU_GPCSetLpsrDigLdoTargetVoltage(1U << i, g_lpsrDigLdoTargetVoltage[i]); + PMU_GPCSetLpsrDigLdoTargetVoltage(1UL << i, g_lpsrDigLdoTargetVoltage[i]); } PMU_SetLpsrDigLdoControlMode(ANADIG_LDO_SNVS, kPMU_GPCMode); @@ -1032,20 +1034,20 @@ static inline void RT1170_SetSRCControlMode(void) SRC_EnableSetPointTransferReset(SRC, kSRC_LpsrSlice, true); SRC_SetSliceSetPointConfig(SRC, kSRC_LpsrSlice, PM_RT1170_LPSRMIX_SETPOINT_MAP); // e. Reset slice corresponding to Cortex-M4 platform is controlled by entering of suspend mode. - SRC_SetAssignList(SRC, kSRC_M4CoreSlice, kSRC_CM4Core); - SRC_SetSliceDomainModeConfig(SRC, kSRC_M4CoreSlice, kSRC_Cpu1SuspendModeAssertReset); + SRC_SetAssignList(SRC, kSRC_M4CoreSlice, (uint32_t)kSRC_CM4Core); + SRC_SetSliceDomainModeConfig(SRC, kSRC_M4CoreSlice, (uint32_t)kSRC_Cpu1SuspendModeAssertReset); SRC_EnableDomainModeTransferReset(SRC, kSRC_M4CoreSlice, true); // f. Reset slice corresponding to Cortex-M7 platform is controlled by entering of suspend mode. - SRC_SetAssignList(SRC, kSRC_M7CoreSlice, kSRC_CM7Core); - SRC_SetSliceDomainModeConfig(SRC, kSRC_M7CoreSlice, kSRC_Cpu0SuspendModeAssertReset); + SRC_SetAssignList(SRC, kSRC_M7CoreSlice, (uint32_t)kSRC_CM7Core); + SRC_SetSliceDomainModeConfig(SRC, kSRC_M7CoreSlice, (uint32_t)kSRC_Cpu0SuspendModeAssertReset); SRC_EnableDomainModeTransferReset(SRC, kSRC_M7CoreSlice, true); // g. Reset slice corresponding to CM4 Debug is controlled by entering of suspend mode. - SRC_SetAssignList(SRC, kSRC_M4DebugSlice, kSRC_CM4Core); - SRC_SetSliceDomainModeConfig(SRC, kSRC_M4DebugSlice, kSRC_Cpu1SuspendModeAssertReset); + SRC_SetAssignList(SRC, kSRC_M4DebugSlice, (uint32_t)kSRC_CM4Core); + SRC_SetSliceDomainModeConfig(SRC, kSRC_M4DebugSlice, (uint32_t)kSRC_Cpu1SuspendModeAssertReset); SRC_EnableDomainModeTransferReset(SRC, kSRC_M4DebugSlice, true); // h. Reset slice corresponding to CM7 Debug is controlled by entering of suspend mode. - SRC_SetAssignList(SRC, kSRC_M7DebugSlice, kSRC_CM7Core); - SRC_SetSliceDomainModeConfig(SRC, kSRC_M7DebugSlice, kSRC_Cpu0SuspendModeAssertReset); + SRC_SetAssignList(SRC, kSRC_M7DebugSlice, (uint32_t)kSRC_CM7Core); + SRC_SetSliceDomainModeConfig(SRC, kSRC_M7DebugSlice, (uint32_t)kSRC_Cpu0SuspendModeAssertReset); SRC_EnableDomainModeTransferReset(SRC, kSRC_M7DebugSlice, true); // i. Reset slice corresponding to USBPHY1 and USBPHY2 is controlled by WAKEUP domain's setpoint request. SRC_EnableSetPointTransferReset(SRC, kSRC_Usbphy1Slice, true); @@ -1209,7 +1211,7 @@ static inline void RT1170_SetCore1PlatformSetpointMap(GPC_CPU_MODE_CTRL_Type *ba uint8_t i, j; uint32_t u32Tmp; - uint8_t coreSetpointMap[17U][17U] = PM_RT1170_CM4_COMPATIBLE_SETPOINT_MAP; + uint32_t coreSetpointMap[17U][17U] = PM_RT1170_CM4_COMPATIBLE_SETPOINT_MAP; // Enable CPU sleep hold. GPC_CM_EnableCpuSleepHold(base, true); @@ -1344,7 +1346,7 @@ static void RT1170_PreparePowerSetting(void) // 5. Control body bias via GPC, CM7 is responsible for this. /* Check if FBB need to be enabled in OverDrive(OD) mode. Note: FUSE could not be read out if OTP memory is powered off.*/ - if (((OCOTP->FUSEN[7].FUSE & 0x10U) >> 4U) != 1) + if (((OCOTP->FUSEN[7].FUSE & 0x10UL) >> 4UL) != 1UL) { PMU_GPCEnableBodyBias(kPMU_FBB_CM7, PM_RT1170_FBB_EN_SETPOINT_MAP); } @@ -1435,9 +1437,9 @@ static void RT1170_EnterPowerState(uint8_t stateIndex, pm_resc_mask_t *pSoftResc else { // 1. Get CPU mode to transit based on application request. - if (pSoftRescMask->rescMask[0] & (1UL << kResc_CPU_PLATFORM)) + if ((pSoftRescMask->rescMask[0] & (1UL << kResc_CPU_PLATFORM)) != 0UL) { - switch (RT1170_FindOperateMode(kResc_CPU_PLATFORM, pSysRescGroup)) + switch (RT1170_FindOperateMode((uint32_t)kResc_CPU_PLATFORM, pSysRescGroup)) { case PM_RESOURCE_FULL_ON: // In case of application request PM_RESC_CORE_DOMAIN_RUN. @@ -1495,7 +1497,7 @@ static void RT1170_EnterPowerState(uint8_t stateIndex, pm_resc_mask_t *pSoftResc GPC_CM_ClearStandbyModeRequest(CURRENT_GPC_INSTANCE, kGPC_StopMode); GPC_CM_ClearStandbyModeRequest(CURRENT_GPC_INSTANCE, kGPC_SuspendMode); - if (RT1170_FindOperateMode(kResc_STBY_REQ, pSysRescGroup) != PM_RESOURCE_FULL_ON) + if (RT1170_FindOperateMode((uint32_t)kResc_STBY_REQ, pSysRescGroup) != PM_RESOURCE_FULL_ON) { // If not request to de-assert standby request, assert standby request when CPU entering selected CPU // mode. @@ -1527,13 +1529,13 @@ static status_t RT1170_ManageWakeupSource(pm_wakeup_source_t *ws, bool enable) if (enable) { // Enabled selected wakeup source, including enable it in NVIC and GPC. - EnableIRQ((IRQn_Type)irqId); + (void)EnableIRQ((IRQn_Type)irqId); GPC_CM_EnableIrqWakeup(CURRENT_GPC_INSTANCE, irqId, true); } else { // Disable selected wakeup source, including disable it in NVIC and GPC. - DisableIRQ((IRQn_Type)irqId); + (void)DisableIRQ((IRQn_Type)irqId); GPC_CM_EnableIrqWakeup(CURRENT_GPC_INSTANCE, irqId, false); } diff --git a/components/power_manager/devices/MIMXRT1173/fsl_pm_device.c b/components/power_manager/devices/MIMXRT1173/fsl_pm_device.c index b078092b1..4ce3c7b6e 100644 --- a/components/power_manager/devices/MIMXRT1173/fsl_pm_device.c +++ b/components/power_manager/devices/MIMXRT1173/fsl_pm_device.c @@ -1,5 +1,5 @@ /* - * Copyright 2023 NXP + * Copyright 2023~2024 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -98,23 +98,23 @@ #define PM_RT1170_LPSR_ANA_LDO_LP_MODE_SETPOINT_MAP \ (0xFFFFU) // LPSR_ANA_LDO lowpower mode is disabled for all setpoints. #define PM_RT1170_LPSR_ANA_LDO_TRACKING_EN_SETPOINT_MAP \ - (~PM_RT1170_LPSR_ANA_LDO_EN_SETPOINT_MAP) // LPSR_ANA_DO tracking is enabled + ((uint32_t)(~PM_RT1170_LPSR_ANA_LDO_EN_SETPOINT_MAP)) // LPSR_ANA_DO tracking is enabled // from setpoint 0 to setpoint 10. #define PM_RT1170_LPSR_ANA_LDO_BYPASS_EN_SETPOINT_MAP \ - (~PM_RT1170_LPSR_ANA_LDO_EN_SETPOINT_MAP) // LPSR_ANA_DO bypass is enabled from + ((uint32_t)(~PM_RT1170_LPSR_ANA_LDO_EN_SETPOINT_MAP)) // LPSR_ANA_DO bypass is enabled from // setpoint 0 to setpoint 10. #define PM_RT1170_LPSR_DIG_LDO_EN_SETPOINT_MAP \ - (0xF81C) // LPSR_DIG_DO is enabled from setpoint 2 to setpoint 4, + (0xF81CU) // LPSR_DIG_DO is enabled from setpoint 2 to setpoint 4, // and setpoint 11 to setpoint 15. #define PM_RT1170_LPSR_DIG_LDO_STANDBY_SETPOINT_MAP (0xFFFFU) // LPSR_DIG_DO standby mode is disabled for all setpoints. #define PM_RT1170_LPSR_DIG_LDO_LP_MODE_SETPOINT_MAP \ (0xFFFFU) // LPSR_DIG_DO lowpower mode is disabled for all setpoints. #define PM_RT1170_LPSR_DIG_LDO_TRACKING_EN_SETPOINT_MAP \ - (~PM_RT1170_LPSR_DIG_LDO_EN_SETPOINT_MAP) // LPSR_DIG_DO tracking is enabled + ((uint32_t)(~PM_RT1170_LPSR_DIG_LDO_EN_SETPOINT_MAP)) // LPSR_DIG_DO tracking is enabled // from setpoint 0 to setpoint 1, // and setpoint 5 to setpoint 10. #define PM_RT1170_LPSR_DIG_LDO_BYPASS_EN_SETPOINT_MAP \ - (~PM_RT1170_LPSR_DIG_LDO_EN_SETPOINT_MAP) // LPSR_DIG_DO bypass is enabled from + ((uint32_t)(~PM_RT1170_LPSR_DIG_LDO_EN_SETPOINT_MAP)) // LPSR_DIG_DO bypass is enabled from // setpoint 0 to setpoint 1, // and setpoint 5 to setpoint 10. @@ -212,6 +212,7 @@ static bool RT1170_IsWakeupSource(pm_wakeup_source_t *ws); ******************************************************************************/ #if __CORTEX_M == 7 +extern const uint16_t g_clockSourceSpMapping[29U]; const uint16_t g_clockSourceSpMapping[29U] = { 0xFFFFU, /*!< Clock Source OSCPLL0: 16MHz RC OSC output, turn on in all setpoints. */ 0x0000U, /*!< Clock Source OSCPLL1: 48MHz RC OSC output, turn off in all setpoints. */ @@ -831,17 +832,18 @@ const pm_device_option_t g_devicePMOption = { */ static inline uint8_t RT1170_FindOperateMode(uint32_t rescIndex, pm_resc_group_t *pSysRescGroup) { - uint8_t u8Tmp = (pSysRescGroup->groupSlice[rescIndex / 8UL] >> (4UL * (rescIndex % 8UL))) & 0xFUL; + uint32_t u32Tmp = (pSysRescGroup->groupSlice[rescIndex / 8UL] >> (4UL * (rescIndex % 8UL))) & 0xFUL; // Find first set, that is the operate mode to set. - u8Tmp |= (u8Tmp >> 1U); - u8Tmp |= (u8Tmp >> 2U); + u32Tmp |= (u32Tmp >> 1U); + u32Tmp |= (u32Tmp >> 2U); - return ((u8Tmp + 1U) >> 1U); + return (uint8_t)(uint32_t)((u32Tmp + 1UL) >> 1UL); } #if __CORTEX_M == 7 /*! + * @brief Configure setpoint mapping for CM7. */ static inline void RT1170_SetCore0PlatformSetpointMap(GPC_CPU_MODE_CTRL_Type *base) @@ -849,7 +851,7 @@ static inline void RT1170_SetCore0PlatformSetpointMap(GPC_CPU_MODE_CTRL_Type *ba uint8_t i, j; uint32_t u32Tmp; - uint8_t coreSetpointMap[17U][17U] = PM_RT1170_CM7_COMPATIBLE_SETPOINT_MAP; + uint32_t coreSetpointMap[17U][17U] = PM_RT1170_CM7_COMPATIBLE_SETPOINT_MAP; // Enable CPU sleep hold. GPC_CM_EnableCpuSleepHold(base, true); @@ -893,15 +895,15 @@ static inline void RT1170_SetClockSourcesControlBySetpoint(void) ANADIG_PLL->PLL_AUDIO_CTRL &= ~ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_MASK; ANADIG_PLL->PLL_VIDEO_CTRL &= ~ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_MASK; - clock_name_t clockSourceName = kCLOCK_OscRc16M; - for (clockSourceName = kCLOCK_OscRc16M; clockSourceName <= kCLOCK_VideoPllOut; clockSourceName++) + uint8_t clockSourceName = (uint8_t)kCLOCK_OscRc16M; + for (clockSourceName = (uint8_t)kCLOCK_OscRc16M; clockSourceName <= (uint8_t)kCLOCK_VideoPllOut; clockSourceName++) { if (!CLOCK_OSCPLL_IsSetPointImplemented((clock_name_t)clockSourceName)) { assert(0); } // keep clock source init state aligned with set point 0 state. - if ((g_clockSourceSpMapping[(uint8_t)clockSourceName] & 0x1) == 0) + if ((g_clockSourceSpMapping[(uint8_t)clockSourceName] & (uint16_t)0x1U) == (uint16_t)0U) { CCM->OSCPLL[(uint8_t)clockSourceName].DIRECT = 0; } @@ -910,12 +912,12 @@ static inline void RT1170_SetClockSourcesControlBySetpoint(void) CCM->OSCPLL[(uint8_t)clockSourceName].DIRECT = 1; } // All clock sources except OSC_RC 16M are turned off in standby mode. - uint32_t standbyValue = 0UL; - if (clockSourceName == kCLOCK_OscRc16M) + uint16_t standbyValue = 0U; + if ((clock_name_t)clockSourceName == kCLOCK_OscRc16M) { standbyValue = 0xFFFFU; } - CLOCK_OSCPLL_ControlBySetPointMode(clockSourceName, g_clockSourceSpMapping[(uint8_t)clockSourceName], + CLOCK_OSCPLL_ControlBySetPointMode((clock_name_t)clockSourceName, g_clockSourceSpMapping[(uint8_t)clockSourceName], standbyValue); } @@ -1000,7 +1002,7 @@ static inline void RT1170_SetPowerSupplyControlBySetpoint(void) PMU_GPCEnableLdoBypassMode(kPMU_LpsrDigLdo, PM_RT1170_LPSR_DIG_LDO_BYPASS_EN_SETPOINT_MAP); for (uint8_t i = 0U; i < 16U; i++) { - PMU_GPCSetLpsrDigLdoTargetVoltage(1U << i, g_lpsrDigLdoTargetVoltage[i]); + PMU_GPCSetLpsrDigLdoTargetVoltage(1UL << i, g_lpsrDigLdoTargetVoltage[i]); } PMU_SetLpsrDigLdoControlMode(ANADIG_LDO_SNVS, kPMU_GPCMode); @@ -1032,20 +1034,20 @@ static inline void RT1170_SetSRCControlMode(void) SRC_EnableSetPointTransferReset(SRC, kSRC_LpsrSlice, true); SRC_SetSliceSetPointConfig(SRC, kSRC_LpsrSlice, PM_RT1170_LPSRMIX_SETPOINT_MAP); // e. Reset slice corresponding to Cortex-M4 platform is controlled by entering of suspend mode. - SRC_SetAssignList(SRC, kSRC_M4CoreSlice, kSRC_CM4Core); - SRC_SetSliceDomainModeConfig(SRC, kSRC_M4CoreSlice, kSRC_Cpu1SuspendModeAssertReset); + SRC_SetAssignList(SRC, kSRC_M4CoreSlice, (uint32_t)kSRC_CM4Core); + SRC_SetSliceDomainModeConfig(SRC, kSRC_M4CoreSlice, (uint32_t)kSRC_Cpu1SuspendModeAssertReset); SRC_EnableDomainModeTransferReset(SRC, kSRC_M4CoreSlice, true); // f. Reset slice corresponding to Cortex-M7 platform is controlled by entering of suspend mode. - SRC_SetAssignList(SRC, kSRC_M7CoreSlice, kSRC_CM7Core); - SRC_SetSliceDomainModeConfig(SRC, kSRC_M7CoreSlice, kSRC_Cpu0SuspendModeAssertReset); + SRC_SetAssignList(SRC, kSRC_M7CoreSlice, (uint32_t)kSRC_CM7Core); + SRC_SetSliceDomainModeConfig(SRC, kSRC_M7CoreSlice, (uint32_t)kSRC_Cpu0SuspendModeAssertReset); SRC_EnableDomainModeTransferReset(SRC, kSRC_M7CoreSlice, true); // g. Reset slice corresponding to CM4 Debug is controlled by entering of suspend mode. - SRC_SetAssignList(SRC, kSRC_M4DebugSlice, kSRC_CM4Core); - SRC_SetSliceDomainModeConfig(SRC, kSRC_M4DebugSlice, kSRC_Cpu1SuspendModeAssertReset); + SRC_SetAssignList(SRC, kSRC_M4DebugSlice, (uint32_t)kSRC_CM4Core); + SRC_SetSliceDomainModeConfig(SRC, kSRC_M4DebugSlice, (uint32_t)kSRC_Cpu1SuspendModeAssertReset); SRC_EnableDomainModeTransferReset(SRC, kSRC_M4DebugSlice, true); // h. Reset slice corresponding to CM7 Debug is controlled by entering of suspend mode. - SRC_SetAssignList(SRC, kSRC_M7DebugSlice, kSRC_CM7Core); - SRC_SetSliceDomainModeConfig(SRC, kSRC_M7DebugSlice, kSRC_Cpu0SuspendModeAssertReset); + SRC_SetAssignList(SRC, kSRC_M7DebugSlice, (uint32_t)kSRC_CM7Core); + SRC_SetSliceDomainModeConfig(SRC, kSRC_M7DebugSlice, (uint32_t)kSRC_Cpu0SuspendModeAssertReset); SRC_EnableDomainModeTransferReset(SRC, kSRC_M7DebugSlice, true); // i. Reset slice corresponding to USBPHY1 and USBPHY2 is controlled by WAKEUP domain's setpoint request. SRC_EnableSetPointTransferReset(SRC, kSRC_Usbphy1Slice, true); @@ -1209,7 +1211,7 @@ static inline void RT1170_SetCore1PlatformSetpointMap(GPC_CPU_MODE_CTRL_Type *ba uint8_t i, j; uint32_t u32Tmp; - uint8_t coreSetpointMap[17U][17U] = PM_RT1170_CM4_COMPATIBLE_SETPOINT_MAP; + uint32_t coreSetpointMap[17U][17U] = PM_RT1170_CM4_COMPATIBLE_SETPOINT_MAP; // Enable CPU sleep hold. GPC_CM_EnableCpuSleepHold(base, true); @@ -1344,7 +1346,7 @@ static void RT1170_PreparePowerSetting(void) // 5. Control body bias via GPC, CM7 is responsible for this. /* Check if FBB need to be enabled in OverDrive(OD) mode. Note: FUSE could not be read out if OTP memory is powered off.*/ - if (((OCOTP->FUSEN[7].FUSE & 0x10U) >> 4U) != 1) + if (((OCOTP->FUSEN[7].FUSE & 0x10UL) >> 4UL) != 1UL) { PMU_GPCEnableBodyBias(kPMU_FBB_CM7, PM_RT1170_FBB_EN_SETPOINT_MAP); } @@ -1435,9 +1437,9 @@ static void RT1170_EnterPowerState(uint8_t stateIndex, pm_resc_mask_t *pSoftResc else { // 1. Get CPU mode to transit based on application request. - if (pSoftRescMask->rescMask[0] & (1UL << kResc_CPU_PLATFORM)) + if ((pSoftRescMask->rescMask[0] & (1UL << kResc_CPU_PLATFORM)) != 0UL) { - switch (RT1170_FindOperateMode(kResc_CPU_PLATFORM, pSysRescGroup)) + switch (RT1170_FindOperateMode((uint32_t)kResc_CPU_PLATFORM, pSysRescGroup)) { case PM_RESOURCE_FULL_ON: // In case of application request PM_RESC_CORE_DOMAIN_RUN. @@ -1495,7 +1497,7 @@ static void RT1170_EnterPowerState(uint8_t stateIndex, pm_resc_mask_t *pSoftResc GPC_CM_ClearStandbyModeRequest(CURRENT_GPC_INSTANCE, kGPC_StopMode); GPC_CM_ClearStandbyModeRequest(CURRENT_GPC_INSTANCE, kGPC_SuspendMode); - if (RT1170_FindOperateMode(kResc_STBY_REQ, pSysRescGroup) != PM_RESOURCE_FULL_ON) + if (RT1170_FindOperateMode((uint32_t)kResc_STBY_REQ, pSysRescGroup) != PM_RESOURCE_FULL_ON) { // If not request to de-assert standby request, assert standby request when CPU entering selected CPU // mode. @@ -1527,13 +1529,13 @@ static status_t RT1170_ManageWakeupSource(pm_wakeup_source_t *ws, bool enable) if (enable) { // Enabled selected wakeup source, including enable it in NVIC and GPC. - EnableIRQ((IRQn_Type)irqId); + (void)EnableIRQ((IRQn_Type)irqId); GPC_CM_EnableIrqWakeup(CURRENT_GPC_INSTANCE, irqId, true); } else { // Disable selected wakeup source, including disable it in NVIC and GPC. - DisableIRQ((IRQn_Type)irqId); + (void)DisableIRQ((IRQn_Type)irqId); GPC_CM_EnableIrqWakeup(CURRENT_GPC_INSTANCE, irqId, false); } diff --git a/components/power_manager/devices/MIMXRT1175/fsl_pm_device.c b/components/power_manager/devices/MIMXRT1175/fsl_pm_device.c index b078092b1..4ce3c7b6e 100644 --- a/components/power_manager/devices/MIMXRT1175/fsl_pm_device.c +++ b/components/power_manager/devices/MIMXRT1175/fsl_pm_device.c @@ -1,5 +1,5 @@ /* - * Copyright 2023 NXP + * Copyright 2023~2024 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -98,23 +98,23 @@ #define PM_RT1170_LPSR_ANA_LDO_LP_MODE_SETPOINT_MAP \ (0xFFFFU) // LPSR_ANA_LDO lowpower mode is disabled for all setpoints. #define PM_RT1170_LPSR_ANA_LDO_TRACKING_EN_SETPOINT_MAP \ - (~PM_RT1170_LPSR_ANA_LDO_EN_SETPOINT_MAP) // LPSR_ANA_DO tracking is enabled + ((uint32_t)(~PM_RT1170_LPSR_ANA_LDO_EN_SETPOINT_MAP)) // LPSR_ANA_DO tracking is enabled // from setpoint 0 to setpoint 10. #define PM_RT1170_LPSR_ANA_LDO_BYPASS_EN_SETPOINT_MAP \ - (~PM_RT1170_LPSR_ANA_LDO_EN_SETPOINT_MAP) // LPSR_ANA_DO bypass is enabled from + ((uint32_t)(~PM_RT1170_LPSR_ANA_LDO_EN_SETPOINT_MAP)) // LPSR_ANA_DO bypass is enabled from // setpoint 0 to setpoint 10. #define PM_RT1170_LPSR_DIG_LDO_EN_SETPOINT_MAP \ - (0xF81C) // LPSR_DIG_DO is enabled from setpoint 2 to setpoint 4, + (0xF81CU) // LPSR_DIG_DO is enabled from setpoint 2 to setpoint 4, // and setpoint 11 to setpoint 15. #define PM_RT1170_LPSR_DIG_LDO_STANDBY_SETPOINT_MAP (0xFFFFU) // LPSR_DIG_DO standby mode is disabled for all setpoints. #define PM_RT1170_LPSR_DIG_LDO_LP_MODE_SETPOINT_MAP \ (0xFFFFU) // LPSR_DIG_DO lowpower mode is disabled for all setpoints. #define PM_RT1170_LPSR_DIG_LDO_TRACKING_EN_SETPOINT_MAP \ - (~PM_RT1170_LPSR_DIG_LDO_EN_SETPOINT_MAP) // LPSR_DIG_DO tracking is enabled + ((uint32_t)(~PM_RT1170_LPSR_DIG_LDO_EN_SETPOINT_MAP)) // LPSR_DIG_DO tracking is enabled // from setpoint 0 to setpoint 1, // and setpoint 5 to setpoint 10. #define PM_RT1170_LPSR_DIG_LDO_BYPASS_EN_SETPOINT_MAP \ - (~PM_RT1170_LPSR_DIG_LDO_EN_SETPOINT_MAP) // LPSR_DIG_DO bypass is enabled from + ((uint32_t)(~PM_RT1170_LPSR_DIG_LDO_EN_SETPOINT_MAP)) // LPSR_DIG_DO bypass is enabled from // setpoint 0 to setpoint 1, // and setpoint 5 to setpoint 10. @@ -212,6 +212,7 @@ static bool RT1170_IsWakeupSource(pm_wakeup_source_t *ws); ******************************************************************************/ #if __CORTEX_M == 7 +extern const uint16_t g_clockSourceSpMapping[29U]; const uint16_t g_clockSourceSpMapping[29U] = { 0xFFFFU, /*!< Clock Source OSCPLL0: 16MHz RC OSC output, turn on in all setpoints. */ 0x0000U, /*!< Clock Source OSCPLL1: 48MHz RC OSC output, turn off in all setpoints. */ @@ -831,17 +832,18 @@ const pm_device_option_t g_devicePMOption = { */ static inline uint8_t RT1170_FindOperateMode(uint32_t rescIndex, pm_resc_group_t *pSysRescGroup) { - uint8_t u8Tmp = (pSysRescGroup->groupSlice[rescIndex / 8UL] >> (4UL * (rescIndex % 8UL))) & 0xFUL; + uint32_t u32Tmp = (pSysRescGroup->groupSlice[rescIndex / 8UL] >> (4UL * (rescIndex % 8UL))) & 0xFUL; // Find first set, that is the operate mode to set. - u8Tmp |= (u8Tmp >> 1U); - u8Tmp |= (u8Tmp >> 2U); + u32Tmp |= (u32Tmp >> 1U); + u32Tmp |= (u32Tmp >> 2U); - return ((u8Tmp + 1U) >> 1U); + return (uint8_t)(uint32_t)((u32Tmp + 1UL) >> 1UL); } #if __CORTEX_M == 7 /*! + * @brief Configure setpoint mapping for CM7. */ static inline void RT1170_SetCore0PlatformSetpointMap(GPC_CPU_MODE_CTRL_Type *base) @@ -849,7 +851,7 @@ static inline void RT1170_SetCore0PlatformSetpointMap(GPC_CPU_MODE_CTRL_Type *ba uint8_t i, j; uint32_t u32Tmp; - uint8_t coreSetpointMap[17U][17U] = PM_RT1170_CM7_COMPATIBLE_SETPOINT_MAP; + uint32_t coreSetpointMap[17U][17U] = PM_RT1170_CM7_COMPATIBLE_SETPOINT_MAP; // Enable CPU sleep hold. GPC_CM_EnableCpuSleepHold(base, true); @@ -893,15 +895,15 @@ static inline void RT1170_SetClockSourcesControlBySetpoint(void) ANADIG_PLL->PLL_AUDIO_CTRL &= ~ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_MASK; ANADIG_PLL->PLL_VIDEO_CTRL &= ~ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_MASK; - clock_name_t clockSourceName = kCLOCK_OscRc16M; - for (clockSourceName = kCLOCK_OscRc16M; clockSourceName <= kCLOCK_VideoPllOut; clockSourceName++) + uint8_t clockSourceName = (uint8_t)kCLOCK_OscRc16M; + for (clockSourceName = (uint8_t)kCLOCK_OscRc16M; clockSourceName <= (uint8_t)kCLOCK_VideoPllOut; clockSourceName++) { if (!CLOCK_OSCPLL_IsSetPointImplemented((clock_name_t)clockSourceName)) { assert(0); } // keep clock source init state aligned with set point 0 state. - if ((g_clockSourceSpMapping[(uint8_t)clockSourceName] & 0x1) == 0) + if ((g_clockSourceSpMapping[(uint8_t)clockSourceName] & (uint16_t)0x1U) == (uint16_t)0U) { CCM->OSCPLL[(uint8_t)clockSourceName].DIRECT = 0; } @@ -910,12 +912,12 @@ static inline void RT1170_SetClockSourcesControlBySetpoint(void) CCM->OSCPLL[(uint8_t)clockSourceName].DIRECT = 1; } // All clock sources except OSC_RC 16M are turned off in standby mode. - uint32_t standbyValue = 0UL; - if (clockSourceName == kCLOCK_OscRc16M) + uint16_t standbyValue = 0U; + if ((clock_name_t)clockSourceName == kCLOCK_OscRc16M) { standbyValue = 0xFFFFU; } - CLOCK_OSCPLL_ControlBySetPointMode(clockSourceName, g_clockSourceSpMapping[(uint8_t)clockSourceName], + CLOCK_OSCPLL_ControlBySetPointMode((clock_name_t)clockSourceName, g_clockSourceSpMapping[(uint8_t)clockSourceName], standbyValue); } @@ -1000,7 +1002,7 @@ static inline void RT1170_SetPowerSupplyControlBySetpoint(void) PMU_GPCEnableLdoBypassMode(kPMU_LpsrDigLdo, PM_RT1170_LPSR_DIG_LDO_BYPASS_EN_SETPOINT_MAP); for (uint8_t i = 0U; i < 16U; i++) { - PMU_GPCSetLpsrDigLdoTargetVoltage(1U << i, g_lpsrDigLdoTargetVoltage[i]); + PMU_GPCSetLpsrDigLdoTargetVoltage(1UL << i, g_lpsrDigLdoTargetVoltage[i]); } PMU_SetLpsrDigLdoControlMode(ANADIG_LDO_SNVS, kPMU_GPCMode); @@ -1032,20 +1034,20 @@ static inline void RT1170_SetSRCControlMode(void) SRC_EnableSetPointTransferReset(SRC, kSRC_LpsrSlice, true); SRC_SetSliceSetPointConfig(SRC, kSRC_LpsrSlice, PM_RT1170_LPSRMIX_SETPOINT_MAP); // e. Reset slice corresponding to Cortex-M4 platform is controlled by entering of suspend mode. - SRC_SetAssignList(SRC, kSRC_M4CoreSlice, kSRC_CM4Core); - SRC_SetSliceDomainModeConfig(SRC, kSRC_M4CoreSlice, kSRC_Cpu1SuspendModeAssertReset); + SRC_SetAssignList(SRC, kSRC_M4CoreSlice, (uint32_t)kSRC_CM4Core); + SRC_SetSliceDomainModeConfig(SRC, kSRC_M4CoreSlice, (uint32_t)kSRC_Cpu1SuspendModeAssertReset); SRC_EnableDomainModeTransferReset(SRC, kSRC_M4CoreSlice, true); // f. Reset slice corresponding to Cortex-M7 platform is controlled by entering of suspend mode. - SRC_SetAssignList(SRC, kSRC_M7CoreSlice, kSRC_CM7Core); - SRC_SetSliceDomainModeConfig(SRC, kSRC_M7CoreSlice, kSRC_Cpu0SuspendModeAssertReset); + SRC_SetAssignList(SRC, kSRC_M7CoreSlice, (uint32_t)kSRC_CM7Core); + SRC_SetSliceDomainModeConfig(SRC, kSRC_M7CoreSlice, (uint32_t)kSRC_Cpu0SuspendModeAssertReset); SRC_EnableDomainModeTransferReset(SRC, kSRC_M7CoreSlice, true); // g. Reset slice corresponding to CM4 Debug is controlled by entering of suspend mode. - SRC_SetAssignList(SRC, kSRC_M4DebugSlice, kSRC_CM4Core); - SRC_SetSliceDomainModeConfig(SRC, kSRC_M4DebugSlice, kSRC_Cpu1SuspendModeAssertReset); + SRC_SetAssignList(SRC, kSRC_M4DebugSlice, (uint32_t)kSRC_CM4Core); + SRC_SetSliceDomainModeConfig(SRC, kSRC_M4DebugSlice, (uint32_t)kSRC_Cpu1SuspendModeAssertReset); SRC_EnableDomainModeTransferReset(SRC, kSRC_M4DebugSlice, true); // h. Reset slice corresponding to CM7 Debug is controlled by entering of suspend mode. - SRC_SetAssignList(SRC, kSRC_M7DebugSlice, kSRC_CM7Core); - SRC_SetSliceDomainModeConfig(SRC, kSRC_M7DebugSlice, kSRC_Cpu0SuspendModeAssertReset); + SRC_SetAssignList(SRC, kSRC_M7DebugSlice, (uint32_t)kSRC_CM7Core); + SRC_SetSliceDomainModeConfig(SRC, kSRC_M7DebugSlice, (uint32_t)kSRC_Cpu0SuspendModeAssertReset); SRC_EnableDomainModeTransferReset(SRC, kSRC_M7DebugSlice, true); // i. Reset slice corresponding to USBPHY1 and USBPHY2 is controlled by WAKEUP domain's setpoint request. SRC_EnableSetPointTransferReset(SRC, kSRC_Usbphy1Slice, true); @@ -1209,7 +1211,7 @@ static inline void RT1170_SetCore1PlatformSetpointMap(GPC_CPU_MODE_CTRL_Type *ba uint8_t i, j; uint32_t u32Tmp; - uint8_t coreSetpointMap[17U][17U] = PM_RT1170_CM4_COMPATIBLE_SETPOINT_MAP; + uint32_t coreSetpointMap[17U][17U] = PM_RT1170_CM4_COMPATIBLE_SETPOINT_MAP; // Enable CPU sleep hold. GPC_CM_EnableCpuSleepHold(base, true); @@ -1344,7 +1346,7 @@ static void RT1170_PreparePowerSetting(void) // 5. Control body bias via GPC, CM7 is responsible for this. /* Check if FBB need to be enabled in OverDrive(OD) mode. Note: FUSE could not be read out if OTP memory is powered off.*/ - if (((OCOTP->FUSEN[7].FUSE & 0x10U) >> 4U) != 1) + if (((OCOTP->FUSEN[7].FUSE & 0x10UL) >> 4UL) != 1UL) { PMU_GPCEnableBodyBias(kPMU_FBB_CM7, PM_RT1170_FBB_EN_SETPOINT_MAP); } @@ -1435,9 +1437,9 @@ static void RT1170_EnterPowerState(uint8_t stateIndex, pm_resc_mask_t *pSoftResc else { // 1. Get CPU mode to transit based on application request. - if (pSoftRescMask->rescMask[0] & (1UL << kResc_CPU_PLATFORM)) + if ((pSoftRescMask->rescMask[0] & (1UL << kResc_CPU_PLATFORM)) != 0UL) { - switch (RT1170_FindOperateMode(kResc_CPU_PLATFORM, pSysRescGroup)) + switch (RT1170_FindOperateMode((uint32_t)kResc_CPU_PLATFORM, pSysRescGroup)) { case PM_RESOURCE_FULL_ON: // In case of application request PM_RESC_CORE_DOMAIN_RUN. @@ -1495,7 +1497,7 @@ static void RT1170_EnterPowerState(uint8_t stateIndex, pm_resc_mask_t *pSoftResc GPC_CM_ClearStandbyModeRequest(CURRENT_GPC_INSTANCE, kGPC_StopMode); GPC_CM_ClearStandbyModeRequest(CURRENT_GPC_INSTANCE, kGPC_SuspendMode); - if (RT1170_FindOperateMode(kResc_STBY_REQ, pSysRescGroup) != PM_RESOURCE_FULL_ON) + if (RT1170_FindOperateMode((uint32_t)kResc_STBY_REQ, pSysRescGroup) != PM_RESOURCE_FULL_ON) { // If not request to de-assert standby request, assert standby request when CPU entering selected CPU // mode. @@ -1527,13 +1529,13 @@ static status_t RT1170_ManageWakeupSource(pm_wakeup_source_t *ws, bool enable) if (enable) { // Enabled selected wakeup source, including enable it in NVIC and GPC. - EnableIRQ((IRQn_Type)irqId); + (void)EnableIRQ((IRQn_Type)irqId); GPC_CM_EnableIrqWakeup(CURRENT_GPC_INSTANCE, irqId, true); } else { // Disable selected wakeup source, including disable it in NVIC and GPC. - DisableIRQ((IRQn_Type)irqId); + (void)DisableIRQ((IRQn_Type)irqId); GPC_CM_EnableIrqWakeup(CURRENT_GPC_INSTANCE, irqId, false); } diff --git a/components/power_manager/devices/MIMXRT1176/fsl_pm_device.c b/components/power_manager/devices/MIMXRT1176/fsl_pm_device.c index b078092b1..4ce3c7b6e 100644 --- a/components/power_manager/devices/MIMXRT1176/fsl_pm_device.c +++ b/components/power_manager/devices/MIMXRT1176/fsl_pm_device.c @@ -1,5 +1,5 @@ /* - * Copyright 2023 NXP + * Copyright 2023~2024 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -98,23 +98,23 @@ #define PM_RT1170_LPSR_ANA_LDO_LP_MODE_SETPOINT_MAP \ (0xFFFFU) // LPSR_ANA_LDO lowpower mode is disabled for all setpoints. #define PM_RT1170_LPSR_ANA_LDO_TRACKING_EN_SETPOINT_MAP \ - (~PM_RT1170_LPSR_ANA_LDO_EN_SETPOINT_MAP) // LPSR_ANA_DO tracking is enabled + ((uint32_t)(~PM_RT1170_LPSR_ANA_LDO_EN_SETPOINT_MAP)) // LPSR_ANA_DO tracking is enabled // from setpoint 0 to setpoint 10. #define PM_RT1170_LPSR_ANA_LDO_BYPASS_EN_SETPOINT_MAP \ - (~PM_RT1170_LPSR_ANA_LDO_EN_SETPOINT_MAP) // LPSR_ANA_DO bypass is enabled from + ((uint32_t)(~PM_RT1170_LPSR_ANA_LDO_EN_SETPOINT_MAP)) // LPSR_ANA_DO bypass is enabled from // setpoint 0 to setpoint 10. #define PM_RT1170_LPSR_DIG_LDO_EN_SETPOINT_MAP \ - (0xF81C) // LPSR_DIG_DO is enabled from setpoint 2 to setpoint 4, + (0xF81CU) // LPSR_DIG_DO is enabled from setpoint 2 to setpoint 4, // and setpoint 11 to setpoint 15. #define PM_RT1170_LPSR_DIG_LDO_STANDBY_SETPOINT_MAP (0xFFFFU) // LPSR_DIG_DO standby mode is disabled for all setpoints. #define PM_RT1170_LPSR_DIG_LDO_LP_MODE_SETPOINT_MAP \ (0xFFFFU) // LPSR_DIG_DO lowpower mode is disabled for all setpoints. #define PM_RT1170_LPSR_DIG_LDO_TRACKING_EN_SETPOINT_MAP \ - (~PM_RT1170_LPSR_DIG_LDO_EN_SETPOINT_MAP) // LPSR_DIG_DO tracking is enabled + ((uint32_t)(~PM_RT1170_LPSR_DIG_LDO_EN_SETPOINT_MAP)) // LPSR_DIG_DO tracking is enabled // from setpoint 0 to setpoint 1, // and setpoint 5 to setpoint 10. #define PM_RT1170_LPSR_DIG_LDO_BYPASS_EN_SETPOINT_MAP \ - (~PM_RT1170_LPSR_DIG_LDO_EN_SETPOINT_MAP) // LPSR_DIG_DO bypass is enabled from + ((uint32_t)(~PM_RT1170_LPSR_DIG_LDO_EN_SETPOINT_MAP)) // LPSR_DIG_DO bypass is enabled from // setpoint 0 to setpoint 1, // and setpoint 5 to setpoint 10. @@ -212,6 +212,7 @@ static bool RT1170_IsWakeupSource(pm_wakeup_source_t *ws); ******************************************************************************/ #if __CORTEX_M == 7 +extern const uint16_t g_clockSourceSpMapping[29U]; const uint16_t g_clockSourceSpMapping[29U] = { 0xFFFFU, /*!< Clock Source OSCPLL0: 16MHz RC OSC output, turn on in all setpoints. */ 0x0000U, /*!< Clock Source OSCPLL1: 48MHz RC OSC output, turn off in all setpoints. */ @@ -831,17 +832,18 @@ const pm_device_option_t g_devicePMOption = { */ static inline uint8_t RT1170_FindOperateMode(uint32_t rescIndex, pm_resc_group_t *pSysRescGroup) { - uint8_t u8Tmp = (pSysRescGroup->groupSlice[rescIndex / 8UL] >> (4UL * (rescIndex % 8UL))) & 0xFUL; + uint32_t u32Tmp = (pSysRescGroup->groupSlice[rescIndex / 8UL] >> (4UL * (rescIndex % 8UL))) & 0xFUL; // Find first set, that is the operate mode to set. - u8Tmp |= (u8Tmp >> 1U); - u8Tmp |= (u8Tmp >> 2U); + u32Tmp |= (u32Tmp >> 1U); + u32Tmp |= (u32Tmp >> 2U); - return ((u8Tmp + 1U) >> 1U); + return (uint8_t)(uint32_t)((u32Tmp + 1UL) >> 1UL); } #if __CORTEX_M == 7 /*! + * @brief Configure setpoint mapping for CM7. */ static inline void RT1170_SetCore0PlatformSetpointMap(GPC_CPU_MODE_CTRL_Type *base) @@ -849,7 +851,7 @@ static inline void RT1170_SetCore0PlatformSetpointMap(GPC_CPU_MODE_CTRL_Type *ba uint8_t i, j; uint32_t u32Tmp; - uint8_t coreSetpointMap[17U][17U] = PM_RT1170_CM7_COMPATIBLE_SETPOINT_MAP; + uint32_t coreSetpointMap[17U][17U] = PM_RT1170_CM7_COMPATIBLE_SETPOINT_MAP; // Enable CPU sleep hold. GPC_CM_EnableCpuSleepHold(base, true); @@ -893,15 +895,15 @@ static inline void RT1170_SetClockSourcesControlBySetpoint(void) ANADIG_PLL->PLL_AUDIO_CTRL &= ~ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_MASK; ANADIG_PLL->PLL_VIDEO_CTRL &= ~ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_MASK; - clock_name_t clockSourceName = kCLOCK_OscRc16M; - for (clockSourceName = kCLOCK_OscRc16M; clockSourceName <= kCLOCK_VideoPllOut; clockSourceName++) + uint8_t clockSourceName = (uint8_t)kCLOCK_OscRc16M; + for (clockSourceName = (uint8_t)kCLOCK_OscRc16M; clockSourceName <= (uint8_t)kCLOCK_VideoPllOut; clockSourceName++) { if (!CLOCK_OSCPLL_IsSetPointImplemented((clock_name_t)clockSourceName)) { assert(0); } // keep clock source init state aligned with set point 0 state. - if ((g_clockSourceSpMapping[(uint8_t)clockSourceName] & 0x1) == 0) + if ((g_clockSourceSpMapping[(uint8_t)clockSourceName] & (uint16_t)0x1U) == (uint16_t)0U) { CCM->OSCPLL[(uint8_t)clockSourceName].DIRECT = 0; } @@ -910,12 +912,12 @@ static inline void RT1170_SetClockSourcesControlBySetpoint(void) CCM->OSCPLL[(uint8_t)clockSourceName].DIRECT = 1; } // All clock sources except OSC_RC 16M are turned off in standby mode. - uint32_t standbyValue = 0UL; - if (clockSourceName == kCLOCK_OscRc16M) + uint16_t standbyValue = 0U; + if ((clock_name_t)clockSourceName == kCLOCK_OscRc16M) { standbyValue = 0xFFFFU; } - CLOCK_OSCPLL_ControlBySetPointMode(clockSourceName, g_clockSourceSpMapping[(uint8_t)clockSourceName], + CLOCK_OSCPLL_ControlBySetPointMode((clock_name_t)clockSourceName, g_clockSourceSpMapping[(uint8_t)clockSourceName], standbyValue); } @@ -1000,7 +1002,7 @@ static inline void RT1170_SetPowerSupplyControlBySetpoint(void) PMU_GPCEnableLdoBypassMode(kPMU_LpsrDigLdo, PM_RT1170_LPSR_DIG_LDO_BYPASS_EN_SETPOINT_MAP); for (uint8_t i = 0U; i < 16U; i++) { - PMU_GPCSetLpsrDigLdoTargetVoltage(1U << i, g_lpsrDigLdoTargetVoltage[i]); + PMU_GPCSetLpsrDigLdoTargetVoltage(1UL << i, g_lpsrDigLdoTargetVoltage[i]); } PMU_SetLpsrDigLdoControlMode(ANADIG_LDO_SNVS, kPMU_GPCMode); @@ -1032,20 +1034,20 @@ static inline void RT1170_SetSRCControlMode(void) SRC_EnableSetPointTransferReset(SRC, kSRC_LpsrSlice, true); SRC_SetSliceSetPointConfig(SRC, kSRC_LpsrSlice, PM_RT1170_LPSRMIX_SETPOINT_MAP); // e. Reset slice corresponding to Cortex-M4 platform is controlled by entering of suspend mode. - SRC_SetAssignList(SRC, kSRC_M4CoreSlice, kSRC_CM4Core); - SRC_SetSliceDomainModeConfig(SRC, kSRC_M4CoreSlice, kSRC_Cpu1SuspendModeAssertReset); + SRC_SetAssignList(SRC, kSRC_M4CoreSlice, (uint32_t)kSRC_CM4Core); + SRC_SetSliceDomainModeConfig(SRC, kSRC_M4CoreSlice, (uint32_t)kSRC_Cpu1SuspendModeAssertReset); SRC_EnableDomainModeTransferReset(SRC, kSRC_M4CoreSlice, true); // f. Reset slice corresponding to Cortex-M7 platform is controlled by entering of suspend mode. - SRC_SetAssignList(SRC, kSRC_M7CoreSlice, kSRC_CM7Core); - SRC_SetSliceDomainModeConfig(SRC, kSRC_M7CoreSlice, kSRC_Cpu0SuspendModeAssertReset); + SRC_SetAssignList(SRC, kSRC_M7CoreSlice, (uint32_t)kSRC_CM7Core); + SRC_SetSliceDomainModeConfig(SRC, kSRC_M7CoreSlice, (uint32_t)kSRC_Cpu0SuspendModeAssertReset); SRC_EnableDomainModeTransferReset(SRC, kSRC_M7CoreSlice, true); // g. Reset slice corresponding to CM4 Debug is controlled by entering of suspend mode. - SRC_SetAssignList(SRC, kSRC_M4DebugSlice, kSRC_CM4Core); - SRC_SetSliceDomainModeConfig(SRC, kSRC_M4DebugSlice, kSRC_Cpu1SuspendModeAssertReset); + SRC_SetAssignList(SRC, kSRC_M4DebugSlice, (uint32_t)kSRC_CM4Core); + SRC_SetSliceDomainModeConfig(SRC, kSRC_M4DebugSlice, (uint32_t)kSRC_Cpu1SuspendModeAssertReset); SRC_EnableDomainModeTransferReset(SRC, kSRC_M4DebugSlice, true); // h. Reset slice corresponding to CM7 Debug is controlled by entering of suspend mode. - SRC_SetAssignList(SRC, kSRC_M7DebugSlice, kSRC_CM7Core); - SRC_SetSliceDomainModeConfig(SRC, kSRC_M7DebugSlice, kSRC_Cpu0SuspendModeAssertReset); + SRC_SetAssignList(SRC, kSRC_M7DebugSlice, (uint32_t)kSRC_CM7Core); + SRC_SetSliceDomainModeConfig(SRC, kSRC_M7DebugSlice, (uint32_t)kSRC_Cpu0SuspendModeAssertReset); SRC_EnableDomainModeTransferReset(SRC, kSRC_M7DebugSlice, true); // i. Reset slice corresponding to USBPHY1 and USBPHY2 is controlled by WAKEUP domain's setpoint request. SRC_EnableSetPointTransferReset(SRC, kSRC_Usbphy1Slice, true); @@ -1209,7 +1211,7 @@ static inline void RT1170_SetCore1PlatformSetpointMap(GPC_CPU_MODE_CTRL_Type *ba uint8_t i, j; uint32_t u32Tmp; - uint8_t coreSetpointMap[17U][17U] = PM_RT1170_CM4_COMPATIBLE_SETPOINT_MAP; + uint32_t coreSetpointMap[17U][17U] = PM_RT1170_CM4_COMPATIBLE_SETPOINT_MAP; // Enable CPU sleep hold. GPC_CM_EnableCpuSleepHold(base, true); @@ -1344,7 +1346,7 @@ static void RT1170_PreparePowerSetting(void) // 5. Control body bias via GPC, CM7 is responsible for this. /* Check if FBB need to be enabled in OverDrive(OD) mode. Note: FUSE could not be read out if OTP memory is powered off.*/ - if (((OCOTP->FUSEN[7].FUSE & 0x10U) >> 4U) != 1) + if (((OCOTP->FUSEN[7].FUSE & 0x10UL) >> 4UL) != 1UL) { PMU_GPCEnableBodyBias(kPMU_FBB_CM7, PM_RT1170_FBB_EN_SETPOINT_MAP); } @@ -1435,9 +1437,9 @@ static void RT1170_EnterPowerState(uint8_t stateIndex, pm_resc_mask_t *pSoftResc else { // 1. Get CPU mode to transit based on application request. - if (pSoftRescMask->rescMask[0] & (1UL << kResc_CPU_PLATFORM)) + if ((pSoftRescMask->rescMask[0] & (1UL << kResc_CPU_PLATFORM)) != 0UL) { - switch (RT1170_FindOperateMode(kResc_CPU_PLATFORM, pSysRescGroup)) + switch (RT1170_FindOperateMode((uint32_t)kResc_CPU_PLATFORM, pSysRescGroup)) { case PM_RESOURCE_FULL_ON: // In case of application request PM_RESC_CORE_DOMAIN_RUN. @@ -1495,7 +1497,7 @@ static void RT1170_EnterPowerState(uint8_t stateIndex, pm_resc_mask_t *pSoftResc GPC_CM_ClearStandbyModeRequest(CURRENT_GPC_INSTANCE, kGPC_StopMode); GPC_CM_ClearStandbyModeRequest(CURRENT_GPC_INSTANCE, kGPC_SuspendMode); - if (RT1170_FindOperateMode(kResc_STBY_REQ, pSysRescGroup) != PM_RESOURCE_FULL_ON) + if (RT1170_FindOperateMode((uint32_t)kResc_STBY_REQ, pSysRescGroup) != PM_RESOURCE_FULL_ON) { // If not request to de-assert standby request, assert standby request when CPU entering selected CPU // mode. @@ -1527,13 +1529,13 @@ static status_t RT1170_ManageWakeupSource(pm_wakeup_source_t *ws, bool enable) if (enable) { // Enabled selected wakeup source, including enable it in NVIC and GPC. - EnableIRQ((IRQn_Type)irqId); + (void)EnableIRQ((IRQn_Type)irqId); GPC_CM_EnableIrqWakeup(CURRENT_GPC_INSTANCE, irqId, true); } else { // Disable selected wakeup source, including disable it in NVIC and GPC. - DisableIRQ((IRQn_Type)irqId); + (void)DisableIRQ((IRQn_Type)irqId); GPC_CM_EnableIrqWakeup(CURRENT_GPC_INSTANCE, irqId, false); } diff --git a/components/serial_manager/fsl_component_serial_manager.c b/components/serial_manager/fsl_component_serial_manager.c index d1570d9a0..45de8c0e2 100644 --- a/components/serial_manager/fsl_component_serial_manager.c +++ b/components/serial_manager/fsl_component_serial_manager.c @@ -1,5 +1,5 @@ /* - * Copyright 2018-2023 NXP + * Copyright 2018-2024 NXP * All rights reserved. * * @@ -627,10 +627,10 @@ static void SerialManager_Task(void *param) #endif #endif { - (void)SerialManager_StartWriting(serHandle); #if defined(OSA_USED) #if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) #else + (void)SerialManager_StartWriting(serHandle); primask = DisableGlobalIRQ(); serHandle->serialManagerState[SERIAL_EVENT_DATA_START_SEND]--; EnableGlobalIRQ(primask); @@ -787,10 +787,7 @@ static void SerialManager_TxCallback(void *callbackParam, #endif /* SERIAL_MANAGER_USE_COMMON_TASK */ #else /* OSA_USED && SERIAL_MANAGER_TASK_HANDLE_TX */ - if (kSerialManager_TransmissionBlocking == writeHandle->transfer.mode) - { - (void)SerialManager_StartWriting(serHandle); - } + (void)SerialManager_StartWriting(serHandle); #endif /* OSA_USED && SERIAL_MANAGER_TASK_HANDLE_TX */ writeHandle->transfer.soFar = message->length; @@ -1028,17 +1025,9 @@ static serial_manager_status_t SerialManager_Write(serial_write_handle_t writeHa { serial_manager_write_handle_t *serialWriteHandle; serial_manager_handle_t *serHandle; - -#if (defined(OSA_USED) && defined(SERIAL_MANAGER_TASK_HANDLE_TX) && (SERIAL_MANAGER_TASK_HANDLE_TX == 1)) -#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) - /* Need to support common_task. */ -#else /* SERIAL_MANAGER_USE_COMMON_TASK */ - /* Do nothing. */ -#endif /* SERIAL_MANAGER_USE_COMMON_TASK */ -#else /* OSA_USED && SERIAL_MANAGER_TASK_HANDLE_TX */ +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) serial_manager_status_t status = kStatus_SerialManager_Success; -#endif /* OSA_USED && SERIAL_MANAGER_TASK_HANDLE_TX */ - +#endif /* SERIAL_PORT_TYPE_USBCDC */ uint32_t primask; uint8_t isEmpty = 0U; @@ -1073,30 +1062,37 @@ static serial_manager_status_t SerialManager_Write(serial_write_handle_t writeHa if (0U != isEmpty) { +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + if (serHandle->serialPortType == kSerialPort_UsbCdc) + { + status = Serial_UsbCdcGetConnectedStatus((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]); + if (status == kStatus_SerialManager_NotConnected) + { + SerialManager_RemoveHead(&serHandle->runningWriteHandleHead); + serialWriteHandle->transfer.buffer = 0U; + serialWriteHandle->transfer.length = 0U; + return status; + } + } +#endif /* SERIAL_PORT_TYPE_USBCDC */ #if (defined(OSA_USED) && defined(SERIAL_MANAGER_TASK_HANDLE_TX) && (SERIAL_MANAGER_TASK_HANDLE_TX == 1)) #if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) /* Need to support common_task. */ #else /* SERIAL_MANAGER_USE_COMMON_TASK */ - primask = DisableGlobalIRQ(); - serHandle->serialManagerState[SERIAL_EVENT_DATA_START_SEND]++; - EnableGlobalIRQ(primask); - (void)OSA_SemaphorePost((osa_semaphore_handle_t)serHandle->serSemaphore); - -#endif /* SERIAL_MANAGER_USE_COMMON_TASK */ -#else /* OSA_USED && SERIAL_MANAGER_TASK_HANDLE_TX */ - status = SerialManager_StartWriting(serHandle); - if ((serial_manager_status_t)kStatus_SerialManager_Success != status) + if (kSerialManager_TransmissionBlocking == mode) { -#if (defined(USB_CDC_SERIAL_MANAGER_RUN_NO_HOST) && (USB_CDC_SERIAL_MANAGER_RUN_NO_HOST == 1)) - if (status == kStatus_SerialManager_NotConnected) - { - SerialManager_RemoveHead(&serHandle->runningWriteHandleHead); - serialWriteHandle->transfer.buffer = 0U; - serialWriteHandle->transfer.length = 0U; - } -#endif /* USB_CDC_SERIAL_MANAGER_RUN_NO_HOST == 1 */ - return status; + (void)SerialManager_StartWriting(serHandle); + } + else + { + primask = DisableGlobalIRQ(); + serHandle->serialManagerState[SERIAL_EVENT_DATA_START_SEND]++; + EnableGlobalIRQ(primask); + (void)OSA_SemaphorePost((osa_semaphore_handle_t)serHandle->serSemaphore); } +#endif /* SERIAL_MANAGER_USE_COMMON_TASK */ +#else /* OSA_USED && SERIAL_MANAGER_TASK_HANDLE_TX */ + (void)SerialManager_StartWriting(serHandle); #endif /* OSA_USED && SERIAL_MANAGER_TASK_HANDLE_TX */ } @@ -1284,7 +1280,11 @@ serial_manager_status_t SerialManager_Init(serial_handle_t serialHandle, const s { serial_manager_handle_t *serHandle; serial_manager_status_t status = kStatus_SerialManager_Error; - +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +#if (defined(OSA_USED) && !(defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))) + osa_task_def_t serTaskConfig; +#endif +#endif assert(NULL != serialConfig); assert(NULL != serialHandle); @@ -1318,13 +1318,18 @@ serial_manager_status_t SerialManager_Init(serial_handle_t serialHandle, const s { return kStatus_SerialManager_Error; } - - if (KOSA_StatusSuccess != OSA_TaskCreate((osa_task_handle_t)serHandle->taskId, OSA_TASK(SerialManager_Task), serHandle)) + (void)memcpy(&serTaskConfig, (osa_task_def_t *)OSA_TASK(SerialManager_Task), sizeof(osa_task_def_t)); + if (serialConfig->serialTaskConfig != NULL) + { + (void)memcpy(&serTaskConfig, serialConfig->serialTaskConfig, sizeof(osa_task_def_t)); + serTaskConfig.pthread = ((osa_task_def_t *)OSA_TASK(SerialManager_Task))->pthread; + serTaskConfig.tname = ((osa_task_def_t *)OSA_TASK(SerialManager_Task))->tname; + } + if (KOSA_StatusSuccess != OSA_TaskCreate((osa_task_handle_t)serHandle->taskId,(const osa_task_def_t *)&serTaskConfig, serHandle)) { return kStatus_SerialManager_Error; } #endif - #endif #endif @@ -1629,7 +1634,7 @@ serial_manager_status_t SerialManager_CloseWriteHandle(serial_write_handle_t wri serialHandle->openedWriteHandleCount--; } EnableGlobalIRQ(primask); -#if (defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && (DEBUG_CONSOLE_TRANSFER_NON_BLOCKING > 0U)) +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) (void)memset(writeHandle, 0, SERIAL_MANAGER_WRITE_HANDLE_SIZE); #else (void)memset(writeHandle, 0, SERIAL_MANAGER_WRITE_BLOCK_HANDLE_SIZE); @@ -1701,7 +1706,7 @@ serial_manager_status_t SerialManager_CloseReadHandle(serial_read_handle_t readH primask = DisableGlobalIRQ(); serialHandle->openedReadHandleHead = NULL; EnableGlobalIRQ(primask); -#if (defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && (DEBUG_CONSOLE_TRANSFER_NON_BLOCKING > 0U)) +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) (void)memset(readHandle, 0, SERIAL_MANAGER_READ_HANDLE_SIZE); #else (void)memset(readHandle, 0, SERIAL_MANAGER_READ_BLOCK_HANDLE_SIZE); diff --git a/components/serial_manager/fsl_component_serial_manager.h b/components/serial_manager/fsl_component_serial_manager.h index 16d7ef5a5..e09bbe9f6 100644 --- a/components/serial_manager/fsl_component_serial_manager.h +++ b/components/serial_manager/fsl_component_serial_manager.h @@ -1,5 +1,5 @@ /* - * Copyright 2018-2023 NXP + * Copyright 2018-2024 NXP * All rights reserved. * * @@ -266,6 +266,12 @@ #endif #endif +#if (defined(SERIAL_MANAGER_TASK_HANDLE_TX) && (SERIAL_MANAGER_TASK_HANDLE_TX > 0U)) +#ifndef OSA_USED +#error When SERIAL_MANAGER_TASK_HANDLE_TX=1, OSA_USED must be set. +#endif +#endif + #if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) #if (defined(OSA_USED) && !(defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))) #include "fsl_os_abstraction.h" @@ -390,11 +396,16 @@ typedef enum _serial_manager_type /*! @brief serial manager config structure*/ typedef struct _serial_manager_config { -#if defined(SERIAL_MANAGER_NON_BLOCKING_MODE) +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) uint8_t *ringBuffer; /*!< Ring buffer address, it is used to buffer data received by the hardware. Besides, the memory space cannot be free during the lifetime of the serial manager module. */ uint32_t ringBufferSize; /*!< The size of the ring buffer */ +#if (defined(OSA_USED) && !(defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))) + osa_task_def_t *serialTaskConfig; /*!< Serial manager task configuration, can be defined the serial manager + task configuration for this instance, if serialTaskConfig is NULL, will use the + default serial manager configure provided by serial manger module.*/ +#endif #endif serial_port_type_t type; /*!< Serial port type */ serial_manager_type_t blockType; /*!< Serial manager port type */ @@ -495,6 +506,36 @@ extern "C" { * SerialManager_Init((serial_handle_t)s_serialHandle, &config); * @endcode * + * Example below shows how to use this API to configure the Serial Manager task configuration. + * For example if user need do specfical configuration(s_os_thread_def_serialmanager)for the + * serial mananger task, + * @code + * #define SERIAL_MANAGER_RING_BUFFER_SIZE (256U) + * static SERIAL_MANAGER_HANDLE_DEFINE(s_serialHandle); + * static uint8_t s_ringBuffer[SERIAL_MANAGER_RING_BUFFER_SIZE]; + * const osa_task_def_t s_os_thread_def_serialmanager = { + * .tpriority = 4, + * .instances = 1, + * .stacksize = 2048, + * }; + * serial_manager_config_t config; + * serial_port_uart_config_t uartConfig; + * config.type = kSerialPort_Uart; + * config.ringBuffer = &s_ringBuffer[0]; + * config.ringBufferSize = SERIAL_MANAGER_RING_BUFFER_SIZE; + * config.serialTaskConfig = (osa_task_def_t *)&s_os_thread_def_serialmanager, + * uartConfig.instance = 0; + * uartConfig.clockRate = 24000000; + * uartConfig.baudRate = 115200; + * uartConfig.parityMode = kSerialManager_UartParityDisabled; + * uartConfig.stopBitCount = kSerialManager_UartOneStopBit; + * uartConfig.enableRx = 1; + * uartConfig.enableTx = 1; + * uartConfig.enableRxRTS = 0; + * uartConfig.enableTxCTS = 0; + * config.portConfig = &uartConfig; + * SerialManager_Init((serial_handle_t)s_serialHandle, &config); + * @endcode * @param serialHandle Pointer to point to a memory space of size #SERIAL_MANAGER_HANDLE_SIZE allocated by the caller. * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. * You can define the handle in the following two ways: diff --git a/components/serial_manager/fsl_component_serial_port_internal.h b/components/serial_manager/fsl_component_serial_port_internal.h index c2090348d..1dd3271b3 100644 --- a/components/serial_manager/fsl_component_serial_port_internal.h +++ b/components/serial_manager/fsl_component_serial_port_internal.h @@ -1,5 +1,5 @@ /* - * Copyright 2019-2020, 2023 NXP + * Copyright 2019-2020, 2023-2024 NXP * All rights reserved. * * @@ -93,6 +93,7 @@ serial_manager_status_t Serial_UsbCdcInstallRxCallback(serial_handle_t serialHan serial_manager_callback_t callback, void *callbackParam); void Serial_UsbCdcIsrFunction(serial_handle_t serialHandle); +serial_manager_status_t Serial_UsbCdcGetConnectedStatus(serial_handle_t serialHandle); #endif #if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) diff --git a/components/serial_manager/fsl_component_serial_port_usb.c b/components/serial_manager/fsl_component_serial_port_usb.c index ca1134bc8..2ba4c231e 100644 --- a/components/serial_manager/fsl_component_serial_port_usb.c +++ b/components/serial_manager/fsl_component_serial_port_usb.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. - * Copyright 2016 - 2020, 2023 NXP + * Copyright 2016 - 2020, 2023-2024 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -882,21 +882,7 @@ serial_manager_status_t Serial_UsbCdcWrite(serial_handle_t serialHandle, uint8_t { return kStatus_SerialManager_Busy; } - -#if (defined(USB_CDC_SERIAL_MANAGER_RUN_NO_HOST) && (USB_CDC_SERIAL_MANAGER_RUN_NO_HOST == 1)) - /* Prevents SerialManager_Write from blocking when no USB Host is attached */ - if ((serialUsbCdc->attach == 0U)) - { - return kStatus_SerialManager_NotConnected; - } - - /* Prevents SerialManager_Write from blocking when USB Host is attached but CDC terminal is closed */ - if ((serialUsbCdc->attach == 1U) && (serialUsbCdc->startTransactions == 0U)) - { - return kStatus_SerialManager_NotConnected; - } -#endif /* USB_CDC_SERIAL_MANAGER_RUN_NO_HOST == 1 */ - + serialUsbCdc->tx.busy = 1U; serialUsbCdc->tx.waiting4Prime = 0U; @@ -1022,6 +1008,18 @@ serial_manager_status_t Serial_UsbCdcInstallRxCallback(serial_handle_t serialHan return kStatus_SerialManager_Success; } +serial_manager_status_t Serial_UsbCdcGetConnectedStatus(serial_handle_t serialHandle) +{ +#if (defined(USB_CDC_SERIAL_MANAGER_RUN_NO_HOST) && (USB_CDC_SERIAL_MANAGER_RUN_NO_HOST == 1)) + serial_usb_cdc_state_t *serialUsbCdc; + assert(serialHandle); + serialUsbCdc = (serial_usb_cdc_state_t *)serialHandle; + return ((serialUsbCdc->attach == 1U) && (serialUsbCdc->startTransactions == 1U)) ? kStatus_SerialManager_Success : kStatus_SerialManager_NotConnected; +#else/* USB_CDC_SERIAL_MANAGER_RUN_NO_HOST == 1 */ + return kStatus_SerialManager_Success; +#endif +} + void Serial_UsbCdcIsrFunction(serial_handle_t serialHandle) { serial_usb_cdc_state_t *serialUsbCdc; diff --git a/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_1XK_WW.h b/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_1XK_WW.h index de2acfb0b..aa161d4b6 100644 --- a/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_1XK_WW.h +++ b/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_1XK_WW.h @@ -37,6 +37,9 @@ * SOFTWARE. */ +#ifndef _WLAN_TXPWRLIMIT_CFG_MURATA_1XK_WW_H_ +#define _WLAN_TXPWRLIMIT_CFG_MURATA_1XK_WW_H_ + #define WLAN_REGION_CODE "WW" static wlan_chanlist_t chanlist_2g_cfg = {.num_chans = 13, @@ -830,3 +833,5 @@ static wifi_txpwrlimit_t tx_pwrlimit_5g_cfg = { [39] = {0}, }}; #endif /* CONFIG_5GHz_SUPPORT */ + +#endif /* _WLAN_TXPWRLIMIT_CFG_MURATA_1XK_WW_H_ */ diff --git a/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_1ZM_WW.h b/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_1ZM_WW.h index bf5999ca2..c9ccebe03 100644 --- a/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_1ZM_WW.h +++ b/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_1ZM_WW.h @@ -37,6 +37,9 @@ * SOFTWARE. */ +#ifndef _WLAN_TXPWRLIMIT_CFG_MURATA_1ZM_WW_H_ +#define _WLAN_TXPWRLIMIT_CFG_MURATA_1ZM_WW_H_ + #define WLAN_REGION_CODE "WW" static wlan_chanlist_t chanlist_2g_cfg = {.num_chans = 13, @@ -1901,3 +1904,5 @@ static wifi_txpwrlimit_t tx_pwrlimit_5g_cfg = {.subband = (wifi_SubBand_t)0x00 }}; #endif /* CONFIG_5GHz_SUPPORT */ #endif /* CONFIG_11AC */ + +#endif /* _WLAN_TXPWRLIMIT_CFG_MURATA_1ZM_WW_H_ */ diff --git a/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_2DS_WW.h b/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_2DS_WW.h index c615d37fc..9067d0f53 100644 --- a/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_2DS_WW.h +++ b/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_2DS_WW.h @@ -37,6 +37,9 @@ * SOFTWARE. */ +#ifndef _WLAN_TXPWRLIMIT_CFG_MURATA_2DS_WW_H_ +#define _WLAN_TXPWRLIMIT_CFG_MURATA_2DS_WW_H_ + #define WLAN_REGION_CODE "WW" static wlan_chanlist_t chanlist_2g_cfg = {.num_chans = 13, @@ -347,3 +350,5 @@ static wifi_txpwrlimit_t tx_pwrlimit_2g_cfg = { [38] = {0}, [39] = {0}, }}; + +#endif /* _WLAN_TXPWRLIMIT_CFG_MURATA_2DS_WW_H_ */ diff --git a/components/wifi_bt_module/incl/wifi_bt_module_config.h b/components/wifi_bt_module/incl/wifi_bt_module_config.h index 38506eec8..b579cd12d 100644 --- a/components/wifi_bt_module/incl/wifi_bt_module_config.h +++ b/components/wifi_bt_module/incl/wifi_bt_module_config.h @@ -5,6 +5,9 @@ * SPDX-License-Identifier: BSD-3-Clause */ +#ifndef _WIFI_BT_MODULE_CONFIG_H_ +#define _WIFI_BT_MODULE_CONFIG_H_ + /* Wi-Fi boards configuration list */ /* AzureWave AW-NM191-uSD */ @@ -354,3 +357,5 @@ #else #error "Please define macro related to wifi board" #endif + +#endif /* _WIFI_BT_MODULE_CONFIG_H_ */ diff --git a/devices/MIMXRT1042/all_lib_device.cmake b/devices/MIMXRT1042/all_lib_device.cmake index c42c010b7..17bc227d8 100644 --- a/devices/MIMXRT1042/all_lib_device.cmake +++ b/devices/MIMXRT1042/all_lib_device.cmake @@ -969,6 +969,12 @@ # # description: edgefast_bluetooth le_audio.tmap # set(CONFIG_USE_middleware_edgefast_bluetooth_le_audio_tmap true) +# # description: edgefast_bluetooth le_audio.gmap +# set(CONFIG_USE_middleware_edgefast_bluetooth_le_audio_gmap true) + +# # description: edgefast_bluetooth le_audio.pbp +# set(CONFIG_USE_middleware_edgefast_bluetooth_le_audio_pbp true) + # # description: edgefast_bluetooth PAL configuration template # set(CONFIG_USE_middleware_edgefast_bluetooth_config_template true) @@ -1150,9 +1156,6 @@ # # description: A mixed-radix Fast Fourier Transform library # set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_third_party_kissfft true) -# # description: Xtensa HiFi4 NN library -# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_third_party_xa_nnlib_hifi4 true) - # # description: Utilities for Glow NN compiler. # set(CONFIG_USE_middleware_eiq_glow true) @@ -1168,9 +1171,6 @@ # # description: TensorFlow Lite Micro library binary with core specific kernel implementations # set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_binary true) -# # description: TensorFlow Lite Micro library with CMSIS-NN and Ethos-U kernel implementations -# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_cmsis_nn_ethosu true) - # # description: TensorFlow Lite Micro library header files # set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_headers true) diff --git a/devices/MIMXRT1052/all_lib_device.cmake b/devices/MIMXRT1052/all_lib_device.cmake index d948c694b..98f89e1c8 100644 --- a/devices/MIMXRT1052/all_lib_device.cmake +++ b/devices/MIMXRT1052/all_lib_device.cmake @@ -981,9 +981,6 @@ # # description: A mixed-radix Fast Fourier Transform library # set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_third_party_kissfft true) -# # description: Xtensa HiFi4 NN library -# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_third_party_xa_nnlib_hifi4 true) - # # description: Utilities for Glow NN compiler. # set(CONFIG_USE_middleware_eiq_glow true) @@ -1002,9 +999,6 @@ # # description: TensorFlow Lite Micro library binary with core specific kernel implementations # set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_binary true) -# # description: TensorFlow Lite Micro library with CMSIS-NN and Ethos-U kernel implementations -# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_cmsis_nn_ethosu true) - # # description: TensorFlow Lite Micro library header files # set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_headers true) diff --git a/devices/MIMXRT1062/all_lib_device.cmake b/devices/MIMXRT1062/all_lib_device.cmake index bca9b3a5e..860077900 100644 --- a/devices/MIMXRT1062/all_lib_device.cmake +++ b/devices/MIMXRT1062/all_lib_device.cmake @@ -1,11 +1,4 @@ # Copy variable into project config.cmake to use software component -#set.board.evkbmimxrt1060 -# # description: Board_project_template evkbmimxrt1060 -# set(CONFIG_USE_BOARD_Project_Template_evkbmimxrt1060 true) - -# # description: XIP Board Driver -# set(CONFIG_USE_driver_xip_board_evkbmimxrt1060 true) - #set.board.evkcmimxrt1060 # # description: Board_project_template evkcmimxrt1060 # set(CONFIG_USE_BOARD_Project_Template_evkcmimxrt1060 true) @@ -20,6 +13,13 @@ # # description: XIP Board Driver # set(CONFIG_USE_driver_xip_board_evkmimxrt1060 true) +#set.board.evkbmimxrt1060 +# # description: Board_project_template evkbmimxrt1060 +# set(CONFIG_USE_BOARD_Project_Template_evkbmimxrt1060 true) + +# # description: XIP Board Driver +# set(CONFIG_USE_driver_xip_board_evkbmimxrt1060 true) + #set.middleware.wireless.framework # # description: Middleware wireless framework_sec_lib # set(CONFIG_USE_middleware_wireless_framework_sec_lib true) @@ -30,6 +30,9 @@ # # description: Middleware wireless framework_platform_coex # set(CONFIG_USE_middleware_wireless_framework_platform_coex_rt1060 true) +# # description: Middleware wireless framework_platform_internal_flash +# set(CONFIG_USE_middleware_wireless_framework_platform_internal_flash_rt1060 true) + # # description: Middleware wireless framework_board_lp # set(CONFIG_USE_middleware_wireless_framework_board_lp_MIMXRT1062 true) @@ -57,6 +60,9 @@ # # description: Middleware wireless framework_rpmsg_config # set(CONFIG_USE_middleware_wireless_framework_rpmsg_config true) +# # description: Middleware wireless framework_mbedtls_config +# set(CONFIG_USE_middleware_wireless_framework_mbedtls_config_rt1060 true) + # # description: Middleware wireless framework platform ot coex # set(CONFIG_USE_middleware_wireless_framework_platform_rt_ot_coex true) @@ -102,9 +108,6 @@ # # description: Middleware wireless framework_sbtsnoop_nxp_ble_port # set(CONFIG_USE_middleware_wireless_framework_sbtsnoop_nxp_ble_port true) -# # description: Middleware wireless framework_fwk_debug -# set(CONFIG_USE_middleware_wireless_framework_fwk_debug true) - # # description: Middleware wireless framework_linkscripts_kw45 # set(CONFIG_USE_middleware_wireless_framework_linkscripts_kw45 true) @@ -129,6 +132,9 @@ # # description: Middleware wireless framework_PDUM # set(CONFIG_USE_middleware_wireless_framework_PDUM true) +# # description: Middleware wireless framework_PDUM rt1060 +# set(CONFIG_USE_middleware_wireless_framework_PDUM_rt1060 true) + # # description: Middleware wireless framework_markdown # set(CONFIG_USE_middleware_wireless_framework_markdown true) @@ -150,6 +156,15 @@ # # description: Middleware wireless fwk_lfs_mflash # set(CONFIG_USE_middleware_wireless_framework_fsabstraction_littlefs true) +# # description: Single wire output debug +# set(CONFIG_USE_middleware_wireless_framework_swo_dbg true) + +# # description: Middleware wireless framework_settings +# set(CONFIG_USE_middleware_wireless_framework_settings true) + +# # description: Middleware wireless framework_settings +# set(CONFIG_USE_middleware_wireless_framework_NVS true) + # # description: Middleware wireless framework_platform # set(CONFIG_USE_middleware_wireless_framework_platform_rt1060 true) @@ -165,6 +180,15 @@ # # description: Middleware wireless framework_platform_ota # set(CONFIG_USE_middleware_wireless_framework_platform_ota_rt1060 true) +# # description: Middleware wireless framework_platform_ics +# set(CONFIG_USE_middleware_wireless_framework_platform_ics_rt1060 true) + +# # description: Middleware wireless framework_mws +# set(CONFIG_USE_middleware_wireless_framework_MWS true) + +# # description: Middleware wireless framework_mws intercore +# set(CONFIG_USE_middleware_wireless_framework_MWS_Intercore true) + # # description: Middleware wireless framework_platform_mws # set(CONFIG_USE_middleware_wireless_framework_platform_mws_rt1060 true) @@ -183,6 +207,12 @@ # # description: Middleware wireless framework_platform_lowpower_timer # set(CONFIG_USE_middleware_wireless_framework_platform_lowpower_timer_rt1060 true) +# # description: Middleware wireless framework_platform_reset +# set(CONFIG_USE_middleware_wireless_framework_platform_reset_rt1060 true) + +# # description: Middleware wireless framework_sec_lib_mbedtls +# set(CONFIG_USE_middleware_wireless_framework_sec_lib_mbedtls_m7 true) + # # description: Middleware wireless framework_sec_lib_sss # set(CONFIG_USE_middleware_wireless_framework_sec_lib_sss_m7 true) @@ -192,6 +222,12 @@ # # description: Middleware wireless framework_sbtsnoop # set(CONFIG_USE_middleware_wireless_framework_sbtsnoop true) +# # description: Middleware wireless framework_fwk_debug +# set(CONFIG_USE_middleware_wireless_framework_fwk_debug true) + +# # description: Middleware wireless sensors +# set(CONFIG_USE_middleware_wireless_Sensors true) + # # description: FreeRTOS heap for framework mem_manager # set(CONFIG_USE_middleware_wireless_freertos_heap true) @@ -1317,161 +1353,6 @@ # # description: Voice intelligent technology library for Cortex M7 # set(CONFIG_USE_middleware_vit_cm7 true) -#set.middleware.eiq -# # description: Flatbuffers library -# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_third_party_flatbuffers true) - -# # description: Gemmlowp library -# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_third_party_gemmlowp true) - -# # description: Ruy library -# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_third_party_ruy true) - -# # description: General Purpose FFT (Fast Fourier/Cosine/Sine Transform) Package -# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_third_party_fft2d true) - -# # description: A mixed-radix Fast Fourier Transform library -# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_third_party_kissfft true) - -# # description: Xtensa HiFi4 NN library -# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_third_party_xa_nnlib_hifi4 true) - -# # description: Utilities for Glow NN compiler. -# set(CONFIG_USE_middleware_eiq_glow true) - -# # description: CMSIS-NN library -# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_third_party_cmsis_nn true) - -# # description: TensorFlow Lite Micro library with reference kernel implementations -# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_reference true) - -# # description: TensorFlow Lite Micro library with CMSIS-NN kernel implementations -# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_cmsis_nn true) - -# # description: TensorFlow Lite Micro library binary with core specific kernel implementations -# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_binary true) - -# # description: TensorFlow Lite Micro library with CMSIS-NN and Ethos-U kernel implementations -# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_cmsis_nn_ethosu true) - -# # description: TensorFlow Lite Micro library header files -# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_headers true) - -# # description: TensorFlow Lite Micro library -# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro true) - -# # description: TensorFlow Lite Micro word detection library -# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_examples_microspeech true) - -# # description: DeepViewRT Runtime library -# set(CONFIG_USE_middleware_eiq_deepviewrt_nnlib true) - -# # description: DeepViewRT modelrunner server library -# set(CONFIG_USE_middleware_eiq_deepviewrt_modelrunner_server true) - -# # description: DeepViewRT modelrunner server library -# set(CONFIG_USE_middleware_eiq_deepviewrt_modelrunner_server_flash true) - -# # description: DeepViewRT modelrunner server library -# set(CONFIG_USE_middleware_eiq_deepviewrt_deps_flatcc true) - -# # description: DeepViewRT modelrunner server library -# set(CONFIG_USE_middleware_eiq_deepviewrt_deps_json true) - -# # description: DeepViewRT modelrunner server library -# set(CONFIG_USE_middleware_eiq_deepviewrt_deps_stb true) - -#set.middleware.azure_rtos -# # description: Azure RTOS Core -# set(CONFIG_USE_middleware_azure_rtos_tx_template true) - -# # description: Azure RTOS Core -# set(CONFIG_USE_middleware_azure_rtos_tx_mgr_template true) - -# # description: Real Time Operating System Kernel -# set(CONFIG_USE_middleware_azure_rtos_tx_lib true) - -# # description: Real Time Operating System Kernel -# set(CONFIG_USE_middleware_azure_rtos_tx_mgr_lib true) - -# # description: Real Time Operating System Kernel -# set(CONFIG_USE_middleware_azure_rtos_txm_lib true) - -# # description: A file system based on azure RTOS -# set(CONFIG_USE_middleware_azure_rtos_fx_template true) - -# # description: A file system based on azure RTOS -# set(CONFIG_USE_middleware_azure_rtos_fx_lib true) - -# # description: A GUI library based on azure RTOS -# set(CONFIG_USE_middleware_azure_rtos_gx_lib true) - -# # description: A network protocol stack based on azure RTOS -# set(CONFIG_USE_middleware_azure_rtos_nxd_template true) - -# # description: A network protocol stack based on azure RTOS -# set(CONFIG_USE_middleware_azure_rtos_nxd_lib true) - -# # description: A USB library based on azure RTOS -# set(CONFIG_USE_middleware_azure_rtos_ux_template true) - -# # description: Azure RTOS USBX Host Controller EHCI -# set(CONFIG_USE_middleware_azure_rtos_ux_ehci true) - -# # description: Azure RTOS USBX Host Controller OHCI -# set(CONFIG_USE_middleware_azure_rtos_ux_ohci true) - -# # description: Azure RTOS USBX Host Controller IP3516 -# set(CONFIG_USE_middleware_azure_rtos_ux_ip3516 true) - -# # description: Azure RTOS USBX Device Controller IP3511 -# set(CONFIG_USE_middleware_azure_rtos_ux_ip3511 true) - -# # description: Azure RTOS USBX Device Controller for i.MX RT -# set(CONFIG_USE_middleware_azure_rtos_ux_dci true) - -# # description: A USB library based on azure RTOS -# set(CONFIG_USE_middleware_azure_rtos_ux_lib true) - -# # description: Azure RTOS Core -# set(CONFIG_USE_middleware_azure_rtos_tx true) - -# # description: Azure RTOS Core -# set(CONFIG_USE_middleware_azure_rtos_tx_mgr true) - -# # description: Azure RTOS Core -# set(CONFIG_USE_middleware_azure_rtos_tx_sp true) - -# # description: A file system based on azure RTOS -# set(CONFIG_USE_middleware_azure_rtos_fx true) - -# # description: A file system based on azure RTOS -# set(CONFIG_USE_middleware_azure_rtos_fx_sp true) - -# # description: A GUI library based on azure RTOS -# set(CONFIG_USE_middleware_azure_rtos_gx true) - -# # description: LevelX provides NAND and NOR flash wear leveling facilities to embedded applications -# set(CONFIG_USE_middleware_azure_rtos_lx true) - -# # description: A network protocol stack based on azure RTOS -# set(CONFIG_USE_middleware_azure_rtos_nxd true) - -# # description: A network protocol stack based on azure RTOS -# set(CONFIG_USE_middleware_azure_rtos_nxd_sp true) - -# # description: Azure NetX Duo driver based on i.MXRT series -# set(CONFIG_USE_middleware_netxduo_imxrt true) - -# # description: A USB library based on azure RTOS -# set(CONFIG_USE_middleware_azure_rtos_ux true) - -# # description: A USB library based on azure RTOS -# set(CONFIG_USE_middleware_azure_rtos_ux_sp true) - -# # description: A software package that connects to the IoT Hub through Azure RTOS -# set(CONFIG_USE_middleware_azure_rtos_azure_iot true) - #set.middleware.edgefast_bluetooth # # description: edgefast_bluetooth configuration template for LE audio # set(CONFIG_USE_middleware_edgefast_bluetooth_le_audio_config_template true) @@ -1503,6 +1384,12 @@ # # description: edgefast_bluetooth le_audio.tmap # set(CONFIG_USE_middleware_edgefast_bluetooth_le_audio_tmap true) +# # description: edgefast_bluetooth le_audio.gmap +# set(CONFIG_USE_middleware_edgefast_bluetooth_le_audio_gmap true) + +# # description: edgefast_bluetooth le_audio.pbp +# set(CONFIG_USE_middleware_edgefast_bluetooth_le_audio_pbp true) + # # description: edgefast_bluetooth PAL configuration template # set(CONFIG_USE_middleware_edgefast_bluetooth_config_template true) @@ -1668,6 +1555,155 @@ # # description: BLE libraries for bt_ble Host stack # set(CONFIG_USE_middleware_edgefast_bluetooth_ble_ethermind_lib_lc3_cm7f true) +#set.middleware.eiq +# # description: Flatbuffers library +# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_third_party_flatbuffers true) + +# # description: Gemmlowp library +# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_third_party_gemmlowp true) + +# # description: Ruy library +# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_third_party_ruy true) + +# # description: General Purpose FFT (Fast Fourier/Cosine/Sine Transform) Package +# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_third_party_fft2d true) + +# # description: A mixed-radix Fast Fourier Transform library +# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_third_party_kissfft true) + +# # description: Utilities for Glow NN compiler. +# set(CONFIG_USE_middleware_eiq_glow true) + +# # description: CMSIS-NN library +# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_third_party_cmsis_nn true) + +# # description: TensorFlow Lite Micro library with reference kernel implementations +# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_reference true) + +# # description: TensorFlow Lite Micro library with CMSIS-NN kernel implementations +# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_cmsis_nn true) + +# # description: TensorFlow Lite Micro library binary with core specific kernel implementations +# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_binary true) + +# # description: TensorFlow Lite Micro library header files +# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_headers true) + +# # description: TensorFlow Lite Micro library +# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro true) + +# # description: TensorFlow Lite Micro word detection library +# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_examples_microspeech true) + +# # description: DeepViewRT Runtime library +# set(CONFIG_USE_middleware_eiq_deepviewrt_nnlib true) + +# # description: DeepViewRT modelrunner server library +# set(CONFIG_USE_middleware_eiq_deepviewrt_modelrunner_server true) + +# # description: DeepViewRT modelrunner server library +# set(CONFIG_USE_middleware_eiq_deepviewrt_modelrunner_server_flash true) + +# # description: DeepViewRT modelrunner server library +# set(CONFIG_USE_middleware_eiq_deepviewrt_deps_flatcc true) + +# # description: DeepViewRT modelrunner server library +# set(CONFIG_USE_middleware_eiq_deepviewrt_deps_json true) + +# # description: DeepViewRT modelrunner server library +# set(CONFIG_USE_middleware_eiq_deepviewrt_deps_stb true) + +#set.middleware.azure_rtos +# # description: Azure RTOS Core +# set(CONFIG_USE_middleware_azure_rtos_tx_template true) + +# # description: Azure RTOS Core +# set(CONFIG_USE_middleware_azure_rtos_tx_mgr_template true) + +# # description: Real Time Operating System Kernel +# set(CONFIG_USE_middleware_azure_rtos_tx_lib true) + +# # description: Real Time Operating System Kernel +# set(CONFIG_USE_middleware_azure_rtos_tx_mgr_lib true) + +# # description: Real Time Operating System Kernel +# set(CONFIG_USE_middleware_azure_rtos_txm_lib true) + +# # description: A file system based on azure RTOS +# set(CONFIG_USE_middleware_azure_rtos_fx_template true) + +# # description: A file system based on azure RTOS +# set(CONFIG_USE_middleware_azure_rtos_fx_lib true) + +# # description: A GUI library based on azure RTOS +# set(CONFIG_USE_middleware_azure_rtos_gx_lib true) + +# # description: A network protocol stack based on azure RTOS +# set(CONFIG_USE_middleware_azure_rtos_nxd_template true) + +# # description: A network protocol stack based on azure RTOS +# set(CONFIG_USE_middleware_azure_rtos_nxd_lib true) + +# # description: A USB library based on azure RTOS +# set(CONFIG_USE_middleware_azure_rtos_ux_template true) + +# # description: Azure RTOS USBX Host Controller EHCI +# set(CONFIG_USE_middleware_azure_rtos_ux_ehci true) + +# # description: Azure RTOS USBX Host Controller OHCI +# set(CONFIG_USE_middleware_azure_rtos_ux_ohci true) + +# # description: Azure RTOS USBX Host Controller IP3516 +# set(CONFIG_USE_middleware_azure_rtos_ux_ip3516 true) + +# # description: Azure RTOS USBX Device Controller IP3511 +# set(CONFIG_USE_middleware_azure_rtos_ux_ip3511 true) + +# # description: Azure RTOS USBX Device Controller for i.MX RT +# set(CONFIG_USE_middleware_azure_rtos_ux_dci true) + +# # description: A USB library based on azure RTOS +# set(CONFIG_USE_middleware_azure_rtos_ux_lib true) + +# # description: Azure RTOS Core +# set(CONFIG_USE_middleware_azure_rtos_tx true) + +# # description: Azure RTOS Core +# set(CONFIG_USE_middleware_azure_rtos_tx_mgr true) + +# # description: Azure RTOS Core +# set(CONFIG_USE_middleware_azure_rtos_tx_sp true) + +# # description: A file system based on azure RTOS +# set(CONFIG_USE_middleware_azure_rtos_fx true) + +# # description: A file system based on azure RTOS +# set(CONFIG_USE_middleware_azure_rtos_fx_sp true) + +# # description: A GUI library based on azure RTOS +# set(CONFIG_USE_middleware_azure_rtos_gx true) + +# # description: LevelX provides NAND and NOR flash wear leveling facilities to embedded applications +# set(CONFIG_USE_middleware_azure_rtos_lx true) + +# # description: A network protocol stack based on azure RTOS +# set(CONFIG_USE_middleware_azure_rtos_nxd true) + +# # description: A network protocol stack based on azure RTOS +# set(CONFIG_USE_middleware_azure_rtos_nxd_sp true) + +# # description: Azure NetX Duo driver based on i.MXRT series +# set(CONFIG_USE_middleware_netxduo_imxrt true) + +# # description: A USB library based on azure RTOS +# set(CONFIG_USE_middleware_azure_rtos_ux true) + +# # description: A USB library based on azure RTOS +# set(CONFIG_USE_middleware_azure_rtos_ux_sp true) + +# # description: A software package that connects to the IoT Hub through Azure RTOS +# set(CONFIG_USE_middleware_azure_rtos_azure_iot true) + #set.middleware.wireless.wpa_supplicant # # description: Wpa supplicant rtos # set(CONFIG_USE_middleware_wireless_wpa_supplicant_rtos true) diff --git a/devices/MIMXRT1064/all_lib_device.cmake b/devices/MIMXRT1064/all_lib_device.cmake index 62c2d5223..c0deda376 100644 --- a/devices/MIMXRT1064/all_lib_device.cmake +++ b/devices/MIMXRT1064/all_lib_device.cmake @@ -978,9 +978,6 @@ # # description: A mixed-radix Fast Fourier Transform library # set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_third_party_kissfft true) -# # description: Xtensa HiFi4 NN library -# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_third_party_xa_nnlib_hifi4 true) - # # description: DeepViewRT Runtime library # set(CONFIG_USE_middleware_eiq_deepviewrt_nnlib true) @@ -1011,9 +1008,6 @@ # # description: TensorFlow Lite Micro library binary with core specific kernel implementations # set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_binary true) -# # description: TensorFlow Lite Micro library with CMSIS-NN and Ethos-U kernel implementations -# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_cmsis_nn_ethosu true) - # # description: TensorFlow Lite Micro library header files # set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_headers true) diff --git a/devices/MIMXRT1166/all_lib_device.cmake b/devices/MIMXRT1166/all_lib_device.cmake index 69c6a82e7..7f53bd459 100644 --- a/devices/MIMXRT1166/all_lib_device.cmake +++ b/devices/MIMXRT1166/all_lib_device.cmake @@ -1223,9 +1223,6 @@ # # description: A mixed-radix Fast Fourier Transform library # set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_third_party_kissfft true) -# # description: Xtensa HiFi4 NN library -# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_third_party_xa_nnlib_hifi4 true) - # # description: Utilities for Glow NN compiler. # set(CONFIG_USE_middleware_eiq_glow true) @@ -1241,9 +1238,6 @@ # # description: TensorFlow Lite Micro library binary with core specific kernel implementations # set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_binary true) -# # description: TensorFlow Lite Micro library with CMSIS-NN and Ethos-U kernel implementations -# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_cmsis_nn_ethosu true) - # # description: TensorFlow Lite Micro library header files # set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_headers true) diff --git a/devices/MIMXRT1176/all_lib_device.cmake b/devices/MIMXRT1176/all_lib_device.cmake index 15337180f..233e7f628 100644 --- a/devices/MIMXRT1176/all_lib_device.cmake +++ b/devices/MIMXRT1176/all_lib_device.cmake @@ -1,4 +1,14 @@ # Copy variable into project config.cmake to use software component +#set.board.evkbmimxrt1170 +# # description: Board_project_template evkbmimxrt1170 +# set(CONFIG_USE_BOARD_Project_Template_evkbmimxrt1170 true) + +# # description: XIP Board Driver +# set(CONFIG_USE_driver_xip_board_evkbmimxrt1170 true) + +# # description: XMCD Driver +# set(CONFIG_USE_driver_xmcd_evkbmimxrt1170 true) + #set.board.evkmimxrt1170 # # description: XIP Board Driver # set(CONFIG_USE_driver_xip_board_evkmimxrt1170 true) @@ -9,15 +19,30 @@ # # description: Board_project_template evkmimxrt1170 # set(CONFIG_USE_BOARD_Project_Template_evkmimxrt1170 true) -#set.board.evkbmimxrt1170 -# # description: Board_project_template evkbmimxrt1170 -# set(CONFIG_USE_BOARD_Project_Template_evkbmimxrt1170 true) +#set.middleware.maestro_framework +# # description: maestro_framework template +# set(CONFIG_USE_middleware_maestro_framework_template true) -# # description: XIP Board Driver -# set(CONFIG_USE_driver_xip_board_evkbmimxrt1170 true) +# # description: MCU Maestro Audio Framework Doc +# set(CONFIG_USE_middleware_maestro_framework_doc true) -# # description: XMCD Driver -# set(CONFIG_USE_driver_xmcd_evkbmimxrt1170 true) +# # description: MCU Maestro Audio Framework Codecs +# set(CONFIG_USE_middleware_maestro_framework_codecs true) + +# # description: MCU Maestro Audio Framework Streamer Core +# set(CONFIG_USE_middleware_maestro_framework true) + +# # description: MCU Maestro Audio Framework Opus +# set(CONFIG_USE_middleware_maestro_framework_opus true) + +# # description: MCU Maestro Audio Framework Opusfile +# set(CONFIG_USE_middleware_maestro_framework_opusfile true) + +# # description: MCU Maestro Audio Framework Ogg +# set(CONFIG_USE_middleware_maestro_framework_ogg true) + +# # description: MCU Maestro Audio Framework ASRC +# set(CONFIG_USE_middleware_maestro_framework_asrc true) #set.device.MIMXRT1176 # # description: Middleware baremetal @@ -900,31 +925,6 @@ # # description: lwIP UDP Echo Raw API contrib # set(CONFIG_USE_middleware_lwip_contrib_udpecho_raw true) -#set.middleware.maestro_framework -# # description: maestro_framework template -# set(CONFIG_USE_middleware_maestro_framework_template true) - -# # description: MCU Maestro Audio Framework Doc -# set(CONFIG_USE_middleware_maestro_framework_doc true) - -# # description: MCU Maestro Audio Framework Codecs -# set(CONFIG_USE_middleware_maestro_framework_codecs true) - -# # description: MCU Maestro Audio Framework Streamer Core -# set(CONFIG_USE_middleware_maestro_framework true) - -# # description: MCU Maestro Audio Framework Opus -# set(CONFIG_USE_middleware_maestro_framework_opus true) - -# # description: MCU Maestro Audio Framework Opusfile -# set(CONFIG_USE_middleware_maestro_framework_opusfile true) - -# # description: MCU Maestro Audio Framework Ogg -# set(CONFIG_USE_middleware_maestro_framework_ogg true) - -# # description: MCU Maestro Audio Framework ASRC -# set(CONFIG_USE_middleware_maestro_framework_asrc true) - #set.middleware.mcuboot # # description: mcuboot # set(CONFIG_USE_middleware_mcuboot true) @@ -1274,164 +1274,6 @@ # # description: Voice intelligent technology library for Cortex M7 # set(CONFIG_USE_middleware_vit_cm7 true) -#set.middleware.eiq -# # description: Utilities for Glow NN compiler. -# set(CONFIG_USE_middleware_eiq_glow true) - -# # description: Flatbuffers library -# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_third_party_flatbuffers true) - -# # description: Gemmlowp library -# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_third_party_gemmlowp true) - -# # description: Ruy library -# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_third_party_ruy true) - -# # description: General Purpose FFT (Fast Fourier/Cosine/Sine Transform) Package -# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_third_party_fft2d true) - -# # description: A mixed-radix Fast Fourier Transform library -# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_third_party_kissfft true) - -# # description: Xtensa HiFi4 NN library -# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_third_party_xa_nnlib_hifi4 true) - -# # description: Multimedia Processing Pipelines Library -# set(CONFIG_USE_middleware_eiq_mpp true) - -# # description: CMSIS-NN library -# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_third_party_cmsis_nn true) - -# # description: TensorFlow Lite Micro library with reference kernel implementations -# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_reference true) - -# # description: TensorFlow Lite Micro library with CMSIS-NN kernel implementations -# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_cmsis_nn true) - -# # description: TensorFlow Lite Micro library binary with core specific kernel implementations -# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_binary true) - -# # description: TensorFlow Lite Micro library with CMSIS-NN and Ethos-U kernel implementations -# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_cmsis_nn_ethosu true) - -# # description: TensorFlow Lite Micro library header files -# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_headers true) - -# # description: TensorFlow Lite Micro library -# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro true) - -# # description: TensorFlow Lite Micro word detection library -# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_examples_microspeech true) - -# # description: DeepViewRT Runtime library -# set(CONFIG_USE_middleware_eiq_deepviewrt_nnlib true) - -# # description: DeepViewRT modelrunner server library -# set(CONFIG_USE_middleware_eiq_deepviewrt_modelrunner_server true) - -# # description: DeepViewRT modelrunner server library -# set(CONFIG_USE_middleware_eiq_deepviewrt_modelrunner_server_flash true) - -# # description: DeepViewRT modelrunner server library -# set(CONFIG_USE_middleware_eiq_deepviewrt_deps_flatcc true) - -# # description: DeepViewRT modelrunner server library -# set(CONFIG_USE_middleware_eiq_deepviewrt_deps_json true) - -# # description: DeepViewRT modelrunner server library -# set(CONFIG_USE_middleware_eiq_deepviewrt_deps_stb true) - -#set.middleware.azure_rtos -# # description: Azure RTOS Core -# set(CONFIG_USE_middleware_azure_rtos_tx_template true) - -# # description: Azure RTOS Core -# set(CONFIG_USE_middleware_azure_rtos_tx_mgr_template true) - -# # description: Real Time Operating System Kernel -# set(CONFIG_USE_middleware_azure_rtos_tx_lib true) - -# # description: Real Time Operating System Kernel -# set(CONFIG_USE_middleware_azure_rtos_tx_mgr_lib true) - -# # description: Real Time Operating System Kernel -# set(CONFIG_USE_middleware_azure_rtos_txm_lib true) - -# # description: A file system based on azure RTOS -# set(CONFIG_USE_middleware_azure_rtos_fx_template true) - -# # description: A file system based on azure RTOS -# set(CONFIG_USE_middleware_azure_rtos_fx_lib true) - -# # description: A GUI library based on azure RTOS -# set(CONFIG_USE_middleware_azure_rtos_gx_lib true) - -# # description: A network protocol stack based on azure RTOS -# set(CONFIG_USE_middleware_azure_rtos_nxd_template true) - -# # description: A network protocol stack based on azure RTOS -# set(CONFIG_USE_middleware_azure_rtos_nxd_lib true) - -# # description: A USB library based on azure RTOS -# set(CONFIG_USE_middleware_azure_rtos_ux_template true) - -# # description: Azure RTOS USBX Host Controller EHCI -# set(CONFIG_USE_middleware_azure_rtos_ux_ehci true) - -# # description: Azure RTOS USBX Host Controller OHCI -# set(CONFIG_USE_middleware_azure_rtos_ux_ohci true) - -# # description: Azure RTOS USBX Host Controller IP3516 -# set(CONFIG_USE_middleware_azure_rtos_ux_ip3516 true) - -# # description: Azure RTOS USBX Device Controller IP3511 -# set(CONFIG_USE_middleware_azure_rtos_ux_ip3511 true) - -# # description: Azure RTOS USBX Device Controller for i.MX RT -# set(CONFIG_USE_middleware_azure_rtos_ux_dci true) - -# # description: A USB library based on azure RTOS -# set(CONFIG_USE_middleware_azure_rtos_ux_lib true) - -# # description: Azure RTOS Core -# set(CONFIG_USE_middleware_azure_rtos_tx true) - -# # description: Azure RTOS Core -# set(CONFIG_USE_middleware_azure_rtos_tx_mgr true) - -# # description: Azure RTOS Core -# set(CONFIG_USE_middleware_azure_rtos_tx_sp true) - -# # description: A file system based on azure RTOS -# set(CONFIG_USE_middleware_azure_rtos_fx true) - -# # description: A file system based on azure RTOS -# set(CONFIG_USE_middleware_azure_rtos_fx_sp true) - -# # description: A GUI library based on azure RTOS -# set(CONFIG_USE_middleware_azure_rtos_gx true) - -# # description: LevelX provides NAND and NOR flash wear leveling facilities to embedded applications -# set(CONFIG_USE_middleware_azure_rtos_lx true) - -# # description: A network protocol stack based on azure RTOS -# set(CONFIG_USE_middleware_azure_rtos_nxd true) - -# # description: A network protocol stack based on azure RTOS -# set(CONFIG_USE_middleware_azure_rtos_nxd_sp true) - -# # description: Azure NetX Duo driver based on i.MXRT series -# set(CONFIG_USE_middleware_netxduo_imxrt true) - -# # description: A USB library based on azure RTOS -# set(CONFIG_USE_middleware_azure_rtos_ux true) - -# # description: A USB library based on azure RTOS -# set(CONFIG_USE_middleware_azure_rtos_ux_sp true) - -# # description: A software package that connects to the IoT Hub through Azure RTOS -# set(CONFIG_USE_middleware_azure_rtos_azure_iot true) - #set.middleware.edgefast_bluetooth # # description: edgefast_bluetooth configuration template for LE audio # set(CONFIG_USE_middleware_edgefast_bluetooth_le_audio_config_template true) @@ -1463,6 +1305,12 @@ # # description: edgefast_bluetooth le_audio.tmap # set(CONFIG_USE_middleware_edgefast_bluetooth_le_audio_tmap true) +# # description: edgefast_bluetooth le_audio.gmap +# set(CONFIG_USE_middleware_edgefast_bluetooth_le_audio_gmap true) + +# # description: edgefast_bluetooth le_audio.pbp +# set(CONFIG_USE_middleware_edgefast_bluetooth_le_audio_pbp true) + # # description: edgefast_bluetooth PAL configuration template # set(CONFIG_USE_middleware_edgefast_bluetooth_config_template true) @@ -1655,6 +1503,67 @@ # # description: BLE libraries for bt_ble Host stack # set(CONFIG_USE_middleware_edgefast_bluetooth_ble_ethermind_lib_lc3_cm7f true) +#set.middleware.eiq +# # description: Flatbuffers library +# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_third_party_flatbuffers true) + +# # description: Gemmlowp library +# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_third_party_gemmlowp true) + +# # description: Ruy library +# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_third_party_ruy true) + +# # description: General Purpose FFT (Fast Fourier/Cosine/Sine Transform) Package +# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_third_party_fft2d true) + +# # description: A mixed-radix Fast Fourier Transform library +# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_third_party_kissfft true) + +# # description: Utilities for Glow NN compiler. +# set(CONFIG_USE_middleware_eiq_glow true) + +# # description: Multimedia Processing Pipelines Library +# set(CONFIG_USE_middleware_eiq_mpp true) + +# # description: CMSIS-NN library +# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_third_party_cmsis_nn true) + +# # description: TensorFlow Lite Micro library with reference kernel implementations +# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_reference true) + +# # description: TensorFlow Lite Micro library with CMSIS-NN kernel implementations +# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_cmsis_nn true) + +# # description: TensorFlow Lite Micro library binary with core specific kernel implementations +# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_binary true) + +# # description: TensorFlow Lite Micro library header files +# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_headers true) + +# # description: TensorFlow Lite Micro library +# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro true) + +# # description: TensorFlow Lite Micro word detection library +# set(CONFIG_USE_middleware_eiq_tensorflow_lite_micro_examples_microspeech true) + +# # description: DeepViewRT Runtime library +# set(CONFIG_USE_middleware_eiq_deepviewrt_nnlib true) + +# # description: DeepViewRT modelrunner server library +# set(CONFIG_USE_middleware_eiq_deepviewrt_modelrunner_server true) + +# # description: DeepViewRT modelrunner server library +# set(CONFIG_USE_middleware_eiq_deepviewrt_modelrunner_server_flash true) + +# # description: DeepViewRT modelrunner server library +# set(CONFIG_USE_middleware_eiq_deepviewrt_deps_flatcc true) + +# # description: DeepViewRT modelrunner server library +# set(CONFIG_USE_middleware_eiq_deepviewrt_deps_json true) + +# # description: DeepViewRT modelrunner server library +# set(CONFIG_USE_middleware_eiq_deepviewrt_deps_stb true) + #set.middleware.wireless.framework # # description: Middleware wireless framework_sec_lib # set(CONFIG_USE_middleware_wireless_framework_sec_lib true) @@ -1665,6 +1574,9 @@ # # description: Middleware wireless framework_platform_coex # set(CONFIG_USE_middleware_wireless_framework_platform_coex_rt1170 true) +# # description: Middleware wireless framework_platform_internal_flash +# set(CONFIG_USE_middleware_wireless_framework_platform_internal_flash_rt1170 true) + # # description: Middleware wireless framework_board_lp # set(CONFIG_USE_middleware_wireless_framework_board_lp_MIMXRT1176 true) @@ -1692,6 +1604,9 @@ # # description: Middleware wireless framework_rpmsg_config # set(CONFIG_USE_middleware_wireless_framework_rpmsg_config true) +# # description: Middleware wireless framework_mbedtls_config +# set(CONFIG_USE_middleware_wireless_framework_mbedtls_config_rt1170 true) + # # description: Middleware wireless framework platform ot coex # set(CONFIG_USE_middleware_wireless_framework_platform_rt_ot_coex true) @@ -1737,9 +1652,6 @@ # # description: Middleware wireless framework_sbtsnoop_nxp_ble_port # set(CONFIG_USE_middleware_wireless_framework_sbtsnoop_nxp_ble_port true) -# # description: Middleware wireless framework_fwk_debug -# set(CONFIG_USE_middleware_wireless_framework_fwk_debug true) - # # description: Middleware wireless framework_linkscripts_kw45 # set(CONFIG_USE_middleware_wireless_framework_linkscripts_kw45 true) @@ -1764,6 +1676,9 @@ # # description: Middleware wireless framework_PDUM # set(CONFIG_USE_middleware_wireless_framework_PDUM true) +# # description: Middleware wireless framework_PDUM rt1170 +# set(CONFIG_USE_middleware_wireless_framework_PDUM_rt1170 true) + # # description: Middleware wireless framework_markdown # set(CONFIG_USE_middleware_wireless_framework_markdown true) @@ -1785,6 +1700,15 @@ # # description: Middleware wireless fwk_lfs_mflash # set(CONFIG_USE_middleware_wireless_framework_fsabstraction_littlefs true) +# # description: Single wire output debug +# set(CONFIG_USE_middleware_wireless_framework_swo_dbg true) + +# # description: Middleware wireless framework_settings +# set(CONFIG_USE_middleware_wireless_framework_settings true) + +# # description: Middleware wireless framework_settings +# set(CONFIG_USE_middleware_wireless_framework_NVS true) + # # description: Middleware wireless framework_platform # set(CONFIG_USE_middleware_wireless_framework_platform_rt1170 true) @@ -1800,6 +1724,15 @@ # # description: Middleware wireless framework_platform_ota # set(CONFIG_USE_middleware_wireless_framework_platform_ota_rt1170 true) +# # description: Middleware wireless framework_platform_ics +# set(CONFIG_USE_middleware_wireless_framework_platform_ics_rt1170 true) + +# # description: Middleware wireless framework_mws +# set(CONFIG_USE_middleware_wireless_framework_MWS true) + +# # description: Middleware wireless framework_mws intercore +# set(CONFIG_USE_middleware_wireless_framework_MWS_Intercore true) + # # description: Middleware wireless framework_platform_mws # set(CONFIG_USE_middleware_wireless_framework_platform_mws_rt1170 true) @@ -1818,6 +1751,12 @@ # # description: Middleware wireless framework_platform_lowpower_timer # set(CONFIG_USE_middleware_wireless_framework_platform_lowpower_timer_rt1170 true) +# # description: Middleware wireless framework_platform_reset +# set(CONFIG_USE_middleware_wireless_framework_platform_reset_rt1170 true) + +# # description: Middleware wireless framework_sec_lib_mbedtls +# set(CONFIG_USE_middleware_wireless_framework_sec_lib_mbedtls_m7 true) + # # description: Middleware wireless framework_sec_lib_sss # set(CONFIG_USE_middleware_wireless_framework_sec_lib_sss_m7 true) @@ -1827,6 +1766,12 @@ # # description: Middleware wireless framework_sbtsnoop # set(CONFIG_USE_middleware_wireless_framework_sbtsnoop true) +# # description: Middleware wireless framework_fwk_debug +# set(CONFIG_USE_middleware_wireless_framework_fwk_debug true) + +# # description: Middleware wireless sensors +# set(CONFIG_USE_middleware_wireless_Sensors true) + # # description: FreeRTOS heap for framework mem_manager # set(CONFIG_USE_middleware_wireless_freertos_heap true) @@ -1851,6 +1796,97 @@ # # description: Middleware wireless KeyStorage # set(CONFIG_USE_middleware_wireless_framework_keystorage true) +#set.middleware.azure_rtos +# # description: Azure RTOS Core +# set(CONFIG_USE_middleware_azure_rtos_tx_template true) + +# # description: Azure RTOS Core +# set(CONFIG_USE_middleware_azure_rtos_tx_mgr_template true) + +# # description: Real Time Operating System Kernel +# set(CONFIG_USE_middleware_azure_rtos_tx_lib true) + +# # description: Real Time Operating System Kernel +# set(CONFIG_USE_middleware_azure_rtos_tx_mgr_lib true) + +# # description: Real Time Operating System Kernel +# set(CONFIG_USE_middleware_azure_rtos_txm_lib true) + +# # description: A file system based on azure RTOS +# set(CONFIG_USE_middleware_azure_rtos_fx_template true) + +# # description: A file system based on azure RTOS +# set(CONFIG_USE_middleware_azure_rtos_fx_lib true) + +# # description: A GUI library based on azure RTOS +# set(CONFIG_USE_middleware_azure_rtos_gx_lib true) + +# # description: A network protocol stack based on azure RTOS +# set(CONFIG_USE_middleware_azure_rtos_nxd_template true) + +# # description: A network protocol stack based on azure RTOS +# set(CONFIG_USE_middleware_azure_rtos_nxd_lib true) + +# # description: A USB library based on azure RTOS +# set(CONFIG_USE_middleware_azure_rtos_ux_template true) + +# # description: Azure RTOS USBX Host Controller EHCI +# set(CONFIG_USE_middleware_azure_rtos_ux_ehci true) + +# # description: Azure RTOS USBX Host Controller OHCI +# set(CONFIG_USE_middleware_azure_rtos_ux_ohci true) + +# # description: Azure RTOS USBX Host Controller IP3516 +# set(CONFIG_USE_middleware_azure_rtos_ux_ip3516 true) + +# # description: Azure RTOS USBX Device Controller IP3511 +# set(CONFIG_USE_middleware_azure_rtos_ux_ip3511 true) + +# # description: Azure RTOS USBX Device Controller for i.MX RT +# set(CONFIG_USE_middleware_azure_rtos_ux_dci true) + +# # description: A USB library based on azure RTOS +# set(CONFIG_USE_middleware_azure_rtos_ux_lib true) + +# # description: Azure RTOS Core +# set(CONFIG_USE_middleware_azure_rtos_tx true) + +# # description: Azure RTOS Core +# set(CONFIG_USE_middleware_azure_rtos_tx_mgr true) + +# # description: Azure RTOS Core +# set(CONFIG_USE_middleware_azure_rtos_tx_sp true) + +# # description: A file system based on azure RTOS +# set(CONFIG_USE_middleware_azure_rtos_fx true) + +# # description: A file system based on azure RTOS +# set(CONFIG_USE_middleware_azure_rtos_fx_sp true) + +# # description: A GUI library based on azure RTOS +# set(CONFIG_USE_middleware_azure_rtos_gx true) + +# # description: LevelX provides NAND and NOR flash wear leveling facilities to embedded applications +# set(CONFIG_USE_middleware_azure_rtos_lx true) + +# # description: A network protocol stack based on azure RTOS +# set(CONFIG_USE_middleware_azure_rtos_nxd true) + +# # description: A network protocol stack based on azure RTOS +# set(CONFIG_USE_middleware_azure_rtos_nxd_sp true) + +# # description: Azure NetX Duo driver based on i.MXRT series +# set(CONFIG_USE_middleware_netxduo_imxrt true) + +# # description: A USB library based on azure RTOS +# set(CONFIG_USE_middleware_azure_rtos_ux true) + +# # description: A USB library based on azure RTOS +# set(CONFIG_USE_middleware_azure_rtos_ux_sp true) + +# # description: A software package that connects to the IoT Hub through Azure RTOS +# set(CONFIG_USE_middleware_azure_rtos_azure_iot true) + #set.middleware.wireless.wpa_supplicant # # description: Wpa supplicant rtos # set(CONFIG_USE_middleware_wireless_wpa_supplicant_rtos true) diff --git a/manifests/EVK-MIMXRT1020_manifest_v3_14.xml b/manifests/EVK-MIMXRT1020_manifest_v3_14.xml index 1aa19ace8..a2a56bd0b 100644 --- a/manifests/EVK-MIMXRT1020_manifest_v3_14.xml +++ b/manifests/EVK-MIMXRT1020_manifest_v3_14.xml @@ -1,5 +1,5 @@ - + @@ -9,7 +9,7 @@ - + diff --git a/manifests/EVK-MIMXRT1060_manifest_v3_14.xml b/manifests/EVK-MIMXRT1060_manifest_v3_14.xml index 35803454c..108dfe1d1 100644 --- a/manifests/EVK-MIMXRT1060_manifest_v3_14.xml +++ b/manifests/EVK-MIMXRT1060_manifest_v3_14.xml @@ -1,5 +1,5 @@ - + @@ -17,7 +17,7 @@ - + @@ -33,9 +33,9 @@ + - @@ -2773,7 +2773,7 @@ ${load} - + @@ -2781,14 +2781,11 @@ ${load} - - - - - + + - + @@ -2796,11 +2793,14 @@ ${load} - - + + + + + - + @@ -2808,10 +2808,8 @@ ${load} - - - - + + diff --git a/manifests/EVK-MIMXRT1064_manifest_v3_14.xml b/manifests/EVK-MIMXRT1064_manifest_v3_14.xml index 6384ebda6..f7c53b9ef 100644 --- a/manifests/EVK-MIMXRT1064_manifest_v3_14.xml +++ b/manifests/EVK-MIMXRT1064_manifest_v3_14.xml @@ -1,5 +1,5 @@ - + @@ -10,7 +10,7 @@ - + diff --git a/manifests/EVKB-IMXRT1050_manifest_v3_14.xml b/manifests/EVKB-IMXRT1050_manifest_v3_14.xml index 7656d18f1..8a546850f 100644 --- a/manifests/EVKB-IMXRT1050_manifest_v3_14.xml +++ b/manifests/EVKB-IMXRT1050_manifest_v3_14.xml @@ -1,5 +1,5 @@ - + @@ -10,7 +10,7 @@ - + diff --git a/manifests/LPCXpresso55S06_manifest_v3_14.xml b/manifests/LPCXpresso55S06_manifest_v3_14.xml index 52bb08317..5c992a957 100644 --- a/manifests/LPCXpresso55S06_manifest_v3_14.xml +++ b/manifests/LPCXpresso55S06_manifest_v3_14.xml @@ -1,12 +1,12 @@ - + - + diff --git a/manifests/LPCXpresso55S16_manifest_v3_14.xml b/manifests/LPCXpresso55S16_manifest_v3_14.xml index 8042d7317..7a3a7fd4d 100644 --- a/manifests/LPCXpresso55S16_manifest_v3_14.xml +++ b/manifests/LPCXpresso55S16_manifest_v3_14.xml @@ -1,5 +1,5 @@ - + @@ -8,7 +8,7 @@ - + diff --git a/manifests/LPCXpresso55S28_manifest_v3_14.xml b/manifests/LPCXpresso55S28_manifest_v3_14.xml index ec0e5bc8b..a4d079ff7 100644 --- a/manifests/LPCXpresso55S28_manifest_v3_14.xml +++ b/manifests/LPCXpresso55S28_manifest_v3_14.xml @@ -1,5 +1,5 @@ - + @@ -8,7 +8,7 @@ - + @@ -2944,8 +2944,6 @@ ${load} - - @@ -2965,16 +2963,16 @@ ${load} + - + - + - @@ -3006,9 +3004,9 @@ ${load} + - @@ -3026,16 +3024,16 @@ ${load} + - + - @@ -3043,11 +3041,13 @@ ${load} + - - + + + diff --git a/manifests/LPCXpresso55S36_manifest_v3_14.xml b/manifests/LPCXpresso55S36_manifest_v3_14.xml index 80b3e3046..fbdc0135b 100644 --- a/manifests/LPCXpresso55S36_manifest_v3_14.xml +++ b/manifests/LPCXpresso55S36_manifest_v3_14.xml @@ -1,5 +1,5 @@ - + @@ -11,7 +11,7 @@ - + diff --git a/manifests/LPCXpresso55S69_manifest_v3_14.xml b/manifests/LPCXpresso55S69_manifest_v3_14.xml index df430ef19..d3f6fa0f6 100644 --- a/manifests/LPCXpresso55S69_manifest_v3_14.xml +++ b/manifests/LPCXpresso55S69_manifest_v3_14.xml @@ -1,5 +1,5 @@ - + @@ -11,7 +11,7 @@ - + diff --git a/manifests/MIMXRT1040-EVK_manifest_v3_14.xml b/manifests/MIMXRT1040-EVK_manifest_v3_14.xml index 889fe3445..ca69c15a6 100644 --- a/manifests/MIMXRT1040-EVK_manifest_v3_14.xml +++ b/manifests/MIMXRT1040-EVK_manifest_v3_14.xml @@ -1,5 +1,5 @@ - + @@ -10,7 +10,7 @@ - + diff --git a/manifests/MIMXRT1060-EVKB_manifest_v3_14.xml b/manifests/MIMXRT1060-EVKB_manifest_v3_14.xml index 413317665..db378d1d8 100644 --- a/manifests/MIMXRT1060-EVKB_manifest_v3_14.xml +++ b/manifests/MIMXRT1060-EVKB_manifest_v3_14.xml @@ -1,5 +1,5 @@ - + @@ -17,7 +17,7 @@ - + @@ -33,9 +33,9 @@ + - @@ -2773,7 +2773,7 @@ ${load} - + @@ -2781,14 +2781,11 @@ ${load} - - - - - + + - + @@ -2796,11 +2793,14 @@ ${load} - - + + + + + - + @@ -2808,10 +2808,8 @@ ${load} - - - - + + diff --git a/manifests/MIMXRT1060-EVKC_manifest_v3_14.xml b/manifests/MIMXRT1060-EVKC_manifest_v3_14.xml index 9dd6dbd52..4e9b5f7b1 100644 --- a/manifests/MIMXRT1060-EVKC_manifest_v3_14.xml +++ b/manifests/MIMXRT1060-EVKC_manifest_v3_14.xml @@ -1,5 +1,5 @@ - + @@ -17,7 +17,7 @@ - + @@ -33,9 +33,9 @@ + - @@ -2773,7 +2773,7 @@ ${load} - + @@ -2781,14 +2781,11 @@ ${load} - - - - - + + - + @@ -2796,11 +2793,14 @@ ${load} - - + + + + + - + @@ -2808,10 +2808,8 @@ ${load} - - - - + + diff --git a/manifests/MIMXRT1160-EVK_manifest_v3_14.xml b/manifests/MIMXRT1160-EVK_manifest_v3_14.xml index 51b79d6ef..c35b98efb 100644 --- a/manifests/MIMXRT1160-EVK_manifest_v3_14.xml +++ b/manifests/MIMXRT1160-EVK_manifest_v3_14.xml @@ -1,5 +1,5 @@ - + @@ -12,7 +12,7 @@ - + diff --git a/manifests/MIMXRT1170-EVKB_manifest_v3_14.xml b/manifests/MIMXRT1170-EVKB_manifest_v3_14.xml index 4030c1ca5..1e35e07e1 100644 --- a/manifests/MIMXRT1170-EVKB_manifest_v3_14.xml +++ b/manifests/MIMXRT1170-EVKB_manifest_v3_14.xml @@ -1,13 +1,13 @@ - + + - @@ -17,15 +17,15 @@ - + + - @@ -33,10 +33,10 @@ - - + + @@ -2706,6 +2706,17 @@ ${load} + + + + + + + + + + + @@ -2727,15 +2738,15 @@ ${load} - + - + + + + - - - - + @@ -4710,17 +4721,6 @@ ${load} - - - - - - - - - - - diff --git a/manifests/MIMXRT1170-EVK_manifest_v3_14.xml b/manifests/MIMXRT1170-EVK_manifest_v3_14.xml index a4c217bbd..b2f9e118a 100644 --- a/manifests/MIMXRT1170-EVK_manifest_v3_14.xml +++ b/manifests/MIMXRT1170-EVK_manifest_v3_14.xml @@ -1,13 +1,13 @@ - + + - @@ -17,15 +17,15 @@ - + + - @@ -33,10 +33,10 @@ - - + + @@ -2717,6 +2717,17 @@ ${load} + + + + + + + + + + + @@ -2738,15 +2749,15 @@ ${load} - + - + + + + - - - - + @@ -4721,17 +4732,6 @@ ${load} - - - - - - - - - - - diff --git a/middleware/mmcau/manifests/middleware_nxp_mmcau_MIMXRT1166_manifest_v3_14.xml b/middleware/mmcau/manifests/middleware_nxp_mmcau_MIMXRT1166_manifest_v3_14.xml index 5941525b6..d4be759cb 100644 --- a/middleware/mmcau/manifests/middleware_nxp_mmcau_MIMXRT1166_manifest_v3_14.xml +++ b/middleware/mmcau/manifests/middleware_nxp_mmcau_MIMXRT1166_manifest_v3_14.xml @@ -10,7 +10,7 @@ - + diff --git a/middleware/mmcau/manifests/middleware_nxp_mmcau_MIMXRT1176_manifest_v3_14.xml b/middleware/mmcau/manifests/middleware_nxp_mmcau_MIMXRT1176_manifest_v3_14.xml index 0b3cff3c4..1a207659f 100644 --- a/middleware/mmcau/manifests/middleware_nxp_mmcau_MIMXRT1176_manifest_v3_14.xml +++ b/middleware/mmcau/manifests/middleware_nxp_mmcau_MIMXRT1176_manifest_v3_14.xml @@ -10,7 +10,7 @@ - + diff --git a/middleware/mmcau/set_middleware_mmcau.cmake b/middleware/mmcau/set_middleware_mmcau.cmake index e25d6c466..994682c2a 100644 --- a/middleware/mmcau/set_middleware_mmcau.cmake +++ b/middleware/mmcau/set_middleware_mmcau.cmake @@ -6,16 +6,6 @@ if (CONFIG_USE_middleware_mmcau_mmcau_files) message("middleware_mmcau_mmcau_files component is included from ${CMAKE_CURRENT_LIST_FILE}.") -if(CONFIG_CORE STREQUAL cm0p) - target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE - ${CMAKE_CURRENT_LIST_DIR}/./asm-cm0p/src/mmcau_aes_functions.s - ${CMAKE_CURRENT_LIST_DIR}/./asm-cm0p/src/mmcau_des_functions.s - ${CMAKE_CURRENT_LIST_DIR}/./asm-cm0p/src/mmcau_md5_functions.s - ${CMAKE_CURRENT_LIST_DIR}/./asm-cm0p/src/mmcau_sha1_functions.s - ${CMAKE_CURRENT_LIST_DIR}/./asm-cm0p/src/mmcau_sha256_functions.s - ) -endif() - if((CONFIG_CORE STREQUAL cm4f OR CONFIG_CORE STREQUAL cm7f)) target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE ${CMAKE_CURRENT_LIST_DIR}/./asm-cm4-cm7/src/mmcau_aes_functions.s @@ -58,34 +48,6 @@ endif() endif() -if (CONFIG_USE_middleware_mmcau_cm0p) -# Add set(CONFIG_USE_middleware_mmcau_cm0p true) in config.cmake to use this component - -message("middleware_mmcau_cm0p component is included from ${CMAKE_CURRENT_LIST_FILE}.") - -if((CONFIG_CORE STREQUAL cm0p) AND CONFIG_USE_middleware_mmcau_common_files AND CONFIG_USE_driver_clock AND CONFIG_USE_driver_common) - -target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC - ${CMAKE_CURRENT_LIST_DIR}/./. -) - -if((CONFIG_TOOLCHAIN STREQUAL armgcc OR CONFIG_TOOLCHAIN STREQUAL mcux)) - target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE - -Wl,--start-group - ${CMAKE_CURRENT_LIST_DIR}/./asm-cm0p/lib_mmcau-cm0p.a - -Wl,--end-group - ) -endif() - -else() - -message(SEND_ERROR "middleware_mmcau_cm0p dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") - -endif() - -endif() - - if (CONFIG_USE_middleware_mmcau_common_files) # Add set(CONFIG_USE_middleware_mmcau_common_files true) in config.cmake to use this component diff --git a/utilities/debug_console/fsl_debug_console.c b/utilities/debug_console/fsl_debug_console.c index a5df8e14b..58d26021f 100644 --- a/utilities/debug_console/fsl_debug_console.c +++ b/utilities/debug_console/fsl_debug_console.c @@ -428,8 +428,8 @@ status_t DbgConsole_ReadOneCharacter(uint8_t *ch) #if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \ (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM) && defined(OSA_USED) return (status_t)kStatus_Fail; -#else /*defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == \ - DEBUG_CONSOLE_SYNCHRONIZATION_BM) && defined(OSA_USED)*/ +#else /*defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == \ + DEBUG_CONSOLE_SYNCHRONIZATION_BM) && defined(OSA_USED)*/ serial_manager_status_t serialManagerStatus = kStatus_SerialManager_Error; /* recieve one char every time */ @@ -437,7 +437,8 @@ status_t DbgConsole_ReadOneCharacter(uint8_t *ch) serialManagerStatus = SerialManager_ReadNonBlocking(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), ch, 1); #else /*defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)*/ - serialManagerStatus = SerialManager_ReadBlocking(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), ch, 1); + serialManagerStatus = + SerialManager_ReadBlocking(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), ch, 1); #endif /*defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)*/ if (kStatus_SerialManager_Success != serialManagerStatus) { @@ -453,7 +454,7 @@ status_t DbgConsole_ReadOneCharacter(uint8_t *ch) #endif /*defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == \ DEBUG_CONSOLE_SYNCHRONIZATION_BM) && defined(OSA_USED)*/ -#else /*(defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))*/ +#else /*(defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))*/ return (status_t)kStatus_Fail; @@ -771,8 +772,8 @@ static const serial_port_uart_config_t uartConfig = {.instance = BOARD_DEBUG /* See fsl_debug_console.h for documentation of this function. */ status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t device, uint32_t clkSrcFreq) { - serial_manager_config_t serialConfig = {0}; - serial_manager_status_t serialManagerStatus = kStatus_SerialManager_Success; + serial_manager_config_t serialConfig; + serial_manager_status_t serialManagerStatus = kStatus_SerialManager_Success; #if (defined(SERIAL_USE_CONFIGURE_STRUCTURE) && (SERIAL_USE_CONFIGURE_STRUCTURE == 0U)) #if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) @@ -793,7 +794,7 @@ status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t }; #endif #endif - + (void)memset(&serialConfig, 0x0, sizeof(serial_manager_config_t)); #if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) serial_port_usb_cdc_config_t usbCdcConfig = { .controllerIndex = (serial_port_usb_cdc_controller_index_t)instance, @@ -882,7 +883,7 @@ status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t #endif s_debugConsoleState.serialHandle = (serial_handle_t)&s_debugConsoleState.serialHandleBuffer[0]; - serialManagerStatus = SerialManager_Init(s_debugConsoleState.serialHandle, &serialConfig); + serialManagerStatus = SerialManager_Init(s_debugConsoleState.serialHandle, &serialConfig); assert(kStatus_SerialManager_Success == serialManagerStatus); @@ -1002,7 +1003,7 @@ status_t DbgConsole_Deinit(void) } #endif /* ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART)) */ -#if (((defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK))) || \ +#if (((defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK))) || \ ((SDK_DEBUGCONSOLE != DEBUGCONSOLE_REDIRECT_TO_SDK) && defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \ (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U)))) DEBUG_CONSOLE_FUNCTION_PREFIX status_t DbgConsole_Flush(void) @@ -1142,7 +1143,7 @@ int DbgConsole_BlockingVprintf(const char *fmt_s, va_list formatStringArg) status_t DbgConsole_TryGetchar(char *ch) { #if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) - uint32_t length = 0; + uint32_t length = 0; status_t dbgConsoleStatus = (status_t)kStatus_Fail; assert(ch); diff --git a/west.yml b/west.yml index adc388052..edaf661d9 100644 --- a/west.yml +++ b/west.yml @@ -10,17 +10,17 @@ manifest: remote: nxp-mcuxpresso projects: - name: mcux-sdk-examples - revision: MCUX_2.15.000 + revision: MCUX_2.15.100 path: examples - name: FreeRTOS-Kernel - revision: MCUX_2.15.000 + revision: MCUX_2.15.100 path: rtos/freertos/freertos-kernel - name: mcux-sdk-middleware-sdmmc - revision: MCUX_2.15.000 + revision: MCUX_2.15.100 path: middleware/sdmmc - name: mcux-sdk-middleware-multicore path: middleware/multicore - revision: MCUX_2.15.000 + revision: MCUX_2.15.100 - name: rpmsg-lite path: middleware/multicore/rpmsg_lite revision: v5.1.1 @@ -33,9 +33,9 @@ manifest: path: svd - name: fatfs path: middleware/fatfs - revision: MCUX_2.15.000 + revision: MCUX_2.15.100 - name: mcux-sdk-middleware-eiq - revision: MCUX_2.15.000 + revision: MCUX_2.15.100 path: middleware/eiq - name: mcux-sdk-middleware-deepviewrt revision: MCUX_2.13.1 @@ -44,65 +44,65 @@ manifest: revision: MCUX_2.15.000 path: middleware/eiq/glow - name: mcux-sdk-middleware-tensorflow - revision: MCUX_2.15.000 + revision: MCUX_2.15.100 path: middleware/eiq/tensorflow-lite - name: mcux-sdk-middleware-usb path: middleware/usb - revision: MCUX_2.15.000 + revision: MCUX_2.15.100 - name: mcux-sdk-middleware-edgefast-bluetooth path: middleware/edgefast_bluetooth - revision: MCUX_2.15.000 + revision: MCUX_2.15.100 - name: mcux-sdk-middleware-ethermind path: middleware/wireless/ethermind - revision: MCUX_2.15.000 + revision: MCUX_2.15.100 remote: nxp - name: azure-rtos path: rtos/azure-rtos - revision: MCUX_2.15.000 + revision: MCUX_2.15.100 remote: nxp - name: threadx path: rtos/azure-rtos/threadx - revision: MCUX_2.15.000 + revision: MCUX_2.15.100 remote: nxp - name: filex path: rtos/azure-rtos/filex - revision: MCUX_2.15.000 + revision: MCUX_2.15.100 remote: nxp - name: levelx path: rtos/azure-rtos/levelx - revision: MCUX_2.15.000 + revision: MCUX_2.15.100 remote: nxp - name: netxduo path: rtos/azure-rtos/netxduo - revision: MCUX_2.15.000 + revision: MCUX_2.15.100 remote: nxp - name: usbx path: rtos/azure-rtos/usbx - revision: MCUX_2.15.000 + revision: MCUX_2.15.100 remote: nxp - name: guix path: rtos/azure-rtos/guix - revision: MCUX_2.15.000 + revision: MCUX_2.15.100 remote: nxp - name: mbedtls path: middleware/mbedtls - revision: MCUX_2.15.000 + revision: MCUX_2.15.100 - name: wifi_nxp path: middleware/wifi_nxp - revision: MCUX_2.15.000 + revision: MCUX_2.15.100 remote: nxp - name: lwip path: middleware/lwip - revision: MCUX_2.15.000 + revision: MCUX_2.15.100 - name: littlefs path: middleware/littlefs - revision: MCUX_2.15.000 + revision: MCUX_2.15.100 - name: maestro path: middleware/maestro - revision: MCUX_2.15.000 + revision: MCUX_2.15.100 - name: mcuboot path: middleware/mcuboot_opensource - revision: MCUX_2.15.000 + revision: MCUX_2.15.100 remote: nxp_zephyr - name: CMSIS_5 path: core/CMSIS @@ -112,19 +112,19 @@ manifest: revision: MCUX_2.14.0 - name: VIT path: middleware/vit - revision: MCUX_2.15.000 + revision: MCUX_2.15.100 - name: VoiceSeeker path: middleware/voice_seeker - revision: MCUX_2.15.000 + revision: MCUX_2.15.100 - name: NatureDSP path: middleware/dsp revision: MCUX_2.15.000 - name: wpa_supplicant-rtos path: middleware/wireless/wpa_supplicant-rtos - revision: MCUX_2.15.000 + revision: MCUX_2.15.100 - name: mcux-sdk-middleware-connectivity-framework path: middleware/wireless/framework - revision: MCUX_2.15.000 + revision: MCUX_2.15.100 remote: nxp self: path: core