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Feature request: precise TTL output control from the Open Ephys aquisition board #13

@paulmthompson

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@paulmthompson

I currently use old custom software (https://github.com/paulmthompson/Intan.jl) to control the Intan version of the acquisition board to generate pulse trains. I had to do some verilog modifications (similar to what the RHS system uses) so that I could have the FPGA generate precisely timed TTLs with custom frequency, pulse width etc.

Soon I am going to be using a different rig with a Open Ephys acquisition board. I believe OpenEphys currently lacks this functionality, correct? Consequently, I am going to have to adapt my previous custom verilog code to use the OpenEphys board.

Would you be interested if I made a pull request of this feature? I can do the verilog modifications here in this repository and generate the bitfile but I might need some help making the OpenEphys plugin.

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