From 2fc51022f803a2eab07adc9120f3dd7173fa0cf7 Mon Sep 17 00:00:00 2001 From: Paul Date: Fri, 3 Jun 2022 15:15:41 -0400 Subject: [PATCH 1/3] added digital output sequencer --- RHD2000InterfaceXEM6010.xise | 2 +- digout_sequencer.v | 188 +++++++++++++++++++++++++++++++++++ main.v | 107 ++++++++++++++++++-- 3 files changed, 290 insertions(+), 7 deletions(-) create mode 100644 digout_sequencer.v diff --git a/RHD2000InterfaceXEM6010.xise b/RHD2000InterfaceXEM6010.xise index c36a7d4..070ad54 100755 --- a/RHD2000InterfaceXEM6010.xise +++ b/RHD2000InterfaceXEM6010.xise @@ -167,7 +167,7 @@ - + diff --git a/digout_sequencer.v b/digout_sequencer.v new file mode 100644 index 0000000..aa33a41 --- /dev/null +++ b/digout_sequencer.v @@ -0,0 +1,188 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: Intan Technologies, LLC +// +// Design Name: RHS2000 Rhythm Stim Interface +// Module Name: digout_sequencer +// Project Name: Opal Kelly FPGA/USB RHS2000 Interface +// Target Devices: +// Tool versions: +// Description: Generate pulse control signals for 16 digital outputs. +// +// Dependencies: +// +// Revision: 1.0 (26 October 2016) +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +module digout_sequencer #( + parameter MODULE = 0 + ) + ( + input wire reset, + input wire dataclk, + input wire [31:0] main_state, + input wire [5:0] channel, + input wire [3:0] prog_channel, + input wire [3:0] prog_address, + input wire [4:0] prog_module, + input wire [31:0] prog_word, //Make this a 32 bit wire value + input wire prog_trig, + input wire [31:0] triggers, + output reg [15:0] digout, + output wire [15:0] digout_enabled, + input wire shutdown, + input wire reset_sequencer + ); + + reg [31:0] counter[15:0]; //Adjust counter so it can go up to 32 bits for all 16 channels + + reg [4:0] trigger_source[15:0]; + reg [15:0] trigger_on_edge; + reg [15:0] trigger_polarity; + reg [15:0] trigger_enable; + + reg [7:0] number_of_stim_pulses[15:0]; + + reg [15:0] waiting_for_trigger, waiting_for_edge; + reg [7:0] stim_counter[15:0]; // Keeps track of the total number of pulses + + // We can have 32 bit registers here to accept 32 bit wire in values in order to have longer + // stimulation pulses and delays between each. + reg [31:0] event_start_stim[15:0]; + reg [31:0] event_end_stim[15:0]; + reg [31:0] event_repeat_stim[15:0]; + reg [31:0] event_end[15:0]; + + assign digout_enabled = trigger_enable; + + // Trigger selection + reg [15:0] trigger_in; + + always @(posedge dataclk) begin + if (channel == 0 && (main_state == 99 || main_state == 100)) begin + trigger_in[0] <= triggers[trigger_source[0]] ^ trigger_polarity[0]; + trigger_in[1] <= triggers[trigger_source[1]] ^ trigger_polarity[1]; + trigger_in[2] <= triggers[trigger_source[2]] ^ trigger_polarity[2]; + trigger_in[3] <= triggers[trigger_source[3]] ^ trigger_polarity[3]; + trigger_in[4] <= triggers[trigger_source[4]] ^ trigger_polarity[4]; + trigger_in[5] <= triggers[trigger_source[5]] ^ trigger_polarity[5]; + trigger_in[6] <= triggers[trigger_source[6]] ^ trigger_polarity[6]; + trigger_in[7] <= triggers[trigger_source[7]] ^ trigger_polarity[7]; + trigger_in[8] <= triggers[trigger_source[8]] ^ trigger_polarity[8]; + trigger_in[9] <= triggers[trigger_source[9]] ^ trigger_polarity[9]; + trigger_in[10] <= triggers[trigger_source[10]] ^ trigger_polarity[10]; + trigger_in[11] <= triggers[trigger_source[11]] ^ trigger_polarity[11]; + trigger_in[12] <= triggers[trigger_source[12]] ^ trigger_polarity[12]; + trigger_in[13] <= triggers[trigger_source[13]] ^ trigger_polarity[13]; + trigger_in[14] <= triggers[trigger_source[14]] ^ trigger_polarity[14]; + trigger_in[15] <= triggers[trigger_source[15]] ^ trigger_polarity[15]; + end + end + + // Register programming + always @(posedge prog_trig) begin + if (prog_module == MODULE) begin + case (prog_address) + 0: begin + trigger_source[prog_channel] <= prog_word[4:0]; + trigger_on_edge[prog_channel] <= prog_word[5]; + trigger_polarity[prog_channel] <= prog_word[6]; + trigger_enable[prog_channel] <= prog_word[7]; + end + 1: begin + number_of_stim_pulses[prog_channel] <= prog_word[7:0]; + end + 4: event_start_stim[prog_channel] <= prog_word; + 7: event_end_stim[prog_channel] <= prog_word; + 8: event_repeat_stim[prog_channel] <= prog_word; + 13: event_end[prog_channel] <= prog_word; + endcase + end + end + + wire [3:0] addr; + assign addr = channel[3:0]; + + // State machine for stim sequencing + + always @(posedge dataclk) begin + if (reset) begin + digout <= 16'b0; + waiting_for_trigger <=16'hffff; + waiting_for_edge <=16'hffff; + end else begin + if (channel[5:4] == 2'b00) begin // only for channel = 0-15 + case (main_state) + 99: begin + if (reset_sequencer) begin + digout <= 16'b0; + waiting_for_trigger <=16'hffff; + waiting_for_edge <=16'hffff; + end + end + 102: begin + if (waiting_for_edge[addr] && waiting_for_trigger[addr] && trigger_on_edge[addr]) begin + if (~trigger_in[addr]) begin + waiting_for_edge[addr] <= 1'b0; + end + end + if (waiting_for_trigger[addr]) begin + counter[addr] <= 32'b0; + stim_counter[addr] <= number_of_stim_pulses[addr]; + if (trigger_enable[addr] && trigger_in[addr] && (~trigger_on_edge[addr] || ~waiting_for_edge[addr])) begin + waiting_for_trigger[addr] <= 1'b0; + end else begin + digout[addr] <= 1'b0; + end + end + end + + 106: begin + if (~waiting_for_trigger[addr]) begin + if (event_start_stim[addr] == counter[addr]) begin + digout[addr] <= 1'b1; + end + end + end + + 110: begin + if (~waiting_for_trigger[addr]) begin + if (event_end_stim[addr] == counter[addr]) begin + digout[addr] <= 1'b0; + end + end + end + + 114: begin + if (shutdown) begin + digout[addr] <= 1'b0; + end + end + + 118: begin + // If we have reachd the end repeat time, and there are still pulses + if (event_repeat_stim[addr] == counter[addr] && stim_counter[addr] != 8'b0) begin + counter[addr] <= event_start_stim[addr]; + stim_counter[addr] <= stim_counter[addr] - 1; + + // We have reached the end and there are no pulses left + end else if (event_end[addr] == counter[addr] && stim_counter[addr] == 8'b0) begin + counter[addr] <= 32'b0; + waiting_for_trigger[addr] <= 1'b1; + waiting_for_edge[addr] <= trigger_on_edge[addr]; + end else begin + counter[addr] <= counter[addr] + 1; + end + end + default: begin + + end + endcase + end + end + end + +endmodule diff --git a/main.v b/main.v index 5e73a1a..563ce1a 100755 --- a/main.v +++ b/main.v @@ -174,7 +174,7 @@ module main #( output wire sync, // BNC-clock output input wire [15:0] TTL_in, - output wire [15:0] TTL_out, + output wire [15:0] TTL_out_direct, output wire DAC_SYNC, output wire DAC_SCLK, @@ -346,8 +346,7 @@ module main #( wire [15:0] data_stream_ADC_1, data_stream_ADC_2, data_stream_ADC_3, data_stream_ADC_4; wire [15:0] data_stream_ADC_5, data_stream_ADC_6, data_stream_ADC_7, data_stream_ADC_8; - wire TTL_out_mode; - reg [15:0] TTL_out_user; + wire [7:0] TTL_out_mode; wire reset, SPI_start, SPI_run_continuous; reg SPI_running; @@ -399,9 +398,13 @@ module main #( reg [3:0] external_fast_settle_channel; reg external_fast_settle, external_fast_settle_prev; - reg external_digout_enable_A, external_digout_enable_B, external_digout_enable_C, external_digout_enable_D; - reg [3:0] external_digout_channel_A, external_digout_channel_B, external_digout_channel_C, external_digout_channel_D; - reg external_digout_A, external_digout_B, external_digout_C, external_digout_D; + //PMT - Stimulation + reg external_digout_enable_A, external_digout_enable_B, external_digout_enable_C, external_digout_enable_D; + reg external_digout_enable_E, external_digout_enable_F, external_digout_enable_G, external_digout_enable_H; + reg [3:0] external_digout_channel_A, external_digout_channel_B, external_digout_channel_C, external_digout_channel_D; + reg [3:0] external_digout_channel_E, external_digout_channel_F, external_digout_channel_G, external_digout_channel_H; + reg external_digout_A, external_digout_B, external_digout_C, external_digout_D; + reg external_digout_E, external_digout_F, external_digout_G, external_digout_H; wire [7:0] led_in; @@ -414,6 +417,10 @@ module main #( wire pipeout_rdy; reg [31:0] usb3_blocksize; reg [31:0] ddr_blocksize; + + //Stimulation - PMT + wire reset_sequences; + wire [15:0] manual_triggers; // Opal Kelly USB Host Interface @@ -432,6 +439,15 @@ module main #( wire [31:0] ep38wireout, ep39wireout, ep3awireout, ep3bwireout, ep3cwireout, ep3dwireout, ep3ewireout, ep3fwireout; wire [31:0] ep40trigin, ep41trigin, ep42trigin, ep43trigin, ep44trigin, ep45trigin, ep46trigin, ep5atrigin; + + //Stimulation - PMT ep41 second bit will be for resetting sequencers, back 16 bits of ep43 will be for enabling digital output + wire [31:0] ep5btrigin; + + //Stimulation - PMT + wire stim_cm_en, prog_trig; + wire [3:0] prog_channel, prog_address; + wire [4:0] prog_module; + wire [31:0] prog_word; // USB WireIn inputs @@ -443,6 +459,7 @@ module main #( assign DAC_noise_suppress = ep00wirein[12:6]; assign DAC_gain = ep00wirein[15:13]; assign pipeout_override_en = ep00wirein[16]; //Open-ephys USB 3 support + assign TTL_out_mode = ep00wirein[24:17]; // PMT - stimulation assign max_timestep_in[15:0] = ep01wirein[15:0]; assign max_timestep_in[31:16] = ep02wirein[15:0]; @@ -574,10 +591,13 @@ module main #( assign DCM_prog_trigger = ep40trigin[0]; assign SPI_start = ep41trigin[0]; + assign reset_sequences = ep41trigin[1]; // PMT for stimulation assign RAM_we_1 = ep42trigin[0]; assign RAM_we_2 = ep42trigin[1]; assign RAM_we_3 = ep42trigin[2]; + + assign prog_trig = ep5btrigin[1]; // PMT for stimulation always @(posedge ep43trigin[0]) begin DAC_thresh_1 <= ep1fwirein[15:0]; @@ -627,6 +647,57 @@ module main #( always @(posedge ep43trigin[15]) begin DAC_thresh_pol_8 <= ep1fwirein[0]; end + + //Stimulation PMT + always @(posedge ep43trigin[16]) begin + external_digout_enable_A <= ep1fwirein[0]; + end + always @(posedge ep43trigin[17]) begin + external_digout_enable_B <= ep1fwirein[0]; + end + always @(posedge ep43trigin[18]) begin + external_digout_enable_C <= ep1fwirein[0]; + end + always @(posedge ep43trigin[19]) begin + external_digout_enable_D <= ep1fwirein[0]; + end + always @(posedge ep43trigin[20]) begin + external_digout_enable_E <= ep1fwirein[0]; + end + always @(posedge ep43trigin[21]) begin + external_digout_enable_F <= ep1fwirein[0]; + end + always @(posedge ep43trigin[22]) begin + external_digout_enable_G <= ep1fwirein[0]; + end + always @(posedge ep43trigin[23]) begin + external_digout_enable_H <= ep1fwirein[0]; + end + + always @(posedge ep43trigin[24]) begin + external_digout_channel_A <= ep1fwirein[3:0]; + end + always @(posedge ep43trigin[25]) begin + external_digout_channel_B <= ep1fwirein[3:0]; + end + always @(posedge ep43trigin[26]) begin + external_digout_channel_C <= ep1fwirein[3:0]; + end + always @(posedge ep43trigin[27]) begin + external_digout_channel_D <= ep1fwirein[3:0]; + end + always @(posedge ep43trigin[28]) begin + external_digout_channel_E <= ep1fwirein[3:0]; + end + always @(posedge ep43trigin[29]) begin + external_digout_channel_F <= ep1fwirein[3:0]; + end + always @(posedge ep43trigin[30]) begin + external_digout_channel_G <= ep1fwirein[3:0]; + end + always @(posedge ep43trigin[31]) begin + external_digout_channel_H <= ep1fwirein[3:0]; + end always @(posedge ep44trigin[0]) begin HPF_en <= ep1fwirein[0]; @@ -2555,6 +2626,29 @@ module main #( endcase end end + + //Digital output Control - PMT + wire [31:0] triggers; + assign triggers = {manual_triggers[7:0], ADC_triggers, TTL_in }; + + wire [15:0] digout_sequencer, digout_sequencer_enabled, TTL_out_DAC_thres; + + digout_sequencer #(16) digout_sequencer_1 (.reset(reset), .dataclk(dataclk), .main_state(main_state), .channel(channel), + .prog_channel(prog_channel), .prog_address(prog_address), .prog_module(prog_module), .prog_word(prog_word), .prog_trig(prog_trig), + .triggers(triggers), .digout(digout_sequencer), .digout_enabled(digout_sequencer_enabled), .shutdown(shutdown), + .reset_sequencer(reset_sequencers)); + + assign TTL_out_DAC_thres = { 8'b00000000, DAC_thresh_out }; + + assign TTL_out_direct[0] = TTL_out_mode[0] ? manual_triggers[0] : digout_sequencer[0]; + assign TTL_out_direct[1] = TTL_out_mode[1] ? manual_triggers[1] : digout_sequencer[1]; + assign TTL_out_direct[2] = TTL_out_mode[2] ? manual_triggers[2] : digout_sequencer[2]; + assign TTL_out_direct[3] = TTL_out_mode[3] ? manual_triggers[3] : digout_sequencer[3]; + assign TTL_out_direct[4] = TTL_out_mode[4] ? TTL_out_DAC_thres[4] : digout_sequencer[4]; + assign TTL_out_direct[5] = TTL_out_mode[5] ? TTL_out_DAC_thres[5] : digout_sequencer[5]; + assign TTL_out_direct[6] = TTL_out_mode[6] ? TTL_out_DAC_thres[6] : digout_sequencer[6]; + assign TTL_out_direct[7] = TTL_out_mode[7] ? TTL_out_DAC_thres[7] : digout_sequencer[7]; + assign TTL_out_direct[15:8] = digout_sequencer[15:8]; // Evaluation board 16-bit DAC outputs @@ -3324,6 +3418,7 @@ module main #( okTriggerIn ti45 (.okHE(okHE), .ep_addr(8'h45), .ep_clk(ti_clk), .ep_trigger(ep45trigin)); okTriggerIn ti46 (.okHE(okHE), .ep_addr(8'h46), .ep_clk(ti_clk), .ep_trigger(ep46trigin)); okTriggerIn ti5a (.okHE(okHE), .ep_addr(8'h5a), .ep_clk(ti_clk), .ep_trigger(ep5atrigin)); + okTriggerIn ti5b (.okHE(okHE), .ep_addr(8'h5b), .ep_clk(ti_clk), .ep_trigger(ep5btrigin)); okWireOut wo20 (.okHE(okHE), .okEH(okEHx[ 0*65 +: 65 ]), .ep_addr(8'h20), .ep_datain(ep20wireout)); okWireOut wo21 (.okHE(okHE), .okEH(okEHx[ 1*65 +: 65 ]), .ep_addr(8'h21), .ep_datain(ep21wireout)); From c6b7d70263d7cc505dc52dd7d3f883fb2d676021 Mon Sep 17 00:00:00 2001 From: Paul Date: Fri, 3 Jun 2022 17:05:44 -0400 Subject: [PATCH 2/3] changes made to compile. breaking changes with previous version of open ephys would be how max_aux_cmd_index_x_in and loop_aux_cmd_index_x variables are handled. these have been reduced to use ep0b and ep0c bits, freeing up ep0d, 0e, 0f, and 10 for stimulation --- RHD2000InterfaceXEM6010.xise | 10 +- main.v | 256 ++++++++++++++++++++--------------- xem6310.ucf | 32 ++--- 3 files changed, 168 insertions(+), 130 deletions(-) diff --git a/RHD2000InterfaceXEM6010.xise b/RHD2000InterfaceXEM6010.xise index 070ad54..84f572b 100755 --- a/RHD2000InterfaceXEM6010.xise +++ b/RHD2000InterfaceXEM6010.xise @@ -25,7 +25,7 @@ - + @@ -81,7 +81,7 @@ - + @@ -93,7 +93,7 @@ - + @@ -140,6 +140,10 @@ + + + + diff --git a/main.v b/main.v index 563ce1a..432f6dc 100755 --- a/main.v +++ b/main.v @@ -287,8 +287,9 @@ module main #( reg [15:0] RAM_data_out_1, RAM_data_out_2, RAM_data_out_3; wire RAM_we_1, RAM_we_2, RAM_we_3; + reg shutdown; // PMT reg [5:0] channel, channel_MISO; // varies from 0-34 (amplfier channels 0-31, plus 3 auxiliary commands) - reg [15:0] MOSI_cmd_A, MOSI_cmd_B, MOSI_cmd_C, MOSI_cmd_D; + reg [15:0] MOSI_cmd_A, MOSI_cmd_B, MOSI_cmd_C, MOSI_cmd_D, MOSI_cmd_E, MOSI_cmd_F, MOSI_cmd_G, MOSI_cmd_H; reg [73:0] in4x_A1, in4x_A2; reg [73:0] in4x_B1, in4x_B2; @@ -346,6 +347,7 @@ module main #( wire [15:0] data_stream_ADC_1, data_stream_ADC_2, data_stream_ADC_3, data_stream_ADC_4; wire [15:0] data_stream_ADC_5, data_stream_ADC_6, data_stream_ADC_7, data_stream_ADC_8; + reg [7:0] ADC_triggers; wire [7:0] TTL_out_mode; wire reset, SPI_start, SPI_run_continuous; @@ -356,8 +358,9 @@ module main #( wire DSP_settle; wire [15:0] MOSI_cmd_selected_A, MOSI_cmd_selected_B, MOSI_cmd_selected_C, MOSI_cmd_selected_D; + wire [15:0] MOSI_cmd_selected_E, MOSI_cmd_selected_F, MOSI_cmd_selected_G, MOSI_cmd_selected_H; - reg [15:0] aux_cmd_A, aux_cmd_B, aux_cmd_C, aux_cmd_D; + reg [15:0] aux_cmd_A, aux_cmd_B, aux_cmd_C, aux_cmd_D, aux_cmd_E, aux_cmd_F, aux_cmd_G, aux_cmd_H; reg [9:0] aux_cmd_index_1, aux_cmd_index_2, aux_cmd_index_3; wire [9:0] max_aux_cmd_index_1_in, max_aux_cmd_index_2_in, max_aux_cmd_index_3_in; reg [9:0] max_aux_cmd_index_1, max_aux_cmd_index_2, max_aux_cmd_index_3; @@ -399,11 +402,11 @@ module main #( reg external_fast_settle, external_fast_settle_prev; //PMT - Stimulation - reg external_digout_enable_A, external_digout_enable_B, external_digout_enable_C, external_digout_enable_D; - reg external_digout_enable_E, external_digout_enable_F, external_digout_enable_G, external_digout_enable_H; - reg [3:0] external_digout_channel_A, external_digout_channel_B, external_digout_channel_C, external_digout_channel_D; - reg [3:0] external_digout_channel_E, external_digout_channel_F, external_digout_channel_G, external_digout_channel_H; - reg external_digout_A, external_digout_B, external_digout_C, external_digout_D; + reg external_digout_enable_A, external_digout_enable_B, external_digout_enable_C, external_digout_enable_D; + reg external_digout_enable_E, external_digout_enable_F, external_digout_enable_G, external_digout_enable_H; + reg [3:0] external_digout_channel_A, external_digout_channel_B, external_digout_channel_C, external_digout_channel_D; + reg [3:0] external_digout_channel_E, external_digout_channel_F, external_digout_channel_G, external_digout_channel_H; + reg external_digout_A, external_digout_B, external_digout_C, external_digout_D; reg external_digout_E, external_digout_F, external_digout_G, external_digout_H; wire [7:0] led_in; @@ -444,7 +447,7 @@ module main #( wire [31:0] ep5btrigin; //Stimulation - PMT - wire stim_cm_en, prog_trig; + wire stim_cmd_en, prog_trig; wire [3:0] prog_channel, prog_address; wire [4:0] prog_module; wire [31:0] prog_word; @@ -455,11 +458,9 @@ module main #( assign reset = ep00wirein[0]; assign SPI_run_continuous = ep00wirein[1]; assign DSP_settle = ep00wirein[2]; - assign TTL_out_mode = ep00wirein[3]; assign DAC_noise_suppress = ep00wirein[12:6]; assign DAC_gain = ep00wirein[15:13]; assign pipeout_override_en = ep00wirein[16]; //Open-ephys USB 3 support - assign TTL_out_mode = ep00wirein[24:17]; // PMT - stimulation assign max_timestep_in[15:0] = ep01wirein[15:0]; assign max_timestep_in[31:16] = ep02wirein[15:0]; @@ -495,14 +496,16 @@ module main #( assign aux_cmd_bank_3_C_in = ep0awirein[11:8]; assign aux_cmd_bank_3_D_in = ep0awirein[15:12]; - assign max_aux_cmd_index_1_in = ep0bwirein[9:0]; - assign max_aux_cmd_index_2_in = ep0cwirein[9:0]; - assign max_aux_cmd_index_3_in = ep0dwirein[9:0]; + // PMT Combined these to save a few wireins + // We will now have 0d, 0e, 0f and 10 available because they are consolidated to 0b and 0c + assign max_aux_cmd_index_1_in = ep0bwirein[9:0]; + assign max_aux_cmd_index_2_in = ep0bwirein[19:10]; + assign max_aux_cmd_index_3_in = ep0bwirein[29:20]; always @(posedge dataclk) begin - loop_aux_cmd_index_1 <= ep0ewirein[9:0]; - loop_aux_cmd_index_2 <= ep0fwirein[9:0]; - loop_aux_cmd_index_3 <= ep10wirein[9:0]; + loop_aux_cmd_index_1 <= ep0cwirein[9:0]; + loop_aux_cmd_index_2 <= ep0cwirein[19:10]; + loop_aux_cmd_index_3 <= ep0cwirein[29:20]; end assign led_in = ep11wirein[7:0]; @@ -543,12 +546,19 @@ module main #( assign data_stream_15_en_in = ep14wirein[14]; assign data_stream_16_en_in = ep14wirein[15]; - always @(posedge dataclk) begin - TTL_out_user <= ep15wirein[15:0]; - end - - assign TTL_out = TTL_out_mode ? {TTL_out_user[15:8], DAC_thresh_out} : TTL_out_user; - + // Stimulation - PMT + assign stim_cmd_en = ep0dwirein[0]; // single bit + assign prog_address = ep0ewirein[3:0]; + assign prog_channel = ep0ewirein[7:4]; + assign prog_module = ep0ewirein[12:8]; + + assign prog_word = ep0fwirein; // 32 bit + + + assign TTL_out_mode = ep15wirein[7:0]; + assign manual_triggers = ep15wirein[31:16]; + + assign DAC_channel_sel_1 = ep16wirein[4:0]; assign DAC_stream_sel_1 = ep16wirein[9:5]; assign DAC_en_1 = ep16wirein[10]; @@ -585,7 +595,6 @@ module main #( DAC_manual <= ep1ewirein[15:0]; end - // USB TriggerIn inputs assign DCM_prog_trigger = ep40trigin[0]; @@ -649,94 +658,70 @@ module main #( end //Stimulation PMT - always @(posedge ep43trigin[16]) begin - external_digout_enable_A <= ep1fwirein[0]; - end - always @(posedge ep43trigin[17]) begin - external_digout_enable_B <= ep1fwirein[0]; - end - always @(posedge ep43trigin[18]) begin - external_digout_enable_C <= ep1fwirein[0]; - end - always @(posedge ep43trigin[19]) begin - external_digout_enable_D <= ep1fwirein[0]; - end - always @(posedge ep43trigin[20]) begin - external_digout_enable_E <= ep1fwirein[0]; - end - always @(posedge ep43trigin[21]) begin - external_digout_enable_F <= ep1fwirein[0]; - end - always @(posedge ep43trigin[22]) begin - external_digout_enable_G <= ep1fwirein[0]; - end - always @(posedge ep43trigin[23]) begin - external_digout_enable_H <= ep1fwirein[0]; - end - - always @(posedge ep43trigin[24]) begin - external_digout_channel_A <= ep1fwirein[3:0]; - end - always @(posedge ep43trigin[25]) begin - external_digout_channel_B <= ep1fwirein[3:0]; - end - always @(posedge ep43trigin[26]) begin - external_digout_channel_C <= ep1fwirein[3:0]; - end - always @(posedge ep43trigin[27]) begin - external_digout_channel_D <= ep1fwirein[3:0]; - end - always @(posedge ep43trigin[28]) begin - external_digout_channel_E <= ep1fwirein[3:0]; - end - always @(posedge ep43trigin[29]) begin - external_digout_channel_F <= ep1fwirein[3:0]; - end - always @(posedge ep43trigin[30]) begin - external_digout_channel_G <= ep1fwirein[3:0]; - end - always @(posedge ep43trigin[31]) begin - external_digout_channel_H <= ep1fwirein[3:0]; - end - - always @(posedge ep44trigin[0]) begin - HPF_en <= ep1fwirein[0]; - end - always @(posedge ep44trigin[1]) begin - HPF_coefficient <= ep1fwirein[15:0]; - end - - always @(posedge ep45trigin[0]) begin - external_fast_settle_enable <= ep1fwirein[0]; - end - always @(posedge ep45trigin[1]) begin - external_fast_settle_channel <= ep1fwirein[3:0]; - end - - always @(posedge ep46trigin[0]) begin + always @(posedge ep43trigin[16]) begin external_digout_enable_A <= ep1fwirein[0]; end - always @(posedge ep46trigin[1]) begin + always @(posedge ep43trigin[17]) begin external_digout_enable_B <= ep1fwirein[0]; end - always @(posedge ep46trigin[2]) begin + always @(posedge ep43trigin[18]) begin external_digout_enable_C <= ep1fwirein[0]; end - always @(posedge ep46trigin[3]) begin + always @(posedge ep43trigin[19]) begin external_digout_enable_D <= ep1fwirein[0]; end - always @(posedge ep46trigin[4]) begin + always @(posedge ep43trigin[20]) begin + external_digout_enable_E <= ep1fwirein[0]; + end + always @(posedge ep43trigin[21]) begin + external_digout_enable_F <= ep1fwirein[0]; + end + always @(posedge ep43trigin[22]) begin + external_digout_enable_G <= ep1fwirein[0]; + end + always @(posedge ep43trigin[23]) begin + external_digout_enable_H <= ep1fwirein[0]; + end + + always @(posedge ep43trigin[24]) begin external_digout_channel_A <= ep1fwirein[3:0]; end - always @(posedge ep46trigin[5]) begin + always @(posedge ep43trigin[25]) begin external_digout_channel_B <= ep1fwirein[3:0]; end - always @(posedge ep46trigin[6]) begin + always @(posedge ep43trigin[26]) begin external_digout_channel_C <= ep1fwirein[3:0]; end - always @(posedge ep46trigin[7]) begin + always @(posedge ep43trigin[27]) begin external_digout_channel_D <= ep1fwirein[3:0]; end + always @(posedge ep43trigin[28]) begin + external_digout_channel_E <= ep1fwirein[3:0]; + end + always @(posedge ep43trigin[29]) begin + external_digout_channel_F <= ep1fwirein[3:0]; + end + always @(posedge ep43trigin[30]) begin + external_digout_channel_G <= ep1fwirein[3:0]; + end + always @(posedge ep43trigin[31]) begin + external_digout_channel_H <= ep1fwirein[3:0]; + end + + always @(posedge ep44trigin[0]) begin + HPF_en <= ep1fwirein[0]; + end + always @(posedge ep44trigin[1]) begin + HPF_coefficient <= ep1fwirein[15:0]; + end + + always @(posedge ep45trigin[0]) begin + external_fast_settle_enable <= ep1fwirein[0]; + end + always @(posedge ep45trigin[1]) begin + external_fast_settle_channel <= ep1fwirein[3:0]; + end + //Open-ephys triggers always @(posedge ep5atrigin[0] or posedge reset) begin if (reset) begin @@ -1097,7 +1082,17 @@ module main #( command_selector command_selector_D ( .channel(channel), .DSP_settle(DSP_settle), .aux_cmd(aux_cmd_D), .digout_override(external_digout_D), .MOSI_cmd(MOSI_cmd_selected_D)); + command_selector command_selector_E ( + .channel(channel), .DSP_settle(DSP_settle), .aux_cmd(aux_cmd_E), .digout_override(external_digout_E), .MOSI_cmd(MOSI_cmd_selected_E)); + + command_selector command_selector_F ( + .channel(channel), .DSP_settle(DSP_settle), .aux_cmd(aux_cmd_F), .digout_override(external_digout_F), .MOSI_cmd(MOSI_cmd_selected_F)); + + command_selector command_selector_G ( + .channel(channel), .DSP_settle(DSP_settle), .aux_cmd(aux_cmd_G), .digout_override(external_digout_G), .MOSI_cmd(MOSI_cmd_selected_G)); + command_selector command_selector_H ( + .channel(channel), .DSP_settle(DSP_settle), .aux_cmd(aux_cmd_H), .digout_override(external_digout_H), .MOSI_cmd(MOSI_cmd_selected_H)); assign header_magic_number = 64'hC691199927021942; // Fixed 64-bit "magic number" that begins each data frame // to aid in synchronization. assign data_stream_filler = 16'd0; @@ -1202,7 +1197,9 @@ module main #( MOSI_C <= 1'b0; MOSI_D <= 1'b0; FIFO_data_in <= 16'b0; - FIFO_write_to <= 1'b0; + FIFO_write_to <= 1'b0; + ADC_triggers <= 1'b0; + shutdown <= 1'b0; end else begin CS_b <= 1'b0; SCLK <= 1'b0; @@ -1289,6 +1286,7 @@ module main #( DAC_pre_register_8 <= 16'h8000; SPI_running <= 1'b0; + shutdown <= 1'b0; if (SPI_start) begin main_state <= ms_cs_n; @@ -1301,6 +1299,10 @@ module main #( MOSI_cmd_B <= MOSI_cmd_selected_B; MOSI_cmd_C <= MOSI_cmd_selected_C; MOSI_cmd_D <= MOSI_cmd_selected_D; + MOSI_cmd_E <= MOSI_cmd_selected_E; + MOSI_cmd_F <= MOSI_cmd_selected_F; + MOSI_cmd_G <= MOSI_cmd_selected_G; + MOSI_cmd_H <= MOSI_cmd_selected_H; CS_b <= 1'b1; main_state <= ms_clk1_a; end @@ -1314,7 +1316,7 @@ module main #( if (channel == 0) begin // grab TTL inputs, and grab current state of TTL outputs and manual DAC outputs data_stream_TTL_in <= TTL_in; - data_stream_TTL_out <= TTL_out; + data_stream_TTL_out <= TTL_out_direct; // Route selected TTL input to external fast settle signal external_fast_settle_prev <= external_fast_settle; // save previous value so we can detecting rising/falling edges @@ -1324,7 +1326,11 @@ module main #( external_digout_A <= external_digout_enable_A ? TTL_in[external_digout_channel_A] : 0; external_digout_B <= external_digout_enable_B ? TTL_in[external_digout_channel_B] : 0; external_digout_C <= external_digout_enable_C ? TTL_in[external_digout_channel_C] : 0; - external_digout_D <= external_digout_enable_D ? TTL_in[external_digout_channel_D] : 0; + external_digout_D <= external_digout_enable_D ? TTL_in[external_digout_channel_D] : 0; + external_digout_E <= external_digout_enable_E ? TTL_in[external_digout_channel_E] : 0; + external_digout_F <= external_digout_enable_F ? TTL_in[external_digout_channel_F] : 0; + external_digout_G <= external_digout_enable_G ? TTL_in[external_digout_channel_G] : 0; + external_digout_H <= external_digout_enable_H ? TTL_in[external_digout_channel_H] : 0; end if (channel == 0) begin // update all DAC registers simultaneously @@ -1558,6 +1564,13 @@ module main #( end ms_clk3_d: begin + if (channel == 31) begin + aux_cmd_E <= RAM_data_out_1; + end else if (channel == 32) begin + aux_cmd_E <= RAM_data_out_2; + end else if (channel == 33) begin + aux_cmd_E <= RAM_data_out_3; + end if (data_stream_5_en == 1'b1) begin FIFO_data_in <= data_stream_5; FIFO_write_to <= 1'b1; @@ -1589,6 +1602,13 @@ module main #( end ms_clk4_b: begin + if (channel == 31) begin + aux_cmd_F <= RAM_data_out_1; + end else if (channel == 32) begin + aux_cmd_F <= RAM_data_out_2; + end else if (channel == 33) begin + aux_cmd_F <= RAM_data_out_3; + end if (data_stream_7_en == 1'b1) begin FIFO_data_in <= data_stream_7; FIFO_write_to <= 1'b1; @@ -1616,6 +1636,13 @@ module main #( end ms_clk4_d: begin + if (channel == 31) begin + aux_cmd_G <= RAM_data_out_1; + end else if (channel == 32) begin + aux_cmd_G <= RAM_data_out_2; + end else if (channel == 33) begin + aux_cmd_G <= RAM_data_out_3; + end if (data_stream_9_en == 1'b1) begin FIFO_data_in <= data_stream_9; FIFO_write_to <= 1'b1; @@ -1647,6 +1674,13 @@ module main #( end ms_clk5_b: begin + if (channel == 31) begin + aux_cmd_H <= RAM_data_out_1; + end else if (channel == 32) begin + aux_cmd_H <= RAM_data_out_2; + end else if (channel == 33) begin + aux_cmd_H <= RAM_data_out_3; + end if (data_stream_11_en == 1'b1) begin FIFO_data_in <= data_stream_11; FIFO_write_to <= 1'b1; @@ -2633,21 +2667,21 @@ module main #( wire [15:0] digout_sequencer, digout_sequencer_enabled, TTL_out_DAC_thres; - digout_sequencer #(16) digout_sequencer_1 (.reset(reset), .dataclk(dataclk), .main_state(main_state), .channel(channel), - .prog_channel(prog_channel), .prog_address(prog_address), .prog_module(prog_module), .prog_word(prog_word), .prog_trig(prog_trig), - .triggers(triggers), .digout(digout_sequencer), .digout_enabled(digout_sequencer_enabled), .shutdown(shutdown), + digout_sequencer #(16) digout_sequencer_1 (.reset(reset), .dataclk(dataclk), .main_state(main_state), .channel(channel), + .prog_channel(prog_channel), .prog_address(prog_address), .prog_module(prog_module), .prog_word(prog_word), .prog_trig(prog_trig), + .triggers(triggers), .digout(digout_sequencer), .digout_enabled(digout_sequencer_enabled), .shutdown(shutdown), .reset_sequencer(reset_sequencers)); - assign TTL_out_DAC_thres = { 8'b00000000, DAC_thresh_out }; - - assign TTL_out_direct[0] = TTL_out_mode[0] ? manual_triggers[0] : digout_sequencer[0]; - assign TTL_out_direct[1] = TTL_out_mode[1] ? manual_triggers[1] : digout_sequencer[1]; - assign TTL_out_direct[2] = TTL_out_mode[2] ? manual_triggers[2] : digout_sequencer[2]; - assign TTL_out_direct[3] = TTL_out_mode[3] ? manual_triggers[3] : digout_sequencer[3]; - assign TTL_out_direct[4] = TTL_out_mode[4] ? TTL_out_DAC_thres[4] : digout_sequencer[4]; - assign TTL_out_direct[5] = TTL_out_mode[5] ? TTL_out_DAC_thres[5] : digout_sequencer[5]; - assign TTL_out_direct[6] = TTL_out_mode[6] ? TTL_out_DAC_thres[6] : digout_sequencer[6]; - assign TTL_out_direct[7] = TTL_out_mode[7] ? TTL_out_DAC_thres[7] : digout_sequencer[7]; + assign TTL_out_DAC_thres = { 8'b00000000, DAC_thresh_out }; + + assign TTL_out_direct[0] = TTL_out_mode[0] ? manual_triggers[0] : digout_sequencer[0]; + assign TTL_out_direct[1] = TTL_out_mode[1] ? manual_triggers[1] : digout_sequencer[1]; + assign TTL_out_direct[2] = TTL_out_mode[2] ? manual_triggers[2] : digout_sequencer[2]; + assign TTL_out_direct[3] = TTL_out_mode[3] ? manual_triggers[3] : digout_sequencer[3]; + assign TTL_out_direct[4] = TTL_out_mode[4] ? TTL_out_DAC_thres[4] : digout_sequencer[4]; + assign TTL_out_direct[5] = TTL_out_mode[5] ? TTL_out_DAC_thres[5] : digout_sequencer[5]; + assign TTL_out_direct[6] = TTL_out_mode[6] ? TTL_out_DAC_thres[6] : digout_sequencer[6]; + assign TTL_out_direct[7] = TTL_out_mode[7] ? TTL_out_DAC_thres[7] : digout_sequencer[7]; assign TTL_out_direct[15:8] = digout_sequencer[15:8]; diff --git a/xem6310.ucf b/xem6310.ucf index 058cd18..fe83150 100644 --- a/xem6310.ucf +++ b/xem6310.ucf @@ -402,22 +402,22 @@ NET "TTL_in[15]" LOC="J22" | IOSTANDARD=LVCMOS33; # TTL outputs -NET "TTL_out[0]" LOC="U22" | IOSTANDARD=LVCMOS33; -NET "TTL_out[1]" LOC="R20" | IOSTANDARD=LVCMOS33; -NET "TTL_out[2]" LOC="R22" | IOSTANDARD=LVCMOS33; -NET "TTL_out[3]" LOC="N20" | IOSTANDARD=LVCMOS33; -NET "TTL_out[4]" LOC="N22" | IOSTANDARD=LVCMOS33; -NET "TTL_out[5]" LOC="M20" | IOSTANDARD=LVCMOS33; -NET "TTL_out[6]" LOC="L19" | IOSTANDARD=LVCMOS33; -NET "TTL_out[7]" LOC="K21" | IOSTANDARD=LVCMOS33; -NET "TTL_out[8]" LOC="K22" | IOSTANDARD=LVCMOS33; -NET "TTL_out[9]" LOC="G20" | IOSTANDARD=LVCMOS33; -NET "TTL_out[10]" LOC="G22" | IOSTANDARD=LVCMOS33; -NET "TTL_out[11]" LOC="E20" | IOSTANDARD=LVCMOS33; -NET "TTL_out[12]" LOC="E22" | IOSTANDARD=LVCMOS33; -NET "TTL_out[13]" LOC="C20" | IOSTANDARD=LVCMOS33; -NET "TTL_out[14]" LOC="C22" | IOSTANDARD=LVCMOS33; -NET "TTL_out[15]" LOC="A20" | IOSTANDARD=LVCMOS33; +NET "TTL_out_direct[0]" LOC="U22" | IOSTANDARD=LVCMOS33; +NET "TTL_out_direct[1]" LOC="R20" | IOSTANDARD=LVCMOS33; +NET "TTL_out_direct[2]" LOC="R22" | IOSTANDARD=LVCMOS33; +NET "TTL_out_direct[3]" LOC="N20" | IOSTANDARD=LVCMOS33; +NET "TTL_out_direct[4]" LOC="N22" | IOSTANDARD=LVCMOS33; +NET "TTL_out_direct[5]" LOC="M20" | IOSTANDARD=LVCMOS33; +NET "TTL_out_direct[6]" LOC="L19" | IOSTANDARD=LVCMOS33; +NET "TTL_out_direct[7]" LOC="K21" | IOSTANDARD=LVCMOS33; +NET "TTL_out_direct[8]" LOC="K22" | IOSTANDARD=LVCMOS33; +NET "TTL_out_direct[9]" LOC="G20" | IOSTANDARD=LVCMOS33; +NET "TTL_out_direct[10]" LOC="G22" | IOSTANDARD=LVCMOS33; +NET "TTL_out_direct[11]" LOC="E20" | IOSTANDARD=LVCMOS33; +NET "TTL_out_direct[12]" LOC="E22" | IOSTANDARD=LVCMOS33; +NET "TTL_out_direct[13]" LOC="C20" | IOSTANDARD=LVCMOS33; +NET "TTL_out_direct[14]" LOC="C22" | IOSTANDARD=LVCMOS33; +NET "TTL_out_direct[15]" LOC="A20" | IOSTANDARD=LVCMOS33; # DAC control From 29b8c7c51e9f5a05f2dbacfc151370a2c87dfd5c Mon Sep 17 00:00:00 2001 From: Paul Date: Fri, 3 Jun 2022 18:01:43 -0400 Subject: [PATCH 3/3] change manual trigger so it conforms to Intan.jl --- main.v | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/main.v b/main.v index 432f6dc..cf45fae 100755 --- a/main.v +++ b/main.v @@ -591,8 +591,10 @@ module main #( assign DAC_stream_sel_8 = ep1dwirein[9:5]; assign DAC_en_8 = ep1dwirein[10]; + assign manual_triggers = ep1ewirein[15:0]; + always @(posedge dataclk) begin - DAC_manual <= ep1ewirein[15:0]; + DAC_manual <= ep1ewirein[31:16]; end // USB TriggerIn inputs