From 113e7e8e381398f974b4d6a9e0ce446fe8841f5e Mon Sep 17 00:00:00 2001 From: Xavier Aubert Date: Thu, 15 Feb 2024 09:26:24 +0100 Subject: [PATCH 1/3] added missing N-ext CSRs access --- .../cv32e40pv2_illegal_ro_csr_access_test.S | 98 +++++++++++++------ 1 file changed, 67 insertions(+), 31 deletions(-) diff --git a/cv32e40p/tests/programs/custom/cv32e40pv2_illegal_ro_csr_access_test/cv32e40pv2_illegal_ro_csr_access_test.S b/cv32e40p/tests/programs/custom/cv32e40pv2_illegal_ro_csr_access_test/cv32e40pv2_illegal_ro_csr_access_test.S index aa26cc5960..b52a68f8af 100644 --- a/cv32e40p/tests/programs/custom/cv32e40pv2_illegal_ro_csr_access_test/cv32e40pv2_illegal_ro_csr_access_test.S +++ b/cv32e40p/tests/programs/custom/cv32e40pv2_illegal_ro_csr_access_test/cv32e40pv2_illegal_ro_csr_access_test.S @@ -36,7 +36,7 @@ #define MSTATUS_FS_INITIAL 0x00003800 -#define BASE_EXPECTED_ILLEGAL_INSTRUCTIONS 576 +#define BASE_EXPECTED_ILLEGAL_INSTRUCTIONS 604 #define FPU_EXPECTED_ILLEGAL_INSTRUCTIONS 21 #define NO_FPU_EXPECTED_ILLEGAL_INSTRUCTIONS 21 #define PULP_EXPECTED_ILLEGAL_INSTRUCTIONS 36 @@ -133,40 +133,76 @@ main: ######### N-extension registers # ustatus - csrrc x5, 0x001, x0 # illegal instruction : register not present - csrrc x0, 0x001, x5 # illegal instruction : register not present - csrrci x0, 0x001, 0x0a # illegal instruction : register not present - csrrs x0, 0x001, x5 # illegal instruction : register not present - csrrsi x0, 0x001, 0x0a # illegal instruction : register not present - csrrw x0, 0x001, x0 # illegal instruction : register not present - csrrwi x0, 0x001, 0x0a # illegal instruction : register not present + csrrc x5, 0x000, x0 # illegal instruction : register not present + csrrc x0, 0x000, x5 # illegal instruction : register not present + csrrci x0, 0x000, 0x0a # illegal instruction : register not present + csrrs x0, 0x000, x5 # illegal instruction : register not present + csrrsi x0, 0x000, 0x0a # illegal instruction : register not present + csrrw x0, 0x000, x0 # illegal instruction : register not present + csrrwi x0, 0x000, 0x0a # illegal instruction : register not present + + # uie + csrrc x5, 0x004, x0 # illegal instruction : register not present + csrrc x0, 0x004, x5 # illegal instruction : register not present + csrrci x0, 0x004, 0x0a # illegal instruction : register not present + csrrs x0, 0x004, x5 # illegal instruction : register not present + csrrsi x0, 0x004, 0x0a # illegal instruction : register not present + csrrw x0, 0x004, x0 # illegal instruction : register not present + csrrwi x0, 0x004, 0x0a # illegal instruction : register not present + + # utvec + csrrc x5, 0x005, x0 # illegal instruction : register not present + csrrc x0, 0x005, x5 # illegal instruction : register not present + csrrci x0, 0x005, 0x0a # illegal instruction : register not present + csrrs x0, 0x005, x5 # illegal instruction : register not present + csrrsi x0, 0x005, 0x0a # illegal instruction : register not present + csrrw x0, 0x005, x0 # illegal instruction : register not present + csrrwi x0, 0x005, 0x0a # illegal instruction : register not present + + # uscratch + csrrc x5, 0x040, x0 # illegal instruction : register not present + csrrc x0, 0x040, x5 # illegal instruction : register not present + csrrci x0, 0x040, 0x0a # illegal instruction : register not present + csrrs x0, 0x040, x5 # illegal instruction : register not present + csrrsi x0, 0x040, 0x0a # illegal instruction : register not present + csrrw x0, 0x040, x0 # illegal instruction : register not present + csrrwi x0, 0x040, 0x0a # illegal instruction : register not present # uepc - csrrc x5, 0x001, x0 # illegal instruction : register not present - csrrc x0, 0x001, x5 # illegal instruction : register not present - csrrci x0, 0x001, 0x0a # illegal instruction : register not present - csrrs x0, 0x001, x5 # illegal instruction : register not present - csrrsi x0, 0x001, 0x0a # illegal instruction : register not present - csrrw x0, 0x001, x0 # illegal instruction : register not present - csrrwi x0, 0x001, 0x0a # illegal instruction : register not present + csrrc x5, 0x041, x0 # illegal instruction : register not present + csrrc x0, 0x041, x5 # illegal instruction : register not present + csrrci x0, 0x041, 0x0a # illegal instruction : register not present + csrrs x0, 0x041, x5 # illegal instruction : register not present + csrrsi x0, 0x041, 0x0a # illegal instruction : register not present + csrrw x0, 0x041, x0 # illegal instruction : register not present + csrrwi x0, 0x041, 0x0a # illegal instruction : register not present # ucause - csrrc x5, 0x001, x0 # illegal instruction : register not present - csrrc x0, 0x001, x5 # illegal instruction : register not present - csrrci x0, 0x001, 0x0a # illegal instruction : register not present - csrrs x0, 0x001, x5 # illegal instruction : register not present - csrrsi x0, 0x001, 0x0a # illegal instruction : register not present - csrrw x0, 0x001, x0 # illegal instruction : register not present - csrrwi x0, 0x001, 0x0a # illegal instruction : register not present - - # utvec - csrrc x5, 0x001, x0 # illegal instruction : register not present - csrrc x0, 0x001, x5 # illegal instruction : register not present - csrrci x0, 0x001, 0x0a # illegal instruction : register not present - csrrs x0, 0x001, x5 # illegal instruction : register not present - csrrsi x0, 0x001, 0x0a # illegal instruction : register not present - csrrw x0, 0x001, x0 # illegal instruction : register not present - csrrwi x0, 0x001, 0x0a # illegal instruction : register not present + csrrc x5, 0x042, x0 # illegal instruction : register not present + csrrc x0, 0x042, x5 # illegal instruction : register not present + csrrci x0, 0x042, 0x0a # illegal instruction : register not present + csrrs x0, 0x042, x5 # illegal instruction : register not present + csrrsi x0, 0x042, 0x0a # illegal instruction : register not present + csrrw x0, 0x042, x0 # illegal instruction : register not present + csrrwi x0, 0x042, 0x0a # illegal instruction : register not present + + # utval + csrrc x5, 0x043, x0 # illegal instruction : register not present + csrrc x0, 0x043, x5 # illegal instruction : register not present + csrrci x0, 0x043, 0x0a # illegal instruction : register not present + csrrs x0, 0x043, x5 # illegal instruction : register not present + csrrsi x0, 0x043, 0x0a # illegal instruction : register not present + csrrw x0, 0x043, x0 # illegal instruction : register not present + csrrwi x0, 0x043, 0x0a # illegal instruction : register not present + + # uip + csrrc x5, 0x044, x0 # illegal instruction : register not present + csrrc x0, 0x044, x5 # illegal instruction : register not present + csrrci x0, 0x044, 0x0a # illegal instruction : register not present + csrrs x0, 0x044, x5 # illegal instruction : register not present + csrrsi x0, 0x044, 0x0a # illegal instruction : register not present + csrrw x0, 0x044, x0 # illegal instruction : register not present + csrrwi x0, 0x044, 0x0a # illegal instruction : register not present ######### FPU RELATED # Start FPU disabled => some CSR access are illegal From 6acc300cd82f440470e972cb57ff21849a5d9d3e Mon Sep 17 00:00:00 2001 From: Xavier Aubert Date: Thu, 15 Feb 2024 15:55:24 +0100 Subject: [PATCH 2/3] added mcounteren access to illegal as the register should not be present (MPP hardwired to 11) --- .../cv32e40pv2_illegal_ro_csr_access_test.S | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/cv32e40p/tests/programs/custom/cv32e40pv2_illegal_ro_csr_access_test/cv32e40pv2_illegal_ro_csr_access_test.S b/cv32e40p/tests/programs/custom/cv32e40pv2_illegal_ro_csr_access_test/cv32e40pv2_illegal_ro_csr_access_test.S index b52a68f8af..4e996a0f82 100644 --- a/cv32e40p/tests/programs/custom/cv32e40pv2_illegal_ro_csr_access_test/cv32e40pv2_illegal_ro_csr_access_test.S +++ b/cv32e40p/tests/programs/custom/cv32e40pv2_illegal_ro_csr_access_test/cv32e40pv2_illegal_ro_csr_access_test.S @@ -36,7 +36,7 @@ #define MSTATUS_FS_INITIAL 0x00003800 -#define BASE_EXPECTED_ILLEGAL_INSTRUCTIONS 604 +#define BASE_EXPECTED_ILLEGAL_INSTRUCTIONS 611 #define FPU_EXPECTED_ILLEGAL_INSTRUCTIONS 21 #define NO_FPU_EXPECTED_ILLEGAL_INSTRUCTIONS 21 #define PULP_EXPECTED_ILLEGAL_INSTRUCTIONS 36 @@ -204,6 +204,18 @@ main: csrrw x0, 0x044, x0 # illegal instruction : register not present csrrwi x0, 0x044, 0x0a # illegal instruction : register not present +######### N-extension registers + # mcounteren + csrrc x5, 0x306, x0 # illegal instruction : register not present + csrrc x0, 0x306, x5 # illegal instruction : register not present + csrrci x0, 0x306, 0x0a # illegal instruction : register not present + csrrs x0, 0x306, x5 # illegal instruction : register not present + csrrsi x0, 0x306, 0x0a # illegal instruction : register not present + csrrw x0, 0x306, x0 # illegal instruction : register not present + csrrwi x0, 0x306, 0x0a # illegal instruction : register not present + + + ######### FPU RELATED # Start FPU disabled => some CSR access are illegal # If Zfinx is enabled, FS is hardwired and below instructions should be legal, From 51804a3acec31c2f0bfacc40fb6abae17241d368 Mon Sep 17 00:00:00 2001 From: XavierAubert Date: Thu, 15 Feb 2024 15:59:46 +0100 Subject: [PATCH 3/3] added header to the file and small comment update --- .../cv32e40pv2_illegal_ro_csr_access_test.S | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/cv32e40p/tests/programs/custom/cv32e40pv2_illegal_ro_csr_access_test/cv32e40pv2_illegal_ro_csr_access_test.S b/cv32e40p/tests/programs/custom/cv32e40pv2_illegal_ro_csr_access_test/cv32e40pv2_illegal_ro_csr_access_test.S index 4e996a0f82..448a97e836 100644 --- a/cv32e40p/tests/programs/custom/cv32e40pv2_illegal_ro_csr_access_test/cv32e40pv2_illegal_ro_csr_access_test.S +++ b/cv32e40p/tests/programs/custom/cv32e40pv2_illegal_ro_csr_access_test/cv32e40pv2_illegal_ro_csr_access_test.S @@ -1,6 +1,7 @@ # # Copyright (C) EM Microelectronic US Inc. # Copyright (C) 2020 OpenHW Group +# Copyright (C) 2024 Dolphin Design # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -19,7 +20,7 @@ # SPDX-License-Identifier: Apache-2.0 # ############################################################################### -# READ ONLY CSRs: access read-only CSRs and check for side-effects. +# NOT-PRESENT & READ ONLY CSRs: access read-only and not-present CSRs and check for side-effects. ############################################################################### .globl _start @@ -204,7 +205,7 @@ main: csrrw x0, 0x044, x0 # illegal instruction : register not present csrrwi x0, 0x044, 0x0a # illegal instruction : register not present -######### N-extension registers +######### Other User-mode-only registers # mcounteren csrrc x5, 0x306, x0 # illegal instruction : register not present csrrc x0, 0x306, x5 # illegal instruction : register not present