From 6b1beaa871c02ccd570d8e6ad80f99bc4133aa26 Mon Sep 17 00:00:00 2001 From: Andrey Bacherov Date: Sat, 15 Jan 2022 11:34:23 +0300 Subject: [PATCH] Make FPCSR is R/W accessible for both user- and supervisor- modes. --- rtl/verilog/mor1kx_ctrl_cappuccino.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rtl/verilog/mor1kx_ctrl_cappuccino.v b/rtl/verilog/mor1kx_ctrl_cappuccino.v index f9aec219..40d11cfd 100644 --- a/rtl/verilog/mor1kx_ctrl_cappuccino.v +++ b/rtl/verilog/mor1kx_ctrl_cappuccino.v @@ -618,7 +618,7 @@ module mor1kx_ctrl_cappuccino spr_fpcsr[`OR1K_FPCSR_FPEE] <= 1'b0; end else if ((spr_we & spr_access[`OR1K_SPR_SYS_BASE] & - (spr_sr[`OR1K_SPR_SR_SM] & padv_ctrl | du_access)) && + (padv_ctrl | du_access)) && `SPR_OFFSET(spr_addr)==`SPR_OFFSET(`OR1K_SPR_FPCSR_ADDR)) begin spr_fpcsr <= spr_write_dat[`OR1K_FPCSR_WIDTH-1:0]; // update all fields `ifdef OR1K_FPCSR_MASK_FLAGS