Bring up issues on the Silicon v1.0 design

[andrewgreenberg]

Critical Fixes:

• U4 (INA226)
  • SDA and SCL are connected to the wrong pins (SCL to SDA, SDA to SCL).
  • vbus should be connected to Vin-, not Vin+.
  • Reduce R36 and R37 to either zero ohms or 10 ohms. Add a capacitor across them (see datasheet).
  • Double check the footprint. Are the pads unnecessarily long?
• U3 (LT1618)
  • Datasheet does not have any resistance between shunt and ISP/ISN. Remove resistors R34 and R35.
  • Double check the footprint. Are the pads unnecessarily long?
  • Kill TP5. I think there's no reason to have it.
• U2 and U11 (TMP101) are just... weird. Still! It's like a curse on this idea. Make the symbol match the pin out in the datasheet. Then fix the footprint to match, and make sure that the RIGHT PIN ONE is flagged. It's current wrong on the footprint. Also, while you're fixing the footprint, consider making that slot narrower to better grab the little SOT-23-6 feet.
• Q1 is in backward. Furthermore, there's no reason it needs to be a DMP3050. It's not like we use that anywhere else? So switch to a SOT-23 P channel transistor like our standard NTR4101.
• See the rest of the issues; I think they have very valid points, especially adding a separate shunt resistor for the INA226 and the LT1618. Sharing them is cute, but might be super noisy for the INA226. But there might not be room.
• Add a white serial number area at LEAST on the component surface, but a small one on the side on the cell surface would be great.

[andrewgreenberg]

Other notes:

• You can officially kill TP27, TP26, and TP28, TP29

[JackkP]

Additional Comment, need to change the PN for the smaller cells in the middle from KXOB2502X8F to KXOB2502X8TF the difference being cell thickness. New PN is the thin revision from anysolar.

[JackkP]

• ✅U4 (INA226)
  • ✅SDA and SCL connected to correct pins.
  • ✅Connected Vbus to Vin- (DS pg. 28).
  • ✅Reduced R36 and R37 to either zero ohms or 10 ohms. Added a 100n capacitor across them (DS pg.14).
  • 🛈 Did not change footprint, current footprint matches datasheet recommended landing pattern (DS pg. 38).
• ✅U3 (LT1618)
  • ✅Removed resistors R34 and R35.
  • ✅Check footprint, switched to oresat-ics:MSOP-10_ms to match recommended landing pattern
  • ✅Killed TP5
• ✅U2 and U11 are fixed
  • 🛈 Did not update oresat-ics:DBV6-SLOT footprint (to adjust width). instead, changed the pins in the schematic symbol oresat-ics:TMP101NA; unclear why this was wrong, probably a symbol library conversion error. The pins in the DBV6-SLOT are correct for a slotted inverted IC, but the pins in the schematic symbol were also flipped.
• ✅Switched Q1 to NTR4101P.
• ❓Did not add a separate shunt for the INA226... can probably make space to do that if we think it's worthwhile. Do we want to do this?
• ✅Added white serial number areas on component surface and on cell surface
• ✅Updated KXOB2502X8F to KXOB2502X8TF

These changes are resolved in 5202ddf

Things still needing review:

• 🛈 kill TP27, TP26, and TP28, TP29
• ❓Why is the refdes for the M55 connector CF1?
• ❓Is the white serial number area on the cell side satisfactory?
• ❓Did we figure out why V1.0 boards 1 and 6 have 💩 power output?
• ❓Add separate shunts for INA226 and LT1618?
• ⚠I need to thoroughly review the board before we do a design review and look for bad stuff

[andrewgreenberg]

• Yeah, I think you really can kill those TPs. What do you want to review about it?
• CF1 stands for "Connector, Female". Feel free to change to "J"
• White serial number area is too big. Make it more "square". Big enough to hand-write a two digit number.
• We don't yet know about boards 1 and 6, will have to investigate, but that shouldn't slow down the v1.1 design.
• No, let's skip the separate shunts. I like sharing them until we figure out that sucks.
• OK, do the last minute review, I think we're good to go to try v1.1!