Proof of Concept: A Unum/Posit Module for Calyx

[Mark1626]

Background:

Unum-III/Posits is a number format that is similar to IEEE 754 format. It can be used as a drop in replacement for floats. Posits are hardware friendly to implement and are accurate than floats.

I'm the maintainer of Chisel hardposit. This repo is a Chisel HDL based implementation of Posits. It's part of the work my research group did for CARRV20

Posit accelerators generated using Calyx

What I have been doing

My goal was to create accelerators with the Calyx infrastructure that would use Posits. So I made Calyx bindings for the RTL generated from Chisel. These bindings would then be emitted from a Calyx frontend like Dahlia. This could be either generated when using a custom datatype or float could be swapped to use posits.

PoC replacing floats in Dahlia with posits

To test these binding I added support for floats in Dahlia (in my fork) when targeting the Calyx back-end. This will generate my Calyx binding of the RTL Posit blocks when using floats.

eg) When the following Dahlia code targets the Calyx backend

decl a: float[8];
decl b: float[8];
decl c: float[8];

for (let i:bit<10>=0..8) {
    c[i] := a[i] + b[i];
}

fuse scratch.fuse --lower -b calyx

It would generate Calyx IR, with

import "primitives/core.futil";
import "primitives/memories/seq.futil";
import "primitives/binary_operators.futil";
import "P32.futil";
component main() -> () {
  cells {
    @external(1) a = seq_mem_d1(32,8,4);
    a_read0_0 = std_reg(32);
    add0 = PositAdd();    <---------------------------- Custom
    add1 = std_sadd(10);
    ...
    ...

Simulation and Synthesis

This worked out of the box, I managed to get it running in simulation with Verilator. I'm current exploring how I can put this on an FPGA.

Observation

1. I would be nice to support binding FIRRTL with Calyx. One issue I have is that when I export parameterised Chisel modules, I lose information about it's parameters. This might be a Chisel issue, just thought I'll share my experience of Chisel <--> Calyx

Chisel

class PositAdd(val nbits: Int, val es: Int) extends Module

when exported from Chisel->FIRRTL->SV

module PositAdd(	// <stdin>:423:3
  input         clock,	// <stdin>:424:11
                reset,	// <stdin>:425:11
  input  [31:0] io_num1,	// src/main/scala/PositAdd.scala:80:14
                io_num2,	// src/main/scala/PositAdd.scala:80:14
  input         io_sub,	// src/main/scala/PositAdd.scala:80:14
  output        io_isZero,	// src/main/scala/PositAdd.scala:80:14
                io_isNaR,	// src/main/scala/PositAdd.scala:80:14
  output [31:0] io_out	// src/main/scala/PositAdd.scala:80:14
);

In my Calyx binding I have to define a fixed 32 bit-width. Further in my case I will be having a separate binding for 16bit and 64bit posits, but the primitive names are all going to be PositAdd.

extern "P32/P32.sv" {
    comb primitive PositAdd[](
        @write_together(1) io_num1: 32,
        @write_together(1) io_num2: 32,
        @write_together(1) io_sub: 1,
        @clk clock: 1,
        @reset reset: 1
    ) -> (
        io_isZero: 1,
        io_isNaR : 1,
        io_out: 32
    );

2. Dahlia
   • There are a couple of bugs in lowering Dahlia to Calyx. I'll raise them separately in Dahlia's repo
   • The modifications I made in Dahlia to support floats are a bit specific to posits. It would be useful if there was a kind of plugin to be able to add or change the Calyx IR generated from Dahlia

Questions

1. Are there any other Calyx front-ends or HLS flows with floating point support?
2. Is there any further information/examples of running SV generated by Calyx on FPGAs

---

There are a couple of experiments that I'm running right now, which I will be making public once it's done. I'll be happy to discuss and share more information about this.

[rachitnigam]

@Mark1626 this is unbelievably exciting!!! We've discussed adding posit support to Calyx internally for a while but hadn't had the time. It is super exciting to see the prototype working. A couple of recommendations:

1. Let's move this discussion to the Calyx repo (I can do that if it makes sense)
2. If you're interested, present this prototype during a Calyx open design meeting (ODM): https://github.com/calyxir/project?tab=readme-ov-file#calyx-open-design-meetings

Apart from that, a couple of relevant ongoing efforts:

1. @jiahanxie353 has been working on adding Berkeley HardFloat library to Calyx: Calyx wrapper for Berkeley HardFloat Verilog library #1928
2. We're working with the developers of Allo (https://github.com/cornell-zhang/allo) to make it compile to Calyx. I think allo will be a really nice use case for this kind of customized numerics.
3. @bcarlet has been working on generation approximations for polynomials using Calyx. He might be interested in using the embedding as well.
4. @ayakayorihiro and @ekiwi have been working on a FIRRTL backend and might be able to answer the questions you had.

I'm curious to hear what you think the next steps are but overall, I'd be super excited to figure out how to upstream these changes and use them with various Calyx frontends.

[Mark1626]

Sure, we can move this discussion to the Calyx repo.

I will be happy to present the prototype in a design meeting.

[rachitnigam]

Awesome, I think two weeks from now might be a good day to pick if you can make the time for the meeting?

[Mark1626]

That works for me. What time does it usually happen?

[rachitnigam]

1.30pm ET! I'll add this information the project page.

[Mark1626]

I managed to run and validate 4 benchmarks from the Machsuite using Dahlia as the frontend for the bindings. I want to present this in a design meet and get some feedback. When will the next design meet be happening?

[Mark1626]

I'm having a limitation if I'm converting Chisel to SV to use in my bindings. All my module names are the same so I can either have a 32 or 64 bit (or 8/16 bit) posits. As far as I know Chisel doesn't have a way to create Verilog module parameters.

1. https://groups.google.com/g/chisel-users/c/mk7tVvY_9Cw
2. Make Chisel5 generate parameter in Verilog chipsalliance/chisel#3591

Is there anything in the FIRRTL backend that can help with this?

I'm curious if this came up for #1928 , as the hardfloat repo is also in Chisel.

[ekiwi]

I think some people at SiFive are working on integrating Verilog parameters, but I don't think its fully integrated yet. What I would recommend is that you generate Modules with different names for each parameter value you care about.
You should be able to programmatically change a module's name like this: https://www.chisel-lang.org/docs/explanations/naming#set-a-module-name

[ayakayorihiro]

I ran into a similar problem while trying to translate Calyx primitives (which have parameters since they are implemented as Verilog modules) into FIRRTL modules, since FIRRTL is similarly monomorphic (modules don't have parameters). My solution was to use metaprogramming: (1) I wrote template FIRRTL files (stored in calyx/tools/firrtl/templates) with placeholders for each parameter, and (2) wrote a script that takes in the parameter information and produces the corresponding FIRRTL primitive (using Python string replacement). For example, if I had std_add(32) and std_add(4) in Calyx, then I would produce two FIRRTL modules std_add_32 and std_add_4. I think you may be able to use a similar solution for your Chisel parameters problem! (Right now my script is rather specific to what I want it to do for the FIRRTL backend, but if it would help I can make it more general to take in any template and parameter info)

[Mark1626]

I managed to go down the route of overriding the desiredName variable of each module and it seems to be working