{"payload":{"pageCount":3,"repositories":[{"type":"Public","name":"cvw-arch-verif","owner":"openhwgroup","isFork":false,"description":"The purpose of the repo is to support CORE-V Wally architectural verification","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":1,"issueCount":5,"starsCount":2,"forksCount":19,"license":"Other","participation":[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,5,4,13,8,79,50,50],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-19T20:06:27.251Z"}},{"type":"Public","name":"cvw","owner":"openhwgroup","isFork":false,"description":"CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.","allTopics":[],"primaryLanguage":{"name":"C","color":"#555555"},"pullRequestCount":2,"issueCount":18,"starsCount":238,"forksCount":175,"license":"Other","participation":[17,22,11,35,21,45,32,113,102,42,18,35,65,5,30,44,66,40,66,60,9,48,24,74,84,31,47,29,63,59,71,48,40,61,36,48,29,27,70,61,108,30,41,217,48,55,73,43,43,47,12,20],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-19T20:06:22.488Z"}},{"type":"Public","name":"cva6","owner":"openhwgroup","isFork":false,"description":"The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux","allTopics":["asic","cpu","systemverilog-hdl","rv64gc","ariane","fpga","risc-v"],"primaryLanguage":{"name":"Assembly","color":"#6E4C13"},"pullRequestCount":8,"issueCount":186,"starsCount":2215,"forksCount":673,"license":"Other","participation":[19,8,14,21,7,11,14,16,11,9,17,15,10,1,4,7,8,7,9,8,14,15,9,16,14,15,10,13,17,15,6,13,1,12,23,22,17,23,20,8,13,22,10,24,13,5,7,6,10,8,1,2],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-19T16:31:42.871Z"}},{"type":"Public","name":"core-v-verif","owner":"openhwgroup","isFork":false,"description":"Functional verification project for the CORE-V family of RISC-V cores.","allTopics":["verification","systemverilog","uvm","risc-v"],"primaryLanguage":{"name":"Assembly","color":"#6E4C13"},"pullRequestCount":14,"issueCount":115,"starsCount":426,"forksCount":218,"license":"Other","participation":[4,1,0,1,2,3,1,2,1,0,9,3,3,0,10,6,1,11,4,11,7,6,1,2,2,6,5,7,9,7,3,12,1,8,3,5,8,2,5,11,6,17,5,11,3,3,0,3,8,4,0,2],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-19T12:52:07.867Z"}},{"type":"Public","name":"openhwgroup.org","owner":"openhwgroup","isFork":false,"description":"OpenHW Group is a not-for-profit, global organization driven by its members and individual contributors where hardware and software designers collaborate in the development of open-source cores, related IP, tools and software. OpenHW provides an infrastructure for hosting high quality open-source HW developments in line with industry best practi…","allTopics":["webdev","hugo"],"primaryLanguage":{"name":"HTML","color":"#e34c26"},"pullRequestCount":1,"issueCount":4,"starsCount":16,"forksCount":11,"license":"Eclipse Public License 2.0","participation":[0,2,1,2,2,1,2,1,1,0,0,0,1,0,0,0,0,0,0,1,0,2,0,0,0,6,1,3,0,0,0,1,1,0,1,0,0,2,0,0,0,0,0,0,1,1,2,0,0,0,2,1],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-13T14:58:59.927Z"}},{"type":"Public","name":"programs","owner":"openhwgroup","isFork":false,"description":"Documentation for the OpenHW Group's set of CORE-V RISC-V cores","allTopics":[],"primaryLanguage":{"name":"HTML","color":"#e34c26"},"pullRequestCount":7,"issueCount":9,"starsCount":187,"forksCount":96,"license":"Other","participation":[9,10,0,0,0,2,0,2,2,0,4,0,3,0,0,0,0,5,0,2,0,0,0,4,1,0,0,0,1,0,0,1,5,1,7,4,18,10,13,7,14,14,1,0,0,0,0,0,0,0,1,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-12T15:34:13.198Z"}},{"type":"Public","name":"core-v-sw","owner":"openhwgroup","isFork":false,"description":"Main Repo for the OpenHW Group Software Task Group","allTopics":[],"primaryLanguage":null,"pullRequestCount":0,"issueCount":5,"starsCount":15,"forksCount":28,"license":"Eclipse Public License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-09T13:09:48.690Z"}},{"type":"Public","name":"cv-hpdcache-verif","owner":"openhwgroup","isFork":false,"description":"Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":0,"issueCount":1,"starsCount":5,"forksCount":1,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-06T16:25:34.556Z"}},{"type":"Public","name":"cv32e20-dv","owner":"openhwgroup","isFork":false,"description":"","allTopics":[],"primaryLanguage":{"name":"Assembly","color":"#6E4C13"},"pullRequestCount":0,"issueCount":0,"starsCount":0,"forksCount":5,"license":"Apache License 2.0","participation":[1,8,0,4,0,3,0,3,4,2,0,3,2,0,0,0,0,0,0,0,3,2,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,1,0,0,0,0,1,0,0,0,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-08-21T13:33:06.239Z"}},{"type":"Public","name":"cv-hpdcache","owner":"openhwgroup","isFork":false,"description":"RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":0,"issueCount":2,"starsCount":49,"forksCount":17,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-08-20T09:57:05.827Z"}},{"type":"Public","name":"cv32e40s","owner":"openhwgroup","isFork":false,"description":"4 stage, in-order, secure RISC-V core based on the CV32E40P","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":1,"issueCount":1,"starsCount":127,"forksCount":22,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-08-16T08:00:13.044Z"}},{"type":"Public","name":"corev-qemu","owner":"openhwgroup","isFork":true,"description":"Official QEMU mirror. Please see http://wiki.qemu.org/Contribute/SubmitAPatch for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.","allTopics":[],"primaryLanguage":{"name":"C","color":"#555555"},"pullRequestCount":2,"issueCount":0,"starsCount":1,"forksCount":5490,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-08-16T06:21:46.924Z"}},{"type":"Public","name":"core-v-polara-apu","owner":"openhwgroup","isFork":true,"description":"The OpenPiton Platform","allTopics":[],"primaryLanguage":{"name":"Assembly","color":"#6E4C13"},"pullRequestCount":1,"issueCount":0,"starsCount":15,"forksCount":212,"license":null,"participation":[4,1,0,0,0,1,0,4,6,2,3,0,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-08-14T15:31:46.709Z"}},{"type":"Public","name":"tristan-isolde-unified-access-page","owner":"openhwgroup","isFork":false,"description":"Unified Access Page for the TRISTAN project","allTopics":[],"primaryLanguage":{"name":"HTML","color":"#e34c26"},"pullRequestCount":0,"issueCount":1,"starsCount":11,"forksCount":28,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-08-12T06:07:47.024Z"}},{"type":"Public","name":"cv32e40x","owner":"openhwgroup","isFork":false,"description":"4 stage, in-order, compute RISC-V core based on the CV32E40P","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":4,"issueCount":29,"starsCount":209,"forksCount":49,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-08-08T12:04:11.070Z"}},{"type":"Public","name":"cvfpu","owner":"openhwgroup","isFork":false,"description":"Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":11,"issueCount":38,"starsCount":418,"forksCount":113,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-08-02T14:05:35.698Z"}},{"type":"Public","name":"corev-binutils-gdb","owner":"openhwgroup","isFork":false,"description":"","allTopics":[],"primaryLanguage":{"name":"C","color":"#555555"},"pullRequestCount":0,"issueCount":4,"starsCount":9,"forksCount":26,"license":"GNU General Public License v2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-07-30T17:40:25.097Z"}},{"type":"Public","name":"corev-llvm-project","owner":"openhwgroup","isFork":false,"description":"","allTopics":[],"primaryLanguage":null,"pullRequestCount":2,"issueCount":4,"starsCount":12,"forksCount":18,"license":"Other","participation":[0,0,0,1,0,0,0,1,0,2,2,10,6,5,0,0,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-07-26T03:43:23.934Z"}},{"type":"Public","name":"cv32e40p","owner":"openhwgroup","isFork":false,"description":"CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform","allTopics":["riscv","riscv32imfc"],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":11,"issueCount":49,"starsCount":927,"forksCount":411,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-07-19T14:17:37.022Z"}},{"type":"Public","name":"core-v-mcu-uvm","owner":"openhwgroup","isFork":false,"description":"CORE-V MCU UVM Environment and Test Bench","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":0,"issueCount":16,"starsCount":16,"forksCount":7,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-07-19T12:53:53.936Z"}},{"type":"Public","name":"corev-gcc","owner":"openhwgroup","isFork":false,"description":"","allTopics":[],"primaryLanguage":{"name":"C++","color":"#f34b7d"},"pullRequestCount":1,"issueCount":6,"starsCount":22,"forksCount":23,"license":"GNU General Public License v2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-07-19T08:26:15.611Z"}},{"type":"Public","name":"cva6-sdk","owner":"openhwgroup","isFork":false,"description":"CVA6 SDK containing RISC-V tools and Buildroot","allTopics":[],"primaryLanguage":{"name":"Makefile","color":"#427819"},"pullRequestCount":3,"issueCount":29,"starsCount":59,"forksCount":64,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-22T12:40:11.816Z"}},{"type":"Public","name":"cve2","owner":"openhwgroup","isFork":true,"description":"The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":10,"issueCount":169,"starsCount":28,"forksCount":523,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-19T12:02:12.404Z"}},{"type":"Public","name":"core-v-xif","owner":"openhwgroup","isFork":false,"description":"RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":0,"issueCount":17,"starsCount":60,"forksCount":24,"license":"Other","participation":[0,0,1,1,4,4,0,16,4,4,2,1,0,0,0,4,22,6,22,8,3,5,14,1,3,12,0,0,0,3,0,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-05-22T09:42:14.058Z"}},{"type":"Public","name":"core-v-mcu-cli-test","owner":"openhwgroup","isFork":false,"description":"Eclipse/FreeRTOS/core-v-mcu example program","allTopics":[],"primaryLanguage":{"name":"C","color":"#555555"},"pullRequestCount":1,"issueCount":6,"starsCount":9,"forksCount":9,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-04-22T02:45:45.257Z"}},{"type":"Public","name":"cva5","owner":"openhwgroup","isFork":false,"description":"The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":1,"issueCount":10,"starsCount":58,"forksCount":15,"license":"Apache License 2.0","participation":[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-04-03T02:37:02.525Z"}},{"type":"Public","name":"cv32e40x-dv","owner":"openhwgroup","isFork":false,"description":"CV32E40X Design-Verification environment","allTopics":[],"primaryLanguage":{"name":"Assembly","color":"#6E4C13"},"pullRequestCount":1,"issueCount":4,"starsCount":11,"forksCount":9,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-03-25T13:32:12.266Z"}},{"type":"Public","name":"core-v-cores","owner":"openhwgroup","isFork":false,"description":"CORE-V Family of RISC-V Cores","allTopics":[],"primaryLanguage":null,"pullRequestCount":0,"issueCount":1,"starsCount":199,"forksCount":16,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-02-15T17:42:53.104Z"}},{"type":"Public","name":"cv-mesh","owner":"openhwgroup","isFork":false,"description":"","allTopics":[],"primaryLanguage":null,"pullRequestCount":0,"issueCount":0,"starsCount":3,"forksCount":0,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-02-13T00:16:03.781Z"}},{"type":"Public","name":".github","owner":"openhwgroup","isFork":false,"description":"","allTopics":[],"primaryLanguage":null,"pullRequestCount":0,"issueCount":0,"starsCount":0,"forksCount":1,"license":null,"participation":[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,3,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-02-09T03:07:55.900Z"}}],"repositoryCount":61,"userInfo":null,"searchable":true,"definitions":[],"typeFilters":[{"id":"all","text":"All"},{"id":"public","text":"Public"},{"id":"source","text":"Sources"},{"id":"fork","text":"Forks"},{"id":"archived","text":"Archived"},{"id":"template","text":"Templates"}],"compactMode":false},"title":"openhwgroup repositories"}