Adding sim to test

Author: alaindargelas

EDA-1772/raptor_tcl.tcl

@@ -3,15 +3,21 @@ target_device GEMINI_COMPACT_104x68
 add_include_path ./rtl
 add_library_path ./rtl
 add_library_ext .v .sv
-add_design_file ./rtl/uart_defines.vh
-add_design_file ./rtl/vex_soc.v
+add_design_file ./rtl/uart_defines.vh ./rtl/vex_soc.v
 set_top_module vex_soc
 analyze
 synthesize delay
+
+setup_lec_sim
+
+simulate icarus gate
+
 packing
-global_placement
 place
 route
+
+simulate icarus pnr
+
 sta
 power
 bitstream