keywords.json

{   
    "strategy": "Strategy:",
    "total_runtime": "Duration: ",
    "synthesis_runtime": "",
    "packing_runtime": "",
    "placement_runtime": "",
    "routing_runtime": "",
    "time_analysis_runtime": "",
    "bitstream_runtime": "",
    "reg_id": "RegID:",
    "device": "Target device:",
    "target device": "Target device:",
    "version": "Version  :",
    "git_hash": "Hash     :",
    "built": "Build    :",
    "built_type": "Type     :",
    "status": "ERROR: ,bitstream is generated,is routed,is packed,is placed,is synthesized,is timing analysed!,power didn't change",
    "error_msg": "ERROR: ",
    "post_synth_sim_status": "",
    "post_route_sim_status": "",
    "bitstream_sim_status": "",
    "failure_type": "",
    "fmax_clock1": "Fmax:",
    "fmax_clock2": "Fmax:",
    "fmax_clock3": "Fmax:",
    "fmax_clock4": "Fmax:",
    "fmax_clock5": "Fmax:",
    "fmax_clock6": "Fmax:",
    "wns_clock1": "(sWNS):",
    "wns_clock2": "(sWNS):",
    "wns_clock3": "(sWNS):",
    "wns_clock4": "(sWNS):",
    "wns_clock5": "(sWNS):",
    "wns_clock6": "(sWNS):",
    "tns": "(sTNS):",
    "fmax_geomean": "geomean",
    "registers": " dff          , dffn          , sdff          , sdffn          , dffr          , dffnr          , dffe          , dffne          , sdffre          , sdffnre          , DFFRE          , dffnre          , dffsre          , dffnsre          ",
    "total_luts": " LUT1 , LUT2 , LUT3 , LUT4 , LUT5 , LUT6 ",
    "brams": " RS_TDP36K , TDP36K , TDP_RAM36K , TDP_RAM18KX2 ",
    "dsp": " DSP38 , DSP19x2 , DSP19X2 , RS_DSP_MULT , RS_DSP_MULT_REGIN , RS_DSP_MULT_REGOUT , RS_DSP_MULT_REGIN_REGOUT , RS_DSP_MULTADD , RS_DSP_MULTADD_REGIN , RS_DSP_MULTADD_REGOUT , RS_DSP_MULTADD_REGIN_REGOUT , RS_DSP_MULTACC , RS_DSP_MULTACC_REGIN , RS_DSP_MULTACC_REGOUT , RS_DSP_MULTACC_REGIN_REGOUT ",
    "Adder_Carry": " CARRY           ",
    "CLB": "",
    "LUT_CLB_ratio": "LUT/CLB",
    "CLB_percentage_used":"percent_clbs_used",
    "FLE_Percentage_used": " fle          ",
    "Wirelength_Percentage_used": "X - Directed channels:",
    "logic_level_clock1": "llvl",
    "logic_level_clock2": "llvl",
    "logic_level_clock3": "llvl",
    "logic_level_clock4": "llvl",
    "logic_level_clock5": "llvl",
    "logic_level_clock6": "llvl",
    "total_power": "t_power",
    "dynamic_power": "d_power",
    "static_power": "s_power",
    "target_freq_clock1": "t_freq",
    "target_freq_clock2": "t_freq",
    "target_freq_clock3": "t_freq",
    "target_freq_clock4": "t_freq",
    "target_freq_clock5": "t_freq",
    "target_freq_clock6": "t_freq"
}