From 8aa74af173ef8f51e3d00e0ff31a6e13ae8d9806 Mon Sep 17 00:00:00 2001 From: zhergarvi Date: Wed, 30 Oct 2024 15:31:15 +0500 Subject: [PATCH 1/2] EDA-3187 added setup_lec_sim for des_ao and DFF_AND2_top --- RTL_testcases/Opensta_testcases/DFF_AND2_top/raptor_run.sh | 3 +++ .../RTL_Benchmarks_Gap_Analysis/des_ao/raptor_run.sh | 5 ++++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/RTL_testcases/Opensta_testcases/DFF_AND2_top/raptor_run.sh b/RTL_testcases/Opensta_testcases/DFF_AND2_top/raptor_run.sh index f414ca1e7..21e5d334f 100755 --- a/RTL_testcases/Opensta_testcases/DFF_AND2_top/raptor_run.sh +++ b/RTL_testcases/Opensta_testcases/DFF_AND2_top/raptor_run.sh @@ -206,6 +206,8 @@ parse_cga exit 1; } [ -z "$custom_synth_script" ] && echo "" || echo "custom_synth_script $custom_synth_script">>raptor_tcl.tcl [ -z "$synth_options" ] && echo "" || echo "synth_options $synth_options">>raptor_tcl.tcl [ -z "$strategy" ] && echo "" || echo "synthesize $strategy">>raptor_tcl.tcl + echo "setup_lec_sim">>raptor_tcl.tcl + [ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl if [ "$post_synth_sim" == true ]; then echo "# Open the input file in read mode">>raptor_tcl.tcl echo "set input_file [open \"$design/run_1/synth_1_1/synthesis/$design\_post_synth.v\" r]">>raptor_tcl.tcl @@ -259,6 +261,7 @@ parse_cga exit 1; } else echo "" fi + [ "$tool_name" = "iverilog" ] && echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl echo "sta">>raptor_tcl.tcl echo "power">>raptor_tcl.tcl echo "bitstream $bitstream">>raptor_tcl.tcl diff --git a/RTL_testcases/RTL_Benchmarks_Gap_Analysis/des_ao/raptor_run.sh b/RTL_testcases/RTL_Benchmarks_Gap_Analysis/des_ao/raptor_run.sh index 5dc5b9c5c..d4b336786 100755 --- a/RTL_testcases/RTL_Benchmarks_Gap_Analysis/des_ao/raptor_run.sh +++ b/RTL_testcases/RTL_Benchmarks_Gap_Analysis/des_ao/raptor_run.sh @@ -17,7 +17,7 @@ bitstream_sim=false #raptor options device="GEMINI_COMPACT_104x68" -strategy="delay" #(area, delay, mixed, none) +strategy="area" #(area, delay, mixed, none) add_constraint_file="./raptor_sdc.sdc" #Sets SDC + location constraints Constraints: set_pin_loc, set_mode, all SDC Standard commands @@ -259,6 +259,9 @@ parse_cga exit 1; } else echo "" fi + echo "setup_lec_sim">>raptor_tcl.tcl + [ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl + [ "$tool_name" = "iverilog" ] && echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl echo "sta">>raptor_tcl.tcl echo "power">>raptor_tcl.tcl echo "bitstream $bitstream">>raptor_tcl.tcl From 0b678abaf45b287ab7f24aff1e506acbb9c06f37 Mon Sep 17 00:00:00 2001 From: zhergarvi Date: Wed, 30 Oct 2024 15:33:11 +0500 Subject: [PATCH 2/2] did some reordering --- RTL_testcases/Opensta_testcases/DFF_AND2_top/raptor_run.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/RTL_testcases/Opensta_testcases/DFF_AND2_top/raptor_run.sh b/RTL_testcases/Opensta_testcases/DFF_AND2_top/raptor_run.sh index 21e5d334f..b66b5ba55 100755 --- a/RTL_testcases/Opensta_testcases/DFF_AND2_top/raptor_run.sh +++ b/RTL_testcases/Opensta_testcases/DFF_AND2_top/raptor_run.sh @@ -206,8 +206,6 @@ parse_cga exit 1; } [ -z "$custom_synth_script" ] && echo "" || echo "custom_synth_script $custom_synth_script">>raptor_tcl.tcl [ -z "$synth_options" ] && echo "" || echo "synth_options $synth_options">>raptor_tcl.tcl [ -z "$strategy" ] && echo "" || echo "synthesize $strategy">>raptor_tcl.tcl - echo "setup_lec_sim">>raptor_tcl.tcl - [ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl if [ "$post_synth_sim" == true ]; then echo "# Open the input file in read mode">>raptor_tcl.tcl echo "set input_file [open \"$design/run_1/synth_1_1/synthesis/$design\_post_synth.v\" r]">>raptor_tcl.tcl @@ -261,6 +259,8 @@ parse_cga exit 1; } else echo "" fi + echo "setup_lec_sim">>raptor_tcl.tcl + [ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl [ "$tool_name" = "iverilog" ] && echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl echo "sta">>raptor_tcl.tcl echo "power">>raptor_tcl.tcl