added setup_lec_sim for 3 designs

Author: zhergarvi

RTL_testcases/RTL_Benchmarks_Gap_Analysis/ecg/raptor_run.sh

@@ -7,7 +7,7 @@ start=`date +%s`
 design="ecg"
 ip_name="" #design_level
 #select tool (verilator, vcs, ghdl, iverilog)
-tool_name="iverilog" 
+tool_name="verilator" 
 
 #simulation stages
 post_synth_sim=false 
@@ -262,6 +262,9 @@ parse_cga exit 1; }
         else
             echo ""
         fi
+    echo "setup_lec_sim 5 2">>raptor_tcl.tcl  
+    [ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl 
+    [ "$tool_name" = "iverilog" ] && echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl 
     echo "sta">>raptor_tcl.tcl  
     echo "power">>raptor_tcl.tcl  
     echo "bitstream $bitstream">>raptor_tcl.tcl  

RTL_testcases/RTL_Benchmarks_Gap_Analysis/ecg/rtl/f3m.v

@@ -160,8 +160,10 @@ module f3m_mult3(clk, reset,
                  done);
     input clk, reset;
     input [`WIDTH:0] a0, b0, a1, b1, a2, b2;
-    output reg [`WIDTH:0] c0, c1, c2;
-    output reg done;
+    output reg [`WIDTH:0] c0 = 0;
+    output reg [`WIDTH:0] c1 = 0;
+    output reg [`WIDTH:0] c2 = 0;
+    output reg done = 0;
     reg [3:0] K;
     reg mult_reset, delay1, delay2;
     wire e1, e2, e3, mult_done, delay3, rst;

RTL_testcases/RTL_Benchmarks_Gap_Analysis/fast_antilog/raptor_run.sh

@@ -258,6 +258,9 @@ parse_cga exit 1; }
         else
             echo ""
         fi
+    echo "setup_lec_sim">>raptor_tcl.tcl 
+    [ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl 
+    [ "$tool_name" = "iverilog" ] && echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl 
     echo "sta">>raptor_tcl.tcl  
     echo "power">>raptor_tcl.tcl  
     echo "bitstream $bitstream">>raptor_tcl.tcl  

RTL_testcases/RTL_Benchmarks_Gap_Analysis/fast_fourier_transform/raptor_run.sh

@@ -7,7 +7,7 @@ start=`date +%s`
 design="fast_fourier_transform"
 ip_name="" #design_level
 #select tool (verilator, vcs, ghdl, iverilog)
-tool_name="iverilog" 
+tool_name="verilator" 
 
 #simulation stages
 post_synth_sim=false 
@@ -258,6 +258,9 @@ parse_cga exit 1; }
         else
             echo ""
         fi
+    echo "setup_lec_sim">>raptor_tcl.tcl 
+    [ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl 
+    [ "$tool_name" = "iverilog" ] && echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl 
     echo "sta">>raptor_tcl.tcl  
     echo "power">>raptor_tcl.tcl  
     echo "bitstream $bitstream">>raptor_tcl.tcl  

RTL_testcases/opensource_with_testbench/Encryption/raptor_run.sh

@@ -264,6 +264,10 @@ parse_cga exit 1; }
         else
             echo ""
         fi
+    echo "clear_simulation_files">>raptor_tcl.tcl 
+    echo "setup_lec_sim">>raptor_tcl.tcl 
+    [ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl 
+    [ "$tool_name" = "iverilog" ] && echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl 
     echo "sta">>raptor_tcl.tcl  
     echo "power">>raptor_tcl.tcl  
     echo "bitstream $bitstream">>raptor_tcl.tcl