diff --git a/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/raptor_run.sh b/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/raptor_run.sh
index 7fd18c6f7..dd620888d 100755
--- a/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/raptor_run.sh
+++ b/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/raptor_run.sh
@@ -246,9 +246,9 @@ parse_cga exit 1; }
             echo ""
         fi
     echo "clear_simulation_files">>raptor_tcl.tcl
-    echo "setup_lec_sim">>raptor_tcl.tcl
-    echo "simulate gate icarus">>raptor_tcl.tcl
-    echo "simulate pnr icarus">>raptor_tcl.tcl
+    echo "setup_lec_sim 10 2">>raptor_tcl.tcl 
+    [ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl 
+    [ "$tool_name" = "iverilog" ] && echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl 
     echo "sta">>raptor_tcl.tcl  
     echo "power">>raptor_tcl.tcl  
     echo "bitstream $bitstream">>raptor_tcl.tcl  
diff --git a/RTL_testcases/RTL_Benchmarks_Gap_Analysis/cf_fp_mul/raptor_run.sh b/RTL_testcases/RTL_Benchmarks_Gap_Analysis/cf_fp_mul/raptor_run.sh
index 37aced8d6..a8609705b 100755
--- a/RTL_testcases/RTL_Benchmarks_Gap_Analysis/cf_fp_mul/raptor_run.sh
+++ b/RTL_testcases/RTL_Benchmarks_Gap_Analysis/cf_fp_mul/raptor_run.sh
@@ -258,6 +258,9 @@ parse_cga exit 1; }
         else
             echo ""
         fi
+    echo "setup_lec_sim 10 2">>raptor_tcl.tcl  
+    [ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl 
+    [ "$tool_name" = "iverilog" ] && echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl 
     echo "sta">>raptor_tcl.tcl  
     echo "power">>raptor_tcl.tcl  
     echo "bitstream $bitstream">>raptor_tcl.tcl  
diff --git a/RTL_testcases/RTL_Benchmarks_Gap_Analysis/cic_core/raptor_run.sh b/RTL_testcases/RTL_Benchmarks_Gap_Analysis/cic_core/raptor_run.sh
index 2fb6eaf8d..99fcbd575 100755
--- a/RTL_testcases/RTL_Benchmarks_Gap_Analysis/cic_core/raptor_run.sh
+++ b/RTL_testcases/RTL_Benchmarks_Gap_Analysis/cic_core/raptor_run.sh
@@ -209,7 +209,7 @@ parse_cga exit 1; }
     [ -z "$synthesis_type" ] && echo "" || echo "synthesis_type $synthesis_type">>raptor_tcl.tcl
     [ -z "$custom_synth_script" ] && echo "" || echo "custom_synth_script $custom_synth_script">>raptor_tcl.tcl
     [ -z "$synth_options" ] && echo "" || echo "synth_options $synth_options">>raptor_tcl.tcl
-    [ -z "$strategy" ] && echo "" || echo "synthesize $strategy">>raptor_tcl.tcl  
+    [ -z "$strategy" ] && echo "" || echo "synthesize $strategy">>raptor_tcl.tcl   
     if [ "$post_synth_sim" == true ]; then 
         echo "# Open the input file in read mode">>raptor_tcl.tcl 
         echo "set input_file [open \"$design/run_1/synth_1_1/synthesis/$design\_post_synth.v\" r]">>raptor_tcl.tcl 
@@ -263,6 +263,9 @@ parse_cga exit 1; }
         else
             echo ""
         fi
+    echo "setup_lec_sim 10 2">>raptor_tcl.tcl 
+    [ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl 
+    [ "$tool_name" = "iverilog" ] && echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl 
     echo "sta">>raptor_tcl.tcl  
     echo "power">>raptor_tcl.tcl  
     echo "bitstream $bitstream">>raptor_tcl.tcl