From 5431d868de71a431dc4fc5fb183db76d7b543739 Mon Sep 17 00:00:00 2001 From: zhergarvi Date: Tue, 29 Oct 2024 15:43:34 +0500 Subject: [PATCH 1/3] added setup_lec_sim for clk_buf_primitive_inst --- .../clk_buf_primitive_inst/raptor_run.sh | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/raptor_run.sh b/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/raptor_run.sh index 7fd18c6f7..dd620888d 100755 --- a/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/raptor_run.sh +++ b/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/raptor_run.sh @@ -246,9 +246,9 @@ parse_cga exit 1; } echo "" fi echo "clear_simulation_files">>raptor_tcl.tcl - echo "setup_lec_sim">>raptor_tcl.tcl - echo "simulate gate icarus">>raptor_tcl.tcl - echo "simulate pnr icarus">>raptor_tcl.tcl + echo "setup_lec_sim 10 2">>raptor_tcl.tcl + [ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl + [ "$tool_name" = "iverilog" ] && echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl echo "sta">>raptor_tcl.tcl echo "power">>raptor_tcl.tcl echo "bitstream $bitstream">>raptor_tcl.tcl From 84e8b01cb58585973b2f708e9256aa99d2ce7a43 Mon Sep 17 00:00:00 2001 From: zhergarvi Date: Tue, 29 Oct 2024 15:43:51 +0500 Subject: [PATCH 2/3] added setup_lec_sim for cf_fp_mul --- .../RTL_Benchmarks_Gap_Analysis/cf_fp_mul/raptor_run.sh | 3 +++ 1 file changed, 3 insertions(+) diff --git a/RTL_testcases/RTL_Benchmarks_Gap_Analysis/cf_fp_mul/raptor_run.sh b/RTL_testcases/RTL_Benchmarks_Gap_Analysis/cf_fp_mul/raptor_run.sh index 37aced8d6..a8609705b 100755 --- a/RTL_testcases/RTL_Benchmarks_Gap_Analysis/cf_fp_mul/raptor_run.sh +++ b/RTL_testcases/RTL_Benchmarks_Gap_Analysis/cf_fp_mul/raptor_run.sh @@ -258,6 +258,9 @@ parse_cga exit 1; } else echo "" fi + echo "setup_lec_sim 10 2">>raptor_tcl.tcl + [ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl + [ "$tool_name" = "iverilog" ] && echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl echo "sta">>raptor_tcl.tcl echo "power">>raptor_tcl.tcl echo "bitstream $bitstream">>raptor_tcl.tcl From d74383b58027b771bef82d29ee4a8799ea6f42d2 Mon Sep 17 00:00:00 2001 From: zhergarvi Date: Tue, 29 Oct 2024 15:44:07 +0500 Subject: [PATCH 3/3] added setup_lec_sim for cic_core --- .../RTL_Benchmarks_Gap_Analysis/cic_core/raptor_run.sh | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/RTL_testcases/RTL_Benchmarks_Gap_Analysis/cic_core/raptor_run.sh b/RTL_testcases/RTL_Benchmarks_Gap_Analysis/cic_core/raptor_run.sh index 2fb6eaf8d..99fcbd575 100755 --- a/RTL_testcases/RTL_Benchmarks_Gap_Analysis/cic_core/raptor_run.sh +++ b/RTL_testcases/RTL_Benchmarks_Gap_Analysis/cic_core/raptor_run.sh @@ -209,7 +209,7 @@ parse_cga exit 1; } [ -z "$synthesis_type" ] && echo "" || echo "synthesis_type $synthesis_type">>raptor_tcl.tcl [ -z "$custom_synth_script" ] && echo "" || echo "custom_synth_script $custom_synth_script">>raptor_tcl.tcl [ -z "$synth_options" ] && echo "" || echo "synth_options $synth_options">>raptor_tcl.tcl - [ -z "$strategy" ] && echo "" || echo "synthesize $strategy">>raptor_tcl.tcl + [ -z "$strategy" ] && echo "" || echo "synthesize $strategy">>raptor_tcl.tcl if [ "$post_synth_sim" == true ]; then echo "# Open the input file in read mode">>raptor_tcl.tcl echo "set input_file [open \"$design/run_1/synth_1_1/synthesis/$design\_post_synth.v\" r]">>raptor_tcl.tcl @@ -263,6 +263,9 @@ parse_cga exit 1; } else echo "" fi + echo "setup_lec_sim 10 2">>raptor_tcl.tcl + [ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl + [ "$tool_name" = "iverilog" ] && echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl echo "sta">>raptor_tcl.tcl echo "power">>raptor_tcl.tcl echo "bitstream $bitstream">>raptor_tcl.tcl