From a29e1e3d6ace5498797adbeae4d5588b8ce3a606 Mon Sep 17 00:00:00 2001 From: zhergarvi Date: Wed, 6 Nov 2024 13:51:37 +0500 Subject: [PATCH] added setup_lec_sim for 3 designs --- .../DSP19x2_primitive_inst/raptor_run.sh | 4 ++++ .../RS_FPGA_PRIMITIVES_new/DSP38_primitive_inst/raptor_run.sh | 4 ++++ .../dsp_xml_test/raptor_run.sh | 4 +++- 3 files changed, 11 insertions(+), 1 deletion(-) diff --git a/RTL_testcases/RS_FPGA_PRIMITIVES_new/DSP19x2_primitive_inst/raptor_run.sh b/RTL_testcases/RS_FPGA_PRIMITIVES_new/DSP19x2_primitive_inst/raptor_run.sh index b774565e6..52ba4b8f9 100755 --- a/RTL_testcases/RS_FPGA_PRIMITIVES_new/DSP19x2_primitive_inst/raptor_run.sh +++ b/RTL_testcases/RS_FPGA_PRIMITIVES_new/DSP19x2_primitive_inst/raptor_run.sh @@ -258,6 +258,10 @@ parse_cga exit 1; } else echo "" fi + echo "clear_simulation_files">>raptor_tcl.tcl + echo "setup_lec_sim">>raptor_tcl.tcl + [ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl + [ "$tool_name" = "iverilog" ] && echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl echo "sta">>raptor_tcl.tcl echo "power">>raptor_tcl.tcl echo "bitstream $bitstream">>raptor_tcl.tcl diff --git a/RTL_testcases/RS_FPGA_PRIMITIVES_new/DSP38_primitive_inst/raptor_run.sh b/RTL_testcases/RS_FPGA_PRIMITIVES_new/DSP38_primitive_inst/raptor_run.sh index 5c46ee54d..e95e622e7 100755 --- a/RTL_testcases/RS_FPGA_PRIMITIVES_new/DSP38_primitive_inst/raptor_run.sh +++ b/RTL_testcases/RS_FPGA_PRIMITIVES_new/DSP38_primitive_inst/raptor_run.sh @@ -258,6 +258,10 @@ parse_cga exit 1; } else echo "" fi + echo "clear_simulation_files">>raptor_tcl.tcl + echo "setup_lec_sim">>raptor_tcl.tcl + [ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl + [ "$tool_name" = "iverilog" ] && echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl echo "sta">>raptor_tcl.tcl echo "power">>raptor_tcl.tcl echo "bitstream $bitstream">>raptor_tcl.tcl diff --git a/RTL_testcases/test_vpr_xml_for_enhanced_DSP_features/dsp_xml_test/raptor_run.sh b/RTL_testcases/test_vpr_xml_for_enhanced_DSP_features/dsp_xml_test/raptor_run.sh index 571b5b0a3..3f13a2e0c 100755 --- a/RTL_testcases/test_vpr_xml_for_enhanced_DSP_features/dsp_xml_test/raptor_run.sh +++ b/RTL_testcases/test_vpr_xml_for_enhanced_DSP_features/dsp_xml_test/raptor_run.sh @@ -7,7 +7,7 @@ start=`date +%s` design="dsp_xml_test" ip_name="" #design_level #select tool (verilator, vcs, ghdl, iverilog) -tool_name="iverilog" +tool_name="verilator" #simulation stages post_synth_sim=false @@ -205,6 +205,8 @@ parse_cga exit 1; } [ -z "$custom_synth_script" ] && echo "" || echo "custom_synth_script $custom_synth_script">>raptor_tcl.tcl [ -z "$synth_options" ] && echo "" || echo "synth_options $synth_options">>raptor_tcl.tcl [ -z "$strategy" ] && echo "" || echo "synthesize $strategy">>raptor_tcl.tcl + echo "setup_lec_sim">>raptor_tcl.tcl + [ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl if [ "$post_synth_sim" == true ]; then echo "# Open the input file in read mode">>raptor_tcl.tcl echo "set input_file [open \"$design/run_1/synth_1_1/synthesis/$design\_post_synth.v\" r]">>raptor_tcl.tcl