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kyogenrv_fpga.qsys
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kyogenrv_fpga.qsys
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<?xml version="1.0" encoding="UTF-8"?>
<system name="$${FILENAME}">
<component
name="$${FILENAME}"
displayName="$${FILENAME}"
version="1.0"
description=""
tags=""
categories="System" />
<parameter name="bonusData"><![CDATA[bonusData
{
element KyogenRV_0
{
datum _sortIndex
{
value = "1";
type = "int";
}
}
element clk_0
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
element i2c_0
{
datum _sortIndex
{
value = "6";
type = "int";
}
}
element i2c_0.csr
{
datum baseAddress
{
value = "65536";
type = "String";
}
}
element kyogenrv_fpga
{
datum _originalDeviceFamily
{
value = "Cyclone 10 LP";
type = "String";
}
}
element kyogenrv_fpga
{
datum _originalDeviceFamily
{
value = "Cyclone 10 LP";
type = "String";
}
}
element kyogenrv_fpga
{
datum _originalDeviceFamily
{
value = "Cyclone 10 LP";
type = "String";
}
}
element kyogenrv_fpga
{
datum _originalDeviceFamily
{
value = "Cyclone 10 LP";
type = "String";
}
}
element kyogenrv_fpga
{
datum _originalDeviceFamily
{
value = "Cyclone 10 LP";
type = "String";
}
}
element msgdma_0
{
datum _sortIndex
{
value = "7";
type = "int";
}
}
element msgdma_0.csr
{
datum baseAddress
{
value = "65632";
type = "String";
}
}
element msgdma_0.descriptor_slave
{
datum baseAddress
{
value = "65680";
type = "String";
}
}
element onchip_memory2_0
{
datum _sortIndex
{
value = "2";
type = "int";
}
}
element onchip_memory2_0.s1
{
datum _lockedAddress
{
value = "1";
type = "boolean";
}
datum baseAddress
{
value = "0";
type = "String";
}
}
element pio_0
{
datum _sortIndex
{
value = "3";
type = "int";
}
}
element pio_0.s1
{
datum _lockedAddress
{
value = "0";
type = "boolean";
}
datum baseAddress
{
value = "65664";
type = "String";
}
}
element sdram_0
{
datum _sortIndex
{
value = "5";
type = "int";
}
}
element sdram_0.s1
{
datum _lockedAddress
{
value = "0";
type = "boolean";
}
datum baseAddress
{
value = "8388608";
type = "String";
}
}
element uart_0
{
datum _sortIndex
{
value = "4";
type = "int";
}
}
element uart_0.s1
{
datum _lockedAddress
{
value = "0";
type = "boolean";
}
datum baseAddress
{
value = "65600";
type = "String";
}
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="10CL025YU256C8G" />
<parameter name="deviceFamily" value="Cyclone 10 LP" />
<parameter name="deviceSpeedGrade" value="8" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="false" />
<parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName">kyogenrv_fpga_top.qpf</parameter>
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="0" />
<parameter name="testBenchDutName" value="" />
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface name="clk" internal="clk_0.clk_in" type="clock" dir="end" />
<interface
name="i2c_0_i2c_serial"
internal="i2c_0.i2c_serial"
type="conduit"
dir="end" />
<interface
name="i2c_0_interrupt_sender"
internal="i2c_0.interrupt_sender"
type="interrupt"
dir="end" />
<interface
name="kyogenrv_0_conduit_end"
internal="KyogenRV_0.conduit_end"
type="conduit"
dir="end" />
<interface
name="msgdma_0_csr_irq"
internal="msgdma_0.csr_irq"
type="interrupt"
dir="end" />
<interface
name="msgdma_0_st_sink"
internal="msgdma_0.st_sink"
type="avalon_streaming"
dir="end" />
<interface
name="new_sdram_controller_0_wire"
internal="sdram_0.wire"
type="conduit"
dir="end" />
<interface
name="pio_0_external_connection"
internal="pio_0.external_connection"
type="conduit"
dir="end" />
<interface name="reset" internal="clk_0.clk_in_reset" type="reset" dir="end" />
<interface
name="uart_0_external_connection"
internal="uart_0.external_connection"
type="conduit"
dir="end" />
<interface name="uart_0_irq" internal="uart_0.irq" type="interrupt" dir="end" />
<module name="KyogenRV_0" kind="KyogenRV" version="20.1" enabled="1" />
<module name="clk_0" kind="clock_source" version="20.1" enabled="1">
<parameter name="clockFrequency" value="70000000" />
<parameter name="clockFrequencyKnown" value="true" />
<parameter name="inputClockFrequency" value="0" />
<parameter name="resetSynchronousEdges" value="NONE" />
</module>
<module name="i2c_0" kind="altera_avalon_i2c" version="20.1" enabled="1">
<parameter name="FIFO_DEPTH" value="4" />
<parameter name="USE_AV_ST" value="0" />
<parameter name="clockRate" value="70000000" />
</module>
<module name="msgdma_0" kind="altera_msgdma" version="20.1" enabled="1">
<parameter name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP" value="" />
<parameter
name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH"
value="AddressWidth = -1" />
<parameter name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP" value="" />
<parameter
name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH"
value="AddressWidth = -1" />
<parameter name="AUTO_DEVICE" value="10CL025YU256C8G" />
<parameter name="AUTO_DEVICE_FAMILY" value="Cyclone 10 LP" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="8" />
<parameter name="AUTO_MM_READ_ADDRESS_MAP" value="" />
<parameter name="AUTO_MM_READ_ADDRESS_WIDTH" value="AddressWidth = -1" />
<parameter name="AUTO_MM_WRITE_ADDRESS_MAP"><![CDATA[<address-map><slave name='sdram_0.s1' start='0x800000' end='0x1000000' /></address-map>]]></parameter>
<parameter name="AUTO_MM_WRITE_ADDRESS_WIDTH" value="AddressWidth = 24" />
<parameter name="BURST_ENABLE" value="0" />
<parameter name="BURST_WRAPPING_SUPPORT" value="0" />
<parameter name="CHANNEL_ENABLE" value="0" />
<parameter name="CHANNEL_WIDTH" value="8" />
<parameter name="DATA_FIFO_DEPTH" value="32" />
<parameter name="DATA_WIDTH" value="32" />
<parameter name="DESCRIPTOR_FIFO_DEPTH" value="128" />
<parameter name="ENHANCED_FEATURES" value="0" />
<parameter name="ERROR_ENABLE" value="0" />
<parameter name="ERROR_WIDTH" value="8" />
<parameter name="EXPOSE_ST_PORT" value="0" />
<parameter name="FIX_ADDRESS_WIDTH" value="32" />
<parameter name="MAX_BURST_COUNT" value="2" />
<parameter name="MAX_BYTE" value="1024" />
<parameter name="MAX_STRIDE" value="1" />
<parameter name="MODE" value="2" />
<parameter name="PACKET_ENABLE" value="0" />
<parameter name="PREFETCHER_DATA_WIDTH" value="32" />
<parameter name="PREFETCHER_ENABLE" value="0" />
<parameter name="PREFETCHER_MAX_READ_BURST_COUNT" value="2" />
<parameter name="PREFETCHER_READ_BURST_ENABLE" value="0" />
<parameter name="PROGRAMMABLE_BURST_ENABLE" value="0" />
<parameter name="RESPONSE_PORT" value="2" />
<parameter name="STRIDE_ENABLE" value="0" />
<parameter name="TRANSFER_TYPE" value="Aligned Accesses" />
<parameter name="USE_FIX_ADDRESS_WIDTH" value="0" />
</module>
<module
name="onchip_memory2_0"
kind="altera_avalon_onchip_memory2"
version="20.1"
enabled="1">
<parameter name="allowInSystemMemoryContentEditor" value="false" />
<parameter name="autoInitializationFileName">$${FILENAME}_onchip_memory2_0</parameter>
<parameter name="blockType" value="AUTO" />
<parameter name="copyInitFile" value="false" />
<parameter name="dataWidth" value="32" />
<parameter name="dataWidth2" value="32" />
<parameter name="deviceFamily" value="Cyclone 10 LP" />
<parameter name="deviceFeatures">COMPILER_SUPPORT 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 ANY_QFP 0 ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 HARDCOPY 0 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_BINNING_LIMITS_DATA 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_18_BIT_MULTS 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 IFP_USE_LEGACY_IO_CHECKER 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_BARE_DIE 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_SMI_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_REVE_SILICON 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M144K_MEMORY 0 M10K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_MIGRATABLE 0 NOT_LISTED 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_POF 0 NO_PIN_OUT 0 NO_RPE_SUPPORT 0 NO_TDC_SUPPORT 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORT_HIGH_SPEED_HPS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_CRC 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QMAP_IN_DEVELOPMENT 0 QFIT_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_OCT_AUTO_CALIBRATION 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1</parameter>
<parameter name="dualPort" value="false" />
<parameter name="ecc_enabled" value="false" />
<parameter name="enPRInitMode" value="false" />
<parameter name="enableDiffWidth" value="false" />
<parameter name="initMemContent" value="true" />
<parameter name="initializationFileName">./chisel_generated/blinker_intel.hex</parameter>
<parameter name="instanceID" value="NONE" />
<parameter name="memorySize" value="36864" />
<parameter name="readDuringWriteMode" value="DONT_CARE" />
<parameter name="resetrequest_enabled" value="true" />
<parameter name="simAllowMRAMContentsFile" value="false" />
<parameter name="simMemInitOnlyFilename" value="0" />
<parameter name="singleClockOperation" value="true" />
<parameter name="slave1Latency" value="1" />
<parameter name="slave2Latency" value="1" />
<parameter name="useNonDefaultInitFile" value="true" />
<parameter name="useShallowMemBlocks" value="false" />
<parameter name="writable" value="true" />
</module>
<module name="pio_0" kind="altera_avalon_pio" version="20.1" enabled="1">
<parameter name="bitClearingEdgeCapReg" value="false" />
<parameter name="bitModifyingOutReg" value="false" />
<parameter name="captureEdge" value="false" />
<parameter name="clockRate" value="70000000" />
<parameter name="direction" value="Output" />
<parameter name="edgeType" value="RISING" />
<parameter name="generateIRQ" value="false" />
<parameter name="irqType" value="LEVEL" />
<parameter name="resetValue" value="0" />
<parameter name="simDoTestBenchWiring" value="false" />
<parameter name="simDrivenValue" value="0" />
<parameter name="width" value="8" />
</module>
<module
name="sdram_0"
kind="altera_avalon_new_sdram_controller"
version="20.1"
enabled="1">
<parameter name="TAC" value="5.5" />
<parameter name="TMRD" value="3" />
<parameter name="TRCD" value="20.0" />
<parameter name="TRFC" value="70.0" />
<parameter name="TRP" value="20.0" />
<parameter name="TWR" value="14.0" />
<parameter name="casLatency" value="3" />
<parameter name="clockRate" value="70000000" />
<parameter name="columnWidth" value="8" />
<parameter name="componentName">$${FILENAME}_sdram_0</parameter>
<parameter name="dataWidth" value="16" />
<parameter name="generateSimulationModel" value="false" />
<parameter name="initNOPDelay" value="0.0" />
<parameter name="initRefreshCommands" value="2" />
<parameter name="masteredTristateBridgeSlave" value="0" />
<parameter name="model">single_Micron_MT48LC4M32B2_7_chip</parameter>
<parameter name="numberOfBanks" value="4" />
<parameter name="numberOfChipSelects" value="1" />
<parameter name="pinsSharedViaTriState" value="false" />
<parameter name="powerUpDelay" value="100.0" />
<parameter name="refreshPeriod" value="7.8125" />
<parameter name="registerDataIn" value="true" />
<parameter name="rowWidth" value="12" />
</module>
<module name="uart_0" kind="altera_avalon_uart" version="20.1" enabled="1">
<parameter name="baud" value="115200" />
<parameter name="clockRate" value="70000000" />
<parameter name="dataBits" value="8" />
<parameter name="fixedBaud" value="true" />
<parameter name="parity" value="NONE" />
<parameter name="simCharStream" value="" />
<parameter name="simInteractiveInputEnable" value="false" />
<parameter name="simInteractiveOutputEnable" value="false" />
<parameter name="simTrueBaud" value="false" />
<parameter name="stopBits" value="1" />
<parameter name="syncRegDepth" value="2" />
<parameter name="useCtsRts" value="false" />
<parameter name="useEopRegister" value="false" />
<parameter name="useRelativePathForSimFile" value="false" />
</module>
<connection
kind="avalon"
version="20.1"
start="KyogenRV_0.avalon_data_master"
end="i2c_0.csr">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00010000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="20.1"
start="KyogenRV_0.avalon_data_master"
end="msgdma_0.csr">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00010060" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="20.1"
start="KyogenRV_0.avalon_data_master"
end="msgdma_0.descriptor_slave">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00010090" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="20.1"
start="KyogenRV_0.avalon_data_master"
end="uart_0.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00010040" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="20.1"
start="KyogenRV_0.avalon_data_master"
end="pio_0.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00010080" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="20.1"
start="KyogenRV_0.avalon_data_master"
end="onchip_memory2_0.s1">
<parameter name="arbitrationPriority" value="7" />
<parameter name="baseAddress" value="0x0000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="20.1"
start="KyogenRV_0.avalon_data_master"
end="sdram_0.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00800000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="20.1"
start="KyogenRV_0.avalon_inst_master"
end="onchip_memory2_0.s1">
<parameter name="arbitrationPriority" value="3" />
<parameter name="baseAddress" value="0x0000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="20.1"
start="msgdma_0.mm_write"
end="sdram_0.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00800000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection kind="clock" version="20.1" start="clk_0.clk" end="pio_0.clk" />
<connection kind="clock" version="20.1" start="clk_0.clk" end="uart_0.clk" />
<connection kind="clock" version="20.1" start="clk_0.clk" end="sdram_0.clk" />
<connection
kind="clock"
version="20.1"
start="clk_0.clk"
end="onchip_memory2_0.clk1" />
<connection kind="clock" version="20.1" start="clk_0.clk" end="KyogenRV_0.clock" />
<connection kind="clock" version="20.1" start="clk_0.clk" end="i2c_0.clock" />
<connection kind="clock" version="20.1" start="clk_0.clk" end="msgdma_0.clock" />
<connection kind="reset" version="20.1" start="clk_0.clk_reset" end="pio_0.reset" />
<connection
kind="reset"
version="20.1"
start="clk_0.clk_reset"
end="uart_0.reset" />
<connection
kind="reset"
version="20.1"
start="clk_0.clk_reset"
end="KyogenRV_0.reset" />
<connection
kind="reset"
version="20.1"
start="clk_0.clk_reset"
end="sdram_0.reset" />
<connection
kind="reset"
version="20.1"
start="clk_0.clk_reset"
end="onchip_memory2_0.reset1" />
<connection
kind="reset"
version="20.1"
start="clk_0.clk_reset"
end="msgdma_0.reset_n" />
<connection
kind="reset"
version="20.1"
start="clk_0.clk_reset"
end="i2c_0.reset_sink" />
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
<interconnectRequirement
for="onchip_memory2_0.s1"
name="qsys_mm.arbitrationScheme"
value="fixed-priority" />
</system>