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RegFileLoadSyn.v
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RegFileLoadSyn.v
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/*
* These source files contain a hardware description of a network
* automatically generated by CONNECT (CONfigurable NEtwork Creation Tool).
*
* This product includes a hardware design developed by Carnegie Mellon
* University.
*
* Copyright (c) 2012 by Michael K. Papamichael, Carnegie Mellon University
*
* For more information, see the CONNECT project website at:
* http://www.ece.cmu.edu/~mpapamic/connect
*
* This design is provided for internal, non-commercial research use only,
* cannot be used for, or in support of, goods or services, and is not for
* redistribution, with or without modifications.
*
* You may not use the name "Carnegie Mellon University" or derivations
* thereof to endorse or promote products derived from this software.
*
* THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY
* THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY
* BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT,
* SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN
* ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY,
* CONTRACT, TORT OR OTHERWISE).
*
*/
module RegFileLoadSyn
(CLK, RST_N,
ADDR_IN, D_IN, WE,
ADDR_1, D_OUT_1
);
parameter file = "";
parameter addr_width = 1;
parameter data_width = 1;
parameter lo = 0;
parameter hi = 1;
parameter binary = 0;
input CLK;
input RST_N;
input [addr_width - 1 : 0] ADDR_IN;
input [data_width - 1 : 0] D_IN;
input WE;
input [addr_width - 1 : 0] ADDR_1;
output [data_width - 1 : 0] D_OUT_1;
reg [data_width - 1 : 0] arr[lo:hi];
initial
begin : init_block
$readmemh(file, arr, lo, hi);
end
always@(posedge CLK)
begin
if (WE && RST_N)
arr[ADDR_IN] <= D_IN;
end // always@ (posedge CLK)
assign D_OUT_1 = arr[ADDR_1];
endmodule