diff --git a/.github/workflows/examples.yml b/.github/workflows/examples.yml
index 095da24..140109e 100644
--- a/.github/workflows/examples.yml
+++ b/.github/workflows/examples.yml
@@ -7,13 +7,14 @@ jobs:
     strategy:
       fail-fast: false
       matrix:
-        os: [ubuntu-16.04, windows-latest, macos-latest]
-        python-version: [2.7, 3.7]
+        os: [ubuntu-18.04, windows-latest, macos-latest]
+        python-version: [3.7]
         example:
           - "examples/native-asm"
           - "examples/native-bare_c"
           - "examples/psp-hello-world"
           - "examples/rtosal-freertos"
+          # - "examples/zephyr-hello-world"
     runs-on: ${{ matrix.os }}
     steps:
       - uses: actions/checkout@v2
diff --git a/README.md b/README.md
index aa460e7..027c79f 100644
--- a/README.md
+++ b/README.md
@@ -1,7 +1,7 @@
 # CHIPS Alliance: development platform for [PlatformIO](http://platformio.org)
 
-![alt text](https://github.com/platformio/platform-chipsalliance/workflows/Examples/badge.svg "CHIPS Alliance development platform")
-    
+[![Build Status](https://github.com/platformio/platform-chipsalliance/workflows/Examples/badge.svg)](https://github.com/platformio/platform-chipsalliance/actions)
+
 CHIPS Alliance brings the power of open source and software automation to the semiconductor industry, making it possible to develop new hardware faster and more affordably than ever before.
 
 * [Home](http://platformio.org/platforms/chipsalliance) (home page in PlatformIO Platform Registry)
diff --git a/builder/main.py b/builder/main.py
index eeb13f0..eb7e366 100644
--- a/builder/main.py
+++ b/builder/main.py
@@ -150,6 +150,7 @@ def run_verilator(target, source, env):
     target_elf = env.BuildProgram()
     target_bin = env.ElfToBin(os.path.join("$BUILD_DIR", "${PROGNAME}"), target_elf)
     target_vh = env.BinToVh(os.path.join("$BUILD_DIR", "${PROGNAME}"), target_bin)
+    env.Depends(target_bin, "checkprogsize")
 
 AlwaysBuild(env.Alias("nobuild", target_bin))
 target_buildprog = env.Alias("buildprog", target_bin, target_bin)
@@ -178,6 +179,9 @@ def run_verilator(target, source, env):
 bitstream_file = os.path.abspath(
     board_config.get("build.bitstream_file", "swervolf_0.bit"))
 
+if not os.path.isfile(bitstream_file):
+    bitstream_file = os.path.join(platform.get_dir(), "misc", "bitstream", "rvfpga.bit")
+
 if "program_fpga" in COMMAND_LINE_TARGETS and not os.path.isfile(bitstream_file):
     sys.stderr.write("Error: Couldn't find bitstream file.\n")
     env.Exit(1)
@@ -316,9 +320,10 @@ def run_verilator(target, source, env):
     )
     openocd_args.extend(
         [
-            "-c", "load_image {$SOURCE} %s" % board_config.get(
-                "upload").get("image_offset", ""),
-            "-c", "reset run",
+            "-c", "reset halt",
+            "-c", "load_image {$SOURCE} %s elf" % board_config.get(
+                "upload").get("image_offset", "0x0"),
+            "-c", "resume %s" % board_config.get("upload").get("image_offset", "0x0"),
             "-c", "shutdown"
         ]
     )
diff --git a/misc/bitstream/rvfpga.bit b/misc/bitstream/rvfpga.bit
new file mode 100644
index 0000000..f4f051a
Binary files /dev/null and b/misc/bitstream/rvfpga.bit differ
diff --git a/platform.json b/platform.json
index e0f5a8c..545e72e 100644
--- a/platform.json
+++ b/platform.json
@@ -17,7 +17,7 @@
     "type": "git",
     "url": "https://github.com/platformio/platform-chipsalliance.git"
   },
-  "version": "1.0.3",
+  "version": "1.1.0",
   "frameworks": {
     "wd-riscv-sdk": {
       "package": "framework-wd-riscv-sdk",
@@ -47,7 +47,7 @@
     "tool-openocd-riscv-chipsalliance": {
       "type": "uploader",
       "owner": "platformio",
-      "version": "~1.1000.0"
+      "version": "~1.1100.0"
     },
     "tool-verilator-swervolf": {
       "type": "debugger",
diff --git a/platform.py b/platform.py
index bd4b799..74eb150 100644
--- a/platform.py
+++ b/platform.py
@@ -12,7 +12,7 @@
 # See the License for the specific language governing permissions and
 # limitations under the License.
 
-from os.path import join
+import os
 
 from platformio.managers.platform import PlatformBase
 
@@ -50,7 +50,7 @@ def _add_default_debug_tools(self, board):
             server_package = "tool-openocd-riscv-chipsalliance"
             server_args = [
                 "-s",
-                join(
+                os.path.join(
                     self.get_package_dir("framework-wd-riscv-sdk") or "",
                     "board",
                     board.get("build.variant", ""),
@@ -69,7 +69,7 @@ def _add_default_debug_tools(self, board):
                 "end",
             ]
             if tool == "verilator":
-                openocd_config = join(
+                openocd_config = os.path.join(
                     self.get_dir(),
                     "misc",
                     "openocd",
@@ -94,7 +94,7 @@ def _add_default_debug_tools(self, board):
                     "define pio_reset_run_target",
                     "end",
                 ]
-            elif debug.get("openocd_config"):
+            elif debug.get("openocd_config", ""):
                 server_args.extend(["-f", debug.get("openocd_config")])
             else:
                 assert debug.get("openocd_target"), (
@@ -129,3 +129,16 @@ def _add_default_debug_tools(self, board):
 
         board.manifest["debug"] = debug
         return board
+
+    def configure_debug_options(self, initial_debug_options, ide_data):
+        debug_options = copy.deepcopy(initial_debug_options)
+        adapter_speed = initial_debug_options.get("speed")
+        if adapter_speed:
+            server_options = debug_options.get("server") or {}
+            server_executable = server_options.get("executable", "").lower()
+            if "openocd" in server_executable:
+                debug_options["server"]["arguments"].extend(
+                    ["-c", "adapter speed %s" % adapter_speed]
+                )
+
+        return debug_options