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Capstone-RISC-V Spike Simulator

The Capstone-RISC-V Spike Simulator is based on the Spike RISC-V ISA Simulator.

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The Capstone-RISC-V Spike Simulator simulates a Capstone-RISC-V processor.

The interface of the processor follows the Capstone-RISC-V ISA, and some implementation-defined specifications are provided:

Quick Start

Please refer to the Capstone-RISC-V Spike Simulator SDK.

Building

  1. Build the RISC-V GNU Toolchain.
  2. Build the RISC-V Proxy Kernel.
  3. Follow the building instructions for the Spike RISC-V ISA Simulator.

Common Options

Note: some original options of Spike are not supported in Capstone-RISC-V Spike yet. Please be careful when using the options that are not listed here.

Parameter Description
-h, --help Print help message
-m<a:m,b:n,...> Provide memory regions of size m and n bytes at base addresses a and b (with 4 KiB alignment)
-p<n> Simulate n processors (default 1)
--isa=<name> RISC-V ISA string (default RV64IMAFDC)
-M<a:m> Provide secure memory regions of size m bytes at base addresses a (with 4 KiB alignment)
-R<n> The size of revocation tree (default 1024*1024)
-D Enable debug instructions