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Add axi_xslv
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
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‎Bender.yml

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- src/axi_xp.sv
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- src/autocc_axi_xbar_pkg.sv
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- src/axi_xbar_superwrap.sv
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- src/axi_xslv_superwrap.sv
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- target: synth_test
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files:

‎src/axi_xslv.sv

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// Copyright (c) 2024 ETH Zurich and University of Bologna.
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// Copyright and related rights are licensed under the Solderpad Hardware
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// License, Version 0.51 (the "License"); you may not use this file except in
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// compliance with the License. You may obtain a copy of the License at
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// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
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// or agreed to in writing, software, hardware and materials distributed under
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// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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// CONDITIONS OF ANY KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations under the License.
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//
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// Authors:
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// - Nils Wistoff <nwistoff@iis.ee.ethz.ch>
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module axi_xslv
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import cf_math_pkg::idx_width;
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#(
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parameter axi_pkg::xbar_cfg_t Cfg = '0,
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parameter bit ATOPs = 1'b1,
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parameter bit [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts-1:0] Connectivity = '1,
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parameter type slv_aw_chan_t = logic,
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parameter type mst_aw_chan_t = logic,
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parameter type w_chan_t = logic,
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parameter type slv_b_chan_t = logic,
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parameter type mst_b_chan_t = logic,
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parameter type slv_ar_chan_t = logic,
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parameter type mst_ar_chan_t = logic,
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parameter type slv_r_chan_t = logic,
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parameter type mst_r_chan_t = logic,
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parameter type slv_req_t = logic,
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parameter type slv_resp_t = logic,
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parameter type mst_req_t = logic,
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parameter type mst_resp_t = logic,
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parameter type rule_t = axi_pkg::xbar_rule_64_t
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) (
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/// Clock, positive edge triggered.
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input logic clk_i,
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/// Asynchronous reset, active low.
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input logic rst_ni,
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/// Testmode enable, active high.
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input logic test_i,
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/*AUTOSVA
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slv_port_r_req_0: slv_port_r_req_0 --IN> slv_port_r_resp_0
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slv_port_r_req_0_val = slv_ports_req_i[0].ar_valid
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slv_port_r_req_0_rdy = slv_ports_resp_o[0].ar_ready
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slv_port_r_req_0_transid = slv_ports_req_i[0].ar.id
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slv_port_r_resp_0_val = slv_ports_resp_o[0].r_valid
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slv_port_r_resp_0_rdy = slv_ports_req_i[0].r_ready
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slv_port_r_resp_0_transid = slv_ports_resp_o[0].r.id
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slv_port_r_req_1: slv_port_r_req_1 --IN> slv_port_r_resp_1
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slv_port_r_req_1_val = slv_ports_req_i[1].ar_valid
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slv_port_r_req_1_rdy = slv_ports_resp_o[1].ar_ready
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slv_port_r_req_1_transid = slv_ports_req_i[1].ar.id
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slv_port_r_resp_1_val = slv_ports_resp_o[1].r_valid
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slv_port_r_resp_1_rdy = slv_ports_req_i[1].r_ready
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slv_port_r_resp_1_transid = slv_ports_resp_o[1].r.id
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slv_port_w_req_0: slv_port_w_req_0 --IN> slv_port_w_resp_0
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slv_port_w_req_0_val = slv_ports_req_i[0].aw_valid
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slv_port_w_req_0_rdy = slv_ports_resp_o[0].aw_ready
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slv_port_w_req_0_transid = slv_ports_req_i[0].aw.id
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slv_port_w_resp_0_val = slv_ports_resp_o[0].b_valid
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slv_port_w_resp_0_rdy = slv_ports_req_i[0].b_ready
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slv_port_w_resp_0_transid = slv_ports_resp_o[0].b.id
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slv_port_w_req_1: slv_port_w_req_1 --IN> slv_port_w_resp_1
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slv_port_w_req_1_val = slv_ports_req_i[1].aw_valid
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slv_port_w_req_1_rdy = slv_ports_resp_o[1].aw_ready
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slv_port_w_req_1_transid = slv_ports_req_i[1].aw.id
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slv_port_w_resp_1_val = slv_ports_resp_o[1].b_valid
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slv_port_w_resp_1_rdy = slv_ports_req_i[1].b_ready
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slv_port_w_resp_1_transid = slv_ports_resp_o[1].b.id
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*/
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/// AXI4+ATOP requests to the slave ports.
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input slv_req_t [Cfg.NoSlvPorts-1:0] slv_ports_req_i,
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/// AXI4+ATOP responses of the slave ports.
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output slv_resp_t [Cfg.NoSlvPorts-1:0] slv_ports_resp_o,
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/// Address map array input for the crossbar. This map is global for the whole module.
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/// It is used for routing the transactions to the respective master ports.
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/// Each master port can have multiple different rules.
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input rule_t [Cfg.NoAddrRules-1:0] addr_map_i,
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/// Enable default master port.
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input logic [Cfg.NoSlvPorts-1:0] en_default_mst_port_i,
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`ifdef VCS
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/// Enables a default master port for each slave port. When this is enabled unmapped
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/// transactions get issued at the master port given by `default_mst_port_i`.
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/// When not used, tie to `'0`.
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input logic [Cfg.NoSlvPorts-1:0][MstPortsIdxWidth-1:0] default_mst_port_i
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`else
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/// Enables a default master port for each slave port. When this is enabled unmapped
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/// transactions get issued at the master port given by `default_mst_port_i`.
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/// When not used, tie to `'0`.
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input logic [Cfg.NoSlvPorts-1:0][idx_width(Cfg.NoMstPorts)-1:0] default_mst_port_i
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`endif
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);
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// =========
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// Testbench
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// =========
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mst_req_t [Cfg.NoMstPorts-1:0] mst_ports_req;
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mst_resp_t [Cfg.NoMstPorts-1:0] mst_ports_resp;
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axi_xbar #(
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.Cfg(Cfg),
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.ATOPs(ATOPs),
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.Connectivity(Connectivity),
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.slv_aw_chan_t(slv_aw_chan_t),
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.mst_aw_chan_t(mst_aw_chan_t),
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.w_chan_t(w_chan_t),
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.slv_b_chan_t(slv_b_chan_t),
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.mst_b_chan_t(mst_b_chan_t),
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.slv_ar_chan_t(slv_ar_chan_t),
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.mst_ar_chan_t(mst_ar_chan_t),
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.slv_r_chan_t(slv_r_chan_t),
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.mst_r_chan_t(mst_r_chan_t),
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.slv_req_t(slv_req_t),
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.slv_resp_t(slv_resp_t),
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.mst_req_t(mst_req_t),
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.mst_resp_t(mst_resp_t),
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.rule_t(rule_t)
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) i_axi_xbar (
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.clk_i(clk_i),
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.rst_ni(rst_ni),
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.test_i(test_i),
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.slv_ports_req_i(slv_ports_req_i),
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.slv_ports_resp_o(slv_ports_resp_o),
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.mst_ports_req_o(mst_ports_req),
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.mst_ports_resp_i(mst_ports_resp),
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.addr_map_i(addr_map_i),
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.en_default_mst_port_i(en_default_mst_port_i),
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.default_mst_port_i(default_mst_port_i)
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);
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for (genvar i = 0; i < Cfg.NoSlvPorts; i++) begin : gen_zero_mems
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axi_zero_mem #(
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.axi_req_t(mst_req_t),
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.axi_resp_t(mst_resp_t),
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.AddrWidth($bits(mst_ports_req[0].ar.addr)),
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.DataWidth($bits(mst_ports_req[0].w.data)),
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.IdWidth($bits(mst_ports_req[0].ar.id)),
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.NumBanks(1),
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.BufDepth(1)
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) i_axi_zero_mem (
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.clk_i,
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.rst_ni,
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.busy_o(),
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.axi_req_i(mst_ports_req[i]),
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.axi_resp_o(mst_ports_resp[i])
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);
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end
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endmodule

‎src/axi_xslv_superwrap.sv

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// Copyright (c) 2024 ETH Zurich and University of Bologna.
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// Copyright and related rights are licensed under the Solderpad Hardware
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// License, Version 0.51 (the "License"); you may not use this file except in
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// compliance with the License. You may obtain a copy of the License at
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// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
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// or agreed to in writing, software, hardware and materials distributed under
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// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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// CONDITIONS OF ANY KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations under the License.
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//
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// Authors:
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// - Nils Wistoff <nwistoff@iis.ee.ethz.ch>
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module axi_xslv_superwrap
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import cf_math_pkg::idx_width;
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import autocc_axi_xbar_pkg::*;
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#(
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parameter ASSERT_INPUTS = 0
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) (
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/// Clock, positive edge triggered.
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input logic clk_i,
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/// Asynchronous reset, active low.
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input logic rst_ni,
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/// Testmode enable, active high.
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input logic test_i,
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/// AXI4+ATOP requests to the slave ports.
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input slv_req_t [Cfg.NoSlvPorts-1:0] slv_ports_req_i_2,
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input slv_req_t [Cfg.NoSlvPorts-1:0] slv_ports_req_i,
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/// AXI4+ATOP responses of the slave ports.
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output slv_resp_t [Cfg.NoSlvPorts-1:0] slv_ports_resp_o_2,
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output slv_resp_t [Cfg.NoSlvPorts-1:0] slv_ports_resp_o,
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/// Address map array input for the crossbar. This map is global for the whole module.
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/// It is used for routing the transactions to the respective master ports.
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/// Each master port can have multiple different rules.
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input rule_t [Cfg.NoAddrRules-1:0] addr_map_i,
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/// Enable default master port.
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input logic [Cfg.NoSlvPorts-1:0] en_default_mst_port_i,
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`ifdef VCS
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/// Enables a default master port for each slave port. When this is enabled unmapped
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/// transactions get issued at the master port given by `default_mst_port_i`.
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/// When not used, tie to `'0`.
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input logic [Cfg.NoSlvPorts-1:0][MstPortsIdxWidth-1:0] default_mst_port_i
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`else
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/// Enables a default master port for each slave port. When this is enabled unmapped
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/// transactions get issued at the master port given by `default_mst_port_i`.
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/// When not used, tie to `'0`.
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input logic [Cfg.NoSlvPorts-1:0][idx_width(Cfg.NoMstPorts)-1:0] default_mst_port_i
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`endif
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);
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// =========
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// Testbench
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// =========
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axi_xslv_wrap #(
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.Cfg(Cfg),
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.ATOPs(ATOPs),
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.Connectivity(Connectivity),
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.slv_aw_chan_t(slv_aw_chan_t),
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.mst_aw_chan_t(mst_aw_chan_t),
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.w_chan_t(slv_w_chan_t),
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.slv_b_chan_t(slv_b_chan_t),
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.mst_b_chan_t(mst_b_chan_t),
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.slv_ar_chan_t(slv_ar_chan_t),
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.mst_ar_chan_t(mst_ar_chan_t),
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.slv_r_chan_t(slv_r_chan_t),
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.mst_r_chan_t(mst_r_chan_t),
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.slv_req_t(slv_req_t),
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.slv_resp_t(slv_resp_t),
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.mst_req_t(mst_req_t),
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.mst_resp_t(mst_resp_t),
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.rule_t(rule_t)
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) i_axi_xslv_wrap (
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.clk_i(clk_i),
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.rst_ni(rst_ni),
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.test_i(test_i),
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.slv_ports_req_i_2(slv_ports_req_i_2),
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.slv_ports_req_i(slv_ports_req_i),
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.slv_ports_resp_o_2(slv_ports_resp_o_2),
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.slv_ports_resp_o(slv_ports_resp_o),
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.addr_map_i(addr_map_i),
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.en_default_mst_port_i(en_default_mst_port_i),
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.default_mst_port_i(default_mst_port_i)
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);
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endmodule

‎src/axi_xslv_wrap.sv

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// This property file was autogenerated by AutoCC on 2024-11-22
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// to check the behavior of the original RTL module, whose interface is described below:
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module axi_xslv_wrap
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import cf_math_pkg::idx_width;
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#(
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parameter ASSERT_INPUTS = 0,
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parameter axi_pkg::xbar_cfg_t Cfg = '0,
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parameter bit ATOPs = 1'b1,
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parameter bit [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts-1:0] Connectivity = '1,
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parameter type slv_aw_chan_t = logic,
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parameter type mst_aw_chan_t = logic,
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parameter type w_chan_t = logic,
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parameter type slv_b_chan_t = logic,
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parameter type mst_b_chan_t = logic,
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parameter type slv_ar_chan_t = logic,
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parameter type mst_ar_chan_t = logic,
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parameter type slv_r_chan_t = logic,
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parameter type mst_r_chan_t = logic,
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parameter type slv_req_t = logic,
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parameter type slv_resp_t = logic,
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parameter type mst_req_t = logic,
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parameter type mst_resp_t = logic,
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parameter type rule_t = axi_pkg::xbar_rule_64_t
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) (
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/// Clock, positive edge triggered.
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input logic clk_i,
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/// Asynchronous reset, active low.
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input logic rst_ni,
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/// Testmode enable, active high.
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input logic test_i,
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/// AXI4+ATOP requests to the slave ports.
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input slv_req_t [Cfg.NoSlvPorts-1:0] slv_ports_req_i_2,
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input slv_req_t [Cfg.NoSlvPorts-1:0] slv_ports_req_i,
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/// AXI4+ATOP responses of the slave ports.
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output slv_resp_t [Cfg.NoSlvPorts-1:0] slv_ports_resp_o_2,
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output slv_resp_t [Cfg.NoSlvPorts-1:0] slv_ports_resp_o,
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/// Address map array input for the crossbar. This map is global for the whole module.
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/// It is used for routing the transactions to the respective master ports.
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/// Each master port can have multiple different rules.
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input rule_t [Cfg.NoAddrRules-1:0] addr_map_i,
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/// Enable default master port.
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input logic [Cfg.NoSlvPorts-1:0] en_default_mst_port_i,
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`ifdef VCS
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/// Enables a default master port for each slave port. When this is enabled unmapped
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/// transactions get issued at the master port given by `default_mst_port_i`.
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/// When not used, tie to `'0`.
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input logic [Cfg.NoSlvPorts-1:0][MstPortsIdxWidth-1:0] default_mst_port_i
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`else
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/// Enables a default master port for each slave port. When this is enabled unmapped
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/// transactions get issued at the master port given by `default_mst_port_i`.
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/// When not used, tie to `'0`.
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input logic [Cfg.NoSlvPorts-1:0][idx_width(Cfg.NoMstPorts)-1:0] default_mst_port_i
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`endif
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);
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//==============================================================================
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// Instance Modules
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//==============================================================================
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axi_xslv #(
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.Cfg(Cfg),
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.ATOPs(ATOPs),
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.Connectivity(Connectivity),
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.slv_aw_chan_t(slv_aw_chan_t),
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.mst_aw_chan_t(mst_aw_chan_t),
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.w_chan_t(w_chan_t),
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.slv_b_chan_t(slv_b_chan_t),
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.mst_b_chan_t(mst_b_chan_t),
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.slv_ar_chan_t(slv_ar_chan_t),
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.mst_ar_chan_t(mst_ar_chan_t),
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.slv_r_chan_t(slv_r_chan_t),
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.mst_r_chan_t(mst_r_chan_t),
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.slv_req_t(slv_req_t),
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.slv_resp_t(slv_resp_t),
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.mst_req_t(mst_req_t),
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.mst_resp_t(mst_resp_t),
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.rule_t(rule_t)
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) u_axi_xslv (
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.clk_i(clk_i),
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.rst_ni(rst_ni),
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.test_i(test_i),
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.slv_ports_req_i(slv_ports_req_i),
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.slv_ports_resp_o(slv_ports_resp_o),
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.addr_map_i(addr_map_i),
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.en_default_mst_port_i(en_default_mst_port_i),
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.default_mst_port_i(default_mst_port_i)
88+
);
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axi_xslv #(
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.Cfg(Cfg),
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.ATOPs(ATOPs),
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.Connectivity(Connectivity),
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.slv_aw_chan_t(slv_aw_chan_t),
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.mst_aw_chan_t(mst_aw_chan_t),
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.w_chan_t(w_chan_t),
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.slv_b_chan_t(slv_b_chan_t),
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.mst_b_chan_t(mst_b_chan_t),
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.slv_ar_chan_t(slv_ar_chan_t),
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.mst_ar_chan_t(mst_ar_chan_t),
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.slv_r_chan_t(slv_r_chan_t),
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.mst_r_chan_t(mst_r_chan_t),
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.slv_req_t(slv_req_t),
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.slv_resp_t(slv_resp_t),
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.mst_req_t(mst_req_t),
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.mst_resp_t(mst_resp_t),
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.rule_t(rule_t)
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) u_axi_xslv2 (
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.clk_i(clk_i),
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.rst_ni(rst_ni),
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.test_i(test_i),
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.slv_ports_req_i(slv_ports_req_i_2),
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.slv_ports_resp_o(slv_ports_resp_o_2),
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.addr_map_i(addr_map_i),
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.en_default_mst_port_i(en_default_mst_port_i),
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.default_mst_port_i(default_mst_port_i)
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);
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endmodule

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