common_cells.core

CAPI=2:

name : pulp-platform.org::common_cells:1.39.0
description: Common SystemVerilog components

filesets:
  rtl:
    files:
      - include/common_cells/registers.svh : {is_include_file : true, include_path : include}
      - include/common_cells/assertions.svh : {is_include_file : true, include_path : include}
      # Source files grouped in levels. Files in level 0 have no dependencies on files in this package.
      # Files in level 1 only depend on files in level 0, files in level 2 on files in levels 1 and 0,
      # etc. Files within a level are ordered alphabetically.
      # Level 0
      - src/binary_to_gray.sv
      - src/cb_filter_pkg.sv
      - src/cc_onehot.sv
      - src/cf_math_pkg.sv
      - src/clk_int_div.sv
      - src/clk_int_div_static.sv
      - src/credit_counter.sv
      - src/delta_counter.sv
      - src/ecc_pkg.sv
      - src/edge_propagator_tx.sv
      - src/exp_backoff.sv
      - src/fifo_v3.sv
      - src/gray_to_binary.sv
      - src/isochronous_4phase_handshake.sv
      - src/isochronous_spill_register.sv
      - src/lfsr.sv
      - src/lfsr_16bit.sv
      - src/lfsr_8bit.sv
      - src/multiaddr_decode.sv
      - src/mv_filter.sv
      - src/onehot_to_bin.sv
      - src/plru_tree.sv
      - src/passthrough_stream_fifo.sv
      - src/popcount.sv
      - src/rr_arb_tree.sv
      - src/rstgen_bypass.sv
      - src/serial_deglitch.sv
      - src/shift_reg.sv
      - src/shift_reg_gated.sv
      - src/spill_register_flushable.sv
      - src/stream_demux.sv
      - src/stream_filter.sv
      - src/stream_fork.sv
      - src/stream_intf.sv
      - src/stream_join.sv
      - src/stream_join_dynamic.sv
      - src/stream_mux.sv
      - src/stream_throttle.sv
      - src/sub_per_hash.sv
      - src/sync.sv
      - src/sync_wedge.sv
      - src/unread.sv
      - src/read.sv
      - src/cdc_reset_ctrlr_pkg.sv
      # Level 1
      - src/addr_decode_dync.sv
      - src/cdc_2phase.sv
      - src/cdc_4phase.sv
      - src/cb_filter.sv
      - src/cdc_fifo_2phase.sv
      - src/counter.sv
      - src/ecc_decode.sv
      - src/ecc_encode.sv
      - src/edge_detect.sv
      - src/lzc.sv
      - src/max_counter.sv
      - src/rstgen.sv
      - src/spill_register.sv
      - src/stream_delay.sv
      - src/stream_fifo.sv
      - src/stream_fork_dynamic.sv
      - src/clk_mux_glitch_free.sv
      # Level 2
      - src/addr_decode.sv
      - src/addr_decode_napot.sv
      - src/cdc_reset_ctrlr.sv
      - src/cdc_fifo_gray.sv
      - src/fall_through_register.sv
      - src/id_queue.sv
      - src/stream_to_mem.sv
      - src/stream_arbiter_flushable.sv
      - src/stream_fifo_optimal_wrap.sv
      - src/stream_register.sv
      - src/stream_xbar.sv
      # Level 3
      - src/cdc_fifo_gray_clearable.sv
      - src/cdc_2phase_clearable.sv
      - src/mem_to_banks_detailed.sv
      - src/stream_arbiter.sv
      - src/stream_omega_net.sv
      # Level 4
      - src/mem_to_banks.sv
    file_type : systemVerilogSource

  deprecated:
    files:
      # Deprecated modules
      # Level 0
      - src/deprecated/clock_divider_counter.sv
      - src/deprecated/clk_div.sv
      - src/deprecated/find_first_one.sv
      - src/deprecated/generic_LFSR_8bit.sv
      - src/deprecated/generic_fifo.sv
      - src/deprecated/prioarbiter.sv
      - src/deprecated/pulp_sync.sv
      - src/deprecated/pulp_sync_wedge.sv
      - src/deprecated/rrarbiter.sv
      # Level 1
      - src/deprecated/clock_divider.sv
      - src/deprecated/fifo_v2.sv
      # Level 2
      - src/deprecated/fifo_v1.sv

      # Depend on deprecated modules
      - src/edge_propagator_ack.sv
      - src/edge_propagator.sv
      - src/edge_propagator_rx.sv
    file_type : systemVerilogSource

targets:
  default:
    filesets : [rtl, deprecated]
    parameters: [COMMON_CELLS_ASSERTS_OFF]

parameters:
  COMMON_CELLS_ASSERTS_OFF:
    datatype: bool
    description: Turn off asserts for PULP common cells
    paramtype: vlogdefine