DMA ifcr register doesn't have indexed writer

[gpgreen]

The last commit that added "_array" to the DMA ifcr and isr register, so that interrupt flags can be addressed using the channel index instead of hard coded names is only partially correct.

The isr register, which is Read only, can address each flag separately using and index, here is the code generated for one flag:
/**Channel [1-3] Global interrupt flag*/ #[inline(always)] pub unsafe fn gif(&self, n: u8) -> GIF_R { GIF_R::new(((self.bits >> ((n - 1) * 4)) & 1) != 0) }
The ifcr register, which is Write only, doesn't have that generated code. I am having to redo the bit swizzling in the HAL code as there is no way to clear a flag using a DMA channel index. I think that the problem is in the code generation, as I did not detect any differences in the patched svd file.

[gpgreen]

I wanted to tell you that I will post a PR to your HAL soon, that I am not expecting you to merge. I am updating it to use the embedded-hal 1.0 and am following the stm32f1xx for guidance. I wanted you to be able to see the work and decide what you want to do with it. I would prefer that you eventually merge it, but that is up to you. I am not going to post it till I get DMA, SPI, and Serial mostly working as that is the project that I am targeting. And also, thanks for doing the work to get these repos published, I had started what you have as py32-rs and py32f0xx-hal myself long ago, but never found the time to publish. Now I don't have to.

[creatoy]

Looking forward to your results, I was going to upgrade the embedded-hal to 1.0, but didn't have much time to do it. If you post a PR, I'll take some time to look at it.