diff --git a/dds_test.srcs/sim_1/new/noise_event_tracker_test.sv b/dds_test.srcs/sim_1/new/noise_event_tracker_test.sv
deleted file mode 100644
index 24c2633..0000000
--- a/dds_test.srcs/sim_1/new/noise_event_tracker_test.sv
+++ /dev/null
@@ -1,269 +0,0 @@
-`timescale 1ns / 1ps
-module noise_event_tracker_test();
-
-logic clk = 0;
-localparam CLK_RATE_HZ = 100_000_000;
-always #(0.5s/CLK_RATE_HZ) clk = ~clk;
-
-logic reset;
-logic start, stop;
-logic [15:0] threshold_high, threshold_low;
-
-Axis_If #(.DWIDTH(34)) config_in_if();
-Axis_If #(.DWIDTH(16)) data_in_00_if();
-Axis_If #(.DWIDTH(16)) data_in_02_if();
-Axis_If #(.DWIDTH(128)) data_out_if();
-
-assign config_in_if.data = {start, stop, threshold_high, threshold_low};
-
-noise_event_tracker #(
-  .BUFFER_DEPTH(1024),
-  .SAMPLE_WIDTH(16),
-  .AXI_MM_WIDTH(128),
-  .CLOCK_WIDTH(56)
-) dut_i (
-  .clk,
-  .reset,
-  .data_in_00(data_in_00_if),
-  .data_in_02(data_in_02_if),
-  .data_out(data_out_if),
-  .config_in(config_in_if)
-);
-
-logic [15:0] data_sent [2][$];
-logic [15:0] timestamps_sent [2][$];
-logic [15:0] data_received [2][$];
-logic [15:0] timestamps_received [2][$];
-
-logic [1:0][55:0] sample_count;
-logic [1:0][15:0] data_in_d;
-logic [1:0] data_in_valid_d;
-logic [1:0] is_high, is_high_d;
-logic [1:0] new_is_high;
-
-assign new_is_high = is_high & (~is_high_d);
-
-logic [15:0] data_range_low, data_range_high;
-
-always @(posedge clk) begin
-  if (reset) begin
-    sample_count <= '0;
-    data_in_00_if.data <= '0;
-    data_in_02_if.data <= '0;
-    is_high_d <= '0;
-    is_high <= '0;
-  end else begin
-    data_in_valid_d <= {data_in_02_if.valid, data_in_00_if.valid};
-    if (data_in_00_if.valid && data_in_00_if.ready) begin
-      data_in_d[0] <= data_in_00_if.data;
-      is_high_d[0] <= is_high[0];
-      if ((data_in_00_if.data & 16'hfffe) > threshold_high) begin
-        is_high[0] <= 1'b1;
-      end else if ((data_in_00_if.data & 16'hfffe) < threshold_low) begin
-        is_high[0] <= 1'b0;
-      end
-      sample_count[0] <= sample_count[0] + 1'b1;
-      data_in_00_if.data <= $urandom_range(data_range_low, data_range_high);
-    end
-    if (data_in_02_if.valid && data_in_02_if.ready) begin
-      data_in_d[1] <= data_in_02_if.data;
-      is_high_d[1] <= is_high[1];
-      if ((data_in_02_if.data & 16'hfffe)  > threshold_high) begin
-        is_high[1] <= 1'b1;
-      end else if ((data_in_02_if.data & 16'hfffe) < threshold_low) begin
-        is_high[1] <= 1'b0;
-      end
-      sample_count[1] <= sample_count[1] + 1'b1;
-      data_in_02_if.data <= $urandom_range(data_range_low, data_range_high);
-    end
-    // save data that was sent
-    for (int i = 0; i < 2; i++) begin
-      if (data_in_valid_d[i]) begin
-        if (is_high[i]) begin
-          data_sent[i].push_front({data_in_d[i][15:3], new_is_high[i], 1'b0, 1'(i)});
-        end
-        if (new_is_high[i]) begin
-          for (int j = 0; j < 4; j++) begin
-            timestamps_sent[i].push_front({sample_count[i][14*j+:14], 1'b1, 1'(i)});
-          end
-        end
-      end
-    end
-    if (data_out_if.valid && data_out_if.ready) begin
-      for (int i = 0; i < 8; i++) begin
-        if (data_out_if.data[16*i+1]) begin
-          // timestamp
-          timestamps_received[data_out_if.data[16*i]].push_front(data_out_if.data[16*i+:16]);
-        end else begin
-          // data
-          data_received[data_out_if.data[16*i]].push_front(data_out_if.data[16*i+:16]);
-        end
-      end
-    end
-  end
-end
-
-task send_samples_together(input int n_samples);
-  repeat (n_samples) begin
-    data_in_00_if.valid <= 1'b1;
-    data_in_02_if.valid <= 1'b1;
-    @(posedge clk);
-    data_in_00_if.valid <= 1'b0;
-    data_in_02_if.valid <= 1'b0;
-    repeat (4) @(posedge clk);
-  end
-endtask
-
-task send_samples_separate(input int n_samples);
-  repeat (n_samples) begin
-    if ($urandom_range(0,1) < 1) begin
-      data_in_00_if.valid <= 1'b1;
-      @(posedge clk);
-      data_in_00_if.valid <= 1'b0;
-      repeat (2) @(posedge clk);
-      data_in_02_if.valid <= 1'b1;
-      @(posedge clk);
-      data_in_02_if.valid <= 1'b0;
-      repeat (2) @(posedge clk);
-    end else begin
-      data_in_02_if.valid <= 1'b1;
-      @(posedge clk);
-      data_in_02_if.valid <= 1'b0;
-      repeat (2) @(posedge clk);
-      data_in_00_if.valid <= 1'b1;
-      @(posedge clk);
-      data_in_00_if.valid <= 1'b0;
-      repeat (2) @(posedge clk);
-    end
-  end
-endtask
-
-task do_readout();
-  data_out_if.ready <= 1'b0;
-  stop <= 1'b1;
-  config_in_if.valid <= 1'b1;
-  @(posedge clk);
-  stop <= 1'b0;
-  config_in_if.valid <= 1'b0;
-  repeat (500) @(posedge clk);
-  data_out_if.ready <= 1'b1;
-  repeat ($urandom_range(2,6)) @(posedge clk);
-  data_out_if.ready <= 1'b0;
-  repeat ($urandom_range(3,8)) @(posedge clk);
-  data_out_if.ready <= 1'b1;
-  while (!data_out_if.last) @(posedge clk);
-  @(posedge clk);
-endtask
-
-task check_results(input bit missing_data_okay);
-  for (int i = 0; i < 2; i++) begin
-    $display("checking channel %0d...", i);
-    $display("data_sent[%0d].size() = %0d", i, data_sent[i].size());
-    $display("data_received[%0d].size() = %0d", i, data_received[i].size());
-    if (data_sent[i].size() != data_received[i].size()) begin
-      if (missing_data_okay) begin
-        // if there's intermittent noise, we may have a few missing samples
-        // at the end which don't make it into the buffer; that's okay
-        if (data_sent[i].size() >= data_received[i].size() + 4) begin
-          // however, we should not be missing 4 or more samples
-          $warning("mismatch in amount of sent/received data");
-        end
-      end else begin
-        $warning("mismatch in amount of sent/received data");
-      end
-      // for (int j = data_sent[i].size() - 1; j >= 0; j--) begin
-      //   $display("data_sent[%0d][%0d] = %x", i, j, data_sent[i][j]);
-      // end
-      // for (int j = data_received[i].size() - 1; j >= 0; j--) begin
-      //   $display("data_received[%0d][%0d] = %x", i, j, data_received[i][j]);
-      // end
-    end
-    $display("timestamps_sent[%0d].size() = %0d", i, timestamps_sent[i].size());
-    $display("timestamps_received[%0d].size() = %0d", i, timestamps_received[i].size());
-    if (timestamps_sent[i].size() != timestamps_received[i].size()) begin
-      $warning("mismatch in amount of sent/received timestamps");
-      // for (int j = timestamps_sent[i].size() - 1; j >= 0; j--) begin
-      //   $display("timestamps_sent[%0d][%0d] = %x", i, j, timestamps_sent[i][j]);
-      // end
-      // for (int j = timestamps_received[i].size() - 1; j >= 0; j--) begin
-      //   $display("timestamps_received[%0d][%0d] = %x", i, j, timestamps_received[i][j]);
-      // end
-    end
-    while (data_sent[i].size() > 0 && data_received[i].size() > 0) begin
-      // data from channel 0 can be reordered with data from channel 2
-      if (data_sent[i][$] != data_received[i][$]) begin
-        $warning("data mismatch error (received %x, sent %x)", data_received[i][$], data_sent[i][$]);
-      end
-      data_sent[i].pop_back();
-      data_received[i].pop_back();
-    end
-    while (timestamps_sent[i].size() > 0 && timestamps_received[i].size() > 0) begin
-      if (timestamps_sent[i][$] != timestamps_received[i][$]) begin
-        $warning("timestamp mismatch error (received %x, sent %x)", timestamps_received[i][$], timestamps_sent[i][$]);
-      end
-      timestamps_sent[i].pop_back();
-      timestamps_received[i].pop_back();
-    end
-  end
-endtask
-
-initial begin
-  reset <= 1'b1;
-  start <= 1'b0;
-  stop <= 1'b0;
-  data_range_low <= 16'h0000;
-  data_range_high <= 16'hffff;
-  threshold_low <= '0;
-  threshold_high <= '0;
-  data_in_00_if.valid <= '0;
-  data_in_02_if.valid <= '0;
-  repeat (100) @(posedge clk);
-  reset <= 1'b0;
-  repeat (50) @(posedge clk);
-  // start
-  start <= 1'b1;
-  config_in_if.valid <= 1'b1;
-  @(posedge clk);
-  start <= 1'b0;
-  config_in_if.valid <= 1'b0;
-  repeat (100) @(posedge clk);
-  // send samples
-  send_samples_together(28); // send extra sample since first one is zero and will get dropped
-  repeat (50) @(posedge clk);
-  send_samples_separate(35);
-  repeat (50) @(posedge clk);
-  send_samples_together(18);
-  repeat (50) @(posedge clk);
-  do_readout();
-  $display("######################################################");
-  $display("# checking results for test with constant noise      #");
-  $display("######################################################");
-  check_results(1'b0);
-  // change amplitudes and threshold to check sample-rejection
-  data_range_low <= 16'h00ff;
-  data_range_high <= 16'h0fff;
-  threshold_low <= 16'h03ff;
-  threshold_high <= 16'h07ff;
-  config_in_if.valid <= 1'b1;
-  @(posedge clk);
-  config_in_if.valid <= 1'b0;
-  repeat (100) @(posedge clk);
-  // start
-  start <= 1'b1;
-  config_in_if.valid <= 1'b1;
-  @(posedge clk);
-  start <= 1'b0;
-  config_in_if.valid <= 1'b0;
-  repeat (50) @(posedge clk);
-  send_samples_together(300);
-  repeat (50) @(posedge clk);
-  send_samples_separate(240);
-  do_readout();
-  $display("######################################################");
-  $display("# checking results for test with intermittent noise  #");
-  $display("######################################################");
-  check_results(1'b1);
-  $finish;
-end
-
-endmodule
diff --git a/dds_test.srcs/sim_1/new/sample_buffer_test.sv b/dds_test.srcs/sim_1/new/sample_buffer_test.sv
deleted file mode 100644
index b98f0b2..0000000
--- a/dds_test.srcs/sim_1/new/sample_buffer_test.sv
+++ /dev/null
@@ -1,127 +0,0 @@
-`timescale 1ns / 1ps
-
-module sample_buffer_test ();
-
-logic clk = 0;
-localparam CLK_RATE_HZ = 100_000_000;
-always #(0.5s/CLK_RATE_HZ) clk = ~clk;
-
-logic reset;
-logic [127:0] data_out;
-logic data_out_valid, data_out_last, data_out_ready;
-logic [31:0][15:0] data_in;
-logic data_in_valid, data_in_ready;
-logic capture;
-
-Axis_If #(.DWIDTH(512)) data_in_if();
-Axis_If #(.DWIDTH(128)) data_out_if();
-
-sample_buffer #(
-  .BUFFER_DEPTH(1024),
-  .PARALLEL_SAMPLES(32),
-  .INPUT_SAMPLE_WIDTH(16),
-  .OUTPUT_SAMPLE_WIDTH(16),
-  .AXI_MM_WIDTH(128)
-) buffer_i (
-  .clk,
-  .reset,
-  .data_out(data_out_if),
-  .data_in(data_in_if),
-  .capture
-);
-
-logic [31:0][15:0] data_sent [1024];
-
-assign data_out = data_out_if.data;
-assign data_out_valid = data_out_if.valid;
-assign data_out_last = data_out_if.last;
-assign data_out_if.ready = data_out_ready;
-
-assign data_in_if.data = data_in;
-assign data_in_if.valid = data_in_valid;
-assign data_in_ready = data_in_if.ready;
-
-always @(posedge clk) begin
-  for (int i = 0; i < 32; i++) begin
-    data_in[i] <= $urandom_range(0,1<<16);
-  end
-end
-
-int sent_count;
-always @(posedge clk) begin
-  if (reset) begin
-    sent_count <= 0;
-  end else begin
-    if (capture && data_in_valid && data_in_ready) begin
-      sent_count <= sent_count + 1;
-    end
-  end
-  data_sent[sent_count] <= data_in;
-end
-
-assign data_out_ready = 0;
-assign data_in_valid = 1;
-
-// checker
-int recv_count, error_count;
-bit state;
-always @(posedge clk) begin
-  if (state) begin
-    // report results
-    $display("transaction count: %d", recv_count);
-    $display("error count: %d", error_count);
-    $finish;
-  end
-  if (reset) begin
-    recv_count <= 0;
-    error_count <= 0;
-    state <= 1'b0;
-  end else begin
-    if (data_out_valid && data_out_ready) begin
-      recv_count <= recv_count + 1;
-      for (int i = 0; i < 8; i++) begin
-        if (data_out[16*i+:16] !== data_sent[recv_count >> 2][(recv_count % 4)*8+i]) begin
-          $display("data mismatch, got %h, expected %h", data_out[16*i+:16], data_sent[recv_count >> 2][recv_count % 4]);
-          $display("recv_count: %d", recv_count);
-          error_count <= error_count + 1;
-        end
-      end
-      if (data_out_last) begin
-        state <= 1'b1;
-      end
-    end
-  end
-end
-
-
-initial begin
-  reset <= 1;
-  capture <= 0;
-  repeat (5000) @(posedge clk);
-  reset <= 0;
-  repeat (5000) @(posedge clk);
-  capture <= 1;
-  @(posedge clk);
-  capture <= 0;
-  repeat (5000) @(posedge clk);
-  data_out_ready <= 1;
-  repeat (50) @(posedge clk);
-  data_out_ready <= 0;
-  repeat (100) @(posedge clk);
-  data_out_ready <= 1;
-  repeat (10000) @(posedge clk);
-  capture <= 1;
-  repeat (1000) @(posedge clk);
-  capture <= 0;
-  repeat (1000) @(posedge clk);
-  data_out_ready <= 1;
-  repeat (100) @(posedge clk);
-  data_out_ready <= 0;
-  repeat (100) @(posedge clk);
-  data_out_ready <= 1;
-  repeat (500) @(posedge clk);
-  data_out_ready <= 0;
-  repeat (100) @(posedge clk);
-  data_out_ready <= 1;
-end
-endmodule
diff --git a/dds_test.srcs/sources_1/new/adc_axis_mux.sv b/dds_test.srcs/sources_1/new/adc_axis_mux.sv
deleted file mode 100644
index 37cd2ea..0000000
--- a/dds_test.srcs/sources_1/new/adc_axis_mux.sv
+++ /dev/null
@@ -1,31 +0,0 @@
-module adc_axis_mux (
-  input wire clk, reset,
-  input [127:0] afe_adc_data,
-  input afe_adc_valid,
-  output afe_adc_ready,
-
-  input [127:0] loopback_adc_data,
-  input loopback_adc_valid,
-  output loopback_adc_ready,
-
-  input sel,
-  output logic [127:0] adc_data,
-  output logic adc_valid,
-  input adc_ready
-);
-
-assign afe_adc_ready = adc_ready;
-assign loopback_adc_ready = adc_ready;
-
-always_ff @(posedge clk) begin
-  if (reset) begin
-    adc_data <= '0;
-    adc_valid <= 1'b0;
-  end else begin
-    if (adc_ready) begin
-      adc_valid <= sel ? loopback_adc_valid : afe_adc_valid;
-      adc_data <= sel ? loopback_adc_data : afe_adc_data;
-    end
-  end
-end
-endmodule
diff --git a/dds_test.srcs/sources_1/new/adc_axis_mux_wrapper.v b/dds_test.srcs/sources_1/new/adc_axis_mux_wrapper.v
deleted file mode 100644
index e30a635..0000000
--- a/dds_test.srcs/sources_1/new/adc_axis_mux_wrapper.v
+++ /dev/null
@@ -1,33 +0,0 @@
-module adc_axis_mux_wrapper (
-  input clk, reset_n,
-
-  input [127:0] afe_adc_tdata,
-  input afe_adc_tvalid,
-  output afe_adc_tready,
-
-  input [127:0] loopback_adc_tdata,
-  input loopback_adc_tvalid,
-  output loopback_adc_tready,
-
-  input sel,
-  output [127:0] adc_tdata,
-  output adc_tvalid,
-  input adc_tready
-);
-
-adc_axis_mux (
-  .clk(clk),
-  .reset(~reset_n),
-  .afe_adc_data(afe_adc_tdata),
-  .afe_adc_valid(afe_adc_tvalid),
-  .afe_adc_ready(afe_adc_tready),
-  .loopback_adc_data(loopback_adc_tdata),
-  .loopback_adc_valid(loopback_adc_tvalid),
-  .loopback_adc_ready(loopback_adc_tready),
-  .sel(sel),
-  .adc_data(adc_tdata),
-  .adc_valid(adc_tvalid),
-  .adc_ready(adc_tready)
-);
-
-endmodule
diff --git a/dds_test.srcs/sources_1/new/noise_event_tracker.sv b/dds_test.srcs/sources_1/new/noise_event_tracker.sv
deleted file mode 100644
index 971d600..0000000
--- a/dds_test.srcs/sources_1/new/noise_event_tracker.sv
+++ /dev/null
@@ -1,281 +0,0 @@
-// noise event tracker - Reed Foster
-// performs real-time compression of incoming noise signal
-// if samples are above some high threshold, then record the samples
-// once they dip below a low threshold, stop recording until they go above the
-// high threshold again.  for the first sample that exceeds the high threshold
-// after a period of low samples, also output a timestamp
-// (CLOCK_WIDTH bits) immediately following the sample.
-//
-// data format (LSB 1'bx is channel index)
-// sample: {sample[15:3], 1'bx, 1'b0, 1'bx} bit 2 1'bx is new_is_high
-// timestamp (4 successive transactions): {clock[i*14+:14], 1'b1, 1'bx} for i = 0..3
-// (assumes 56-bit CLOCK_WIDTH, will be different #transactions for
-// wider/narrower sample counters)
-
-module noise_event_tracker #(
-  parameter int BUFFER_DEPTH = 1024, // size will be BUFFER_DEPTH x AXI_MM_WIDTH
-  parameter int SAMPLE_WIDTH = 16,
-  parameter int AXI_MM_WIDTH = 128,
-  parameter int CLOCK_WIDTH = 42
-) (
-  input wire clk, reset,
-  Axis_If.Master_Full data_out, // collection of samples
-  Axis_If.Slave_Simple data_in_00, // two least significant bits of each sample will be trimmed off
-  Axis_If.Slave_Simple data_in_02,
-  Axis_If.Slave_Simple config_in // {start, stop, threshold_high, threshold_low}
-);
-
-// always accept transactions
-assign config_in.ready = 1'b1;
-
-Axis_If #(.DWIDTH(SAMPLE_WIDTH)) ch_00_disc_in ();
-Axis_If #(.DWIDTH(SAMPLE_WIDTH)) ch_02_disc_in ();
-Axis_If #(.DWIDTH(SAMPLE_WIDTH)) ch_00_disc_out ();
-Axis_If #(.DWIDTH(SAMPLE_WIDTH)) ch_02_disc_out ();
-Axis_If #(.DWIDTH(2*SAMPLE_WIDTH)) ch_00_config_in ();
-Axis_If #(.DWIDTH(2*SAMPLE_WIDTH)) ch_02_config_in ();
-
-// disc_in inputs
-assign ch_00_disc_in.valid = data_in_00.valid;
-assign ch_02_disc_in.valid = data_in_02.valid;
-assign data_in_00.ready = ch_00_disc_in.ready;
-assign data_in_02.ready = ch_02_disc_in.ready;
-assign ch_00_disc_in.data = {data_in_00.data[SAMPLE_WIDTH-1:1], 1'b0};
-assign ch_02_disc_in.data = {data_in_02.data[SAMPLE_WIDTH-1:1], 1'b1};
-
-// merge config; we'll use the same threshold for both channels
-assign ch_00_config_in.valid = config_in.valid;
-assign ch_02_config_in.valid = config_in.valid;
-assign ch_00_config_in.data = config_in.data[2*SAMPLE_WIDTH-1:0];
-assign ch_02_config_in.data = config_in.data[2*SAMPLE_WIDTH-1:0];
-
-// split up config vector
-logic config_in_start, config_in_stop;
-assign config_in_start = config_in.data[2*SAMPLE_WIDTH+1];
-assign config_in_stop = config_in.data[2*SAMPLE_WIDTH];
-
-//////////////////////////////////////////////////////
-// combine FIFO outputs into a single word
-//////////////////////////////////////////////////////
-
-logic fifo_select;
-logic [1:0] fifo_valid;
-logic [1:0][SAMPLE_WIDTH-1:0] fifo_out_data;
-assign fifo_valid = {ch_02_disc_out.valid, ch_00_disc_out.valid};
-assign fifo_out_data = {ch_02_disc_out.data, ch_00_disc_out.data};
-
-always_comb begin
-  if (ch_00_disc_out.valid) begin
-    fifo_select = 0;
-    ch_00_disc_out.ready = 1'b1;
-    ch_02_disc_out.ready = 1'b0;
-  end else begin
-    if (ch_02_disc_out.valid) begin
-      fifo_select = 1;
-      ch_00_disc_out.ready = 1'b0;
-      ch_02_disc_out.ready = 1'b1;
-    end else begin
-      // default to fifo 0, but don't actually enable either
-      fifo_select = 0;
-      ch_00_disc_out.ready = 1'b0;
-      ch_02_disc_out.ready = 1'b0;
-    end
-  end
-end
-
-sample_discriminator #(
-  .SAMPLE_WIDTH(SAMPLE_WIDTH),
-  .CLOCK_WIDTH(CLOCK_WIDTH)
-) sample_discriminator_ch_00 (
-  .clk,
-  .reset,
-  .data_in(ch_00_disc_in),
-  .data_out(ch_00_disc_out),
-  .config_in(ch_00_config_in)
-);
-
-sample_discriminator #(
-  .SAMPLE_WIDTH(SAMPLE_WIDTH),
-  .CLOCK_WIDTH(CLOCK_WIDTH)
-) sample_discriminator_ch_02 (
-  .clk,
-  .reset,
-  .data_in(ch_02_disc_in),
-  .data_out(ch_02_disc_out),
-  .config_in(ch_02_config_in)
-);
-
-//////////////////////////////////////////////////////
-// sample buffer and state machine
-//////////////////////////////////////////////////////
-// state machine and buffer signals
-enum {IDLE, CAPTURE, TRANSFER, POSTTRANSFER} state;
-logic [AXI_MM_WIDTH-1:0] buffer [BUFFER_DEPTH];
-logic [$clog2(BUFFER_DEPTH)-1:0] write_addr, read_addr, read_stop_addr, read_addr_d;
-logic [AXI_MM_WIDTH-1:0] data_out_word;
-logic [2:0] data_out_valid; // extra valid and last to match latency of BRAM
-assign data_out.valid = data_out_valid[1];
-// memory read/write bus have the same width (wider than sample width)
-// select appropriate subword range of input word when writing from FIFOs
-localparam int WORD_SIZE = 2**($clog2(SAMPLE_WIDTH));
-localparam int WORD_SELECT_BITS = $clog2(AXI_MM_WIDTH) - $clog2(WORD_SIZE);
-logic [WORD_SELECT_BITS-1:0] data_word_select;
-logic [AXI_MM_WIDTH-1:0] data_in_word;
-logic data_in_word_valid;
-always_ff @(posedge clk) begin
-  if (reset) begin
-    data_word_select <= '0;
-    data_in_word <= '0;
-    data_in_word_valid <= 1'b0;
-  end else begin
-    if (fifo_valid[fifo_select]) begin
-      // word will continuously update and only be read into sample buffer
-      // when a capture is started.
-      data_in_word[data_word_select*WORD_SIZE+:WORD_SIZE] <= fifo_out_data[fifo_select];
-      data_word_select <= data_word_select + 1'b1; // rolls over since AXI_MM_WIDTH is a power of 2
-    end
-    data_in_word_valid <= fifo_valid[fifo_select] && (data_word_select == 2**WORD_SELECT_BITS - 1);
-  end
-end
-
-// state machine
-always_ff @(posedge clk) begin
-  if (reset) begin
-    state <= IDLE;
-  end else begin
-    unique case (state)
-      // config_in.ready is held high, so whenever config_in.valid goes high,
-      // an AXI-stream transaction can take place
-      IDLE: if (config_in.valid && config_in_start) state <= CAPTURE;
-      CAPTURE: begin
-        if ((config_in.valid && config_in_stop)
-            || (data_in_word_valid && (write_addr == BUFFER_DEPTH - 1))) begin
-          state <= TRANSFER;
-        end
-      end
-      TRANSFER: if ((read_addr_d == read_stop_addr) && data_out.ready) state <= POSTTRANSFER;
-      POSTTRANSFER: if (data_out.last && data_out.valid && data_out.ready) state <= IDLE;
-    endcase
-  end
-end
-// sample buffer logic
-// let's actually make the data_out_valid to spec
-// will be a little bit of work, since we want to register the output (so
-// valid will have to be delayed appropriately), but valid shouldn't
-// depend on ready signal from DMA IP (according to spec).
-// buffer design
-always_ff @(posedge clk) begin
-  if (reset) begin
-    data_out_valid <= '0;
-    data_out.last <= '0;
-    read_addr <= '0;
-    read_addr_d <= '0;
-    write_addr <= '0;
-  end else begin
-    unique case (state)
-      IDLE: begin
-        data_out_valid <= '0;
-        data_out.last <= '0;
-        read_addr <= '0;
-        read_addr_d <= '0;
-        write_addr <= '0;
-        read_stop_addr <= '0;
-      end
-      CAPTURE: begin
-        if (data_in_word_valid) begin
-          buffer[write_addr] <= data_in_word;
-          write_addr <= write_addr + 1'b1;
-          read_stop_addr <= write_addr;
-        end
-      end
-      TRANSFER: begin
-        if (data_out.ready || !data_out.valid) begin // as long as output is ready, increment address
-          if (read_addr != read_stop_addr) begin
-            read_addr <= read_addr + 1'b1;
-            data_out_valid <= {data_out_valid[0], 1'b1};
-          end
-          if (read_addr_d == read_stop_addr) begin
-            data_out_valid <= {data_out_valid[0], 1'b0};
-            data_out.last <= 1'b1;
-          end
-          data_out_word <= buffer[read_addr];
-          data_out.data <= data_out_word;
-          read_addr_d <= read_addr;
-        end
-      end
-      POSTTRANSFER: begin
-        // handle last signal
-        if (data_out.ready) begin
-          data_out.last <= 1'b0;
-          data_out_valid <= {data_out_valid[0], 1'b0};
-        end
-      end
-    endcase
-  end
-end
-
-endmodule
-
-module noise_event_tracker_sv_wrapper #(
-  parameter int BUFFER_DEPTH = 1024,
-  parameter int SAMPLE_WIDTH = 16,
-  parameter int AXI_MM_WIDTH = 128,
-  parameter int CLOCK_WIDTH = 42
-) (
-  input wire clk, reset,
-
-  output [AXI_MM_WIDTH-1:0] data_out,
-  output data_out_valid,
-  output data_out_last,
-  input data_out_ready,
-
-  input [SAMPLE_WIDTH-1:0] data_in_00,
-  input data_in_00_valid,
-  output data_in_00_ready,
-
-  input [SAMPLE_WIDTH-1:0] data_in_02,
-  input data_in_02_valid,
-  output data_in_02_ready,
-
-  input [2+2*SAMPLE_WIDTH-1:0] config_in,
-  input config_in_valid,
-  output config_in_ready
-);
-
-Axis_If #(.DWIDTH(SAMPLE_WIDTH)) data_in_00_if();
-Axis_If #(.DWIDTH(SAMPLE_WIDTH)) data_in_02_if();
-Axis_If #(.DWIDTH(AXI_MM_WIDTH)) data_out_if();
-Axis_If #(.DWIDTH(2+2*SAMPLE_WIDTH)) config_in_if();
-
-noise_event_tracker #(
-  .BUFFER_DEPTH(BUFFER_DEPTH),
-  .SAMPLE_WIDTH(SAMPLE_WIDTH),
-  .AXI_MM_WIDTH(AXI_MM_WIDTH),
-  .CLOCK_WIDTH(CLOCK_WIDTH)
-) noise_event_tracker_i (
-  .clk,
-  .reset,
-  .data_out(data_out_if),
-  .data_in_00(data_in_00_if),
-  .data_in_02(data_in_02_if),
-  .config_in(config_in_if)
-);
-
-assign data_out = data_out_if.data;
-assign data_out_valid = data_out_if.valid;
-assign data_out_last = data_out_if.last;
-assign data_out_if.ready = data_out_ready;
-
-assign data_in_00_if.data = data_in_00;
-assign data_in_00_if.valid = data_in_00_valid;
-assign data_in_00_ready = data_in_00_if.ready;
-
-assign data_in_02_if.data = data_in_02;
-assign data_in_02_if.valid = data_in_02_valid;
-assign data_in_02_ready = data_in_02_if.ready;
-
-assign config_in_if.data = config_in;
-assign config_in_if.valid = config_in_valid;
-assign config_in_ready = config_in_if.ready;
-
-endmodule
diff --git a/dds_test.srcs/sources_1/new/noise_event_tracker_wrapper.v b/dds_test.srcs/sources_1/new/noise_event_tracker_wrapper.v
deleted file mode 100644
index c76cb2f..0000000
--- a/dds_test.srcs/sources_1/new/noise_event_tracker_wrapper.v
+++ /dev/null
@@ -1,47 +0,0 @@
-module noise_event_tracker_wrapper (
-  input wire clk, reset_n,
-
-  output [127:0] m_axis_tdata,
-  output [15:0] m_axis_tkeep,
-  output m_axis_tvalid, m_axis_tlast,
-  input m_axis_tready,
-
-  input [15:0] s00_axis_tdata,
-  input s00_axis_tvalid,
-  output s00_axis_tready,
-
-  input [15:0] s02_axis_tdata,
-  input s02_axis_tvalid,
-  output s02_axis_tready,
-
-  input [63:0] s_axis_config_tdata,
-  input s_axis_config_tvalid,
-  output s_axis_config_tready
-);
-
-assign m_axis_tkeep = 16'hffff;
-
-noise_event_tracker_sv_wrapper #(
-  .BUFFER_DEPTH(32768),
-  .SAMPLE_WIDTH(16),
-  .AXI_MM_WIDTH(128),
-  .CLOCK_WIDTH(42)
-) noise_event_tracker_sv_wrapper_i (
-  .clk(clk),
-  .reset(~reset_n),
-  .data_out(m_axis_tdata),
-  .data_out_valid(m_axis_tvalid),
-  .data_out_ready(m_axis_tready),
-  .data_out_last(m_axis_tlast),
-  .data_in_00(s00_axis_tdata),
-  .data_in_00_valid(s00_axis_tvalid),
-  .data_in_00_ready(s00_axis_tready),
-  .data_in_02(s02_axis_tdata),
-  .data_in_02_valid(s02_axis_tvalid),
-  .data_in_02_ready(s02_axis_tready),
-  .config_in(s_axis_config_tdata[33:0]),
-  .config_in_valid(s_axis_config_tvalid),
-  .config_in_ready(s_axis_config_tready)
-);
-
-endmodule
diff --git a/dds_test.srcs/sources_1/new/sample_buffer.sv b/dds_test.srcs/sources_1/new/sample_buffer.sv
deleted file mode 100644
index 910af47..0000000
--- a/dds_test.srcs/sources_1/new/sample_buffer.sv
+++ /dev/null
@@ -1,172 +0,0 @@
-// sample buffer
-module sample_buffer # (
-  parameter int BUFFER_DEPTH = 1024,
-  parameter int PARALLEL_SAMPLES = 4,
-  parameter int INPUT_SAMPLE_WIDTH = 18,
-  parameter int OUTPUT_SAMPLE_WIDTH = 16,
-  parameter int AXI_MM_WIDTH = 128
-)(
-  input wire clk, reset,
-  Axis_If.Master_Full data_out, // packed pair of samples
-  Axis_If.Slave_Simple data_in,
-  input wire capture, // trigger capture of samples in buffer
-  input wire pinc_change, // trigger capture when pinc of the DDS is changed
-  input wire trigger_select // choose which trigger is active (0: capture, 1: pinc_change)
-);
-
-assign data_in.ready = 1'b1; // always accept data
-
-// trigger logic
-enum {IDLE, CAPTURE, TRANSFER} state;
-logic capture_d, pinc_change_d;
-logic triggered;
-assign triggered = trigger_select ? (pinc_change && !pinc_change_d) : (capture && !capture_d);
-
-// buffer
-logic [PARALLEL_SAMPLES*OUTPUT_SAMPLE_WIDTH-1:0] buffer [BUFFER_DEPTH];
-logic [$clog2(BUFFER_DEPTH)-1:0] write_addr, read_addr;
-logic [PARALLEL_SAMPLES*OUTPUT_SAMPLE_WIDTH-1:0] buffer_data_in;
-logic [PARALLEL_SAMPLES*OUTPUT_SAMPLE_WIDTH-1:0] data_out_full_width;
-logic data_out_valid;
-logic data_out_last;
-// handling of mismatched read/write widths
-localparam bit UNEQUAL_RW_WIDTH = PARALLEL_SAMPLES*OUTPUT_SAMPLE_WIDTH != AXI_MM_WIDTH;
-localparam int WORD_SELECT_BITS = $clog2(PARALLEL_SAMPLES*OUTPUT_SAMPLE_WIDTH)-$clog2(AXI_MM_WIDTH);
-localparam int WORD_SELECT_MAX = 2**WORD_SELECT_BITS - 1;
-logic [WORD_SELECT_BITS-1:0] read_word_select, read_word_select_d;
-
-// state transitions
-always @(posedge clk) begin
-  if (reset) begin
-    state <= IDLE;
-  end else begin
-    unique case (state)
-      IDLE: if (triggered) state <= CAPTURE;
-      CAPTURE: if (write_addr == {$clog2(BUFFER_DEPTH){1'b1}}) state <= TRANSFER;
-      TRANSFER: if (data_out_last) state <= IDLE;
-    endcase
-  end
-end
-
-always @(posedge clk) begin
-  capture_d <= capture;
-  pinc_change_d <= pinc_change;
-  if (reset) begin
-    write_addr <= '0;
-    read_addr <= '0;
-    read_word_select <= '0;
-    read_word_select_d <= '0;
-    data_out_valid <= '0;
-    data_out_last <= 1'b0;
-  end else begin
-    unique case (state)
-      IDLE: begin
-        write_addr <= '0;
-        read_addr <= '0;
-        read_word_select <= '0;
-        read_word_select_d <= '0;
-        data_out_valid <= 1'b0;
-        data_out.valid <= 1'b0;
-        data_out_last <= 1'b0;
-        data_out.last <= 1'b0;
-      end
-      CAPTURE: begin
-        if (data_in.valid) begin
-          buffer[write_addr] <= buffer_data_in;
-          write_addr <= write_addr + 1'b1;
-        end
-      end
-      TRANSFER: begin
-        if (data_out.ready) begin
-          data_out_valid <= 1'b1;
-          data_out.valid <= data_out_valid;
-          data_out.last <= data_out_last;
-          data_out_full_width <= buffer[read_addr];
-          read_word_select_d <= read_word_select;
-          if (UNEQUAL_RW_WIDTH) begin
-            data_out.data <= data_out_full_width[AXI_MM_WIDTH*read_word_select_d+:AXI_MM_WIDTH];
-            if (read_word_select == WORD_SELECT_MAX) begin
-              read_word_select <= '0;
-              if (read_addr == {$clog2(BUFFER_DEPTH){1'b1}}) begin
-                data_out_last <= 1'b1;
-                read_addr <= '0;
-              end else begin
-                read_addr <= read_addr + 1'b1;
-              end
-            end else begin
-              read_word_select <= read_word_select + 1'b1;
-            end
-          end else begin
-            data_out.data <= data_out_full_width;
-            if (read_addr == {$clog2(BUFFER_DEPTH){1'b1}}) begin
-              data_out_last <= 1'b1;
-              read_addr <= '0;
-            end else begin
-              read_addr <= read_addr + 1'b1;
-            end
-          end
-        end
-      end
-    endcase
-  end
-end
-
-// buffer input and output
-always @(posedge clk) begin
-  for (int i = 0; i < PARALLEL_SAMPLES; i++) begin
-    // only take OUTPUT_SAMPLE_WIDTH MSBs of each parallel sample of input data
-    buffer_data_in[OUTPUT_SAMPLE_WIDTH*i+:OUTPUT_SAMPLE_WIDTH] <= data_in.data[(i+1)*INPUT_SAMPLE_WIDTH-OUTPUT_SAMPLE_WIDTH+:OUTPUT_SAMPLE_WIDTH];
-  end
-end
-
-endmodule
-
-// wrapper so this can be instantiated in .v file
-module sample_buffer_sv_wrapper #(
-  parameter int BUFFER_DEPTH = 1024,
-  parameter int PARALLEL_SAMPLES = 4,
-  parameter int INPUT_SAMPLE_WIDTH = 18,
-  parameter int OUTPUT_SAMPLE_WIDTH = 16,
-  parameter int AXI_MM_WIDTH = 128
-) (
-  input wire clk, reset,
-  output [AXI_MM_WIDTH-1:0] data_out,
-  output data_out_valid, data_out_last,
-  input data_out_ready,
-  input [INPUT_SAMPLE_WIDTH*PARALLEL_SAMPLES:0] data_in,
-  input data_in_valid,
-  output data_in_ready,
-  input wire capture,
-  input wire pinc_change,
-  input wire trigger_select
-);
-
-Axis_If #(.DWIDTH(INPUT_SAMPLE_WIDTH*PARALLEL_SAMPLES)) data_in_if();
-Axis_If #(.DWIDTH(AXI_MM_WIDTH)) data_out_if();
-
-sample_buffer #(
-  .BUFFER_DEPTH(BUFFER_DEPTH),
-  .PARALLEL_SAMPLES(PARALLEL_SAMPLES),
-  .INPUT_SAMPLE_WIDTH(INPUT_SAMPLE_WIDTH),
-  .OUTPUT_SAMPLE_WIDTH(OUTPUT_SAMPLE_WIDTH),
-  .AXI_MM_WIDTH(AXI_MM_WIDTH)
-) buffer_i (
-  .clk,
-  .reset,
-  .data_out(data_out_if),
-  .data_in(data_in_if),
-  .capture,
-  .pinc_change,
-  .trigger_select
-);
-
-assign data_out = data_out_if.data;
-assign data_out_valid = data_out_if.valid;
-assign data_out_last = data_out_if.last;
-assign data_out_if.ready = data_out_ready;
-
-assign data_in_if.data = data_in;
-assign data_in_if.valid = data_in_valid;
-assign data_in_ready = data_in_if.ready;
-
-endmodule
diff --git a/dds_test.srcs/sources_1/new/sample_buffer_wrapper.v b/dds_test.srcs/sources_1/new/sample_buffer_wrapper.v
deleted file mode 100644
index 5bbd5b4..0000000
--- a/dds_test.srcs/sources_1/new/sample_buffer_wrapper.v
+++ /dev/null
@@ -1,38 +0,0 @@
-module sample_buffer_wrapper (
-  input wire clk, reset_n,
-  output [127:0] data_out_tdata,
-  output data_out_tvalid, data_out_tlast,
-  input data_out_tready,
-  output [15:0] data_out_tkeep,
-  input [1023:0] data_in_tdata,
-  input data_in_tvalid,
-  output data_in_tready,
-  input wire capture,
-  input wire pinc_change,
-  input wire trigger_select
-);
-
-assign data_out_tkeep = 16'hffff;
-
-sample_buffer_sv_wrapper #(
-  .BUFFER_DEPTH(16384),
-  .PARALLEL_SAMPLES(64),
-  .INPUT_SAMPLE_WIDTH(16),
-  .OUTPUT_SAMPLE_WIDTH(16),
-  .AXI_MM_WIDTH(128)
-) sample_buffer_sv_wrapper_i (
-  .clk(clk),
-  .reset(~reset_n),
-  .data_out(data_out_tdata),
-  .data_out_valid(data_out_tvalid),
-  .data_out_last(data_out_tlast),
-  .data_out_ready(data_out_tready),
-  .data_in(data_in_tdata),
-  .data_in_valid(data_in_tvalid),
-  .data_in_ready(data_in_tready),
-  .capture(capture),
-  .pinc_change(pinc_change),
-  .trigger_select(trigger_select)
-);
-
-endmodule
diff --git a/dds_test.srcs/sources_1/new/sample_interleaver.v b/dds_test.srcs/sources_1/new/sample_interleaver.v
deleted file mode 100644
index 2ea4d4b..0000000
--- a/dds_test.srcs/sources_1/new/sample_interleaver.v
+++ /dev/null
@@ -1,15 +0,0 @@
-module sample_interleaver (
-  input [255:0] adc_data,
-  input [255:0] dac_feedthrough,
-  output [511:0] interleaved_data
-);
-
-genvar i;
-generate
-  for (i = 0; i < 16; i = i + 1) begin
-    assign interleaved_data[32*i+:16] = adc_data[16*i+:16];
-    assign interleaved_data[32*i+16+:16] = dac_feedthrough[16*i+:16];
-  end
-endgenerate
-
-endmodule
diff --git a/src/rtl/adc_axis_mux.sv b/src/rtl/adc_axis_mux.sv
deleted file mode 120000
index a3f0c19..0000000
--- a/src/rtl/adc_axis_mux.sv
+++ /dev/null
@@ -1 +0,0 @@
-../../dds_test.srcs/sources_1/new/adc_axis_mux.sv
\ No newline at end of file
diff --git a/src/rtl/adc_axis_mux_wrapper.v b/src/rtl/adc_axis_mux_wrapper.v
deleted file mode 120000
index 5ee175d..0000000
--- a/src/rtl/adc_axis_mux_wrapper.v
+++ /dev/null
@@ -1 +0,0 @@
-../../dds_test.srcs/sources_1/new/adc_axis_mux_wrapper.v
\ No newline at end of file
diff --git a/src/rtl/noise_event_tracker.sv b/src/rtl/noise_event_tracker.sv
deleted file mode 120000
index 5d83098..0000000
--- a/src/rtl/noise_event_tracker.sv
+++ /dev/null
@@ -1 +0,0 @@
-../../dds_test.srcs/sources_1/new/noise_event_tracker.sv
\ No newline at end of file
diff --git a/src/rtl/noise_event_tracker_wrapper.v b/src/rtl/noise_event_tracker_wrapper.v
deleted file mode 120000
index f521b7b..0000000
--- a/src/rtl/noise_event_tracker_wrapper.v
+++ /dev/null
@@ -1 +0,0 @@
-../../dds_test.srcs/sources_1/new/noise_event_tracker_wrapper.v
\ No newline at end of file
diff --git a/src/rtl/sample_buffer.sv b/src/rtl/sample_buffer.sv
deleted file mode 120000
index 7e6fbf8..0000000
--- a/src/rtl/sample_buffer.sv
+++ /dev/null
@@ -1 +0,0 @@
-../../dds_test.srcs/sources_1/new/sample_buffer.sv
\ No newline at end of file
diff --git a/src/rtl/sample_buffer_wrapper.v b/src/rtl/sample_buffer_wrapper.v
deleted file mode 120000
index 236e382..0000000
--- a/src/rtl/sample_buffer_wrapper.v
+++ /dev/null
@@ -1 +0,0 @@
-../../dds_test.srcs/sources_1/new/sample_buffer_wrapper.v
\ No newline at end of file
diff --git a/src/rtl/sample_interleaver.v b/src/rtl/sample_interleaver.v
deleted file mode 120000
index 4db916a..0000000
--- a/src/rtl/sample_interleaver.v
+++ /dev/null
@@ -1 +0,0 @@
-../../dds_test.srcs/sources_1/new/sample_interleaver.v
\ No newline at end of file
diff --git a/src/verif/noise_event_tracker_test.sv b/src/verif/noise_event_tracker_test.sv
deleted file mode 120000
index dc832ed..0000000
--- a/src/verif/noise_event_tracker_test.sv
+++ /dev/null
@@ -1 +0,0 @@
-../../dds_test.srcs/sim_1/new/noise_event_tracker_test.sv
\ No newline at end of file
diff --git a/src/verif/sample_buffer_test.sv b/src/verif/sample_buffer_test.sv
deleted file mode 120000
index d6501df..0000000
--- a/src/verif/sample_buffer_test.sv
+++ /dev/null
@@ -1 +0,0 @@
-../../dds_test.srcs/sim_1/new/sample_buffer_test.sv
\ No newline at end of file