diff --git a/buffer_bank_test_behav.wcfg b/buffer_bank_test_behav.wcfg
index f357e81..b94c0cc 100644
--- a/buffer_bank_test_behav.wcfg
+++ b/buffer_bank_test_behav.wcfg
@@ -11,181 +11,185 @@
-
-
-
+
+
+
-
+
-
-
- clk
- clk
-
-
- reset
- reset
-
-
- start
- start
-
-
- stop
- stop
-
-
- full
- full
-
-
- sample_count[31:0]
- sample_count[31:0]
-
-
- CLK_RATE_HZ[31:0]
- CLK_RATE_HZ[31:0]
-
-
- dut
+
+
+ test
label
-
-
- clk
- clk
-
-
- reset
- reset
-
-
- start
- start
-
-
- stop
- stop
-
-
- full
- full
-
-
- state[31:0]
- state[31:0]
-
-
- buffer[0:1023][31:0]
- buffer[0:1023][31:0]
-
-
- write_addr[9:0]
- write_addr[9:0]
-
-
- read_addr[9:0]
- read_addr[9:0]
-
-
- read_stop_addr[9:0]
- read_stop_addr[9:0]
-
-
- read_addr_d[2:0][9:0]
- read_addr_d[2:0][9:0]
-
-
-
- data_out_d[3:0][31:0]
- data_out_d[3:0][31:0]
-
-
-
- data_out_valid[3:0]
- data_out_valid[3:0]
-
-
- buffer_has_data
- buffer_has_data
-
-
- data_out_last
- data_out_last
-
-
- BUFFER_DEPTH[31:0]
- BUFFER_DEPTH[31:0]
-
-
- PARALLEL_SAMPLES[31:0]
- PARALLEL_SAMPLES[31:0]
-
-
- SAMPLE_WIDTH[31:0]
- SAMPLE_WIDTH[31:0]
-
-
+
+ clk
+ clk
+
+
+ reset
+ reset
+
+
+ error_count[31:0]
+ error_count[31:0]
+
+
+ start
+ start
+
+
+ stop
+ stop
+
+
+ full
+ full
+
+
+ sample_count[31:0]
+ sample_count[31:0]
+
+
+ CLK_RATE_HZ[31:0]
+ CLK_RATE_HZ[31:0]
+
+
+
data_in
label
-
-
- data[0:0][15:0]
- data[0:0][15:0]
-
-
- ready[0:0]
- ready[0:0]
-
-
-
- valid[0:0]
- valid[0:0]
-
-
-
- last[0:0]
- last[0:0]
-
-
- DWIDTH[31:0]
- DWIDTH[31:0]
-
-
- PARALLEL_CHANNELS[31:0]
- PARALLEL_CHANNELS[31:0]
-
-
+
+ data[15:0]
+ data[15:0]
+
+
+ ready
+ ready
+
+
+ valid
+ valid
+
+
+ last
+ last
+
+
+ ok
+ ok
+
+
+ DWIDTH[31:0]
+ DWIDTH[31:0]
+
+
+
data_out
label
-
-
- data[0:0][15:0]
- data[0:0][15:0]
-
-
-
- ready[0:0]
- ready[0:0]
-
-
-
- valid[0:0]
- valid[0:0]
-
-
-
- last[0:0]
- last[0:0]
-
-
-
- DWIDTH[31:0]
- DWIDTH[31:0]
-
-
- PARALLEL_CHANNELS[31:0]
- PARALLEL_CHANNELS[31:0]
+
+ data[15:0]
+ data[15:0]
+
+
+ ready
+ ready
+
+
+ valid
+ valid
+
+
+ last
+ last
+
+
+ ok
+ ok
+
+
+ DWIDTH[31:0]
+ DWIDTH[31:0]
+
+
+
+ dut
+ label
+
+ clk
+ clk
+
+
+ reset
+ reset
+
+
+ start
+ start
+
+
+ stop
+ stop
+
+
+ full
+ full
+
+
+ first
+ first
+
+
+ state[31:0]
+ state[31:0]
+
+
+ buffer[0:1023][31:0]
+ buffer[0:1023][31:0]
+
+
+ write_addr[9:0]
+ write_addr[9:0]
+
+
+ read_addr[9:0]
+ read_addr[9:0]
+
+
+ read_addr_d[1:0][9:0]
+ read_addr_d[1:0][9:0]
+
+
+ data_out_d[3:0][31:0]
+ data_out_d[3:0][31:0]
+
+
+ data_out_valid[3:0]
+ data_out_valid[3:0]
+
+
+ data_out_last[3:0]
+ data_out_last[3:0]
+
+
+ buffer_has_data
+ buffer_has_data
+
+
+ readout_begun
+ readout_begun
+
+
+ BUFFER_DEPTH[31:0]
+ BUFFER_DEPTH[31:0]
+
+
+ PARALLEL_SAMPLES[31:0]
+ PARALLEL_SAMPLES[31:0]
+
+
+ SAMPLE_WIDTH[31:0]
+ SAMPLE_WIDTH[31:0]
+
diff --git a/dds_test.srcs/sim_1/new/axis_width_converter_test.sv b/dds_test.srcs/sim_1/new/axis_width_converter_test.sv
index d7acacb..465a562 100644
--- a/dds_test.srcs/sim_1/new/axis_width_converter_test.sv
+++ b/dds_test.srcs/sim_1/new/axis_width_converter_test.sv
@@ -6,7 +6,7 @@ logic clk = 0;
localparam CLK_RATE_HZ = 100_000_000;
always #(0.5s/CLK_RATE_HZ) clk = ~clk;
-int error_count;
+int error_count = 0;
localparam int DWIDTH_DOWN_IN = 256;
localparam int DWIDTH_UP_IN = 16;
diff --git a/dds_test.srcs/sim_1/new/banked_sample_buffer_test.sv b/dds_test.srcs/sim_1/new/banked_sample_buffer_test.sv
index 1f2950b..1ea397f 100644
--- a/dds_test.srcs/sim_1/new/banked_sample_buffer_test.sv
+++ b/dds_test.srcs/sim_1/new/banked_sample_buffer_test.sv
@@ -5,12 +5,14 @@ logic clk = 0;
localparam CLK_RATE_HZ = 100_000_000;
always #(0.5s/CLK_RATE_HZ) clk = ~clk;
+logic reset;
+
+int error_count = 0;
+
localparam int N_CHANNELS = 8;
localparam int PARALLEL_SAMPLES = 1;
localparam int SAMPLE_WIDTH = 16;
-logic reset;
-
logic start, stop;
logic [2:0] banking_mode;
@@ -267,6 +269,8 @@ always #(0.5s/CLK_RATE_HZ) clk = ~clk;
logic reset;
+int error_count = 0;
+
logic start, stop;
logic full;
@@ -291,6 +295,7 @@ int sample_count;
logic [15:0] data_sent [$];
logic [15:0] data_received [$];
+// send data to DUT and save data that was sent/received
always @(posedge clk) begin
if (reset) begin
sample_count <= 0;
@@ -301,7 +306,7 @@ always @(posedge clk) begin
sample_count <= sample_count + 1;
data_in.data <= $urandom_range(1<<16);
end
- // save data that was sent
+ // save data that was sent/received
if (data_in.valid) begin
data_sent.push_front(data_in.data);
end
@@ -320,40 +325,49 @@ task send_samples(input int n_samples, input int delay);
end
endtask
-task do_readout(input bit wait_for_last);
+task automatic do_readout(input bit rand_ready, input int timeout);
+ int cycle_count;
+ cycle_count = 0;
data_out.ready <= 1'b0;
stop <= 1'b1;
@(posedge clk);
stop <= 1'b0;
+ // wait a bit before actually doing the readout
repeat (500) @(posedge clk);
data_out.ready <= 1'b1;
- repeat ($urandom_range(2,4)) @(posedge clk);
- data_out.ready <= 1'b0;
- repeat ($urandom_range(1,3)) @(posedge clk);
- data_out.ready <= 1'b1;
- if (wait_for_last) begin
- while (!data_out.last) @(posedge clk);
- end else begin
- repeat (500) @(posedge clk);
+ // give up after timeout clock cycles if last is not achieved
+ while ((!(data_out.last & data_out.ok)) & (cycle_count < timeout)) begin
+ @(posedge clk);
+ cycle_count = cycle_count + 1;
+ if (rand_ready) begin
+ data_out.ready <= $urandom() & 1'b1;
+ end
end
@(posedge clk);
data_out.ready <= 1'b0;
endtask
+// check that the DUT correctly saved everything
task check_results();
+ // pop first sample received since it is intended to be overwritten in
+ // multibank buffer
+ data_received.pop_back();
$display("data_sent.size() = %0d", data_sent.size());
$display("data_received.size() = %0d", data_received.size());
if ((data_sent.size() + 1) != data_received.size()) begin
$warning("mismatch in amount of sent/received data");
+ error_count = error_count + 1;
end
if (data_received[$] != data_sent.size()) begin
$warning("incorrect sample count reported by buffer");
+ error_count = error_count + 1;
end
data_received.pop_back(); // remove sample count
while (data_sent.size() > 0 && data_received.size() > 0) begin
// data from channel 0 can be reordered with data from channel 2
if (data_sent[$] != data_received[$]) begin
$warning("data mismatch error (received %x, sent %x)", data_received[$], data_sent[$]);
+ error_count = error_count + 1;
end
data_sent.pop_back();
data_received.pop_back();
@@ -374,9 +388,11 @@ initial begin
start <= 1'b0;
repeat (100) @(posedge clk);
// send samples
- send_samples(128, 3);
+ data_in.send_samples(clk, 32, 1'b1, 1'b1);
+ data_in.send_samples(clk, 64, 1'b0, 1'b1);
+ data_in.send_samples(clk, 32, 1'b1, 1'b1);
repeat (50) @(posedge clk);
- do_readout(1'b1);
+ do_readout(1'b1, 100000);
$display("######################################################");
$display("# checking results for test with a few samples #");
$display("######################################################");
@@ -390,9 +406,9 @@ initial begin
start <= 1'b0;
repeat (100) @(posedge clk);
// send samples
- send_samples(1, 4);
+ data_in.send_samples(clk, 1, 1'b0, 1'b1);
repeat (50) @(posedge clk);
- do_readout(1'b0); // don't wait for last signal
+ do_readout(1'b1, 1000);
$display("######################################################");
$display("# checking results for test with one sample #");
$display("######################################################");
@@ -406,7 +422,7 @@ initial begin
repeat (100) @(posedge clk);
// don't send samples
repeat (50) @(posedge clk);
- do_readout(1'b0); // don't wait for last signal
+ do_readout(1'b1, 1000);
$display("######################################################");
$display("# checking results for test with no samples #");
$display("######################################################");
@@ -419,14 +435,26 @@ initial begin
start <= 1'b0;
repeat (100) @(posedge clk);
// send samples
- send_samples(1024, 1);
+ data_in.send_samples(clk, 256, 1'b1, 1'b1);
+ data_in.send_samples(clk, 512, 1'b0, 1'b1);
+ data_in.send_samples(clk, 256, 1'b1, 1'b1);
repeat (50) @(posedge clk);
- do_readout(1'b1);
+ do_readout(1'b1, 100000);
$display("######################################################");
$display("# checking results for test with 1024 samples #");
+ $display("# (full buffer) #");
$display("######################################################");
check_results();
repeat (500) @(posedge clk);
+
+ $display("#################################################");
+ if (error_count == 0) begin
+ $display("# finished with zero errors");
+ end else begin
+ $error("# finished with %0d errors", error_count);
+ $display("#################################################");
+ end
+ $display("#################################################");
$finish;
end
diff --git a/dds_test.srcs/sim_1/new/sample_discriminator_test.sv b/dds_test.srcs/sim_1/new/sample_discriminator_test.sv
index 7276f5e..b86ae65 100644
--- a/dds_test.srcs/sim_1/new/sample_discriminator_test.sv
+++ b/dds_test.srcs/sim_1/new/sample_discriminator_test.sv
@@ -7,6 +7,8 @@ always #(0.5s/CLK_RATE_HZ) clk = ~clk;
logic reset;
+int error_count = 0;
+
localparam int N_CHANNELS = 2;
localparam int SAMPLE_WIDTH = 16;
localparam int PARALLEL_SAMPLES = 4;
@@ -50,6 +52,7 @@ logic [SAMPLE_INDEX_WIDTH+CLOCK_WIDTH-1:0] timestamps_received [N_CHANNELS][$];
logic [N_CHANNELS-1:0][SAMPLE_WIDTH-1:0] data_range_low, data_range_high;
+// save data that was sent to DUT
always @(posedge clk) begin
if (reset) begin
data_in.data <= '0;
@@ -71,42 +74,14 @@ always @(posedge clk) begin
end
end
+// always accept data, which is the expected behavior of the sample buffer
+// that will be connected to the sample discriminator
assign data_out.ready = '1;
assign timestamps_out.ready = '1;
-task send_samples(input int n_samples, input bit rand_arrivals);
- int samples_sent [N_CHANNELS];
- logic [N_CHANNELS-1:0] done;
- if (rand_arrivals) begin
- // reset
- done = '0;
- for (int i = 0; i < N_CHANNELS; i++) begin
- samples_sent[i] = 0;
- end
- while (~done) begin
- for (int i = 0; i < N_CHANNELS; i++) begin
- if (data_in.valid[i]) begin
- if (samples_sent[i] == n_samples - 1) begin
- done[i] = 1'b1;
- end else begin
- samples_sent[i] = samples_sent[i] + 1'b1;
- end
- end
- end
- data_in.valid <= $urandom_range((1< 0) begin
if (any_above_high(data_sent[i][$], threshold_high[i])) begin
if (!is_high[i]) begin
@@ -155,10 +134,12 @@ task check_results (
if (timestamps_received[i].size() > 0) begin
if (timestamps_received[i][$] != {timer[i], sample_index[i]}) begin
$warning("mismatched timestamp: got %x, expected %x", timestamps_received[i][$], {timer[i], sample_index[i]});
+ error_count = error_count + 1;
end
timestamps_received[i].pop_back();
end else begin
$warning("expected a timestamp (with value %x), but no more timestamps left", {timer[i], sample_index[i]});
+ error_count = error_count + 1;
end
end
is_high[i] = 1'b1;
@@ -168,6 +149,7 @@ task check_results (
if (is_high[i]) begin
if (data_sent[i][$] != data_received[i][$]) begin
$warning("mismatched data: got %x, expected %x", data_received[i][$], data_sent[i][$]);
+ error_count = error_count + 1;
end
data_received[i].pop_back();
sample_index[i] = sample_index[i] + 1'b1;
@@ -212,12 +194,13 @@ initial begin
repeat (50) @(posedge clk);
// send a bunch of data with discrimination disabled
- send_samples(10, 1);
+ data_in.send_samples(clk, 10, 1'b1, 1'b1);
repeat (50) @(posedge clk);
- send_samples(10, 0);
+ data_in.send_samples(clk, 10, 1'b0, 1'b1);
repeat (50) @(posedge clk);
$display("######################################################");
$display("# testing run with all data above thresholds #");
+ $display("# first sample will be zero #");
$display("######################################################");
check_results(threshold_low, threshold_high, timer, sample_index, is_high);
@@ -231,9 +214,9 @@ initial begin
@(posedge clk);
config_in.valid <= 1'b0;
repeat (50) @(posedge clk);
- send_samples(100, 1);
+ data_in.send_samples(clk, 100, 1'b1, 1'b1);
repeat (50) @(posedge clk);
- send_samples(100, 0);
+ data_in.send_samples(clk, 100, 1'b0, 1'b1);
repeat (50) @(posedge clk);
$display("######################################################");
$display("# testing run with channel 0 straddling thresholds #");
@@ -252,9 +235,9 @@ initial begin
@(posedge clk);
config_in.valid <= 1'b0;
repeat (50) @(posedge clk);
- send_samples(400, 1);
+ data_in.send_samples(clk, 400, 1'b1, 1'b1);
repeat (50) @(posedge clk);
- send_samples(400, 0);
+ data_in.send_samples(clk, 400, 1'b0, 1'b1);
repeat (50) @(posedge clk);
$display("######################################################");
$display("# testing run with all data below thresholds #");
@@ -272,9 +255,9 @@ initial begin
@(posedge clk);
config_in.valid <= 1'b0;
repeat (50) @(posedge clk);
- send_samples(400, 1);
+ data_in.send_samples(clk, 400, 1'b1, 1'b1);
repeat (50) @(posedge clk);
- send_samples(400, 0);
+ data_in.send_samples(clk, 400, 1'b0, 1'b1);
repeat (50) @(posedge clk);
$display("######################################################");
$display("# testing run with both channels straddling #");
@@ -282,6 +265,14 @@ initial begin
$display("######################################################");
check_results(threshold_low, threshold_high, timer, sample_index, is_high);
+ $display("#################################################");
+ if (error_count == 0) begin
+ $display("# finished with zero errors");
+ end else begin
+ $error("# finished with %0d errors", error_count);
+ $display("#################################################");
+ end
+ $display("#################################################");
$finish;
end
diff --git a/dds_test.srcs/sources_1/new/axis.sv b/dds_test.srcs/sources_1/new/axis.sv
index ab8267e..800d45c 100644
--- a/dds_test.srcs/sources_1/new/axis.sv
+++ b/dds_test.srcs/sources_1/new/axis.sv
@@ -42,6 +42,41 @@ modport Slave_Simple (
output ok
);
+task automatic send_samples(
+ ref clk,
+ input int n_samples,
+ input bit rand_arrivals,
+ input bit reset_valid
+);
+ int samples_sent [PARALLEL_CHANNELS];
+ logic [PARALLEL_CHANNELS-1:0] done;
+ // reset
+ done = '0;
+ for (int i = 0; i < PARALLEL_CHANNELS; i++) begin
+ samples_sent[i] = 0;
+ end
+ valid <= '1; // enable all channels
+ while (~done) begin
+ @(posedge clk);
+ for (int i = 0; i < PARALLEL_CHANNELS; i++) begin
+ if (ok[i]) begin
+ if (samples_sent[i] == n_samples - 1) begin
+ done[i] = 1'b1;
+ end else begin
+ samples_sent[i] = samples_sent[i] + 1;
+ end
+ end
+ end
+ if (rand_arrivals) begin
+ valid <= $urandom_range((1 << PARALLEL_CHANNELS) - 1) & (~done);
+ end
+ end
+ if (reset_valid) begin
+ valid <= '0;
+ @(posedge clk);
+ end
+endtask
+
endinterface
// single axi-stream interface