diff --git a/axis_x2_test_behav.wcfg b/axis_x2_test_behav.wcfg
index 657f004..6d9b1ae 100644
--- a/axis_x2_test_behav.wcfg
+++ b/axis_x2_test_behav.wcfg
@@ -11,15 +11,55 @@
-
-
-
+
+
+
-
-
+
+
-
+
+
+ error_count[31:0]
+ error_count[31:0]
+
+
+ reset
+ reset
+
+
+ clk
+ clk
+
+
+ data_out_test[0:3][35:0]
+ data_out_test[0:3][35:0]
+
+
+ d_in
+ d_in
+
+
+ CLK_RATE_HZ[31:0]
+ CLK_RATE_HZ[31:0]
+
+
+ SAMPLE_WIDTH[31:0]
+ SAMPLE_WIDTH[31:0]
+
+
+ PARALLEL_SAMPLES[31:0]
+ PARALLEL_SAMPLES[31:0]
+
+
+ SAMPLE_FRAC_BITS[31:0]
+ SAMPLE_FRAC_BITS[31:0]
+
+
+ LATENCY[31:0]
+ LATENCY[31:0]
+
dut
label
@@ -33,16 +73,16 @@
reset
- data_in_reg[0:1][15:0]
- data_in_reg[0:1][15:0]
+ data_in_reg[0:1][17:0]
+ data_in_reg[0:1][17:0]
- product[0:1][31:0]
- product[0:1][31:0]
+ product[0:1][35:0]
+ product[0:1][35:0]
- product_d[0:1][15:0]
- product_d[0:1][15:0]
+ product_d[0:1][17:0]
+ product_d[0:1][17:0]
valid_d[3:0]
@@ -61,8 +101,8 @@
label
- data[31:0]
- data[31:0]
+ data[35:0]
+ data[35:0]
ready
@@ -85,8 +125,8 @@
label
- data[31:0]
- data[31:0]
+ data[35:0]
+ data[35:0]
ready
diff --git a/dac_prescaler_test_behav.wcfg b/dac_prescaler_test_behav.wcfg
new file mode 100644
index 0000000..b789022
--- /dev/null
+++ b/dac_prescaler_test_behav.wcfg
@@ -0,0 +1,176 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ error_count[31:0]
+ error_count[31:0]
+
+
+ reset
+ reset
+
+
+ clk
+ clk
+
+
+ scale_factor[17:0]
+ scale_factor[17:0]
+
+
+ scale_factor_d[17:0]
+ scale_factor_d[17:0]
+
+
+ data_out_test[0:3][255:0]
+ data_out_test[0:3][255:0]
+
+
+
+ CLK_RATE_HZ[31:0]
+ CLK_RATE_HZ[31:0]
+
+
+ SAMPLE_WIDTH[31:0]
+ SAMPLE_WIDTH[31:0]
+
+
+ PARALLEL_SAMPLES[31:0]
+ PARALLEL_SAMPLES[31:0]
+
+
+ SCALE_WIDTH[31:0]
+ SCALE_WIDTH[31:0]
+
+
+ SAMPLE_FRAC_BITS[31:0]
+ SAMPLE_FRAC_BITS[31:0]
+
+
+ SCALE_FRAC_BITS[31:0]
+ SCALE_FRAC_BITS[31:0]
+
+
+ LATENCY[31:0]
+ LATENCY[31:0]
+
+
+ data_in
+ label
+
+
+ data[255:0]
+ data[255:0]
+
+
+ ready
+ ready
+
+
+ valid
+ valid
+
+
+ last
+ last
+
+
+ DWIDTH[31:0]
+ DWIDTH[31:0]
+
+
+ data_out
+ label
+
+
+ data[255:0]
+ data[255:0]
+
+
+ ready
+ ready
+
+
+ valid
+ valid
+
+
+ last
+ last
+
+
+ DWIDTH[31:0]
+ DWIDTH[31:0]
+
+
+ dut
+ label
+
+
+ clk
+ clk
+
+
+ reset
+ reset
+
+
+ data_in_reg[0:15][15:0]
+ data_in_reg[0:15][15:0]
+
+
+ scale_factor_reg[17:0]
+ scale_factor_reg[17:0]
+
+
+ product[0:15][33:0]
+ product[0:15][33:0]
+
+
+ product_d[0:15][15:0]
+ product_d[0:15][15:0]
+
+
+ valid_d[3:0]
+ valid_d[3:0]
+
+
+ SAMPLE_WIDTH[31:0]
+ SAMPLE_WIDTH[31:0]
+
+
+ PARALLEL_SAMPLES[31:0]
+ PARALLEL_SAMPLES[31:0]
+
+
+ SCALE_WIDTH[31:0]
+ SCALE_WIDTH[31:0]
+
+
+ SAMPLE_FRAC_BITS[31:0]
+ SAMPLE_FRAC_BITS[31:0]
+
+
+ SCALE_FRAC_BITS[31:0]
+ SCALE_FRAC_BITS[31:0]
+
+
diff --git a/dds_test.srcs/sim_1/new/axis_x2_test.sv b/dds_test.srcs/sim_1/new/axis_x2_test.sv
index eb63a85..12d37c0 100644
--- a/dds_test.srcs/sim_1/new/axis_x2_test.sv
+++ b/dds_test.srcs/sim_1/new/axis_x2_test.sv
@@ -8,8 +8,9 @@ logic clk = 0;
localparam CLK_RATE_HZ = 100_000_000;
always #(0.5s/CLK_RATE_HZ) clk = ~clk;
-localparam int SAMPLE_WIDTH = 16;
+localparam int SAMPLE_WIDTH = 18;
localparam int PARALLEL_SAMPLES = 2;
+localparam int SAMPLE_FRAC_BITS = 16;
Axis_If #(.DWIDTH(SAMPLE_WIDTH*PARALLEL_SAMPLES)) data_out_if();
Axis_If #(.DWIDTH(SAMPLE_WIDTH*PARALLEL_SAMPLES)) data_in_if();
@@ -17,11 +18,10 @@ Axis_If #(.DWIDTH(SAMPLE_WIDTH*PARALLEL_SAMPLES)) data_in_if();
localparam int LATENCY = 4;
logic [SAMPLE_WIDTH*PARALLEL_SAMPLES-1:0] data_out_test [LATENCY];
-assign data_out_if.ready = 1;
-
initial begin
reset <= 1'b1;
data_in_if.valid <= 1'b0;
+ data_out_if.ready <= 1'b1;
repeat (100) @(posedge clk);
reset <= 1'b0;
repeat (500) @(posedge clk);
@@ -30,25 +30,44 @@ initial begin
data_in_if.valid <= 1'b0;
repeat (10) @(posedge clk);
data_in_if.valid <= 1'b1;
+ repeat (10) @(posedge clk);
+ data_out_if.ready <= 1'b0;
+ repeat (10) @(posedge clk);
+ data_out_if.ready <= 1'b1;
+ repeat (20) @(posedge clk);
+ data_out_if.ready <= 1'b0;
+ repeat (10) @(posedge clk);
+ data_in_if.valid <= 1'b0;
+ repeat (5) @(posedge clk);
+ data_out_if.ready <= 1'b1;
+ repeat (5) @(posedge clk);
+ data_in_if.valid <= 1'b1;
repeat (1000) @(posedge clk);
$info("error_count = %d", error_count);
$finish;
end
-typedef logic [SAMPLE_WIDTH-1:0] uint_t;
+typedef logic signed [SAMPLE_WIDTH-1:0] int_t;
+
+real d_in;
always @(posedge clk) begin
if (reset) begin
data_in_if.data <= '0;
- end else if (data_in_if.ready && data_in_if.valid) begin
- for (int i = 0; i < PARALLEL_SAMPLES; i++) begin
- data_in_if.data[i*SAMPLE_WIDTH+:SAMPLE_WIDTH] <= $urandom_range({SAMPLE_WIDTH{1'b1}});
- end
- for (int j = 0; j < LATENCY-1; j++) begin
- data_out_test[j] <= data_out_test[j+1];
+ end else begin
+ if (data_in_if.ready && data_in_if.valid) begin
+ for (int i = 0; i < PARALLEL_SAMPLES; i++) begin
+ data_in_if.data[i*SAMPLE_WIDTH+:SAMPLE_WIDTH] <= $urandom_range({SAMPLE_WIDTH{1'b1}});
+ end
end
- for (int i = 0; i < PARALLEL_SAMPLES; i++) begin
- data_out_test[LATENCY-1][i*SAMPLE_WIDTH+:SAMPLE_WIDTH] <= uint_t'(((real'(data_in_if.data[i*SAMPLE_WIDTH+:SAMPLE_WIDTH])/(2.0**15))**2) * 2.0**14);
+ if (data_out_if.ready) begin
+ for (int j = 0; j < LATENCY-1; j++) begin
+ data_out_test[j] <= data_out_test[j+1];
+ end
+ for (int i = 0; i < PARALLEL_SAMPLES; i++) begin
+ d_in = real'(int_t'(data_in_if.data[i*SAMPLE_WIDTH+:SAMPLE_WIDTH]));
+ data_out_test[LATENCY-1][i*SAMPLE_WIDTH+:SAMPLE_WIDTH] <= int_t'(((d_in/(2.0**SAMPLE_FRAC_BITS))**2) * 2.0**SAMPLE_FRAC_BITS);
+ end
end
end
end
diff --git a/dds_test.srcs/sim_1/new/dac_prescaler_test.sv b/dds_test.srcs/sim_1/new/dac_prescaler_test.sv
index 86d4e7e..8d66e82 100644
--- a/dds_test.srcs/sim_1/new/dac_prescaler_test.sv
+++ b/dds_test.srcs/sim_1/new/dac_prescaler_test.sv
@@ -10,11 +10,17 @@ always #(0.5s/CLK_RATE_HZ) clk = ~clk;
localparam int SAMPLE_WIDTH = 16;
localparam int PARALLEL_SAMPLES = 16;
+localparam int SCALE_WIDTH = 18;
+localparam int SAMPLE_FRAC_BITS = 16;
+localparam int SCALE_FRAC_BITS = 16;
Axis_If #(.DWIDTH(SAMPLE_WIDTH*PARALLEL_SAMPLES)) data_out_if();
Axis_If #(.DWIDTH(SAMPLE_WIDTH*PARALLEL_SAMPLES)) data_in_if();
+Axis_If #(.DWIDTH(SCALE_WIDTH)) scale_factor_if();
-logic [17:0] scale_factor, scale_factor_d;
+assign scale_factor_if.data = scale_factor;
+assign scale_factor_if.valid = 1'b1;
+logic [SCALE_WIDTH-1:0] scale_factor, scale_factor_d;
localparam int LATENCY = 4;
logic [SAMPLE_WIDTH*PARALLEL_SAMPLES-1:0] data_out_test [LATENCY];
@@ -32,25 +38,53 @@ initial begin
repeat (500) @(posedge clk);
scale_factor <= $urandom_range(18'h3ffff);
repeat (500) @(posedge clk);
+ data_in_if.valid <= 1'b1;
+ repeat (500) @(posedge clk);
+ data_in_if.valid <= 1'b0;
+ repeat (10) @(posedge clk);
+ data_in_if.valid <= 1'b1;
+ repeat (10) @(posedge clk);
+ data_out_if.ready <= 1'b0;
+ repeat (10) @(posedge clk);
+ data_out_if.ready <= 1'b1;
+ repeat (20) @(posedge clk);
+ data_out_if.ready <= 1'b0;
+ repeat (10) @(posedge clk);
+ data_in_if.valid <= 1'b0;
+ repeat (5) @(posedge clk);
+ data_out_if.ready <= 1'b1;
+ repeat (5) @(posedge clk);
+ data_in_if.valid <= 1'b1;
+ repeat (1000) @(posedge clk);
$info("error_count = %d", error_count);
$finish;
end
-typedef logic [SAMPLE_WIDTH-1:0] uint_t;
+typedef logic signed [SAMPLE_WIDTH-1:0] int_t;
+typedef logic signed [SCALE_WIDTH-1:0] sc_int_t;
+
+real d_in;
+real scale;
always @(posedge clk) begin
scale_factor_d <= scale_factor;
if (reset) begin
data_in_if.data <= '0;
- end else if (data_in_if.ready && data_in_if.valid) begin
- for (int i = 0; i < PARALLEL_SAMPLES; i++) begin
- data_in_if.data[i*SAMPLE_WIDTH+:SAMPLE_WIDTH] <= $urandom_range({SAMPLE_WIDTH{1'b1}});
- end
- for (int j = 0; j < LATENCY-1; j++) begin
- data_out_test[j] <= data_out_test[j+1];
+ end else begin
+ if (data_in_if.ready && data_in_if.valid) begin
+ for (int i = 0; i < PARALLEL_SAMPLES; i++) begin
+ data_in_if.data[i*SAMPLE_WIDTH+:SAMPLE_WIDTH] <= $urandom_range({SAMPLE_WIDTH{1'b1}});
+ end
end
- for (int i = 0; i < PARALLEL_SAMPLES; i++) begin
- data_out_test[LATENCY-1][i*SAMPLE_WIDTH+:SAMPLE_WIDTH] <= uint_t'((real'(data_in_if.data[i*SAMPLE_WIDTH+:SAMPLE_WIDTH])/(2.0**15) * real'(scale_factor)/(2.0**16)) * 2.0**15);
+ if (data_out_if.ready) begin
+ for (int j = 0; j < LATENCY-1; j++) begin
+ data_out_test[j] <= data_out_test[j+1];
+ end
+ for (int i = 0; i < PARALLEL_SAMPLES; i++) begin
+ d_in = real'(int_t'(data_in_if.data[i*SAMPLE_WIDTH+:SAMPLE_WIDTH]));
+ scale = real'(sc_int_t'(scale_factor_if.data));
+ data_out_test[LATENCY-1][i*SAMPLE_WIDTH+:SAMPLE_WIDTH] <= int_t'(d_in/(2.0**SAMPLE_FRAC_BITS) * scale/(2.0**SCALE_FRAC_BITS) * 2.0**SAMPLE_FRAC_BITS);
+ end
end
end
end
@@ -70,13 +104,16 @@ end
dac_prescaler #(
.SAMPLE_WIDTH(SAMPLE_WIDTH),
- .PARALLEL_SAMPLES(PARALLEL_SAMPLES)
+ .PARALLEL_SAMPLES(PARALLEL_SAMPLES),
+ .SCALE_WIDTH(SCALE_WIDTH),
+ .SAMPLE_FRAC_BITS(SAMPLE_FRAC_BITS),
+ .SCALE_FRAC_BITS(SCALE_FRAC_BITS)
) dut_i (
.clk,
.reset,
.data_out(data_out_if),
.data_in(data_in_if),
- .scale_factor
+ .scale_factor(scale_factor_if)
);
endmodule
diff --git a/dds_test.srcs/sim_1/new/sample_discriminator_test.sv b/dds_test.srcs/sim_1/new/sample_discriminator_test.sv
index 75026ef..c1dc508 100644
--- a/dds_test.srcs/sim_1/new/sample_discriminator_test.sv
+++ b/dds_test.srcs/sim_1/new/sample_discriminator_test.sv
@@ -6,7 +6,7 @@ localparam CLK_RATE_HZ = 100_000_000;
always #(0.5s/CLK_RATE_HZ) clk = ~clk;
logic reset;
-logic [15:0] threshold_high, threshold_low;
+logic signed [15:0] threshold_high, threshold_low;
Axis_If #(.DWIDTH(32)) config_in_if();
Axis_If #(.DWIDTH(16)) data_in_if();
@@ -51,9 +51,9 @@ always @(posedge clk) begin
if (data_in_if.valid && data_in_if.ready) begin
data_in_d <= data_in_if.data;
is_high_d <= is_high;
- if (data_in_if.data > threshold_high) begin
+ if (signed'(data_in_if.data) > threshold_high) begin
is_high <= 1'b1;
- end else if (data_in_if.data < threshold_low) begin
+ end else if (signed'(data_in_if.data) < threshold_low) begin
is_high <= 1'b0;
end
sample_count <= sample_count + 1'b1;
diff --git a/dds_test.srcs/sources_1/new/axis_x2.sv b/dds_test.srcs/sources_1/new/axis_x2.sv
index f22cacb..958df01 100644
--- a/dds_test.srcs/sources_1/new/axis_x2.sv
+++ b/dds_test.srcs/sources_1/new/axis_x2.sv
@@ -2,16 +2,17 @@
// computes x^2 on axi-stream data
module axis_x2 #(
parameter int SAMPLE_WIDTH = 16,
- parameter int PARALLEL_SAMPLES = 1
+ parameter int PARALLEL_SAMPLES = 1,
+ parameter int SAMPLE_FRAC_BITS = 16
) (
input wire clk, reset,
Axis_If.Slave_Simple data_in,
Axis_If.Master_Simple data_out
);
-logic signed [SAMPLE_WIDTH-1:0] data_in_reg [PARALLEL_SAMPLES]; // 1Q15
-logic signed [2*SAMPLE_WIDTH-1:0] product [PARALLEL_SAMPLES]; // 2Q30
-logic signed [SAMPLE_WIDTH-1:0] product_d [PARALLEL_SAMPLES]; // 2Q14
+logic signed [SAMPLE_WIDTH-1:0] data_in_reg [PARALLEL_SAMPLES]; // 0Q16
+logic signed [2*SAMPLE_WIDTH-1:0] product [PARALLEL_SAMPLES]; // 0Q32
+logic signed [SAMPLE_WIDTH-1:0] product_d [PARALLEL_SAMPLES]; // 0Q16
logic [3:0] valid_d;
always_ff @(posedge clk) begin
@@ -20,9 +21,13 @@ always_ff @(posedge clk) begin
end else begin
if (data_in.valid && data_in.ready) begin
for (int i = 0; i < PARALLEL_SAMPLES; i++) begin
- data_in_reg[i] <= data_in.data[i*SAMPLE_WIDTH+:SAMPLE_WIDTH]; // 1Q15
- product[i] <= data_in_reg[i]*data_in_reg[i]; // 1Q15*1Q15 = 2Q30
- product_d[i] <= product[i][2*SAMPLE_WIDTH-1-:SAMPLE_WIDTH]; // 2Q14
+ data_in_reg[i] <= data_in.data[i*SAMPLE_WIDTH+:SAMPLE_WIDTH]; // 0Q16
+ end
+ end
+ if (data_out.ready) begin
+ for (int i = 0; i < PARALLEL_SAMPLES; i++) begin
+ product[i] <= data_in_reg[i]*data_in_reg[i]; // 0Q16*0Q16 = 0Q32
+ product_d[i] <= product[i][SAMPLE_WIDTH+SAMPLE_FRAC_BITS-1-:SAMPLE_WIDTH]; // 0Q16
data_out.data[i*SAMPLE_WIDTH+:SAMPLE_WIDTH] <= product_d[i];
end
valid_d <= {valid_d[2:0], data_in.valid};
diff --git a/dds_test.srcs/sources_1/new/axis_x2_wrapper.v b/dds_test.srcs/sources_1/new/axis_x2_wrapper.v
index bd096fa..5d1ca90 100644
--- a/dds_test.srcs/sources_1/new/axis_x2_wrapper.v
+++ b/dds_test.srcs/sources_1/new/axis_x2_wrapper.v
@@ -1,23 +1,29 @@
-module axis_x2_wrapper (
+module axis_x2_wrapper #(
+ parameter SAMPLE_WIDTH = 16,
+ parameter PARALLEL_SAMPLES = 1
+) (
input wire clk, reset_n,
- output [15:0] m_axis_tdata,
+ output [8*((SAMPLE_WIDTH*PARALLEL_SAMPLES+7)/8)-1:0] m_axis_tdata,
output m_axis_tvalid,
input m_axis_tready,
- input [15:0] s_axis_tdata,
+ input [8*((SAMPLE_WIDTH*PARALLEL_SAMPLES+7)/8)-1:0] s_axis_tdata,
input s_axis_tvalid,
output s_axis_tready
);
+wire [SAMPLE_WIDTH*PARALLEL_SAMPLES-1:0] dout;
+assign m_axis_tdata = dout; // upper bits will be ignored anyway
+
axis_x2_sv_wrapper #(
- .SAMPLE_WIDTH(16),
- .PARALLEL_SAMPLES(1)
+ .SAMPLE_WIDTH(SAMPLE_WIDTH),
+ .PARALLEL_SAMPLES(PARALLEL_SAMPLES)
) axis_x2_sv_wrapper_i (
.clk(clk),
.reset(~reset_n),
- .data_out(m_axis_tdata),
+ .data_out(dout),
.data_out_valid(m_axis_tvalid),
.data_out_ready(m_axis_tready),
- .data_in(s_axis_tdata),
+ .data_in(s_axis_tdata[SAMPLE_WIDTH*PARALLEL_SAMPLES-1:0]),
.data_in_valid(s_axis_tvalid),
.data_in_ready(s_axis_tready)
);
diff --git a/dds_test.srcs/sources_1/new/dac_prescaler.sv b/dds_test.srcs/sources_1/new/dac_prescaler.sv
index 7507386..350a437 100644
--- a/dds_test.srcs/sources_1/new/dac_prescaler.sv
+++ b/dds_test.srcs/sources_1/new/dac_prescaler.sv
@@ -1,7 +1,10 @@
// dac prescaler
module dac_prescaler #(
parameter int SAMPLE_WIDTH = 16,
- parameter int PARALLEL_SAMPLES = 16
+ parameter int PARALLEL_SAMPLES = 16,
+ parameter int SCALE_WIDTH = 18,
+ parameter int SAMPLE_FRAC_BITS = 16,
+ parameter int SCALE_FRAC_BITS = 16
) (
input wire clk, reset,
Axis_If.Master_Simple data_out,
@@ -9,10 +12,10 @@ module dac_prescaler #(
Axis_If.Slave_Simple scale_factor // 2Q16
);
-logic signed [SAMPLE_WIDTH-1:0] data_in_reg [PARALLEL_SAMPLES]; // 1Q15
-logic signed [17:0] scale_factor_reg; // 2Q16
-logic signed [33:0] product [PARALLEL_SAMPLES]; // 3Q31
-logic signed [SAMPLE_WIDTH-1:0] product_d [PARALLEL_SAMPLES]; // 1Q15
+logic signed [SAMPLE_WIDTH-1:0] data_in_reg [PARALLEL_SAMPLES]; // 0Q16
+logic signed [SCALE_WIDTH-1:0] scale_factor_reg; // 2Q16
+logic signed [SAMPLE_WIDTH+SCALE_WIDTH-1:0] product [PARALLEL_SAMPLES]; // 2Q32
+logic signed [SAMPLE_WIDTH-1:0] product_d [PARALLEL_SAMPLES]; // 0Q16
logic [3:0] valid_d;
always_ff @(posedge clk) begin
@@ -24,9 +27,13 @@ always_ff @(posedge clk) begin
end
if (data_in.valid && data_in.ready) begin
for (int i = 0; i < PARALLEL_SAMPLES; i++) begin
- data_in_reg[i] <= data_in.data[i*SAMPLE_WIDTH+:SAMPLE_WIDTH]; // 1Q15*2Q16 = 3Q31
- product[i] <= data_in_reg[i]*scale_factor_reg; // 3Q31
- product_d[i] <= product[i][31-:SAMPLE_WIDTH]; // 1Q15
+ data_in_reg[i] <= data_in.data[i*SAMPLE_WIDTH+:SAMPLE_WIDTH]; // 0Q16*2Q16 = 2Q32
+ end
+ end
+ if (data_out.ready) begin
+ for (int i = 0; i < PARALLEL_SAMPLES; i++) begin
+ product[i] <= data_in_reg[i]*scale_factor_reg; // 2Q32
+ product_d[i] <= product[i][SAMPLE_WIDTH+SCALE_FRAC_BITS-1-:SAMPLE_WIDTH]; // 0Q16
data_out.data[i*SAMPLE_WIDTH+:SAMPLE_WIDTH] <= product_d[i];
end
valid_d <= {valid_d[2:0], data_in.valid};
@@ -41,7 +48,10 @@ endmodule
module dac_prescaler_sv_wrapper #(
parameter int SAMPLE_WIDTH = 16,
- parameter int PARALLEL_SAMPLES = 16
+ parameter int PARALLEL_SAMPLES = 16,
+ parameter int SCALE_WIDTH = 18,
+ parameter int SAMPLE_FRAC_BITS = 16,
+ parameter int SCALE_FRAC_BITS = 16
) (
input wire clk, reset,
output [SAMPLE_WIDTH*PARALLEL_SAMPLES-1:0] data_out,
@@ -50,18 +60,21 @@ module dac_prescaler_sv_wrapper #(
input [SAMPLE_WIDTH*PARALLEL_SAMPLES-1:0] data_in,
input data_in_valid,
output data_in_ready,
- input [17:0] scale_factor, // 2Q16 (2's complement)
+ input [SCALE_WIDTH-1:0] scale_factor, // 2Q16 (2's complement)
input scale_factor_valid,
output scale_factor_ready
);
Axis_If #(.DWIDTH(SAMPLE_WIDTH*PARALLEL_SAMPLES)) data_out_if();
Axis_If #(.DWIDTH(SAMPLE_WIDTH*PARALLEL_SAMPLES)) data_in_if();
-Axis_If #(.DWIDTH(18)) scale_factor_if();
+Axis_If #(.DWIDTH(SCALE_WIDTH)) scale_factor_if();
dac_prescaler #(
.SAMPLE_WIDTH(SAMPLE_WIDTH),
- .PARALLEL_SAMPLES(PARALLEL_SAMPLES)
+ .PARALLEL_SAMPLES(PARALLEL_SAMPLES),
+ .SCALE_WIDTH(SCALE_WIDTH),
+ .SAMPLE_FRAC_BITS(SAMPLE_FRAC_BITS),
+ .SCALE_FRAC_BITS(SCALE_FRAC_BITS)
) dac_prescaler_i (
.clk,
.reset,
diff --git a/dds_test.srcs/sources_1/new/dac_prescaler_wrapper.v b/dds_test.srcs/sources_1/new/dac_prescaler_wrapper.v
index c99c854..83c7659 100644
--- a/dds_test.srcs/sources_1/new/dac_prescaler_wrapper.v
+++ b/dds_test.srcs/sources_1/new/dac_prescaler_wrapper.v
@@ -1,9 +1,15 @@
-module dac_prescaler_wrapper (
+module dac_prescaler_wrapper #(
+ parameter SAMPLE_WIDTH = 16,
+ parameter PARALLEL_SAMPLES = 16,
+ parameter SCALE_WIDTH = 18,
+ parameter SAMPLE_FRAC_BITS = 16,
+ parameter SCALE_FRAC_BITS = 16
+) (
input wire clk, reset_n,
- output [255:0] m_axis_tdata,
+ output [8*((SAMPLE_WIDTH*PARALLEL_SAMPLES+7)/8)-1:0] m_axis_tdata,
output m_axis_tvalid,
input m_axis_tready,
- input [255:0] s_axis_tdata,
+ input [8*((SAMPLE_WIDTH*PARALLEL_SAMPLES+7)/8)-1:0] s_axis_tdata,
input s_axis_tvalid,
output s_axis_tready,
input [31:0] s_axis_scale_tdata, // 2Q16 (2's complement)
@@ -11,19 +17,25 @@ module dac_prescaler_wrapper (
output s_axis_scale_tready
);
+wire [SAMPLE_WIDTH*PARALLEL_SAMPLES-1:0] dout;
+assign m_axis_tdata = dout; // upper bits will be ignored anyway
+
dac_prescaler_sv_wrapper #(
- .SAMPLE_WIDTH(16),
- .PARALLEL_SAMPLES(16)
+ .SAMPLE_WIDTH(SAMPLE_WIDTH),
+ .PARALLEL_SAMPLES(PARALLEL_SAMPLES),
+ .SCALE_WIDTH(SCALE_WIDTH),
+ .SAMPLE_FRAC_BITS(SAMPLE_FRAC_BITS),
+ .SCALE_FRAC_BITS(SCALE_FRAC_BITS)
) dac_prescaler_sv_wrapper_i (
.clk(clk),
.reset(~reset_n),
- .data_out(m_axis_tdata),
+ .data_out(dout),
.data_out_valid(m_axis_tvalid),
.data_out_ready(m_axis_tready),
- .data_in(s_axis_tdata),
+ .data_in(s_axis_tdata[SAMPLE_WIDTH*PARALLEL_SAMPLES-1:0]),
.data_in_valid(s_axis_tvalid),
.data_in_ready(s_axis_tready),
- .scale_factor(s_axis_scale_tdata[17:0]),
+ .scale_factor(s_axis_scale_tdata[SCALE_WIDTH-1:0]),
.scale_factor_valid(s_axis_scale_tvalid),
.scale_factor_ready(s_axis_scale_tready)
);
diff --git a/dds_test.srcs/sources_1/new/noise_event_tracker.sv b/dds_test.srcs/sources_1/new/noise_event_tracker.sv
index 6e326d4..971d600 100644
--- a/dds_test.srcs/sources_1/new/noise_event_tracker.sv
+++ b/dds_test.srcs/sources_1/new/noise_event_tracker.sv
@@ -16,7 +16,7 @@ module noise_event_tracker #(
parameter int BUFFER_DEPTH = 1024, // size will be BUFFER_DEPTH x AXI_MM_WIDTH
parameter int SAMPLE_WIDTH = 16,
parameter int AXI_MM_WIDTH = 128,
- parameter int CLOCK_WIDTH = 56
+ parameter int CLOCK_WIDTH = 42
) (
input wire clk, reset,
Axis_If.Master_Full data_out, // collection of samples
@@ -220,7 +220,7 @@ module noise_event_tracker_sv_wrapper #(
parameter int BUFFER_DEPTH = 1024,
parameter int SAMPLE_WIDTH = 16,
parameter int AXI_MM_WIDTH = 128,
- parameter int CLOCK_WIDTH = 56
+ parameter int CLOCK_WIDTH = 42
) (
input wire clk, reset,
diff --git a/dds_test.srcs/sources_1/new/noise_event_tracker_wrapper.v b/dds_test.srcs/sources_1/new/noise_event_tracker_wrapper.v
index 45d1e64..c76cb2f 100644
--- a/dds_test.srcs/sources_1/new/noise_event_tracker_wrapper.v
+++ b/dds_test.srcs/sources_1/new/noise_event_tracker_wrapper.v
@@ -25,7 +25,7 @@ noise_event_tracker_sv_wrapper #(
.BUFFER_DEPTH(32768),
.SAMPLE_WIDTH(16),
.AXI_MM_WIDTH(128),
- .CLOCK_WIDTH(56)
+ .CLOCK_WIDTH(42)
) noise_event_tracker_sv_wrapper_i (
.clk(clk),
.reset(~reset_n),
diff --git a/dds_test.srcs/sources_1/new/sample_discriminator.sv b/dds_test.srcs/sources_1/new/sample_discriminator.sv
index 34d6879..e052311 100644
--- a/dds_test.srcs/sources_1/new/sample_discriminator.sv
+++ b/dds_test.srcs/sources_1/new/sample_discriminator.sv
@@ -22,7 +22,7 @@ localparam logic [SAMPLE_WIDTH-1:0] DATA_MASK = {{(SAMPLE_WIDTH-1){1'b1}}, 1'b0}
assign config_in.ready = 1'b1;
assign data_in.ready = 1'b1; // always process new samples; we'll just throw them away later if we don't need them
-logic [SAMPLE_WIDTH-1:0] threshold_low, threshold_high;
+logic signed [SAMPLE_WIDTH-1:0] threshold_low, threshold_high;
logic [SAMPLE_WIDTH-1:0] data_in_reg;
logic data_in_valid;
logic [CLOCK_WIDTH-1:0] sample_count;
@@ -55,9 +55,9 @@ always_ff @(posedge clk) begin
data_in_reg <= data_in.data;
is_high_d <= is_high;
sample_count <= sample_count + 1'b1;
- if ((data_in.data & DATA_MASK) > threshold_high) begin
+ if (signed'(data_in.data & DATA_MASK) > threshold_high) begin
is_high <= 1'b1;
- end else if ((data_in.data & DATA_MASK) < threshold_low) begin
+ end else if (signed'(data_in.data & DATA_MASK) < threshold_low) begin
is_high <= 1'b0;
end
end
diff --git a/sample_discriminator_test_behav.wcfg b/sample_discriminator_test_behav.wcfg
index 3eda6c4..b47f940 100644
--- a/sample_discriminator_test_behav.wcfg
+++ b/sample_discriminator_test_behav.wcfg
@@ -11,15 +11,15 @@
-
-
-
+
+
+
-
-
+
+
-
+
clk
clk
@@ -95,6 +95,7 @@
ANALOG_INTERPOLATION_HOLD
ANALOG_OFFSCALE_HIDE
0.000000
+ SIGNEDDECRADIX
data_in_valid
@@ -127,11 +128,36 @@
CLOCK_WIDTH[31:0]
CLOCK_WIDTH[31:0]
+ UNSIGNEDDECRADIX
SPLIT_TIMESTAMP_COUNT[31:0]
SPLIT_TIMESTAMP_COUNT[31:0]
+
+ data_in_if
+ label
+
+
+ data[15:0]
+ data[15:0]
+
+
+ ready
+ ready
+
+
+ valid
+ valid
+
+
+ last
+ last
+
+
+ DWIDTH[31:0]
+ DWIDTH[31:0]
+
data_out_if
label
@@ -171,7 +197,6 @@
buffer[0:15][71:0]
buffer[0:15][71:0]
-
read_addr[4:0]