From 4d685b05dc0839234292ee6f63232ad3fb76b600 Mon Sep 17 00:00:00 2001 From: Reed Foster Date: Thu, 30 Nov 2023 14:00:19 -0500 Subject: [PATCH] update README.md --- README.md | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index 82e38f2..4007a21 100644 --- a/README.md +++ b/README.md @@ -1 +1,16 @@ -# rfsoc_dds \ No newline at end of file +# rfsoc_dds + + Systemverilog for direct digital synthesis of high-purity sinusoids at full sample rate for use with RFSoCs. + Also includes a sample buffer that can perform basic amplitude discrimination on input signals to generate sparse sequences of samples that are time-tagged. + +## Repo structure + +### `dds_test.srcs`: + +Systemverilog for simulation and synthesis. +The key module for direct digital synthesis (DDS) is [here](dds_test.srcs/sources_1/new/dds.sv). +DDS is implemented multiple phase increment registers configured in parallel. +A four-quadrant lookup table is used (I didn't have the energy to optimize a single quadrant scheme to minimize phase quantization noise for only 4x improvement in storage space). +To reduce phase quantization noise, a maximal linear-feedback shift register (LFSR) is used to provide a 1-LSB dither signal. +While this increases the floor of the phase noise as compared to a 0.5-LSB dither, I found in testing that it reduced the correlated phase noise and improved the spurious-free dynamic range of the output. +