diff --git a/dds_test.srcs/sim_1/new/noise_event_tracker_test.sv b/dds_test.srcs/sim_1/new/noise_event_tracker_test.sv index bc6e2ec..06e077d 100644 --- a/dds_test.srcs/sim_1/new/noise_event_tracker_test.sv +++ b/dds_test.srcs/sim_1/new/noise_event_tracker_test.sv @@ -22,7 +22,9 @@ noise_event_tracker #( .BUFFER_DEPTH(32), // 32x128 = 128 samples from each channel can be stored .SAMPLE_WIDTH(16), .AXI_MM_WIDTH(128), - .DECIMATION_BELOW_THRESH(DEC_RATE) // don't decimate for now + .DECIMATION_BELOW_THRESH(DEC_RATE), + .COUNT_BITS(40), + .TIMESTAMP_BUFFER_DEPTH(8) ) dut_i ( .clk, .reset, @@ -117,24 +119,48 @@ end int error_count_00; int error_count_02; int words_checked; +int timestamp_words; +logic data_out_type; // 0 for timestamp, 1 for samples +logic [63:0] timestamps_received_00 [$]; +logic [63:0] timestamps_received_02 [$]; logic [15:0] data_received_00 [$]; logic [15:0] data_received_02 [$]; // check output always @(posedge clk) begin if (reset) begin + data_out_type = '0; + timestamp_words = 0; words_checked = 0; - error_count_00 = 0; - error_count_02 = 0; end else begin if (data_out_if.valid && data_out_if.ready) begin - words_checked = words_checked + 1; - for (int i = 0; i < 8; i++) begin - if (data_out_if.data[i*16+1]) begin - // channel 02 - data_received_02.push_front(data_out_if.data[i*16+:16]); - end else begin - // channel 00 - data_received_00.push_front(data_out_if.data[i*16+:16]); + if (data_out_type) begin + words_checked = words_checked + 1; + for (int i = 0; i < 8; i++) begin + if (data_out_if.data[i*16+2]) begin + // channel 02 + data_received_02.push_front(data_out_if.data[i*16+:16]); + end else begin + // channel 00 + data_received_00.push_front(data_out_if.data[i*16+:16]); + end + end + if (data_out_if.last) begin + data_out_type = 0; + end + end else begin + // save timestamp + timestamp_words = timestamp_words + 1; + // since counter bits = 40, each word will still be 64 bits even + // though addresses are small + if (data_out_if.data[127]) begin + data_out_type = 1; + end + for (int i = 0; i < 2; i++) begin + if (data_out_if.data[i*64]) begin + timestamps_received_02.push_front(data_out_if.data[i*64+:49]); + end else begin + timestamps_received_00.push_front(data_out_if.data[i*64+:49]); + end end end end @@ -168,6 +194,7 @@ task send_samples_together(input int num_pairs); endtask task do_readout(); + data_out_if.ready <= 1'b0; stop <= 1'b1; config_in_if.valid <= 1'b1; @(posedge clk); @@ -184,26 +211,45 @@ task do_readout(); endtask task check_output(); - $info("word count (received: %d, sent: %d)", words_checked, words_stored); - $info("ch00 sample count (received: %d, sent: %d)", data_received_00.size(), data_sent_00.size()); - $info("ch02 sample count (received: %d, sent: %d)", data_received_02.size(), data_sent_02.size()); + string timestamps; + logic [63:0] tstamp_temp; + error_count_00 = 0; + error_count_02 = 0; + $display("word count (received: %d, sent: %d)", words_checked, words_stored); + $display("timestamp word count: ", timestamp_words); + $display("ch00 timestamp count: ", timestamps_received_00.size()); + $display("ch02 timestamp count: ", timestamps_received_02.size()); + timestamps = "ch00 timestamps: "; + while (timestamps_received_00.size() > 0) begin + tstamp_temp = timestamps_received_00.pop_back(); + timestamps = {timestamps, $sformatf("\nt = %0d, addr = 0x%x,0x%x (0x%x raw)", tstamp_temp[48-:40], tstamp_temp[5:1], tstamp_temp[8:6], tstamp_temp)}; + end + $display(timestamps); + timestamps = "ch02 timestamps: "; + while (timestamps_received_02.size() > 0) begin + tstamp_temp = timestamps_received_02.pop_back(); + timestamps = {timestamps, $sformatf("\nt = %0d, addr = 0x%x,0x%x (0x%x raw)", tstamp_temp[48-:40], tstamp_temp[5:1], tstamp_temp[8:6], tstamp_temp)}; + end + $display(timestamps); + $display("ch00 sample count (received: %d, sent: %d)", data_received_00.size(), data_sent_00.size()); + $display("ch02 sample count (received: %d, sent: %d)", data_received_02.size(), data_sent_02.size()); while (data_received_00.size() > 0 && data_sent_00.size() > 0) begin - if ((data_received_00[$] & 16'hfffc) != (data_sent_00[$] & 16'hfffc)) begin - $info("ch00 mismatch (got %x, expected %x)", data_received_00[$] & 16'hfffc, data_sent_00[$] & 16'hfffc); + if ((data_received_00[$] & 16'hfff8) != (data_sent_00[$] & 16'hfff8)) begin + $display("ch00 mismatch (got %x, expected %x)", data_received_00[$] & 16'hfff8, data_sent_00[$] & 16'hfff8); error_count_00 = error_count_00 + 1; end data_sent_00.pop_back(); data_received_00.pop_back(); end while (data_received_02.size() > 0 && data_sent_02.size() > 0) begin - if ((data_received_02[$] & 16'hfffc) != (data_sent_02[$] & 16'hfffc)) begin - $info("ch02 mismatch (got %x, expected %x)", data_received_02[$] & 16'hfffc, data_sent_02[$] & 16'hfffc); + if ((data_received_02[$] & 16'hfff8) != (data_sent_02[$] & 16'hfff8)) begin + $display("ch02 mismatch (got %x, expected %x)", data_received_02[$] & 16'hfff8, data_sent_02[$] & 16'hfff8); error_count_02 = error_count_02 + 1; end data_sent_02.pop_back(); data_received_02.pop_back(); end - $info("error_count = (ch00: %d, ch02: %d)", error_count_00, error_count_02); + $display("error_count = (ch00: %d, ch02: %d)", error_count_00, error_count_02); endtask initial begin @@ -255,7 +301,7 @@ initial begin // stop capture and read out do_readout(); // check everything - $info("mode = 0 (no compression) test results:"); + $display("mode = 0 (no compression) test results:"); check_output(); /////////////////////////////////////// @@ -305,7 +351,7 @@ initial begin // wrap up do_readout(); // check everything - $info("mode = 1 (compression) results:"); + $display("mode = 1 (compression) results:"); check_output(); $finish; diff --git a/dds_test.srcs/sources_1/new/fifo.sv b/dds_test.srcs/sources_1/new/fifo.sv index 9cd586e..385e357 100644 --- a/dds_test.srcs/sources_1/new/fifo.sv +++ b/dds_test.srcs/sources_1/new/fifo.sv @@ -28,7 +28,6 @@ always_ff @(posedge clk) begin if (reset) begin read_addr <= '0; write_addr <= '0; - data_out.data <= '0; end else begin if (!full && data_in.valid) begin buffer[write_addr[ADDR_WIDTH-1:0]] <= data_in.data; diff --git a/dds_test.srcs/sources_1/new/noise_event_tracker.sv b/dds_test.srcs/sources_1/new/noise_event_tracker.sv index 9bfb750..c2c091f 100644 --- a/dds_test.srcs/sources_1/new/noise_event_tracker.sv +++ b/dds_test.srcs/sources_1/new/noise_event_tracker.sv @@ -9,7 +9,9 @@ module noise_event_tracker #( parameter int BUFFER_DEPTH = 1024, // size will be BUFFER_DEPTH x AXI_MM_WIDTH parameter int SAMPLE_WIDTH = 16, parameter int AXI_MM_WIDTH = 128, - parameter int DECIMATION_BELOW_THRESH = 10000 // 200S/s + parameter int DECIMATION_BELOW_THRESH = 10000, // 200S/s + parameter int COUNT_BITS = 40, // rolls over every 6.5 days at 2MS/s + parameter int TIMESTAMP_BUFFER_DEPTH = 128 // store a timestamp every time noise power increases ) ( input wire clk, reset, Axis_If.Master_Full data_out, // packed collection of samples @@ -56,7 +58,7 @@ end // noise dips below the low threshold // two bits: one for each channel, set to 1 if high threshold was exceeded // reset to 0 if noise level subsequently falls below low threshold -logic [1:0] noise_level; +logic [1:0] noise_level, noise_level_d; // merge data from separate streams into indexable signals logic [SAMPLE_WIDTH-1:0] data_in [2]; @@ -68,18 +70,19 @@ assign data_in_valid[0] = data_in_00.valid; assign data_in_valid[1] = data_in_02.valid; // datapath signals +logic [COUNT_BITS-1:0] sample_count [2]; logic [SAMPLE_WIDTH-1:0] data_in_d [2]; logic [1:0] data_in_valid_d [2]; logic [$clog2(DECIMATION_BELOW_THRESH)-1:0] dec_counter [2]; -logic [SAMPLE_WIDTH-1:0] fifo_out_data [2]; +logic [SAMPLE_WIDTH+COUNT_BITS-1:0] fifo_out_data [2]; logic [1:0] fifo_ready; logic [1:0] fifo_not_empty; // apply fifos to merge data from two axi streams generate begin: fifo_gen for (genvar i = 0; i < 2; i++) begin - Axis_If #(.DWIDTH(SAMPLE_WIDTH)) fifo_in (); - Axis_If #(.DWIDTH(SAMPLE_WIDTH)) fifo_out (); + Axis_If #(.DWIDTH(SAMPLE_WIDTH+COUNT_BITS)) fifo_in (); + Axis_If #(.DWIDTH(SAMPLE_WIDTH+COUNT_BITS)) fifo_out (); assign fifo_in.valid = ((dec_counter[i] == 0) || mode == 0) && data_in_valid_d[i][1]; assign fifo_not_empty[i] = fifo_out.valid; @@ -92,14 +95,21 @@ generate begin: fifo_gen // same time, they can be written to the sample buffer sequentially always_ff @(posedge clk) begin + noise_level_d[i] <= noise_level[i]; data_in_d[i] <= data_in[i]; data_in_valid_d[i] <= {data_in_valid_d[i][0], data_in_valid[i]}; - fifo_in.data <= {data_in_d[i][SAMPLE_WIDTH-1:2], 1'(i), noise_level[i]}; + fifo_in.data <= {sample_count[i], data_in_d[i][SAMPLE_WIDTH-1:3], 1'(i), noise_level[i], noise_level[i] & (!noise_level_d[i])}; if (reset) begin noise_level[i] <= '0; dec_counter[i] <= '0; + sample_count[i] <= '0; end else begin - // update noise level register + if (config_in.valid && config_in_start) begin + sample_count[i] <= '0; + end else if (data_in_valid[i]) begin + sample_count[i] <= sample_count[i] + 1'b1; + end + // update noise level register and counter if (data_in_valid[i]) begin if (data_in[i] > threshold_high) begin noise_level[i] <= 1'b1; @@ -124,8 +134,8 @@ generate begin: fifo_gen end fifo #( - .DATA_WIDTH(SAMPLE_WIDTH), - .ADDR_WIDTH(3) + .DATA_WIDTH(SAMPLE_WIDTH+COUNT_BITS), + .ADDR_WIDTH(2) // does not need to be deep at all since samples are arriving at such a low rate ) fifo_i ( .clk, .reset, @@ -157,16 +167,36 @@ always_comb begin end end +////////////////////////////////////////////////////// +// sample and timestamp buffers and state machine +////////////////////////////////////////////////////// +// state machine and buffer signals +enum {IDLE, CAPTURE, POSTCAPTURE, PRETRANSFER, TRANSFER_TIMESTAMPS, TRANSFER_SWITCH, TRANSFER_DATA, POSTTRANSFER} state; +logic [AXI_MM_WIDTH-1:0] buffer [BUFFER_DEPTH]; +logic [AXI_MM_WIDTH-1:0] timestamp_buffer [TIMESTAMP_BUFFER_DEPTH]; // assume +logic [$clog2(BUFFER_DEPTH)-1:0] write_addr, read_addr, read_stop_addr, read_addr_d; +logic [$clog2(BUFFER_DEPTH)-1:0] timestamp_write_addr, timestamp_read_addr, timestamp_read_stop_addr; +logic [AXI_MM_WIDTH-1:0] data_out_word; +logic [AXI_MM_WIDTH-1:0] timestamp_out_word; +logic [2:0] data_out_valid; // extra valid and last to match latency of BRAM +assign data_out.valid = data_out_valid[1]; // memory read/write bus have the same width (wider than sample width) // select appropriate subword range of input word when writing from FIFOs localparam int WORD_SIZE = 2**($clog2(SAMPLE_WIDTH)); -localparam int WORD_SELECT_BITS = $clog2(AXI_MM_WIDTH) - $clog2(SAMPLE_WIDTH); -logic [WORD_SELECT_BITS-1:0] word_select; +localparam int WORD_SELECT_BITS = $clog2(AXI_MM_WIDTH) - $clog2(WORD_SIZE); +localparam int TIMESTAMP_BITS = COUNT_BITS + WORD_SELECT_BITS + $clog2(BUFFER_DEPTH) + 1; +localparam int TIMESTAMP_WORD_SIZE = 2**($clog2(TIMESTAMP_BITS)); +localparam int TIMESTAMP_FLAG_BITS = TIMESTAMP_WORD_SIZE - TIMESTAMP_BITS; +localparam int TIMESTAMP_WORD_SELECT_BITS = $clog2(AXI_MM_WIDTH) - $clog2(TIMESTAMP_WORD_SIZE); +logic [WORD_SELECT_BITS-1:0] data_word_select; +logic [TIMESTAMP_WORD_SELECT_BITS-1:0] timestamp_word_select; logic [AXI_MM_WIDTH-1:0] data_in_word; -logic data_in_word_valid; +logic [AXI_MM_WIDTH-1:0] timestamp_in_word; +logic data_in_word_valid, timestamp_in_word_valid; always_ff @(posedge clk) begin if (reset) begin - word_select <= '0; + data_word_select <= '0; + timestamp_word_select <= '0; data_in_word <= '0; data_in_word_valid <= 1'b0; end else begin @@ -175,25 +205,22 @@ always_ff @(posedge clk) begin // when a capture is started. yes this is a little inefficient but // I didn't think of it in advance and I don't want to rewrite the input // logic - data_in_word[word_select*WORD_SIZE+:WORD_SIZE] <= fifo_out_data[fifo_select]; - word_select <= word_select + 1'b1; // rolls over since AXI_MM_WIDTH is a power of 2 + data_in_word[data_word_select*WORD_SIZE+:WORD_SIZE] <= fifo_out_data[fifo_select][SAMPLE_WIDTH-1:0]; + data_word_select <= data_word_select + 1'b1; // rolls over since AXI_MM_WIDTH is a power of 2 + if (fifo_out_data[fifo_select][0]) begin + // if noise & !noise_d, save the timestamp and location in memory for the sample + // recall that the FIFO stores the following word: + // {sample_count[i], data_in_d[i][SAMPLE_WIDTH-1:3], 1'(i), noise_level[i], noise_level[i] & (!noise_level_d[i])}; + timestamp_in_word[timestamp_word_select*TIMESTAMP_WORD_SIZE+:TIMESTAMP_WORD_SIZE] <= + {'0, fifo_out_data[fifo_select][SAMPLE_WIDTH+:COUNT_BITS], data_word_select, write_addr, fifo_select}; + timestamp_word_select <= timestamp_word_select + 1'b1; + end end - data_in_word_valid <= fifo_not_empty[fifo_select] && (word_select == 2**WORD_SELECT_BITS - 1); + data_in_word_valid <= fifo_not_empty[fifo_select] && (data_word_select == 2**WORD_SELECT_BITS - 1); + timestamp_in_word_valid <= fifo_not_empty[fifo_select] && (timestamp_word_select == 2**TIMESTAMP_WORD_SELECT_BITS - 1); end end -////////////////////////////////////////////////////// -// main state machine and sample buffer -////////////////////////////////////////////////////// -enum {IDLE, CAPTURE, POSTCAPTURE, PRETRANSFER, TRANSFER} state; -logic [AXI_MM_WIDTH-1:0] buffer [BUFFER_DEPTH]; -logic [$clog2(BUFFER_DEPTH)-1:0] write_addr, read_addr, read_stop_addr; -logic [AXI_MM_WIDTH-1:0] data_out_word [2]; -logic [2:0] data_out_valid; // extra valid and last to match latency of BRAM -logic [1:0] data_out_last; -assign data_out.data = data_out_word[1]; -assign data_out.valid = data_out_valid[2]; -assign data_out.last = data_out_last[1]; // state machine always_ff @(posedge clk) begin if (reset) begin @@ -205,13 +232,24 @@ always_ff @(posedge clk) begin IDLE: if (config_in.valid && config_in_start) state <= CAPTURE; CAPTURE: begin if ((config_in.valid && config_in_stop) - || (data_in_word_valid && (write_addr == BUFFER_DEPTH - 1))) begin + || (data_in_word_valid && (write_addr == BUFFER_DEPTH - 1)) + || (timestamp_in_word_valid && (timestamp_write_addr == TIMESTAMP_BUFFER_DEPTH - 1))) begin state <= POSTCAPTURE; end end POSTCAPTURE: state <= PRETRANSFER; - PRETRANSFER: if (data_out_valid[1]) state <= TRANSFER; - TRANSFER: if (data_out.last && data_out.valid && data_out.ready) state <= IDLE; + PRETRANSFER: begin + if (timestamp_read_stop_addr == 0) begin + // skip TRANSFER_TIMESTAMPS + state <= TRANSFER_SWITCH; + end else begin + if (data_out_valid[1]) state <= TRANSFER_TIMESTAMPS; + end + end + TRANSFER_TIMESTAMPS: if (timestamp_read_addr == timestamp_read_stop_addr) state <= TRANSFER_SWITCH; + TRANSFER_SWITCH: if (data_out.valid && data_out.ready) state <= TRANSFER_DATA; // extra state for a cycle to wrap up timestamp transfer and prep for data transfer + TRANSFER_DATA: if ((read_addr_d == read_stop_addr) && data_out.ready) state <= POSTTRANSFER; + POSTTRANSFER: if (data_out.last && data_out.valid && data_out.ready) state <= IDLE; endcase end end @@ -220,19 +258,26 @@ end // will be a little bit of work, since we want to register the output (so // valid will have to be delayed appropriately), but valid shouldn't // depend on ready signal from DMA IP (according to spec). +// buffer design always_ff @(posedge clk) begin if (reset) begin data_out_valid <= '0; - data_out_last <= '0; + data_out.last <= '0; read_addr <= '0; + read_addr_d <= '0; write_addr <= '0; end else begin unique case (state) IDLE: begin data_out_valid <= '0; - data_out_last <= '0; + data_out.last <= '0; read_addr <= '0; + read_addr_d <= '0; write_addr <= '0; + read_stop_addr <= '0; + timestamp_read_addr <= '0; + timestamp_write_addr <= '0; + timestamp_read_stop_addr <= '0; end CAPTURE: begin if (data_in_word_valid) begin @@ -240,36 +285,90 @@ always_ff @(posedge clk) begin write_addr <= write_addr + 1'b1; read_stop_addr <= write_addr; end + if (timestamp_in_word_valid) begin + timestamp_buffer[timestamp_write_addr] <= timestamp_in_word; + timestamp_write_addr <= timestamp_write_addr + 1'b1; + timestamp_read_stop_addr <= timestamp_write_addr; + end end POSTCAPTURE: begin - data_out_valid <= {data_out_valid[1:0], 1'b1}; - data_out_word[0] <= buffer[read_addr]; - data_out_word[1] <= data_out_word[0]; + // first send out timestamps + data_out_valid <= {data_out_valid[0], 1'b1}; + timestamp_out_word <= timestamp_buffer[timestamp_read_addr]; + data_out.data <= timestamp_out_word; end PRETRANSFER: begin // repeats until data_out.valid is high - data_out_valid <= {data_out_valid[1:0], 1'b0}; - data_out_word[0] <= buffer[read_addr]; - data_out_word[1] <= data_out_word[0]; + data_out_valid <= {data_out_valid[0], 1'b0}; + timestamp_out_word <= timestamp_buffer[timestamp_read_addr]; + // if we only have one timestamp to send out, then send it out with + // the proper flag + if (timestamp_read_stop_addr == 0) begin + data_out.data <= {{TIMESTAMP_FLAG_BITS{1'b1}}, timestamp_out_word[AXI_MM_WIDTH-TIMESTAMP_FLAG_BITS-1:0]}; + end else begin + data_out.data <= timestamp_out_word; + end end - TRANSFER: begin + TRANSFER_TIMESTAMPS: begin if (data_out.ready) begin // as long as output is ready, increment address - data_out_word[0] <= buffer[read_addr]; - data_out_word[1] <= data_out_word[0]; - if (read_addr == read_stop_addr) begin - // stop reading after we've finished reading everything that's - // been written to the buffer - // set last signal high and valid signal low - data_out_valid <= {data_out_valid[1:0], 1'b0}; - read_addr <= read_stop_addr; - data_out_last <= {data_out_last[0], ~data_out_last[0]}; - end else begin - // while we're not done reading from the buffer, - // increment the read address and set valid signal high + if (timestamp_read_addr != timestamp_read_stop_addr) begin + timestamp_read_addr <= timestamp_read_addr + 1'b1; + end + timestamp_out_word <= timestamp_buffer[timestamp_read_addr]; + data_out.data <= timestamp_out_word; + data_out_valid <= {data_out_valid[0], 1'b1}; + end else if (!data_out.valid) begin + // as long as output isn't valid, flush out pipeline so that we don't deadlock with AXIS slave + // since slaves are permitted to wait for valid to go high before asserting ready + timestamp_out_word <= timestamp_buffer[timestamp_read_addr]; + data_out.data <= timestamp_out_word; + // if data_out.ready was false, then we didn't update timestamp_read_addr, + // so any data entering the pipeline isn't actually new + data_out_valid <= {data_out_valid[0], 1'b0}; + end + end + TRANSFER_SWITCH: begin + if (data_out.ready) begin + read_addr <= read_addr + 1'b1; + read_addr_d <= read_addr; + // send out final timestamp, setting the upper bits to 1 to indicate + // it is the last timestamp word + data_out.data <= data_out_word; + data_out_word <= buffer[read_addr]; + data_out_valid <= {data_out_valid[0], 1'b1}; + end else if (!data_out.valid) begin + data_out.data <= {{TIMESTAMP_FLAG_BITS{1'b1}}, timestamp_out_word[AXI_MM_WIDTH-TIMESTAMP_FLAG_BITS-1:0]}; + data_out_word <= buffer[read_addr]; + data_out_valid <= {data_out_valid[0], 1'b0}; + end + end + TRANSFER_DATA: begin + if (data_out.ready) begin // as long as output is ready, increment address + if (read_addr != read_stop_addr) begin read_addr <= read_addr + 1'b1; - data_out_valid <= {data_out_valid[1:0], 1'b1}; - data_out_last <= {data_out_last[0], 1'b0}; end + if (read_addr_d == read_stop_addr) begin + data_out_valid <= {data_out_valid[0], 1'b0}; + data_out.last <= 1'b1; + end else begin + data_out_valid <= {data_out_valid[0], 1'b1}; + end + data_out_word <= buffer[read_addr]; + data_out.data <= data_out_word; + read_addr_d <= read_addr; + end else if (!data_out.valid) begin + // as long as output isn't valid, flush out pipeline so that we don't deadlock with AXIS slave + // since slaves are permitted to wait for valid to go high before asserting ready + data_out_word <= buffer[read_addr]; + data_out.data <= data_out_word; + data_out_valid <= {data_out_valid[0], 1'b0}; + end + end + POSTTRANSFER: begin + // handle last signal + if (data_out.ready || (!data_out.valid)) begin + data_out.last <= 1'b0; + data_out_valid <= {data_out_valid[0], 1'b0}; // no new data end end endcase @@ -282,7 +381,9 @@ module noise_event_tracker_sv_wrapper #( parameter int BUFFER_DEPTH = 1024, parameter int SAMPLE_WIDTH = 16, parameter int AXI_MM_WIDTH = 128, - parameter int DECIMATION_BELOW_THRESH = 10000 + parameter int DECIMATION_BELOW_THRESH = 10000, + parameter int COUNT_BITS = 40, + parameter int TIMESTAMP_BUFFER_DEPTH = 128 ) ( input wire clk, reset, @@ -313,7 +414,9 @@ noise_event_tracker #( .BUFFER_DEPTH(BUFFER_DEPTH), .SAMPLE_WIDTH(SAMPLE_WIDTH), .AXI_MM_WIDTH(AXI_MM_WIDTH), - .DECIMATION_BELOW_THRESH(DECIMATION_BELOW_THRESH) + .DECIMATION_BELOW_THRESH(DECIMATION_BELOW_THRESH), + .COUNT_BITS(COUNT_BITS), + .TIMESTAMP_BUFFER_DEPTH(TIMESTAMP_BUFFER_DEPTH) ) noise_event_tracker_i ( .clk, .reset, diff --git a/dds_test.srcs/sources_1/new/noise_event_tracker_wrapper.v b/dds_test.srcs/sources_1/new/noise_event_tracker_wrapper.v index b6cac23..057f591 100644 --- a/dds_test.srcs/sources_1/new/noise_event_tracker_wrapper.v +++ b/dds_test.srcs/sources_1/new/noise_event_tracker_wrapper.v @@ -22,10 +22,12 @@ module noise_event_tracker_wrapper ( assign m_axis_tkeep = 16'hffff; noise_event_tracker_sv_wrapper #( - .BUFFER_DEPTH(8192), + .BUFFER_DEPTH(32768), .SAMPLE_WIDTH(16), .AXI_MM_WIDTH(128), - .DECIMATION_BELOW_THRESH(10000) + .DECIMATION_BELOW_THRESH(10000), + .COUNT_BITS(40), + .TIMESTAMP_BUFFER_DEPTH(1024) ) noise_event_tracker_sv_wrapper_i ( .clk(clk), .reset(~reset_n), diff --git a/noise_event_tracker_test_behav.wcfg b/noise_event_tracker_test_behav.wcfg index 8ac51e0..312dff3 100644 --- a/noise_event_tracker_test_behav.wcfg +++ b/noise_event_tracker_test_behav.wcfg @@ -11,15 +11,15 @@ - - - + + + - - + + - + clk clk @@ -198,31 +198,32 @@ [0][15:0] STYLE_ANALOG 100 + UNSIGNEDDECRADIX ANALOG_YRANGETYPE_AUTO 0.000000 0.000000 ANALOG_INTERPOLATION_HOLD ANALOG_OFFSCALE_HIDE 0.000000 - UNSIGNEDDECRADIX [1][15:0] [1][15:0] STYLE_ANALOG 100 + UNSIGNEDDECRADIX ANALOG_YRANGETYPE_AUTO 0.000000 0.000000 ANALOG_INTERPOLATION_HOLD ANALOG_OFFSCALE_HIDE 0.000000 - UNSIGNEDDECRADIX data_in_valid[1:0] data_in_valid[1:0] + data_in_d[0:1][15:0] @@ -231,23 +232,14 @@ data_in_valid_d[0:1][1:0] data_in_valid_d[0:1][1:0] - - [0][1:0] - [0][1:0] - - - - [1][1:0] - [1][1:0] - dec_counter[0:1][6:0] dec_counter[0:1][6:0] - fifo_out_data[0:1][15:0] - fifo_out_data[0:1][15:0] + fifo_out_data[0:1][55:0] + fifo_out_data[0:1][55:0] fifo_ready[1:0] @@ -261,10 +253,6 @@ fifo_select fifo_select - - word_select[2:0] - word_select[2:0] - data_in_word[127:0] data_in_word[127:0] @@ -281,6 +269,10 @@ buffer[0:31][127:0] buffer[0:31][127:0] + + timestamp_buffer[0:7][127:0] + timestamp_buffer[0:7][127:0] + write_addr[4:0] write_addr[4:0] @@ -293,17 +285,68 @@ read_addr[4:0] read_addr[4:0] + + timestamp_write_addr[4:0] + timestamp_write_addr[4:0] + + + timestamp_read_addr[4:0] + timestamp_read_addr[4:0] + + + timestamp_read_stop_addr[4:0] + timestamp_read_stop_addr[4:0] + - data_out_word[0:1][127:0] - data_out_word[0:1][127:0] + data_out_word[127:0] + data_out_word[127:0] data_out_valid[2:0] data_out_valid[2:0] - - data_out_last[1:0] - data_out_last[1:0] + + timestamp_out_word[127:0] + timestamp_out_word[127:0] + + + timestamp_word_select[0:0] + timestamp_word_select[0:0] + + + timestamp_in_word[127:0] + timestamp_in_word[127:0] + + + timestamp_in_word_valid + timestamp_in_word_valid + + + noise_level[1:0] + noise_level[1:0] + + + noise_level_d[1:0] + noise_level_d[1:0] + + + sample_count[0:1][39:0] + sample_count[0:1][39:0] + + + [0][39:0] + [0][39:0] + UNSIGNEDDECRADIX + + + [1][39:0] + [1][39:0] + UNSIGNEDDECRADIX + + + + data_out_type + data_out_type fifo0 @@ -318,16 +361,16 @@ reset - buffer[0:7][15:0] - buffer[0:7][15:0] + buffer[0:3][55:0] + buffer[0:3][55:0] - read_addr[3:0] - read_addr[3:0] + read_addr[2:0] + read_addr[2:0] - write_addr[3:0] - write_addr[3:0] + write_addr[2:0] + write_addr[2:0] full @@ -346,8 +389,8 @@ label - data[15:0] - data[15:0] + data[55:0] + data[55:0] ready @@ -362,8 +405,8 @@ label - data[15:0] - data[15:0] + data[55:0] + data[55:0] ready @@ -386,16 +429,16 @@ reset - buffer[0:7][15:0] - buffer[0:7][15:0] + buffer[0:3][55:0] + buffer[0:3][55:0] - read_addr[3:0] - read_addr[3:0] + read_addr[2:0] + read_addr[2:0] - write_addr[3:0] - write_addr[3:0] + write_addr[2:0] + write_addr[2:0] full @@ -414,8 +457,8 @@ label - data[15:0] - data[15:0] + data[55:0] + data[55:0] ready @@ -430,8 +473,8 @@ label - data[15:0] - data[15:0] + data[55:0] + data[55:0] ready