Rapidstream seamlessly integrates with AMD Vitis, enabling optimization of Vitis object files (.xo) to enhance FPGA development workflows. By taking .xo files as input, Rapidstream optimizes and outputs optimized .xo files, maintaining compatibility with Vitis's v++ -link command for streamlined development.
In this recipe, we illustrate how to create a Vitis objective file (.xo) using Vitis, then optimize the .xo file with Rapidstream, and finally utilize the optimized output in the ongoing Vitis development process.
The figures below demonstrate how RapidStream seamlessly integrates with the Vitis flow. In Figure (a), within the standard AMD Vitis flow, HLS C++ files undergo initial compilation using Vitis_HLS and are stored as Xilinx Objective files (.xo). Subsequently, Vitis links the .xo file to the target FPGA device, executing tasks such as placement, routing, and bitstream generation.
Figure (b) illustrates the integration of RapidStream with the Vitis flow. Users continue to leverage Vitis HLS for compiling dataflow HLS C++ code into an Xilinx Objective file (.xo). Subsequently, RapidStream processes the .xo file, seamlessly implementing transformations like partitioning, floorplanning, and pipeline insertion. The optimized design is then re-packaged into another .xo file format, which can be integrated with standard Vitis tools to target FPGA devices for generating executable bitstreams (xclbin).
Compared to the standard Vitis flow, the RapidStream-aided Vitis flow shows distinct advantages in layout generation. The standard implementation tends to consolidate all logic within a single SLR (Super Logic Region), which can lead to local routing congestion. In contrast, RapidStream distributes the logic across four separate slots, effectively mitigating this congestion. Additionally, by incorporating pipeline registers after floorplanning, the extended route wires are less likely to impact the clock frequency negatively.
These tutorials target various FPGA devices. The table below lists the tutorials available, and the features and flows showcased in all of these tutorials.
| Design | Developer | Platforms | Sources | Purpose |
| CNN13x2 | AutoBridge | U50 U55c U280 U250 |
Vitis HLS | An HLS accelerator for the convolutional neural network kernel. |
| CNN13x{4..16} | AutoBridge | U250 | Vitis HLS | An HLS accelerator for the convolutional neural network kernel. |
| LLM | AutoBridge | U50 U55c U280 U250 |
Vitis HLS | A model-specific spatial acceleration for Large Language Model (LLM) inference on FPGAs. |