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grouped_modules.json
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{
"bd_0004": true,
"bd_3e84": true,
"bd_c055": true,
"bd_fed5": true,
"clk_map_imp_1D50O8G": true,
"clk_map_imp_1MHI102": true,
"clk_map_imp_A23V1": true,
"clk_map_imp_CF11WU": true,
"design_1": true,
"design_1_gnd_driver_0_0": true,
"design_1_hbm_axi_clk_0": true,
"design_1_hbm_axi_clk_0_clk_wiz": true,
"design_1_kernel3_0_0": true,
"design_1_smartconnect_28_0": true,
"design_1_smartconnect_29_0": true,
"design_1_smartconnect_30_0": true,
"design_1_smartconnect_31_0": true,
"design_1_wrapper": true,
"design_1_xdma_0_axi_periph_0": true,
"kernel3": true,
"kernel3_A_IO_L2_in": true,
"kernel3_A_IO_L2_in_1": true,
"kernel3_A_IO_L2_in_10": true,
"kernel3_A_IO_L2_in_11": true,
"kernel3_A_IO_L2_in_2": true,
"kernel3_A_IO_L2_in_3": true,
"kernel3_A_IO_L2_in_4": true,
"kernel3_A_IO_L2_in_5": true,
"kernel3_A_IO_L2_in_6": true,
"kernel3_A_IO_L2_in_7": true,
"kernel3_A_IO_L2_in_8": true,
"kernel3_A_IO_L2_in_9": true,
"kernel3_A_IO_L2_in_boundary": true,
"kernel3_A_IO_L2_in_inter_trans": true,
"kernel3_A_IO_L2_in_inter_trans_Pipeline_VITIS_LOOP_77_1_VITIS_LOOP_79_2_VITIS_LOOP_81_3": true,
"kernel3_A_IO_L2_in_inter_trans_boundary": true,
"kernel3_A_IO_L2_in_intra_trans": true,
"kernel3_A_IO_L2_in_intra_trans_Pipeline_VITIS_LOOP_51_1_VITIS_LOOP_53_2_VITIS_LOOP_55_3": true,
"kernel3_A_IO_L3_in": true,
"kernel3_A_IO_L3_in_Pipeline_VITIS_LOOP_20_1": true,
"kernel3_A_PE_dummy": true,
"kernel3_A_PE_dummy_12": true,
"kernel3_A_PE_dummy_13": true,
"kernel3_A_PE_dummy_14": true,
"kernel3_A_PE_dummy_15": true,
"kernel3_A_PE_dummy_16": true,
"kernel3_A_PE_dummy_17": true,
"kernel3_A_PE_dummy_18": true,
"kernel3_A_PE_dummy_19": true,
"kernel3_A_PE_dummy_20": true,
"kernel3_A_PE_dummy_21": true,
"kernel3_A_PE_dummy_22": true,
"kernel3_A_PE_dummy_23": true,
"kernel3_B_IO_L2_in": true,
"kernel3_B_IO_L2_in_boundary": true,
"kernel3_B_IO_L2_in_inter_trans": true,
"kernel3_B_IO_L2_in_inter_trans_boundary": true,
"kernel3_B_IO_L2_in_intra_trans": true,
"kernel3_B_IO_L2_in_intra_trans_Pipeline_VITIS_LOOP_298_1_VITIS_LOOP_300_2_VITIS_LOOP_302": true,
"kernel3_B_IO_L3_in": true,
"kernel3_B_IO_L3_in_Pipeline_VITIS_LOOP_267_1": true,
"kernel3_B_PE_dummy": true,
"kernel3_B_PE_dummy_24": true,
"kernel3_C_drain_IO_L1_out": true,
"kernel3_C_drain_IO_L1_out_25": true,
"kernel3_C_drain_IO_L1_out_25_Pipeline_VITIS_LOOP_1027_1_VITIS_LOOP_1029_2_VITIS_LOOP_103": true,
"kernel3_C_drain_IO_L1_out_25_Pipeline_VITIS_LOOP_994_1_VITIS_LOOP_996_2": true,
"kernel3_C_drain_IO_L1_out_26": true,
"kernel3_C_drain_IO_L1_out_26_Pipeline_VITIS_LOOP_1027_1_VITIS_LOOP_1029_2_VITIS_LOOP_103": true,
"kernel3_C_drain_IO_L1_out_26_Pipeline_VITIS_LOOP_994_1_VITIS_LOOP_996_2": true,
"kernel3_C_drain_IO_L1_out_27": true,
"kernel3_C_drain_IO_L1_out_27_Pipeline_VITIS_LOOP_1027_1_VITIS_LOOP_1029_2_VITIS_LOOP_103": true,
"kernel3_C_drain_IO_L1_out_27_Pipeline_VITIS_LOOP_994_1_VITIS_LOOP_996_2": true,
"kernel3_C_drain_IO_L1_out_28": true,
"kernel3_C_drain_IO_L1_out_28_Pipeline_VITIS_LOOP_1027_1_VITIS_LOOP_1029_2_VITIS_LOOP_103": true,
"kernel3_C_drain_IO_L1_out_28_Pipeline_VITIS_LOOP_994_1_VITIS_LOOP_996_2": true,
"kernel3_C_drain_IO_L1_out_29": true,
"kernel3_C_drain_IO_L1_out_29_Pipeline_VITIS_LOOP_1027_1_VITIS_LOOP_1029_2_VITIS_LOOP_103": true,
"kernel3_C_drain_IO_L1_out_29_Pipeline_VITIS_LOOP_994_1_VITIS_LOOP_996_2": true,
"kernel3_C_drain_IO_L1_out_30": true,
"kernel3_C_drain_IO_L1_out_30_Pipeline_VITIS_LOOP_1027_1_VITIS_LOOP_1029_2_VITIS_LOOP_103": true,
"kernel3_C_drain_IO_L1_out_30_Pipeline_VITIS_LOOP_994_1_VITIS_LOOP_996_2": true,
"kernel3_C_drain_IO_L1_out_31": true,
"kernel3_C_drain_IO_L1_out_31_Pipeline_VITIS_LOOP_1027_1_VITIS_LOOP_1029_2_VITIS_LOOP_103": true,
"kernel3_C_drain_IO_L1_out_31_Pipeline_VITIS_LOOP_994_1_VITIS_LOOP_996_2": true,
"kernel3_C_drain_IO_L1_out_32": true,
"kernel3_C_drain_IO_L1_out_32_Pipeline_VITIS_LOOP_1027_1_VITIS_LOOP_1029_2_VITIS_LOOP_103": true,
"kernel3_C_drain_IO_L1_out_32_Pipeline_VITIS_LOOP_994_1_VITIS_LOOP_996_2": true,
"kernel3_C_drain_IO_L1_out_33": true,
"kernel3_C_drain_IO_L1_out_33_Pipeline_VITIS_LOOP_1027_1_VITIS_LOOP_1029_2_VITIS_LOOP_103": true,
"kernel3_C_drain_IO_L1_out_33_Pipeline_VITIS_LOOP_994_1_VITIS_LOOP_996_2": true,
"kernel3_C_drain_IO_L1_out_34": true,
"kernel3_C_drain_IO_L1_out_34_Pipeline_VITIS_LOOP_1027_1_VITIS_LOOP_1029_2_VITIS_LOOP_103": true,
"kernel3_C_drain_IO_L1_out_34_Pipeline_VITIS_LOOP_994_1_VITIS_LOOP_996_2": true,
"kernel3_C_drain_IO_L1_out_35": true,
"kernel3_C_drain_IO_L1_out_35_Pipeline_VITIS_LOOP_1027_1_VITIS_LOOP_1029_2_VITIS_LOOP_103": true,
"kernel3_C_drain_IO_L1_out_35_Pipeline_VITIS_LOOP_994_1_VITIS_LOOP_996_2": true,
"kernel3_C_drain_IO_L1_out_37": true,
"kernel3_C_drain_IO_L1_out_37_Pipeline_VITIS_LOOP_1027_1_VITIS_LOOP_1029_2_VITIS_LOOP_103": true,
"kernel3_C_drain_IO_L1_out_37_Pipeline_VITIS_LOOP_994_1_VITIS_LOOP_996_2": true,
"kernel3_C_drain_IO_L1_out_38": true,
"kernel3_C_drain_IO_L1_out_38_Pipeline_VITIS_LOOP_1027_1_VITIS_LOOP_1029_2_VITIS_LOOP_103": true,
"kernel3_C_drain_IO_L1_out_38_Pipeline_VITIS_LOOP_994_1_VITIS_LOOP_996_2": true,
"kernel3_C_drain_IO_L1_out_39": true,
"kernel3_C_drain_IO_L1_out_39_Pipeline_VITIS_LOOP_1027_1_VITIS_LOOP_1029_2_VITIS_LOOP_103": true,
"kernel3_C_drain_IO_L1_out_39_Pipeline_VITIS_LOOP_994_1_VITIS_LOOP_996_2": true,
"kernel3_C_drain_IO_L1_out_40": true,
"kernel3_C_drain_IO_L1_out_40_Pipeline_VITIS_LOOP_1027_1_VITIS_LOOP_1029_2_VITIS_LOOP_103": true,
"kernel3_C_drain_IO_L1_out_40_Pipeline_VITIS_LOOP_994_1_VITIS_LOOP_996_2": true,
"kernel3_C_drain_IO_L1_out_41": true,
"kernel3_C_drain_IO_L1_out_41_Pipeline_VITIS_LOOP_1027_1_VITIS_LOOP_1029_2_VITIS_LOOP_103": true,
"kernel3_C_drain_IO_L1_out_41_Pipeline_VITIS_LOOP_994_1_VITIS_LOOP_996_2": true,
"kernel3_C_drain_IO_L1_out_42": true,
"kernel3_C_drain_IO_L1_out_42_Pipeline_VITIS_LOOP_1027_1_VITIS_LOOP_1029_2_VITIS_LOOP_103": true,
"kernel3_C_drain_IO_L1_out_42_Pipeline_VITIS_LOOP_994_1_VITIS_LOOP_996_2": true,
"kernel3_C_drain_IO_L1_out_43": true,
"kernel3_C_drain_IO_L1_out_43_Pipeline_VITIS_LOOP_1027_1_VITIS_LOOP_1029_2_VITIS_LOOP_103": true,
"kernel3_C_drain_IO_L1_out_43_Pipeline_VITIS_LOOP_994_1_VITIS_LOOP_996_2": true,
"kernel3_C_drain_IO_L1_out_44": true,
"kernel3_C_drain_IO_L1_out_44_Pipeline_VITIS_LOOP_1027_1_VITIS_LOOP_1029_2_VITIS_LOOP_103": true,
"kernel3_C_drain_IO_L1_out_44_Pipeline_VITIS_LOOP_994_1_VITIS_LOOP_996_2": true,
"kernel3_C_drain_IO_L1_out_45": true,
"kernel3_C_drain_IO_L1_out_45_Pipeline_VITIS_LOOP_1027_1_VITIS_LOOP_1029_2_VITIS_LOOP_103": true,
"kernel3_C_drain_IO_L1_out_45_Pipeline_VITIS_LOOP_994_1_VITIS_LOOP_996_2": true,
"kernel3_C_drain_IO_L1_out_46": true,
"kernel3_C_drain_IO_L1_out_46_Pipeline_VITIS_LOOP_1027_1_VITIS_LOOP_1029_2_VITIS_LOOP_103": true,
"kernel3_C_drain_IO_L1_out_46_Pipeline_VITIS_LOOP_994_1_VITIS_LOOP_996_2": true,
"kernel3_C_drain_IO_L1_out_47": true,
"kernel3_C_drain_IO_L1_out_47_Pipeline_VITIS_LOOP_1027_1_VITIS_LOOP_1029_2_VITIS_LOOP_103": true,
"kernel3_C_drain_IO_L1_out_47_Pipeline_VITIS_LOOP_994_1_VITIS_LOOP_996_2": true,
"kernel3_C_drain_IO_L1_out_48": true,
"kernel3_C_drain_IO_L1_out_48_Pipeline_VITIS_LOOP_1027_1_VITIS_LOOP_1029_2_VITIS_LOOP_103": true,
"kernel3_C_drain_IO_L1_out_48_Pipeline_VITIS_LOOP_994_1_VITIS_LOOP_996_2": true,
"kernel3_C_drain_IO_L1_out_Pipeline_VITIS_LOOP_1027_1_VITIS_LOOP_1029_2_VITIS_LOOP_1031_3": true,
"kernel3_C_drain_IO_L1_out_Pipeline_VITIS_LOOP_994_1_VITIS_LOOP_996_2": true,
"kernel3_C_drain_IO_L1_out_boundary": true,
"kernel3_C_drain_IO_L1_out_boundary_36": true,
"kernel3_C_drain_IO_L1_out_boundary_36_Pipeline_VITIS_LOOP_1056_2_VITIS_LOOP_1058_3": true,
"kernel3_C_drain_IO_L1_out_boundary_36_Pipeline_VITIS_LOOP_994_1_VITIS_LOOP_996_2": true,
"kernel3_C_drain_IO_L1_out_boundary_Pipeline_VITIS_LOOP_1056_2_VITIS_LOOP_1058_3": true,
"kernel3_C_drain_IO_L1_out_boundary_Pipeline_VITIS_LOOP_994_1_VITIS_LOOP_996_2": true,
"kernel3_C_drain_IO_L2_out": true,
"kernel3_C_drain_IO_L2_out_boundary": true,
"kernel3_C_drain_IO_L3_out": true,
"kernel3_C_drain_IO_L3_out_Pipeline_VITIS_LOOP_1190_1": true,
"kernel3_PE": true,
"kernel3_PE_Pipeline_VITIS_LOOP_523_1_VITIS_LOOP_525_2": true,
"kernel3_PE_Pipeline_VITIS_LOOP_534_3_VITIS_LOOP_536_4_VITIS_LOOP_538_5": true,
"kernel3_PE_wrapper_0_0": true,
"kernel3_PE_wrapper_0_1": true,
"kernel3_PE_wrapper_10_0": true,
"kernel3_PE_wrapper_10_1": true,
"kernel3_PE_wrapper_11_0": true,
"kernel3_PE_wrapper_11_1": true,
"kernel3_PE_wrapper_12_0": true,
"kernel3_PE_wrapper_12_1": true,
"kernel3_PE_wrapper_1_0": true,
"kernel3_PE_wrapper_1_1": true,
"kernel3_PE_wrapper_2_0": true,
"kernel3_PE_wrapper_2_1": true,
"kernel3_PE_wrapper_3_0": true,
"kernel3_PE_wrapper_3_1": true,
"kernel3_PE_wrapper_4_0": true,
"kernel3_PE_wrapper_4_1": true,
"kernel3_PE_wrapper_5_0": true,
"kernel3_PE_wrapper_5_1": true,
"kernel3_PE_wrapper_6_0": true,
"kernel3_PE_wrapper_6_1": true,
"kernel3_PE_wrapper_7_0": true,
"kernel3_PE_wrapper_7_1": true,
"kernel3_PE_wrapper_8_0": true,
"kernel3_PE_wrapper_8_1": true,
"kernel3_PE_wrapper_9_0": true,
"kernel3_PE_wrapper_9_1": true,
"kernel3_fadd_32ns_32ns_32_10_full_dsp_1": true,
"kernel3_fifo_w256_d2_S": true,
"kernel3_fifo_w32_d2_S": true,
"kernel3_fifo_w64_d2_S": true,
"kernel3_fifo_w64_d33_A": true,
"kernel3_fmul_32ns_32ns_32_5_max_dsp_1": true,
"kernel3_gmem_A_m_axi": true,
"kernel3_gmem_A_m_axi_fifo": true,
"kernel3_gmem_A_m_axi_load": true,
"kernel3_gmem_A_m_axi_read": true,
"kernel3_gmem_A_m_axi_store": true,
"kernel3_gmem_A_m_axi_throttle": true,
"kernel3_gmem_A_m_axi_write": true,
"kernel3_gmem_B_m_axi": true,
"kernel3_gmem_B_m_axi_fifo": true,
"kernel3_gmem_B_m_axi_load": true,
"kernel3_gmem_B_m_axi_read": true,
"kernel3_gmem_B_m_axi_store": true,
"kernel3_gmem_B_m_axi_throttle": true,
"kernel3_gmem_B_m_axi_write": true,
"kernel3_gmem_C_m_axi": true,
"kernel3_gmem_C_m_axi_fifo": true,
"kernel3_gmem_C_m_axi_load": true,
"kernel3_gmem_C_m_axi_read": true,
"kernel3_gmem_C_m_axi_store": true,
"kernel3_gmem_C_m_axi_throttle": true,
"kernel3_gmem_C_m_axi_write": true,
"m00_exit_pipeline_imp_1MXZ6LX": true,
"m00_exit_pipeline_imp_1XA0JPY": true,
"m00_exit_pipeline_imp_BRIYBT": true,
"m00_exit_pipeline_imp_KG8TPN": true,
"s00_couplers_imp_4M2UOV": true,
"s00_entry_pipeline_imp_1AZ6WJU": true,
"s00_entry_pipeline_imp_1K7U7HK": true,
"s00_entry_pipeline_imp_O7R48M": true,
"s00_entry_pipeline_imp_XZW3PX": true,
"s00_nodes_imp_1GFHFM8": true,
"s00_nodes_imp_1PWY5PU": true,
"s00_nodes_imp_IL7VHO": true,
"s00_nodes_imp_UV6FV3": true
}