diff --git a/benchmarks/vivado_flow/vck5000_dfx/Makefile b/benchmarks/vivado_flow/vck5000_dfx/Makefile
index ae0d8191..70be0200 100644
--- a/benchmarks/vivado_flow/vck5000_dfx/Makefile
+++ b/benchmarks/vivado_flow/vck5000_dfx/Makefile
@@ -1,14 +1,34 @@
 # Copyright (c) 2024 RapidStream Design Automation, Inc. and contributors.  All rights reserved.
 # The contributor(s) of this file has/have agreed to the RapidStream Contributor License Agreement.
 
-TEMP_DIR := $(CURDIR)/build
-VPP      := vivado -source
 
+TEMP_DIR := $(CURDIR)/build
+VPP      := vivado -mode batch -source
+OVERLAY  := $(TEMP_DIR)/overlay.dcp
+OOC      := $(TEMP_DIR)/vadd_bw.dcp
+PROVERLAY:= $(TEMP_DIR)/proverlay.dcp
 m=$(shell date)
 
-all:
+all:$(PROVERLAY)
+
+$(PROVERLAY): $(CURDIR)/tcl/impl.tcl $(OVERLAY) $(OOC)
+	mkdir -p $(TEMP_DIR)
+	cd $(TEMP_DIR) && $(VPP) $<
+
+overlay: $(OVERLAY)
+
+$(OVERLAY): $(CURDIR)/tcl/prj_gen.tcl
 	mkdir -p $(TEMP_DIR)
-	cd $(TEMP_DIR) && $(VPP) ../tcl/prj_gen.tcl
+	cd $(TEMP_DIR) && $(VPP) $<
+
+ooc: $(OOC)
+
+$(OOC): $(CURDIR)/tcl/ooc_syn.tcl
+	mkdir -p $(TEMP_DIR)
+	cd $(TEMP_DIR) && $(VPP) $<
+
+proverlay:$(PROVERLAY)
+
 
 git:
 	git add .
diff --git a/benchmarks/vivado_flow/vck5000_dfx/README.md b/benchmarks/vivado_flow/vck5000_dfx/README.md
new file mode 100644
index 00000000..4123b04a
--- /dev/null
+++ b/benchmarks/vivado_flow/vck5000_dfx/README.md
@@ -0,0 +1,11 @@
+<!--
+Copyright (c) 2024 RapidStream Design Automation, Inc. and contributors.  All rights reserved.
+The contributor(s) of this file has/have agreed to the RapidStream Contributor License Agreement.
+-->
+
+# How to make VCK5000 Overlay
+
+1. Copy vck5000 to <your Vivado installation>/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx
+2. make all.
+3. Find the proverlay.dcp in build directory.
+4. make your design have the same interface as ./v/vadd_bandwidth28r28w_placeholder.
diff --git a/benchmarks/vivado_flow/vck5000_dfx/c/dma/dma_driver.cpp b/benchmarks/vivado_flow/vck5000_dfx/c/dma/dma_driver.cpp
new file mode 100644
index 00000000..6aca796d
--- /dev/null
+++ b/benchmarks/vivado_flow/vck5000_dfx/c/dma/dma_driver.cpp
@@ -0,0 +1,595 @@
+
+#include "xtime_l.h"
+#include "dma_driver.h"
+
+
+
+
+
+#if defined(XPAR_UARTNS550_0_BASEADDR)
+/*****************************************************************************/
+/*
+*
+* Uart16550 setup routine, need to set baudrate to 9600 and data bits to 8
+*
+* @param	None
+*
+* @return	None
+*
+* @note		None.
+*
+
+******************************************************************************/
+static void Uart550_Setup(void)
+{
+	/* Set the baudrate to be predictable
+	 */
+	XUartNs550_SetBaud(XPAR_UARTNS550_0_BASEADDR,
+			XPAR_XUARTNS550_CLOCK_HZ, 9600);
+
+	XUartNs550_SetLineControlReg(XPAR_UARTNS550_0_BASEADDR,
+			XUN_LCR_8_DATA_BITS);
+
+}
+#endif
+
+/*****************************************************************************/
+/**
+*
+* This function sets up RX channel of the DMA engine to be ready for packet
+* reception
+*
+* @param	AxiDmaInstPtr is the pointer to the instance of the DMA engine.
+*
+* @return	- XST_SUCCESS if the setup is successful
+*		- XST_FAILURE if setup is failure
+*
+* @note		None.
+*
+******************************************************************************/
+int dma_inst::RxSetup(XAxiDma * AxiDmaInstPtr)
+{
+	XAxiDma_BdRing *RxRingPtr;
+	int Delay = 0;
+	int Coalesce = 1;
+	int Status;
+	XAxiDma_Bd BdTemplate;
+	XAxiDma_Bd *BdPtr;
+	XAxiDma_Bd *BdCurPtr;
+	u32 BdCount;
+	u32 FreeBdCount;
+	UINTPTR RxBufferPtr;
+	int i;
+
+	RxRingPtr = XAxiDma_GetRxRing(&AxiDma);
+
+	/* Disable all RX interrupts before RxBD space setup */
+
+	XAxiDma_BdRingIntDisable(RxRingPtr, XAXIDMA_IRQ_ALL_MASK);
+
+	/* Set delay and coalescing */
+	XAxiDma_BdRingSetCoalesce(RxRingPtr, Coalesce, Delay);
+
+	/* Setup Rx BD space */
+	BdCount = XAxiDma_BdRingCntCalc(XAXIDMA_BD_MINIMUM_ALIGNMENT,
+			rx_bd_space_high - rx_bd_space_base + 1);
+
+	Status = XAxiDma_BdRingCreate(RxRingPtr, rx_bd_space_base,
+			rx_bd_space_base,
+				XAXIDMA_BD_MINIMUM_ALIGNMENT, BdCount);
+
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Setup an all-zero BD as the template for the Rx channel.
+	 */
+	XAxiDma_BdClear(&BdTemplate);
+
+	Status = XAxiDma_BdRingClone(RxRingPtr, &BdTemplate);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/* Attach buffers to RxBD ring so we are ready to receive packets
+	 */
+	FreeBdCount = XAxiDma_BdRingGetFreeCnt(RxRingPtr);
+	Status = XAxiDma_BdRingAlloc(RxRingPtr, FreeBdCount, &BdPtr);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	BdCurPtr = BdPtr;
+	RxBufferPtr = rx_buffer_base;
+
+	for (i = 0; i < FreeBdCount; i++) {
+
+		Status = XAxiDma_BdSetBufAddr(BdCurPtr, RxBufferPtr);
+		if (Status != XST_SUCCESS) {
+			xil_printf("Rx set buffer addr %x on BD %x failed %d\r\n",
+			(unsigned int)RxBufferPtr, (UINTPTR)BdCurPtr,
+								Status);
+
+			return XST_FAILURE;
+		}
+
+		Status = XAxiDma_BdSetLength(BdCurPtr, max_pkt_len_rx,
+				RxRingPtr->MaxTransferLen);
+		if (Status != XST_SUCCESS) {
+			xil_printf("Rx set length %d on BD %x failed %d\r\n",
+					max_pkt_len_rx, (UINTPTR)BdCurPtr, Status);
+
+			return XST_FAILURE;
+		}
+
+		/* Receive BDs do not need to set anything for the control
+		 * The hardware will set the SOF/EOF bits per stream status
+		 */
+		XAxiDma_BdSetCtrl(BdPtr, 0);
+		XAxiDma_BdSetId(BdCurPtr, RxBufferPtr);
+		RxBufferPtr += max_pkt_len_rx;
+
+		if (i == (FreeBdCount - 1)) {
+			LastRxBdPtr = BdCurPtr;
+		}
+
+		BdCurPtr = (XAxiDma_Bd *)XAxiDma_BdRingNext(RxRingPtr, BdCurPtr);
+	}
+
+	Status = XAxiDma_BdRingToHw(RxRingPtr, FreeBdCount, BdPtr);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/* Start RX DMA channel */
+	Status = XAxiDma_BdRingStart(RxRingPtr);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets up the TX channel of a DMA engine to be ready for packet
+* transmission
+*
+* @param	AxiDmaInstPtr is the instance pointer to the DMA engine.
+*
+* @return	- XST_SUCCESS if the setup is successful
+*		- XST_FAILURE if setup is failure
+*
+* @note     None.
+*
+******************************************************************************/
+int dma_inst::TxSetup(XAxiDma * AxiDmaInstPtr)
+{
+	XAxiDma_BdRing *TxRingPtr;
+	XAxiDma_Bd BdTemplate;
+	int Delay = 0;
+	int Coalesce = 1;
+	int Status;
+	u32 BdCount;
+
+	TxRingPtr = XAxiDma_GetTxRing(&AxiDma);
+
+	/* Disable all TX interrupts before Tx BD space setup */
+
+	XAxiDma_BdRingIntDisable(TxRingPtr, XAXIDMA_IRQ_ALL_MASK);
+
+	/* Set TX delay and coalesce */
+	XAxiDma_BdRingSetCoalesce(TxRingPtr, Coalesce, Delay);
+
+	/* Setup Tx BD space  */
+	BdCount = XAxiDma_BdRingCntCalc(XAXIDMA_BD_MINIMUM_ALIGNMENT,
+			tx_bd_space_high - tx_bd_space_base + 1);
+
+	Status = XAxiDma_BdRingCreate(TxRingPtr, tx_bd_space_base,
+			tx_bd_space_base,
+				XAXIDMA_BD_MINIMUM_ALIGNMENT, BdCount);
+	if (Status != XST_SUCCESS) {
+		xil_printf("failed create BD ring in txsetup\r\n");
+
+		return XST_FAILURE;
+	}
+
+	/*
+	 * We create an all-zero BD as the template.
+	 */
+	XAxiDma_BdClear(&BdTemplate);
+
+	Status = XAxiDma_BdRingClone(TxRingPtr, &BdTemplate);
+	if (Status != XST_SUCCESS) {
+		xil_printf("failed bdring clone in txsetup %d\r\n", Status);
+
+		return XST_FAILURE;
+	}
+
+	/* Start the TX channel */
+	Status = XAxiDma_BdRingStart(TxRingPtr);
+	if (Status != XST_SUCCESS) {
+		xil_printf("failed start bdring txsetup %d\r\n", Status);
+
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+int dma_inst::WR2TxBuffer()
+{
+	u32 *TxPacket;
+	int i;
+
+	/* Create pattern in the packet to transmit
+	 */
+	TxPacket = Packet;
+
+	for(i = 0; i < 32768; i++) {
+		TxPacket[i]   = i+5;
+	}
+
+	/* Flush the SrcBuffer before the DMA transfer, in case the Data Cache
+	 * is enabled
+	 */
+	Xil_DCacheFlushRange((UINTPTR)TxPacket, max_pkt_len *
+			number_of_packets);
+	#ifdef __aarch64__
+	Xil_DCacheFlushRange((UINTPTR)rx_buffer_base, max_pkt_len *
+			number_of_packets);
+	#endif
+
+	return XST_SUCCESS;
+}
+
+int dma_inst::SendPackets()
+{
+	XAxiDma_BdRing *TxRingPtr;
+	int i;
+	XAxiDma_Bd *BdPtr;
+	int Status;
+	UINTPTR BufAddr;
+	XAxiDma_Bd *CurBdPtr;
+
+
+	TxRingPtr = XAxiDma_GetTxRing(&AxiDma);
+
+	/* Allocate BDs */
+	Status = XAxiDma_BdRingAlloc(TxRingPtr, number_of_packets, &BdPtr);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/* Set up the BDs using the information of the packet to transmit */
+	BufAddr = (UINTPTR)Packet;
+	CurBdPtr = BdPtr;
+
+
+	for (i = 0; i < number_of_packets; i++) {
+		u32 CrBits = 0;
+
+		Status = XAxiDma_BdSetBufAddr(CurBdPtr, BufAddr);
+		if (Status != XST_SUCCESS) {
+			xil_printf("Tx set buffer addr %x on BD %x failed %d\r\n",
+			(unsigned int)BufAddr, (UINTPTR)CurBdPtr, Status);
+
+			return XST_FAILURE;
+		}
+
+		Status = XAxiDma_BdSetLength(CurBdPtr, max_pkt_len,
+				TxRingPtr->MaxTransferLen);
+		if (Status != XST_SUCCESS) {
+			xil_printf("Tx set length %d on BD %x failed %d\r\n",
+					max_pkt_len, (UINTPTR)CurBdPtr, Status);
+
+			return XST_FAILURE;
+		}
+
+		if (i == 0) {
+			CrBits |= XAXIDMA_BD_CTRL_TXSOF_MASK;
+
+#if (XPAR_AXIDMA_0_SG_INCLUDE_STSCNTRL_STRM == 1)
+			/* The first BD has total transfer length set in
+			 * the last APP word, this is for the loopback widget
+			 */
+			Status = XAxiDma_BdSetAppWord(CurBdPtr,
+			    XAXIDMA_LAST_APPWORD,
+			    MAX_PKT_LEN * NUMBER_OF_PACKETS);
+
+			if (Status != XST_SUCCESS) {
+				xil_printf("Set app word failed with %d\r\n",
+								Status);
+			}
+#endif
+		}
+		if (i == (number_of_packets - 1)) {
+			CrBits |= XAXIDMA_BD_CTRL_TXEOF_MASK;
+			XAxiDma_BdSetCtrl(CurBdPtr,
+					XAXIDMA_BD_CTRL_TXEOF_MASK);
+		}
+		XAxiDma_BdSetCtrl(CurBdPtr, CrBits);
+
+		XAxiDma_BdSetId(CurBdPtr, BufAddr);
+
+		BufAddr += max_pkt_len;
+		CurBdPtr = (XAxiDma_Bd *)XAxiDma_BdRingNext(TxRingPtr, CurBdPtr);
+	}
+
+	XTime_GetTime(&StartTotal);
+	/* Give the BD to DMA to kick off the transmission. */
+	Status = XAxiDma_BdRingToHw(TxRingPtr, number_of_packets, BdPtr);
+	if (Status != XST_SUCCESS) {
+		xil_printf("to hw failed %d\r\n", Status);
+
+		return XST_FAILURE;
+	}
+
+
+	return XST_SUCCESS;
+}
+
+int dma_inst::CleanTxBuffer()
+{
+	XAxiDma_BdRing *TxRingPtr;
+	u32 ProcessedBdCount = 0;
+	XAxiDma_Bd *BdPtr;
+	int Status;
+
+	TxRingPtr = XAxiDma_GetTxRing(&AxiDma);
+
+	/* Wait until the TX transactions are done */
+	while (ProcessedBdCount < number_of_packets) {
+		ProcessedBdCount += XAxiDma_BdRingFromHw(TxRingPtr,
+					       XAXIDMA_ALL_BDS, &BdPtr);
+	}
+
+	//XTime_GetTime(&End);
+	//Send_time = ((double)(End - Start) / (COUNTS_PER_SECOND / 1000000));
+
+
+	/* Free all processed TX BDs for future transmission */
+	Status = XAxiDma_BdRingFree(TxRingPtr, ProcessedBdCount, BdPtr);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	//print("DMA send success!\n");
+
+	return Status;
+
+}
+
+int dma_inst::RecvPackets()
+{
+	XAxiDma_BdRing *RxRingPtr;
+
+	RxRingPtr = XAxiDma_GetRxRing(&AxiDma);
+	ProcessedBdCount += XAxiDma_BdRingFromHw(RxRingPtr,
+					   XAXIDMA_ALL_BDS, &BdPtrGlobal);
+	xil_printf("Recv begin!\r\n");
+}
+
+
+int dma_inst::RecvWait()
+{
+	XAxiDma_BdRing *RxRingPtr;
+
+
+	RxRingPtr = XAxiDma_GetRxRing(&AxiDma);
+
+	//XTime_GetTime(&Start);
+	//Xil_Out32(SLV_REG4, 1);
+	//printf("SLV_REG4: %x\n", Xil_In32(SLV_REG4));
+	/* Wait until the data has been received by the Rx channel */
+	int total = 0;
+	while (ProcessedBdCount < number_of_packets_rx) {
+
+		ProcessedBdCount += XAxiDma_BdRingFromHw(RxRingPtr,
+					       XAXIDMA_ALL_BDS, &BdPtrGlobal);
+		if(total<10)
+			printf("ProcessedBdCount=%x\n", ProcessedBdCount);
+		total++;
+	}
+
+	XTime_GetTime(&EndTotal);
+	//EndTotal = End;
+	//Recv_time = ((double)(End - Start) / (COUNTS_PER_SECOND / 1000000));
+	//Total_time = (double)(EndTotal - StartTotal);
+	return XST_SUCCESS;
+}
+
+
+
+int dma_inst::CheckData(void)
+{
+	u32 *RxPacket;
+	int i = 0;
+	int j = 0;
+	RxPacket = (u32 *) rx_buffer_base;
+
+	/* Invalidate the DestBuffer before receiving the data, in case the
+	 * Data Cache is enabled
+	 */
+#ifndef __aarch64__
+	Xil_DCacheInvalidateRange((UINTPTR)RxPacket, MAX_PKT_LEN *
+								NUMBER_OF_PACKETS);
+#endif
+
+	int err_cnt = 0;
+	for(i = 32767; i < 32768; i++) {
+			printf("i= %d Rx = %d\n", i, RxPacket[i]);
+	}
+	printf("We got %d errors!\n", err_cnt);
+
+
+
+	return XST_SUCCESS;
+}
+
+
+
+
+int dma_inst::CleanRxBuffer()
+{
+	XAxiDma_BdRing *RxRingPtr;
+	u32 FreeBdCount;
+	int Status;
+
+	RxRingPtr = XAxiDma_GetRxRing(&AxiDma);
+
+	/* Free all processed RX BDs for future transmission */
+	Status = XAxiDma_BdRingFree(RxRingPtr, ProcessedBdCount, BdPtrGlobal);
+	if (Status != XST_SUCCESS) {
+		xil_printf("free bd failed\r\n");
+		return XST_FAILURE;
+	}
+
+	/* Return processed BDs to RX channel so we are ready to receive new
+	 * packets:
+	 *    - Allocate all free RX BDs
+	 *    - Pass the BDs to RX channel
+	 */
+	FreeBdCount = XAxiDma_BdRingGetFreeCnt(RxRingPtr);
+	Status = XAxiDma_BdRingAlloc(RxRingPtr, FreeBdCount, &BdPtrGlobal);
+	if (Status != XST_SUCCESS) {
+		xil_printf("bd alloc failed\r\n");
+		return XST_FAILURE;
+	}
+
+	Status = XAxiDma_BdRingToHw(RxRingPtr, FreeBdCount, BdPtrGlobal);
+
+	return Status;
+}
+
+
+
+
+int dma_inst::run_dma(void)
+{
+	int Status;
+
+	/* Send packets */
+	Status = SendPackets();
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	if (Status != XST_SUCCESS) {
+		xil_printf("AXI DMA poll multi Example Failed\r\n");
+		return XST_FAILURE;
+	}
+
+	xil_printf("Successfully ran AXI DMA poll multi Example\r\n");
+	xil_printf("--- Exiting main() --- \r\n");
+
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+}
+
+dma_inst::dma_inst(u32 DMA_DEV_ID_in,
+		 u32 RX_BD_SPACE_HIGH_in,
+		 u32 RX_BD_SPACE_BASE_in,
+		 u32 MAX_PKT_LEN_in,
+		 u32 MAX_PKT_LEN_RX_in,
+		 u32 TX_BD_SPACE_HIGH_in,
+		 u32 TX_BD_SPACE_BASE_in,
+		 u32 NUMBER_OF_PACKETS_in,
+		 u32 NUMBER_OF_PACKETS_RX_in,
+		 u32 RX_BUFFER_BASE_in,
+		 u32 TX_BUFFER_BASE_in)
+{
+	this->dma_dev_id = DMA_DEV_ID_in;
+	this->rx_bd_space_high = RX_BD_SPACE_HIGH_in;
+	this->rx_bd_space_base = RX_BD_SPACE_BASE_in;
+	this->max_pkt_len = MAX_PKT_LEN_in;
+	this->max_pkt_len_rx = MAX_PKT_LEN_RX_in;
+	this->tx_bd_space_high = TX_BD_SPACE_HIGH_in;
+	this->tx_bd_space_base = TX_BD_SPACE_BASE_in;
+	this->number_of_packets = NUMBER_OF_PACKETS_in;
+	this->number_of_packets_rx = NUMBER_OF_PACKETS_RX_in;
+	this->rx_buffer_base = RX_BUFFER_BASE_in;
+	this->Packet = (u32 *) TX_BUFFER_BASE_in;
+	this->test_start_value = 0xC;
+	this->ProcessedBdCount = 0;
+	/*
+	printf("this->dma_dev_id=%x\r\n",this->dma_dev_id);
+	printf("this->rx_bd_space_high=%x\r\n",this->rx_bd_space_high);
+	printf("this->rx_bd_space_base=%x\r\n",this->rx_bd_space_base);
+	printf("this->max_pkt_len=%x\r\n",this->max_pkt_len);
+	printf("this->tx_bd_space_high=%x\r\n",this->tx_bd_space_high);
+	printf("this->tx_bd_space_base=%x\r\n",this->tx_bd_space_base);
+	printf("this->number_of_packets=%x\r\n",this->number_of_packets);
+	printf("this->rx_buffer_base=%x\r\n",this->rx_buffer_base);
+	printf("this->Packet=%x\r\n",this->Packet);
+	*/
+}
+
+int dma_inst::dma_init()
+{
+
+	int Status;
+	XAxiDma_Config *Config;
+
+#if defined(XPAR_UARTNS550_0_BASEADDR)
+
+	Uart550_Setup();
+
+#endif
+
+	xil_printf("\r\n--- Entering main() --- \r\n");
+#ifdef __aarch64__
+	Xil_SetTlbAttributes(tx_bd_space_base, NORM_NONCACHE);
+	Xil_SetTlbAttributes(rx_bd_space_base, NORM_NONCACHE);
+#endif
+
+	Config = XAxiDma_LookupConfig(dma_dev_id);
+	if (!Config) {
+		xil_printf("No config found for %d\r\n", dma_dev_id);
+		return XST_FAILURE;
+	}
+
+	/* Initialize DMA engine */
+	Status = XAxiDma_CfgInitialize(&AxiDma, Config);
+	if (Status != XST_SUCCESS) {
+		xil_printf("Initialization failed %d\r\n", Status);
+		return XST_FAILURE;
+	}
+
+	if(!XAxiDma_HasSg(&AxiDma)) {
+		xil_printf("Device configured as simple mode \r\n");
+		return XST_FAILURE;
+	}
+
+	Status = TxSetup(&AxiDma);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	Status = RxSetup(&AxiDma);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	return Status;
+}
+
+
+int dma_inst::print_results()
+{
+	//printf("DMA Send Time: %.2lfus\n", Send_time);
+	//printf("DMA Send Throughput: %.2lfMB/s\n", (float)max_pkt_len*number_of_packets/Send_time);
+	//printf("DMA Recv Time: %.2lfus\n", Recv_time);
+	//printf("DMA Recv Throughput: %.2lfMB/s\n", (float)max_pkt_len*number_of_packets/Recv_time);
+	Total_time = ((double)(EndTotal - StartTotal) / (COUNTS_PER_SECOND / 1000000));
+	double Tpt_tx = max_pkt_len*number_of_packets/Total_time;
+	double Tpt_rx = max_pkt_len_rx*number_of_packets_rx/Total_time;
+	printf("Overall Time: %.2lf us\n", Total_time);
+	printf("Tx throughput: %.2lf MB/s\n", Tpt_tx);
+	printf("Rx throughput: %.2lf MB/s\n", Tpt_rx);
+	return XST_SUCCESS;
+}
diff --git a/benchmarks/vivado_flow/vck5000_dfx/c/dma/dma_driver.h b/benchmarks/vivado_flow/vck5000_dfx/c/dma/dma_driver.h
new file mode 100644
index 00000000..f03b7803
--- /dev/null
+++ b/benchmarks/vivado_flow/vck5000_dfx/c/dma/dma_driver.h
@@ -0,0 +1,98 @@
+// Copyright (c) 2024 RapidStream Design Automation, Inc. and contributors.  All rights reserved.
+// The contributor(s) of this file has/have agreed to the RapidStream Contributor License Agreement.
+
+#include "xaxidma.h"
+#include "xparameters.h"
+#include "xdebug.h"
+#include "xtime_l.h"
+#include "stdio.h"
+#include "sleep.h"
+#ifdef __aarch64__
+#include "xil_mmu.h"
+#endif
+
+//width of a packet is 49 bits
+//bft2arm_packet = {1'b1, SLV_REG1[15:0], SLV_REG0[31:0]}
+//arm2bft_packet = {SLV_REG5[16:0], SLV_REG4[31:0]}
+//input fifo empty = SLV_REG3[1]
+//output fifo full = SLV_REG3[0]
+//input fifo rd_en = SLV_REG7[1]
+#if defined(XPAR_UARTNS550_0_BASEADDR)
+#include "xuartns550_l.h"       /* to use uartns550 */
+#endif
+
+#ifndef DEBUG
+extern void xil_printf(const char *format, ...);
+#endif
+
+
+
+void read_from_fifo(int * ctrl_reg);
+
+void write_to_fifo(int high_32_bits, int low_32_bits, int * ctrl_reg);
+
+void init_regs();
+
+int stream_op(int op_type, int i);
+
+int run_dma(void);
+
+
+class dma_inst{
+
+public:
+	XTime Start, End;
+	XTime StartTotal, EndTotal;
+	double Send_time;
+	double Recv_time;
+	double Total_time;
+	XAxiDma AxiDma;
+	u32 *Packet;
+	XAxiDma_Bd *LastRxBdPtr = NULL;
+	dma_inst(u32 DMA_DEV_ID_in,
+			 u32 RX_BD_SPACE_HIGH_in,
+			 u32 RX_BD_SPACE_BASE_in,
+			 u32 MAX_PKT_LEN_in,
+			 u32 MAX_PKT_LEN_RX_in,
+			 u32 TX_BD_SPACE_HIGH_in,
+			 u32 TX_BD_SPACE_BASE_in,
+			 u32 NUMBER_OF_PACKETS_in,
+			 u32 NUMBER_OF_PACKETS_RX_in,
+			 u32 RX_BUFFER_BASE_in,
+			 u32 TX_BUFFER_BASE_in);
+	u32 dma_dev_id;
+	u32 rx_bd_space_high;
+	u32 rx_bd_space_base;
+	u32 max_pkt_len;
+	u32 max_pkt_len_rx;
+	u32 tx_bd_space_high;
+	u32 tx_bd_space_base;
+	u32 number_of_packets;
+	u32 number_of_packets_rx;
+	u32 test_start_value;
+	u32 rx_buffer_base;
+	XAxiDma_Bd *BdPtrGlobal;
+	u32 ProcessedBdCount;
+
+	int RxSetup(XAxiDma * AxiDmaInstPtr);
+	int TxSetup(XAxiDma * AxiDmaInstPtr);
+
+	int dma_init();
+	int WR2TxBuffer();
+	int SendPackets();
+	int CleanTxBuffer();
+	int RecvPackets();
+	int RecvWait();
+	int CheckData();
+	int CleanRxBuffer();
+	int run_dma(void);
+	int print_results();
+
+
+private:
+
+
+
+
+
+};
diff --git a/benchmarks/vivado_flow/vck5000_dfx/c/dma/host.cpp b/benchmarks/vivado_flow/vck5000_dfx/c/dma/host.cpp
new file mode 100644
index 00000000..4683a7c4
--- /dev/null
+++ b/benchmarks/vivado_flow/vck5000_dfx/c/dma/host.cpp
@@ -0,0 +1,96 @@
+#include "xparameters.h"	/* SDK generated parameters */
+//#include "xrtcpsu.h"		/* RTCPSU device driver */
+//#include "xscugic.h"		/* Interrupt controller device driver */
+//#include "xil_exception.h"
+//#include "xil_printf.h"
+
+#include "dma_driver.h"
+#include "typedefs.h"
+#include "sleep.h"
+
+
+
+
+int main(void)
+{
+	int Status;
+	printf("Initialization Completed\n\r");
+
+	dma_inst dma1(DMA_DEV_ID,
+			 RX_BD_SPACE_HIGH,
+			 RX_BD_SPACE_BASE,
+			 MAX_PKT_LEN,
+			 MAX_PKT_LEN_RX,
+			 TX_BD_SPACE_HIGH,
+			 TX_BD_SPACE_BASE,
+			 NUMBER_OF_PACKETS,
+			 NUMBER_OF_PACKETS_RX,
+			 RX_BUFFER_BASE,
+			 TX_BUFFER_BASE);
+
+	Status = dma1.dma_init();
+	if (Status != XST_SUCCESS) {
+		xil_printf("Device Initiation Failed!\r\n");
+		return XST_FAILURE;
+	}
+
+	Status = dma1.RecvPackets();
+		if (Status != XST_SUCCESS) {
+			xil_printf("Receiving Packets Failed!\r\n");
+			return XST_FAILURE;
+	}
+
+	Status = dma1.WR2TxBuffer();
+	if (Status != XST_SUCCESS) {
+		xil_printf("Write Buffer Failed!\r\n");
+		return XST_FAILURE;
+	}
+
+	Status = dma1.SendPackets();
+	if (Status != XST_SUCCESS) {
+		xil_printf("Sending Packets Failed!\r\n");
+		return XST_FAILURE;
+	}
+
+	Status = dma1.CleanTxBuffer();
+	if (Status != XST_SUCCESS) {
+		xil_printf("Cleaning TxBuffer Failed!\r\n");
+		return XST_FAILURE;
+	}
+
+	Status = dma1.RecvWait();
+	if (Status != XST_SUCCESS) {
+		xil_printf("Receiving Waits Failed!\r\n");
+		return XST_FAILURE;
+	}
+
+	Status = dma1.CheckData();
+	if (Status != XST_SUCCESS) {
+		xil_printf("Checking Data Failed!\r\n");
+		return XST_FAILURE;
+	}
+
+	Status = dma1.print_results();
+	if (Status != XST_SUCCESS) {
+		xil_printf("Printing results Failed!\r\n");
+		return XST_FAILURE;
+	}
+
+	Status = dma1.CleanRxBuffer();
+	if (Status != XST_SUCCESS) {
+		xil_printf("Cleaning RxBuffer Failed!\r\n");
+		return XST_FAILURE;
+	}
+
+
+
+	for(int i=0; i<10; i++){
+		sleep(1);
+		//printf("%d seconds\n", i);
+	}
+
+
+	xil_printf("Successfully ran RTC Seconds Interrupt Example Test\r\n");
+	xil_printf("Optical_flow is completed\n\r");
+	return XST_SUCCESS;
+}
diff --git a/benchmarks/vivado_flow/vck5000_dfx/c/dma/typedefs.h b/benchmarks/vivado_flow/vck5000_dfx/c/dma/typedefs.h
new file mode 100644
index 00000000..67aac845
--- /dev/null
+++ b/benchmarks/vivado_flow/vck5000_dfx/c/dma/typedefs.h
@@ -0,0 +1,96 @@
+// Copyright (c) 2024 RapidStream Design Automation, Inc. and contributors.  All rights reserved.
+// The contributor(s) of this file has/have agreed to the RapidStream Contributor License Agreement.
+
+#include "xrtcpsu.h"		/* RTCPSU device driver */
+
+
+#include "xscugic.h"		/* Interrupt controller device driver */
+#include "xil_exception.h"
+#include "xil_printf.h"
+
+
+#define RTC_DEVICE_ID         XPAR_XRTCPSU_0_DEVICE_ID
+#define INTC_DEVICE_ID			XPAR_SCUGIC_SINGLE_DEVICE_ID
+#define RTC_SEC_INT_IRQ_ID	XPAR_XRTCPSU_SECONDS_INTR
+
+#define REPETATIONS 10
+
+#define DMA_BASE_ADDR       XPAR_AXIDMA_0_BASEADDR
+#define DMA_DEV_ID          XPAR_AXIDMA_0_DEVICE_ID
+
+#ifdef XPAR_AXI_7SDDR_0_S_AXI_BASEADDR
+#define DDR_BASE_ADDR       XPAR_AXI_7SDDR_0_S_AXI_BASEADDR
+#elif XPAR_MIG7SERIES_0_BASEADDR
+#define DDR_BASE_ADDR       XPAR_MIG7SERIES_0_BASEADDR
+#elif XPAR_MIG_0_BASEADDR
+#define DDR_BASE_ADDR       XPAR_MIG_0_BASEADDR
+#elif XPAR_PSU_DDR_0_S_AXI_BASEADDR
+#define DDR_BASE_ADDR       XPAR_PSU_DDR_0_S_AXI_BASEADDR
+#endif
+
+
+/******************** Constant Definitions **********************************/
+
+/*********************** TEMPORARY ******************************************/
+/*
+ * Device hardware build related constants.
+ */
+#define DMA_BASE_ADDR       XPAR_AXIDMA_0_BASEADDR
+#define DMA_DEV_ID          XPAR_AXIDMA_0_DEVICE_ID
+
+#ifdef XPAR_AXI_7SDDR_0_S_AXI_BASEADDR
+#define DDR_BASE_ADDR       XPAR_AXI_7SDDR_0_S_AXI_BASEADDR
+#elif XPAR_MIG7SERIES_0_BASEADDR
+#define DDR_BASE_ADDR       XPAR_MIG7SERIES_0_BASEADDR
+#elif XPAR_MIG_0_BASEADDR
+#define DDR_BASE_ADDR       XPAR_MIG_0_BASEADDR
+#elif XPAR_PSU_DDR_0_S_AXI_BASEADDR
+#define DDR_BASE_ADDR       XPAR_PSU_DDR_0_S_AXI_BASEADDR
+#endif
+
+#ifndef DDR_BASE_ADDR
+#warning CHECK FOR THE VALID DDR ADDRESS IN XPARAMETERS.H, \
+		DEFAULT SET TO 0x01000000
+#define MEM_BASE_ADDR       0x01000000
+#else
+#define MEM_BASE_ADDR      (DDR_BASE_ADDR + 0x1000000)
+#endif
+
+
+// 8 MB for tx ring buffer
+#define TX_BD_SPACE_BASE	(MEM_BASE_ADDR)
+#define TX_BD_SPACE_HIGH	(MEM_BASE_ADDR + 0x007FFFFF)
+
+// 8 MB for rx ring buffer
+#define RX_BD_SPACE_BASE	(MEM_BASE_ADDR + 0x00800000)
+#define RX_BD_SPACE_HIGH	(MEM_BASE_ADDR + 0x00FFFFFF)
+
+// 240 MB for tx_buffer
+#define TX_BUFFER_BASE		(MEM_BASE_ADDR + 0x01000000)
+
+// 240 MB for RX buffer
+#define RX_BUFFER_BASE		(MEM_BASE_ADDR + 0x10000000)
+#define RX_BUFFER_HIGH		(MEM_BASE_ADDR + 0x1EFFFFFF)
+
+
+#define MAX_PKT_LEN		0x2000
+//#define NUMBER_OF_PACKETS 	0x400
+#define NUMBER_OF_PACKETS 	0x10
+
+#define MAX_PKT_LEN_RX		0x2000
+//#define NUMBER_OF_PACKETS 	0x400
+#define NUMBER_OF_PACKETS_RX 	0x10
+
+
+#define TEST_START_VALUE	0xC
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+#if defined(XPAR_UARTNS550_0_BASEADDR)
+static void Uart550_Setup(void);
+#endif
diff --git a/benchmarks/vivado_flow/vck5000_dfx/c/src/README.txt b/benchmarks/vivado_flow/vck5000_dfx/c/src/README.txt
deleted file mode 100644
index 7260f5fa..00000000
--- a/benchmarks/vivado_flow/vck5000_dfx/c/src/README.txt
+++ /dev/null
@@ -1,3 +0,0 @@
-# Copyright (c) 2024 RapidStream Design Automation, Inc. and contributors.  All rights reserved.
-# The contributor(s) of this file has/have agreed to the RapidStream Contributor License Agreement.
-Empty application. Add your own sources.
diff --git a/benchmarks/vivado_flow/vck5000_dfx/tcl/design_1.tcl b/benchmarks/vivado_flow/vck5000_dfx/tcl/design_1.tcl
index a338f36e..beff9a99 100644
--- a/benchmarks/vivado_flow/vck5000_dfx/tcl/design_1.tcl
+++ b/benchmarks/vivado_flow/vck5000_dfx/tcl/design_1.tcl
@@ -310,26 +310,208 @@ proc create_root_design { parentCell } {
   set_property -dict [list \
     CONFIG.NUM_MI {0} \
     CONFIG.NUM_NMI {1} \
-    CONFIG.NUM_SI {2} \
+    CONFIG.NUM_SI {28} \
   ] $axi_noc_1
 
 
   set_property -dict [ list \
-   CONFIG.CONNECTIONS {M00_INI {read_bw {1720} write_bw {1720} read_avg_burst {4} write_avg_burst {4}}} \
+   CONFIG.CONNECTIONS {M00_INI { read_bw {100} write_bw {100} read_avg_burst {4} write_avg_burst {4}}} \
    CONFIG.DEST_IDS {} \
    CONFIG.NOC_PARAMS {} \
    CONFIG.CATEGORY {pl} \
  ] [get_bd_intf_pins /axi_noc_1/S00_AXI]
 
   set_property -dict [ list \
-   CONFIG.CONNECTIONS {M00_INI { read_bw {1720} write_bw {1720}}} \
+   CONFIG.CONNECTIONS {M00_INI { read_bw {100} write_bw {100} read_avg_burst {4} write_avg_burst {4}}} \
    CONFIG.DEST_IDS {} \
    CONFIG.NOC_PARAMS {} \
    CONFIG.CATEGORY {pl} \
  ] [get_bd_intf_pins /axi_noc_1/S01_AXI]
 
   set_property -dict [ list \
-   CONFIG.ASSOCIATED_BUSIF {S00_AXI:S01_AXI} \
+   CONFIG.CONNECTIONS {M00_INI { read_bw {100} write_bw {100} read_avg_burst {4} write_avg_burst {4}}} \
+   CONFIG.DEST_IDS {} \
+   CONFIG.NOC_PARAMS {} \
+   CONFIG.CATEGORY {pl} \
+ ] [get_bd_intf_pins /axi_noc_1/S02_AXI]
+
+  set_property -dict [ list \
+   CONFIG.CONNECTIONS {M00_INI { read_bw {100} write_bw {100} read_avg_burst {4} write_avg_burst {4}}} \
+   CONFIG.DEST_IDS {} \
+   CONFIG.NOC_PARAMS {} \
+   CONFIG.CATEGORY {pl} \
+ ] [get_bd_intf_pins /axi_noc_1/S03_AXI]
+
+  set_property -dict [ list \
+   CONFIG.CONNECTIONS {M00_INI { read_bw {100} write_bw {100} read_avg_burst {4} write_avg_burst {4}}} \
+   CONFIG.DEST_IDS {} \
+   CONFIG.NOC_PARAMS {} \
+   CONFIG.CATEGORY {pl} \
+ ] [get_bd_intf_pins /axi_noc_1/S04_AXI]
+
+  set_property -dict [ list \
+   CONFIG.CONNECTIONS {M00_INI { read_bw {100} write_bw {100} read_avg_burst {4} write_avg_burst {4}}} \
+   CONFIG.DEST_IDS {} \
+   CONFIG.NOC_PARAMS {} \
+   CONFIG.CATEGORY {pl} \
+ ] [get_bd_intf_pins /axi_noc_1/S05_AXI]
+
+  set_property -dict [ list \
+   CONFIG.CONNECTIONS {M00_INI { read_bw {100} write_bw {100} read_avg_burst {4} write_avg_burst {4}}} \
+   CONFIG.DEST_IDS {} \
+   CONFIG.NOC_PARAMS {} \
+   CONFIG.CATEGORY {pl} \
+ ] [get_bd_intf_pins /axi_noc_1/S06_AXI]
+
+  set_property -dict [ list \
+   CONFIG.CONNECTIONS {M00_INI { read_bw {100} write_bw {100} read_avg_burst {4} write_avg_burst {4}}} \
+   CONFIG.DEST_IDS {} \
+   CONFIG.NOC_PARAMS {} \
+   CONFIG.CATEGORY {pl} \
+ ] [get_bd_intf_pins /axi_noc_1/S07_AXI]
+
+  set_property -dict [ list \
+   CONFIG.CONNECTIONS {M00_INI { read_bw {100} write_bw {100} read_avg_burst {4} write_avg_burst {4}}} \
+   CONFIG.DEST_IDS {} \
+   CONFIG.NOC_PARAMS {} \
+   CONFIG.CATEGORY {pl} \
+ ] [get_bd_intf_pins /axi_noc_1/S08_AXI]
+
+  set_property -dict [ list \
+   CONFIG.CONNECTIONS {M00_INI { read_bw {100} write_bw {100} read_avg_burst {4} write_avg_burst {4}}} \
+   CONFIG.DEST_IDS {} \
+   CONFIG.NOC_PARAMS {} \
+   CONFIG.CATEGORY {pl} \
+ ] [get_bd_intf_pins /axi_noc_1/S09_AXI]
+
+  set_property -dict [ list \
+   CONFIG.CONNECTIONS {M00_INI { read_bw {100} write_bw {100} read_avg_burst {4} write_avg_burst {4}}} \
+   CONFIG.DEST_IDS {} \
+   CONFIG.NOC_PARAMS {} \
+   CONFIG.CATEGORY {pl} \
+ ] [get_bd_intf_pins /axi_noc_1/S10_AXI]
+
+  set_property -dict [ list \
+   CONFIG.CONNECTIONS {M00_INI { read_bw {100} write_bw {100} read_avg_burst {4} write_avg_burst {4}}} \
+   CONFIG.DEST_IDS {} \
+   CONFIG.NOC_PARAMS {} \
+   CONFIG.CATEGORY {pl} \
+ ] [get_bd_intf_pins /axi_noc_1/S11_AXI]
+
+  set_property -dict [ list \
+   CONFIG.CONNECTIONS {M00_INI { read_bw {100} write_bw {100} read_avg_burst {4} write_avg_burst {4}}} \
+   CONFIG.DEST_IDS {} \
+   CONFIG.NOC_PARAMS {} \
+   CONFIG.CATEGORY {pl} \
+ ] [get_bd_intf_pins /axi_noc_1/S12_AXI]
+
+  set_property -dict [ list \
+   CONFIG.CONNECTIONS {M00_INI { read_bw {100} write_bw {100} read_avg_burst {4} write_avg_burst {4}}} \
+   CONFIG.DEST_IDS {} \
+   CONFIG.NOC_PARAMS {} \
+   CONFIG.CATEGORY {pl} \
+ ] [get_bd_intf_pins /axi_noc_1/S13_AXI]
+
+  set_property -dict [ list \
+   CONFIG.CONNECTIONS {M00_INI { read_bw {100} write_bw {100} read_avg_burst {4} write_avg_burst {4}}} \
+   CONFIG.DEST_IDS {} \
+   CONFIG.NOC_PARAMS {} \
+   CONFIG.CATEGORY {pl} \
+ ] [get_bd_intf_pins /axi_noc_1/S14_AXI]
+
+  set_property -dict [ list \
+   CONFIG.CONNECTIONS {M00_INI { read_bw {100} write_bw {100} read_avg_burst {4} write_avg_burst {4}}} \
+   CONFIG.DEST_IDS {} \
+   CONFIG.NOC_PARAMS {} \
+   CONFIG.CATEGORY {pl} \
+ ] [get_bd_intf_pins /axi_noc_1/S15_AXI]
+
+  set_property -dict [ list \
+   CONFIG.CONNECTIONS {M00_INI { read_bw {100} write_bw {100} read_avg_burst {4} write_avg_burst {4}}} \
+   CONFIG.DEST_IDS {} \
+   CONFIG.NOC_PARAMS {} \
+   CONFIG.CATEGORY {pl} \
+ ] [get_bd_intf_pins /axi_noc_1/S16_AXI]
+
+  set_property -dict [ list \
+   CONFIG.CONNECTIONS {M00_INI { read_bw {100} write_bw {100} read_avg_burst {4} write_avg_burst {4}}} \
+   CONFIG.DEST_IDS {} \
+   CONFIG.NOC_PARAMS {} \
+   CONFIG.CATEGORY {pl} \
+ ] [get_bd_intf_pins /axi_noc_1/S17_AXI]
+
+  set_property -dict [ list \
+   CONFIG.CONNECTIONS {M00_INI { read_bw {100} write_bw {100} read_avg_burst {4} write_avg_burst {4}}} \
+   CONFIG.DEST_IDS {} \
+   CONFIG.NOC_PARAMS {} \
+   CONFIG.CATEGORY {pl} \
+ ] [get_bd_intf_pins /axi_noc_1/S18_AXI]
+
+  set_property -dict [ list \
+   CONFIG.CONNECTIONS {M00_INI { read_bw {100} write_bw {100} read_avg_burst {4} write_avg_burst {4}}} \
+   CONFIG.DEST_IDS {} \
+   CONFIG.NOC_PARAMS {} \
+   CONFIG.CATEGORY {pl} \
+ ] [get_bd_intf_pins /axi_noc_1/S19_AXI]
+
+  set_property -dict [ list \
+   CONFIG.CONNECTIONS {M00_INI { read_bw {100} write_bw {100} read_avg_burst {4} write_avg_burst {4}}} \
+   CONFIG.DEST_IDS {} \
+   CONFIG.NOC_PARAMS {} \
+   CONFIG.CATEGORY {pl} \
+ ] [get_bd_intf_pins /axi_noc_1/S20_AXI]
+
+  set_property -dict [ list \
+   CONFIG.CONNECTIONS {M00_INI { read_bw {100} write_bw {100} read_avg_burst {4} write_avg_burst {4}}} \
+   CONFIG.DEST_IDS {} \
+   CONFIG.NOC_PARAMS {} \
+   CONFIG.CATEGORY {pl} \
+ ] [get_bd_intf_pins /axi_noc_1/S21_AXI]
+
+  set_property -dict [ list \
+   CONFIG.CONNECTIONS {M00_INI { read_bw {100} write_bw {100} read_avg_burst {4} write_avg_burst {4}}} \
+   CONFIG.DEST_IDS {} \
+   CONFIG.NOC_PARAMS {} \
+   CONFIG.CATEGORY {pl} \
+ ] [get_bd_intf_pins /axi_noc_1/S22_AXI]
+
+  set_property -dict [ list \
+   CONFIG.CONNECTIONS {M00_INI { read_bw {100} write_bw {100} read_avg_burst {4} write_avg_burst {4}}} \
+   CONFIG.DEST_IDS {} \
+   CONFIG.NOC_PARAMS {} \
+   CONFIG.CATEGORY {pl} \
+ ] [get_bd_intf_pins /axi_noc_1/S23_AXI]
+
+  set_property -dict [ list \
+   CONFIG.CONNECTIONS {M00_INI { read_bw {100} write_bw {100} read_avg_burst {4} write_avg_burst {4}}} \
+   CONFIG.DEST_IDS {} \
+   CONFIG.NOC_PARAMS {} \
+   CONFIG.CATEGORY {pl} \
+ ] [get_bd_intf_pins /axi_noc_1/S24_AXI]
+
+  set_property -dict [ list \
+   CONFIG.CONNECTIONS {M00_INI { read_bw {100} write_bw {100} read_avg_burst {4} write_avg_burst {4}}} \
+   CONFIG.DEST_IDS {} \
+   CONFIG.NOC_PARAMS {} \
+   CONFIG.CATEGORY {pl} \
+ ] [get_bd_intf_pins /axi_noc_1/S25_AXI]
+
+  set_property -dict [ list \
+   CONFIG.CONNECTIONS {M00_INI { read_bw {100} write_bw {100} read_avg_burst {4} write_avg_burst {4}}} \
+   CONFIG.DEST_IDS {} \
+   CONFIG.NOC_PARAMS {} \
+   CONFIG.CATEGORY {pl} \
+ ] [get_bd_intf_pins /axi_noc_1/S26_AXI]
+
+  set_property -dict [ list \
+   CONFIG.CONNECTIONS {M00_INI { read_bw {100} write_bw {100} read_avg_burst {4} write_avg_burst {4}}} \
+   CONFIG.DEST_IDS {} \
+   CONFIG.NOC_PARAMS {} \
+   CONFIG.CATEGORY {pl} \
+ ] [get_bd_intf_pins /axi_noc_1/S27_AXI]
+
+  set_property -dict [ list \
+   CONFIG.ASSOCIATED_BUSIF {S00_AXI:S01_AXI:S02_AXI:S03_AXI:S04_AXI:S05_AXI:S06_AXI:S07_AXI:S08_AXI:S09_AXI:S10_AXI:S11_AXI:S12_AXI:S13_AXI:S14_AXI:S15_AXI:S16_AXI:S17_AXI:S18_AXI:S19_AXI:S20_AXI:S21_AXI:S22_AXI:S23_AXI:S24_AXI:S25_AXI:S26_AXI:S27_AXI} \
  ] [get_bd_pins /axi_noc_1/aclk0]
 
   # Create instance: proc_sys_reset_0, and set properties
@@ -355,17 +537,120 @@ proc create_root_design { parentCell } {
    }
 
   set_property -dict [ list \
-   CONFIG.FREQ_HZ {99999001} \
+   CONFIG.FREQ_HZ {249997498} \
    CONFIG.CLK_DOMAIN {bd_70da_pspmc_0_0_pl0_ref_clk} \
  ] [get_bd_intf_pins /vadd_bw_0/m_axi_rmem0]
 
   set_property -dict [ list \
-   CONFIG.FREQ_HZ {99999001} \
-   CONFIG.CLK_DOMAIN {bd_70da_pspmc_0_0_pl0_ref_clk} \
- ] [get_bd_intf_pins /vadd_bw_0/m_axi_wmem0]
+   CONFIG.FREQ_HZ {249997498} \
+ ] [get_bd_intf_pins /vadd_bw_0/m_axi_rmem1]
+
+  set_property -dict [ list \
+   CONFIG.FREQ_HZ {249997498} \
+ ] [get_bd_intf_pins /vadd_bw_0/m_axi_rmem2]
+
+  set_property -dict [ list \
+   CONFIG.FREQ_HZ {249997498} \
+ ] [get_bd_intf_pins /vadd_bw_0/m_axi_rmem3]
+
+  set_property -dict [ list \
+   CONFIG.FREQ_HZ {249997498} \
+ ] [get_bd_intf_pins /vadd_bw_0/m_axi_rmem4]
+
+  set_property -dict [ list \
+   CONFIG.FREQ_HZ {249997498} \
+ ] [get_bd_intf_pins /vadd_bw_0/m_axi_rmem5]
 
   set_property -dict [ list \
-   CONFIG.FREQ_HZ {99999001} \
+   CONFIG.FREQ_HZ {249997498} \
+ ] [get_bd_intf_pins /vadd_bw_0/m_axi_rmem6]
+
+  set_property -dict [ list \
+   CONFIG.FREQ_HZ {249997498} \
+ ] [get_bd_intf_pins /vadd_bw_0/m_axi_rmem7]
+
+  set_property -dict [ list \
+   CONFIG.FREQ_HZ {249997498} \
+ ] [get_bd_intf_pins /vadd_bw_0/m_axi_rmem8]
+
+  set_property -dict [ list \
+   CONFIG.FREQ_HZ {249997498} \
+ ] [get_bd_intf_pins /vadd_bw_0/m_axi_rmem9]
+
+  set_property -dict [ list \
+   CONFIG.FREQ_HZ {249997498} \
+ ] [get_bd_intf_pins /vadd_bw_0/m_axi_rmem10]
+
+  set_property -dict [ list \
+   CONFIG.FREQ_HZ {249997498} \
+ ] [get_bd_intf_pins /vadd_bw_0/m_axi_rmem11]
+
+  set_property -dict [ list \
+   CONFIG.FREQ_HZ {249997498} \
+ ] [get_bd_intf_pins /vadd_bw_0/m_axi_rmem12]
+
+  set_property -dict [ list \
+   CONFIG.FREQ_HZ {249997498} \
+ ] [get_bd_intf_pins /vadd_bw_0/m_axi_rmem13]
+
+  set_property -dict [ list \
+   CONFIG.FREQ_HZ {249997498} \
+ ] [get_bd_intf_pins /vadd_bw_0/m_axi_rmem14]
+
+  set_property -dict [ list \
+   CONFIG.FREQ_HZ {249997498} \
+ ] [get_bd_intf_pins /vadd_bw_0/m_axi_rmem15]
+
+  set_property -dict [ list \
+   CONFIG.FREQ_HZ {249997498} \
+ ] [get_bd_intf_pins /vadd_bw_0/m_axi_rmem16]
+
+  set_property -dict [ list \
+   CONFIG.FREQ_HZ {249997498} \
+ ] [get_bd_intf_pins /vadd_bw_0/m_axi_rmem17]
+
+  set_property -dict [ list \
+   CONFIG.FREQ_HZ {249997498} \
+ ] [get_bd_intf_pins /vadd_bw_0/m_axi_rmem18]
+
+  set_property -dict [ list \
+   CONFIG.FREQ_HZ {249997498} \
+ ] [get_bd_intf_pins /vadd_bw_0/m_axi_rmem19]
+
+  set_property -dict [ list \
+   CONFIG.FREQ_HZ {249997498} \
+ ] [get_bd_intf_pins /vadd_bw_0/m_axi_rmem20]
+
+  set_property -dict [ list \
+   CONFIG.FREQ_HZ {249997498} \
+ ] [get_bd_intf_pins /vadd_bw_0/m_axi_rmem21]
+
+  set_property -dict [ list \
+   CONFIG.FREQ_HZ {249997498} \
+ ] [get_bd_intf_pins /vadd_bw_0/m_axi_rmem22]
+
+  set_property -dict [ list \
+   CONFIG.FREQ_HZ {249997498} \
+ ] [get_bd_intf_pins /vadd_bw_0/m_axi_rmem23]
+
+  set_property -dict [ list \
+   CONFIG.FREQ_HZ {249997498} \
+ ] [get_bd_intf_pins /vadd_bw_0/m_axi_rmem24]
+
+  set_property -dict [ list \
+   CONFIG.FREQ_HZ {249997498} \
+ ] [get_bd_intf_pins /vadd_bw_0/m_axi_rmem25]
+
+  set_property -dict [ list \
+   CONFIG.FREQ_HZ {249997498} \
+ ] [get_bd_intf_pins /vadd_bw_0/m_axi_rmem26]
+
+  set_property -dict [ list \
+   CONFIG.FREQ_HZ {249997498} \
+ ] [get_bd_intf_pins /vadd_bw_0/m_axi_rmem27]
+
+  set_property -dict [ list \
+   CONFIG.FREQ_HZ {249997498} \
    CONFIG.CLK_DOMAIN {bd_70da_pspmc_0_0_pl0_ref_clk} \
  ] [get_bd_intf_pins /vadd_bw_0/s_axi_control]
 
@@ -382,7 +667,7 @@ proc create_root_design { parentCell } {
       CLOCK_MODE {Custom} \
       DDR_MEMORY_MODE {Custom} \
       DEBUG_MODE {JTAG} \
-      PMC_CRP_PL0_REF_CTRL_FREQMHZ {100} \
+      PMC_CRP_PL0_REF_CTRL_FREQMHZ {250} \
       PMC_USE_PMC_NOC_AXI0 {1} \
       PS_HSDP_EGRESS_TRAFFIC {JTAG} \
       PS_HSDP_INGRESS_TRAFFIC {JTAG} \
@@ -410,7 +695,33 @@ proc create_root_design { parentCell } {
   connect_bd_intf_net -intf_net ddr4_c0_sysclk_1 [get_bd_intf_ports ddr4_c0_sysclk] [get_bd_intf_pins axi_noc_0/sys_clk0]
   connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins smartconnect_0/M00_AXI] [get_bd_intf_pins vadd_bw_0/s_axi_control]
   connect_bd_intf_net -intf_net vadd_bw_0_m_axi_rmem0 [get_bd_intf_pins axi_noc_1/S00_AXI] [get_bd_intf_pins vadd_bw_0/m_axi_rmem0]
-  connect_bd_intf_net -intf_net vadd_bw_0_m_axi_wmem0 [get_bd_intf_pins axi_noc_1/S01_AXI] [get_bd_intf_pins vadd_bw_0/m_axi_wmem0]
+  connect_bd_intf_net -intf_net vadd_bw_0_m_axi_rmem1 [get_bd_intf_pins axi_noc_1/S01_AXI] [get_bd_intf_pins vadd_bw_0/m_axi_rmem1]
+  connect_bd_intf_net -intf_net vadd_bw_0_m_axi_rmem2 [get_bd_intf_pins axi_noc_1/S02_AXI] [get_bd_intf_pins vadd_bw_0/m_axi_rmem2]
+  connect_bd_intf_net -intf_net vadd_bw_0_m_axi_rmem3 [get_bd_intf_pins axi_noc_1/S03_AXI] [get_bd_intf_pins vadd_bw_0/m_axi_rmem3]
+  connect_bd_intf_net -intf_net vadd_bw_0_m_axi_rmem4 [get_bd_intf_pins axi_noc_1/S04_AXI] [get_bd_intf_pins vadd_bw_0/m_axi_rmem4]
+  connect_bd_intf_net -intf_net vadd_bw_0_m_axi_rmem5 [get_bd_intf_pins axi_noc_1/S05_AXI] [get_bd_intf_pins vadd_bw_0/m_axi_rmem5]
+  connect_bd_intf_net -intf_net vadd_bw_0_m_axi_rmem6 [get_bd_intf_pins axi_noc_1/S06_AXI] [get_bd_intf_pins vadd_bw_0/m_axi_rmem6]
+  connect_bd_intf_net -intf_net vadd_bw_0_m_axi_rmem7 [get_bd_intf_pins axi_noc_1/S07_AXI] [get_bd_intf_pins vadd_bw_0/m_axi_rmem7]
+  connect_bd_intf_net -intf_net vadd_bw_0_m_axi_rmem8 [get_bd_intf_pins axi_noc_1/S08_AXI] [get_bd_intf_pins vadd_bw_0/m_axi_rmem8]
+  connect_bd_intf_net -intf_net vadd_bw_0_m_axi_rmem9 [get_bd_intf_pins axi_noc_1/S09_AXI] [get_bd_intf_pins vadd_bw_0/m_axi_rmem9]
+  connect_bd_intf_net -intf_net vadd_bw_0_m_axi_rmem10 [get_bd_intf_pins axi_noc_1/S10_AXI] [get_bd_intf_pins vadd_bw_0/m_axi_rmem10]
+  connect_bd_intf_net -intf_net vadd_bw_0_m_axi_rmem11 [get_bd_intf_pins axi_noc_1/S11_AXI] [get_bd_intf_pins vadd_bw_0/m_axi_rmem11]
+  connect_bd_intf_net -intf_net vadd_bw_0_m_axi_rmem12 [get_bd_intf_pins axi_noc_1/S12_AXI] [get_bd_intf_pins vadd_bw_0/m_axi_rmem12]
+  connect_bd_intf_net -intf_net vadd_bw_0_m_axi_rmem13 [get_bd_intf_pins axi_noc_1/S13_AXI] [get_bd_intf_pins vadd_bw_0/m_axi_rmem13]
+  connect_bd_intf_net -intf_net vadd_bw_0_m_axi_rmem14 [get_bd_intf_pins axi_noc_1/S14_AXI] [get_bd_intf_pins vadd_bw_0/m_axi_rmem14]
+  connect_bd_intf_net -intf_net vadd_bw_0_m_axi_rmem15 [get_bd_intf_pins axi_noc_1/S15_AXI] [get_bd_intf_pins vadd_bw_0/m_axi_rmem15]
+  connect_bd_intf_net -intf_net vadd_bw_0_m_axi_rmem16 [get_bd_intf_pins axi_noc_1/S16_AXI] [get_bd_intf_pins vadd_bw_0/m_axi_rmem16]
+  connect_bd_intf_net -intf_net vadd_bw_0_m_axi_rmem17 [get_bd_intf_pins axi_noc_1/S17_AXI] [get_bd_intf_pins vadd_bw_0/m_axi_rmem17]
+  connect_bd_intf_net -intf_net vadd_bw_0_m_axi_rmem18 [get_bd_intf_pins axi_noc_1/S18_AXI] [get_bd_intf_pins vadd_bw_0/m_axi_rmem18]
+  connect_bd_intf_net -intf_net vadd_bw_0_m_axi_rmem19 [get_bd_intf_pins axi_noc_1/S19_AXI] [get_bd_intf_pins vadd_bw_0/m_axi_rmem19]
+  connect_bd_intf_net -intf_net vadd_bw_0_m_axi_rmem20 [get_bd_intf_pins axi_noc_1/S20_AXI] [get_bd_intf_pins vadd_bw_0/m_axi_rmem20]
+  connect_bd_intf_net -intf_net vadd_bw_0_m_axi_rmem21 [get_bd_intf_pins axi_noc_1/S21_AXI] [get_bd_intf_pins vadd_bw_0/m_axi_rmem21]
+  connect_bd_intf_net -intf_net vadd_bw_0_m_axi_rmem22 [get_bd_intf_pins axi_noc_1/S22_AXI] [get_bd_intf_pins vadd_bw_0/m_axi_rmem22]
+  connect_bd_intf_net -intf_net vadd_bw_0_m_axi_rmem23 [get_bd_intf_pins axi_noc_1/S23_AXI] [get_bd_intf_pins vadd_bw_0/m_axi_rmem23]
+  connect_bd_intf_net -intf_net vadd_bw_0_m_axi_rmem24 [get_bd_intf_pins axi_noc_1/S24_AXI] [get_bd_intf_pins vadd_bw_0/m_axi_rmem24]
+  connect_bd_intf_net -intf_net vadd_bw_0_m_axi_rmem25 [get_bd_intf_pins axi_noc_1/S25_AXI] [get_bd_intf_pins vadd_bw_0/m_axi_rmem25]
+  connect_bd_intf_net -intf_net vadd_bw_0_m_axi_rmem26 [get_bd_intf_pins axi_noc_1/S26_AXI] [get_bd_intf_pins vadd_bw_0/m_axi_rmem26]
+  connect_bd_intf_net -intf_net vadd_bw_0_m_axi_rmem27 [get_bd_intf_pins axi_noc_1/S27_AXI] [get_bd_intf_pins vadd_bw_0/m_axi_rmem27]
   connect_bd_intf_net -intf_net versal_cips_0_FPD_CCI_NOC_0 [get_bd_intf_pins axi_noc_0/S00_AXI] [get_bd_intf_pins versal_cips_0/FPD_CCI_NOC_0]
   connect_bd_intf_net -intf_net versal_cips_0_FPD_CCI_NOC_1 [get_bd_intf_pins axi_noc_0/S01_AXI] [get_bd_intf_pins versal_cips_0/FPD_CCI_NOC_1]
   connect_bd_intf_net -intf_net versal_cips_0_FPD_CCI_NOC_2 [get_bd_intf_pins axi_noc_0/S02_AXI] [get_bd_intf_pins versal_cips_0/FPD_CCI_NOC_2]
@@ -431,7 +742,33 @@ proc create_root_design { parentCell } {
 
   # Create address segments
   assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces vadd_bw_0/m_axi_rmem0] [get_bd_addr_segs axi_noc_0/S00_INI/C0_DDR_LOW0] -force
-  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces vadd_bw_0/m_axi_wmem0] [get_bd_addr_segs axi_noc_0/S00_INI/C0_DDR_LOW0] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces vadd_bw_0/m_axi_rmem1] [get_bd_addr_segs axi_noc_0/S00_INI/C0_DDR_LOW0] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces vadd_bw_0/m_axi_rmem10] [get_bd_addr_segs axi_noc_0/S00_INI/C0_DDR_LOW0] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces vadd_bw_0/m_axi_rmem11] [get_bd_addr_segs axi_noc_0/S00_INI/C0_DDR_LOW0] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces vadd_bw_0/m_axi_rmem12] [get_bd_addr_segs axi_noc_0/S00_INI/C0_DDR_LOW0] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces vadd_bw_0/m_axi_rmem13] [get_bd_addr_segs axi_noc_0/S00_INI/C0_DDR_LOW0] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces vadd_bw_0/m_axi_rmem14] [get_bd_addr_segs axi_noc_0/S00_INI/C0_DDR_LOW0] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces vadd_bw_0/m_axi_rmem15] [get_bd_addr_segs axi_noc_0/S00_INI/C0_DDR_LOW0] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces vadd_bw_0/m_axi_rmem16] [get_bd_addr_segs axi_noc_0/S00_INI/C0_DDR_LOW0] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces vadd_bw_0/m_axi_rmem17] [get_bd_addr_segs axi_noc_0/S00_INI/C0_DDR_LOW0] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces vadd_bw_0/m_axi_rmem18] [get_bd_addr_segs axi_noc_0/S00_INI/C0_DDR_LOW0] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces vadd_bw_0/m_axi_rmem19] [get_bd_addr_segs axi_noc_0/S00_INI/C0_DDR_LOW0] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces vadd_bw_0/m_axi_rmem2] [get_bd_addr_segs axi_noc_0/S00_INI/C0_DDR_LOW0] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces vadd_bw_0/m_axi_rmem20] [get_bd_addr_segs axi_noc_0/S00_INI/C0_DDR_LOW0] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces vadd_bw_0/m_axi_rmem21] [get_bd_addr_segs axi_noc_0/S00_INI/C0_DDR_LOW0] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces vadd_bw_0/m_axi_rmem22] [get_bd_addr_segs axi_noc_0/S00_INI/C0_DDR_LOW0] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces vadd_bw_0/m_axi_rmem23] [get_bd_addr_segs axi_noc_0/S00_INI/C0_DDR_LOW0] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces vadd_bw_0/m_axi_rmem24] [get_bd_addr_segs axi_noc_0/S00_INI/C0_DDR_LOW0] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces vadd_bw_0/m_axi_rmem25] [get_bd_addr_segs axi_noc_0/S00_INI/C0_DDR_LOW0] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces vadd_bw_0/m_axi_rmem26] [get_bd_addr_segs axi_noc_0/S00_INI/C0_DDR_LOW0] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces vadd_bw_0/m_axi_rmem27] [get_bd_addr_segs axi_noc_0/S00_INI/C0_DDR_LOW0] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces vadd_bw_0/m_axi_rmem3] [get_bd_addr_segs axi_noc_0/S00_INI/C0_DDR_LOW0] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces vadd_bw_0/m_axi_rmem4] [get_bd_addr_segs axi_noc_0/S00_INI/C0_DDR_LOW0] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces vadd_bw_0/m_axi_rmem5] [get_bd_addr_segs axi_noc_0/S00_INI/C0_DDR_LOW0] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces vadd_bw_0/m_axi_rmem6] [get_bd_addr_segs axi_noc_0/S00_INI/C0_DDR_LOW0] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces vadd_bw_0/m_axi_rmem7] [get_bd_addr_segs axi_noc_0/S00_INI/C0_DDR_LOW0] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces vadd_bw_0/m_axi_rmem8] [get_bd_addr_segs axi_noc_0/S00_INI/C0_DDR_LOW0] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces vadd_bw_0/m_axi_rmem9] [get_bd_addr_segs axi_noc_0/S00_INI/C0_DDR_LOW0] -force
   assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces versal_cips_0/FPD_CCI_NOC_0] [get_bd_addr_segs axi_noc_0/S00_AXI/C0_DDR_LOW0] -force
   assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces versal_cips_0/FPD_CCI_NOC_1] [get_bd_addr_segs axi_noc_0/S01_AXI/C0_DDR_LOW0] -force
   assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces versal_cips_0/FPD_CCI_NOC_2] [get_bd_addr_segs axi_noc_0/S02_AXI/C0_DDR_LOW0] -force
@@ -443,6 +780,7 @@ proc create_root_design { parentCell } {
   # Restore current instance
   current_bd_instance $oldCurInst
 
+  validate_bd_design
   save_bd_design
 }
 # End of create_root_design()
@@ -453,6 +791,3 @@ proc create_root_design { parentCell } {
 ##################################################################
 
 create_root_design ""
-
-
-common::send_gid_msg -ssname BD::TCL -id 2053 -severity "WARNING" "This Tcl script was generated from a block design that has not been validated. It is possible that design <$design_name> may result in errors during validation."
diff --git a/benchmarks/vivado_flow/vck5000_dfx/tcl/design_1.tcldma b/benchmarks/vivado_flow/vck5000_dfx/tcl/design_1.tcldma
deleted file mode 100644
index f957cf53..00000000
--- a/benchmarks/vivado_flow/vck5000_dfx/tcl/design_1.tcldma
+++ /dev/null
@@ -1,736 +0,0 @@
-# Copyright (c) 2024 RapidStream Design Automation, Inc. and contributors.  All rights reserved.
-# The contributor(s) of this file has/have agreed to the RapidStream Contributor License Agreement.
-
-################################################################
-# This is a generated script based on design: design_1
-#
-# Though there are limitations about the generated script,
-# the main purpose of this utility is to make learning
-# IP Integrator Tcl commands easier.
-################################################################
-
-namespace eval _tcl {
-proc get_script_folder {} {
-   set script_path [file normalize [info script]]
-   set script_folder [file dirname $script_path]
-   return $script_folder
-}
-}
-variable script_folder
-set script_folder [_tcl::get_script_folder]
-
-################################################################
-# Check if script is running in correct Vivado version.
-################################################################
-set scripts_vivado_version 2022.2
-set current_vivado_version [version -short]
-
-if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
-   puts ""
-   catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
-
-   return 1
-}
-
-################################################################
-# START
-################################################################
-
-# To test this script, run the following commands from Vivado Tcl console:
-# source design_1_script.tcl
-
-# If there is no project opened, this script will create a
-# project, but make sure you do not have an existing project
-# <./myproj/project_1.xpr> in the current working folder.
-
-set list_projs [get_projects -quiet]
-if { $list_projs eq "" } {
-   create_project project_1 myproj -part xczu3eg-sbva484-1-i
-   set_property BOARD_PART avnet.com:ultra96v2:part0:1.2 [current_project]
-}
-
-
-# CHANGE DESIGN NAME HERE
-variable design_name
-set design_name design_1
-
-# If you do not already have an existing IP Integrator design open,
-# you can create a design using the following command:
-#    create_bd_design $design_name
-
-# Creating design if needed
-set errMsg ""
-set nRet 0
-
-set cur_design [current_bd_design -quiet]
-set list_cells [get_bd_cells -quiet]
-
-if { ${design_name} eq "" } {
-   # USE CASES:
-   #    1) Design_name not set
-
-   set errMsg "Please set the variable <design_name> to a non-empty value."
-   set nRet 1
-
-} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
-   # USE CASES:
-   #    2): Current design opened AND is empty AND names same.
-   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
-   #    4): Current design opened AND is empty AND names diff; design_name exists in project.
-
-   if { $cur_design ne $design_name } {
-      common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
-      set design_name [get_property NAME $cur_design]
-   }
-   common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
-
-} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
-   # USE CASES:
-   #    5) Current design opened AND has components AND same names.
-
-   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
-   set nRet 1
-} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
-   # USE CASES:
-   #    6) Current opened design, has components, but diff names, design_name exists in project.
-   #    7) No opened design, design_name exists in project.
-
-   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
-   set nRet 2
-
-} else {
-   # USE CASES:
-   #    8) No opened design, design_name not in project.
-   #    9) Current opened design, has components, but diff names, design_name not in project.
-
-   common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
-
-   create_bd_design $design_name
-
-   common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
-   current_bd_design $design_name
-
-}
-
-common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
-
-if { $nRet != 0 } {
-   catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
-   return $nRet
-}
-
-set bCheckIPsPassed 1
-##################################################################
-# CHECK IPs
-##################################################################
-set bCheckIPs 1
-if { $bCheckIPs == 1 } {
-   set list_check_ips "\
-xilinx.com:ip:axi_dma:7.1\
-xilinx.com:ip:smartconnect:1.0\
-xilinx.com:ip:axis_data_fifo:2.0\
-xilinx.com:ip:proc_sys_reset:5.0\
-xilinx.com:ip:zynq_ultra_ps_e:3.4\
-"
-
-   set list_ips_missing ""
-   common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
-
-   foreach ip_vlnv $list_check_ips {
-      set ip_obj [get_ipdefs -all $ip_vlnv]
-      if { $ip_obj eq "" } {
-         lappend list_ips_missing $ip_vlnv
-      }
-   }
-
-   if { $list_ips_missing ne "" } {
-      catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
-      set bCheckIPsPassed 0
-   }
-
-}
-
-if { $bCheckIPsPassed != 1 } {
-  common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
-  return 3
-}
-
-##################################################################
-# DESIGN PROCs
-##################################################################
-
-
-
-# Procedure to create entire design; Provide argument to make
-# procedure reusable. If parentCell is "", will use root.
-proc create_root_design { parentCell } {
-
-  variable script_folder
-  variable design_name
-
-  if { $parentCell eq "" } {
-     set parentCell [get_bd_cells /]
-  }
-
-  # Get object for parentCell
-  set parentObj [get_bd_cells $parentCell]
-  if { $parentObj == "" } {
-     catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
-     return
-  }
-
-  # Make sure parentObj is hier blk
-  set parentType [get_property TYPE $parentObj]
-  if { $parentType ne "hier" } {
-     catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
-     return
-  }
-
-  # Save current instance; Restore later
-  set oldCurInst [current_bd_instance .]
-
-  # Set parent object as current
-  current_bd_instance $parentObj
-
-
-  # Create interface ports
-
-  # Create ports
-
-  # Create instance: axi_dma_0, and set properties
-  set axi_dma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_0 ]
-  set_property -dict [list \
-    CONFIG.c_include_sg {1} \
-    CONFIG.c_sg_include_stscntrl_strm {0} \
-  ] $axi_dma_0
-
-
-  # Create instance: axi_smc, and set properties
-  set axi_smc [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc ]
-  set_property CONFIG.NUM_SI {3} $axi_smc
-
-
-  # Create instance: axis_data_fifo_0, and set properties
-  set axis_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_0 ]
-
-  # Create instance: ps8_0_axi_periph, and set properties
-  set ps8_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps8_0_axi_periph ]
-  set_property -dict [list \
-    CONFIG.NUM_MI {1} \
-    CONFIG.NUM_SI {2} \
-  ] $ps8_0_axi_periph
-
-
-  # Create instance: rst_ps8_0_100M, and set properties
-  set rst_ps8_0_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps8_0_100M ]
-
-  # Create instance: zynq_ultra_ps_e_0, and set properties
-  set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.4 zynq_ultra_ps_e_0 ]
-  set_property -dict [list \
-    CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
-    CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
-    CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
-    CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS18} \
-    CONFIG.PSU_DDR_RAM_HIGHADDR {0x7FFFFFFF} \
-    CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x00000002} \
-    CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
-    CONFIG.PSU_MIO_12_POLARITY {Default} \
-    CONFIG.PSU_MIO_13_DRIVE_STRENGTH {4} \
-    CONFIG.PSU_MIO_14_DRIVE_STRENGTH {4} \
-    CONFIG.PSU_MIO_15_DRIVE_STRENGTH {4} \
-    CONFIG.PSU_MIO_16_DRIVE_STRENGTH {4} \
-    CONFIG.PSU_MIO_17_POLARITY {Default} \
-    CONFIG.PSU_MIO_18_POLARITY {Default} \
-    CONFIG.PSU_MIO_19_POLARITY {Default} \
-    CONFIG.PSU_MIO_20_POLARITY {Default} \
-    CONFIG.PSU_MIO_21_DRIVE_STRENGTH {4} \
-    CONFIG.PSU_MIO_22_DRIVE_STRENGTH {4} \
-    CONFIG.PSU_MIO_23_POLARITY {Default} \
-    CONFIG.PSU_MIO_25_POLARITY {Default} \
-    CONFIG.PSU_MIO_31_POLARITY {Default} \
-    CONFIG.PSU_MIO_35_POLARITY {Default} \
-    CONFIG.PSU_MIO_36_POLARITY {Default} \
-    CONFIG.PSU_MIO_37_POLARITY {Default} \
-    CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \
-    CONFIG.PSU_MIO_39_POLARITY {Default} \
-    CONFIG.PSU_MIO_39_SLEW {fast} \
-    CONFIG.PSU_MIO_40_POLARITY {Default} \
-    CONFIG.PSU_MIO_44_POLARITY {Default} \
-    CONFIG.PSU_MIO_45_POLARITY {Default} \
-    CONFIG.PSU_MIO_76_POLARITY {Default} \
-    CONFIG.PSU_MIO_77_POLARITY {Default} \
-    CONFIG.PSU_MIO_7_POLARITY {Default} \
-    CONFIG.PSU_MIO_8_POLARITY {Default} \
-    CONFIG.PSU_MIO_TREE_PERIPHERALS {UART 1#UART 1#UART 0#UART 0#I2C 1#I2C 1#SPI 1#GPIO0 MIO#GPIO0 MIO#SPI 1#SPI 1#SPI 1#GPIO0 MIO#SD 0#SD 0#SD 0#SD 0#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#SD 0#SD 0#GPIO0\
-MIO#SD 0#GPIO0 MIO#PMU GPI 0#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#PMU GPO 0#PMU GPO 1#PMU GPO 2#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#SPI 0#GPIO1 MIO#GPIO1 MIO#SPI 0#SPI 0#SPI 0#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD\
-1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#GPIO2 MIO#GPIO2 MIO} \
-    CONFIG.PSU_MIO_TREE_SIGNALS {txd#rxd#rxd#txd#scl_out#sda_out#sclk_out#gpio0[7]#gpio0[8]#n_ss_out[0]#miso#mosi#gpio0[12]#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#gpio0[17]#gpio0[18]#gpio0[19]#gpio0[20]#sdio0_cmd_out#sdio0_clk_out#gpio0[23]#sdio0_cd_n#gpio0[25]#gpi[0]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#gpo[0]#gpo[1]#gpo[2]#gpio1[35]#gpio1[36]#gpio1[37]#sclk_out#gpio1[39]#gpio1[40]#n_ss_out[0]#miso#mosi#gpio1[44]#gpio1[45]#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#gpio2[76]#gpio2[77]}\
-\
-    CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {4} \
-    CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \
-    CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \
-    CONFIG.PSU__ACT_DDR_FREQ_MHZ {533.333313} \
-    CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {0} \
-    CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1200.000000} \
-    CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \
-    CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
-    CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \
-    CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \
-    CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
-    CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \
-    CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000000} \
-    CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \
-    CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
-    CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {2} \
-    CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
-    CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000000} \
-    CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \
-    CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
-    CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {266.666656} \
-    CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {4} \
-    CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {533} \
-    CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
-    CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
-    CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \
-    CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
-    CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
-    CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {64} \
-    CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
-    CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {3} \
-    CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {24.576040} \
-    CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {16} \
-    CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \
-    CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
-    CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {1} \
-    CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.214443} \
-    CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {15} \
-    CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \
-    CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
-    CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {297.029572} \
-    CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {4} \
-    CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \
-    CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
-    CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {1} \
-    CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
-    CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \
-    CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
-    CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {500.000000} \
-    CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {1} \
-    CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
-    CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {2} \
-    CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \
-    CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
-    CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \
-    CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
-    CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {533.333313} \
-    CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \
-    CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \
-    CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \
-    CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {71} \
-    CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.2871} \
-    CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {300} \
-    CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
-    CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {1} \
-    CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \
-    CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000000} \
-    CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \
-    CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
-    CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \
-    CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {51.724136} \
-    CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {29} \
-    CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \
-    CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \
-    CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \
-    CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \
-    CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \
-    CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \
-    CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \
-    CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
-    CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000000} \
-    CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \
-    CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
-    CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {500} \
-    CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {4} \
-    CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ {400} \
-    CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {IOPLL} \
-    CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000000} \
-    CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \
-    CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
-    CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500.000000} \
-    CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \
-    CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \
-    CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \
-    CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \
-    CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \
-    CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \
-    CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \
-    CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \
-    CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \
-    CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \
-    CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \
-    CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
-    CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \
-    CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \
-    CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \
-    CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \
-    CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \
-    CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
-    CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000000} \
-    CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \
-    CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \
-    CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
-    CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {0} \
-    CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {45} \
-    CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
-    CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \
-    CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {250.000000} \
-    CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \
-    CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
-    CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
-    CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \
-    CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
-    CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000000} \
-    CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \
-    CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
-    CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \
-    CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \
-    CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \
-    CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500000} \
-    CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \
-    CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
-    CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {100.000000} \
-    CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \
-    CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \
-    CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
-    CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {24.999975} \
-    CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {15} \
-    CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {4} \
-    CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {299.999700} \
-    CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {5} \
-    CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \
-    CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {374.999625} \
-    CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \
-    CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \
-    CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \
-    CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \
-    CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
-    CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \
-    CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {70} \
-    CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.779} \
-    CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {25} \
-    CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
-    CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {1} \
-    CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {3} \
-    CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {187.500000} \
-    CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {8} \
-    CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \
-    CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {IOPLL} \
-    CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.500000} \
-    CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \
-    CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \
-    CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \
-    CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {187.500000} \
-    CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {8} \
-    CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \
-    CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {IOPLL} \
-    CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {187.500000} \
-    CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {8} \
-    CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \
-    CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {IOPLL} \
-    CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {100.000000} \
-    CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \
-    CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \
-    CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000000} \
-    CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \
-    CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \
-    CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \
-    CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {100.000000} \
-    CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \
-    CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \
-    CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \
-    CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
-    CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \
-    CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \
-    CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \
-    CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \
-    CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
-    CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \
-    CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \
-    CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \
-    CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000000} \
-    CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {5} \
-    CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {15} \
-    CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \
-    CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
-    CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
-    CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \
-    CONFIG.PSU__DDRC__ADDR_MIRROR {1} \
-    CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \
-    CONFIG.PSU__DDRC__BUS_WIDTH {32 Bit} \
-    CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \
-    CONFIG.PSU__DDRC__DEVICE_CAPACITY {16384 MBits} \
-    CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \
-    CONFIG.PSU__DDRC__DQMAP_0_3 {0} \
-    CONFIG.PSU__DDRC__DQMAP_12_15 {0} \
-    CONFIG.PSU__DDRC__DQMAP_16_19 {0} \
-    CONFIG.PSU__DDRC__DQMAP_20_23 {0} \
-    CONFIG.PSU__DDRC__DQMAP_24_27 {0} \
-    CONFIG.PSU__DDRC__DQMAP_28_31 {0} \
-    CONFIG.PSU__DDRC__DQMAP_32_35 {0} \
-    CONFIG.PSU__DDRC__DQMAP_36_39 {0} \
-    CONFIG.PSU__DDRC__DQMAP_40_43 {0} \
-    CONFIG.PSU__DDRC__DQMAP_44_47 {0} \
-    CONFIG.PSU__DDRC__DQMAP_48_51 {0} \
-    CONFIG.PSU__DDRC__DQMAP_4_7 {0} \
-    CONFIG.PSU__DDRC__DQMAP_52_55 {0} \
-    CONFIG.PSU__DDRC__DQMAP_56_59 {0} \
-    CONFIG.PSU__DDRC__DQMAP_60_63 {0} \
-    CONFIG.PSU__DDRC__DQMAP_64_67 {0} \
-    CONFIG.PSU__DDRC__DQMAP_68_71 {0} \
-    CONFIG.PSU__DDRC__DQMAP_8_11 {0} \
-    CONFIG.PSU__DDRC__DRAM_WIDTH {32 Bits} \
-    CONFIG.PSU__DDRC__ECC {Disabled} \
-    CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {1} \
-    CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \
-    CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {High (95 Max)} \
-    CONFIG.PSU__DDRC__MEMORY_TYPE {LPDDR 4} \
-    CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
-    CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
-    CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \
-    CONFIG.PSU__DDRC__ROW_ADDR_COUNT {16} \
-    CONFIG.PSU__DDRC__SPEED_BIN {LPDDR4_1066} \
-    CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
-    CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
-    CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
-    CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
-    CONFIG.PSU__DDRC__T_FAW {40.0} \
-    CONFIG.PSU__DDRC__T_RAS_MIN {42} \
-    CONFIG.PSU__DDRC__T_RC {63} \
-    CONFIG.PSU__DDRC__T_RCD {10} \
-    CONFIG.PSU__DDRC__T_RP {12} \
-    CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \
-    CONFIG.PSU__DDRC__VREF {0} \
-    CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {0} \
-    CONFIG.PSU__DDR_QOS_ENABLE {1} \
-    CONFIG.PSU__DDR_QOS_HP0_RDQOS {7} \
-    CONFIG.PSU__DDR_QOS_HP0_WRQOS {15} \
-    CONFIG.PSU__DDR_QOS_HP1_RDQOS {3} \
-    CONFIG.PSU__DDR_QOS_HP1_WRQOS {3} \
-    CONFIG.PSU__DDR_QOS_HP2_RDQOS {3} \
-    CONFIG.PSU__DDR_QOS_HP2_WRQOS {3} \
-    CONFIG.PSU__DDR_QOS_HP3_RDQOS {3} \
-    CONFIG.PSU__DDR_QOS_HP3_WRQOS {3} \
-    CONFIG.PSU__DDR_QOS_PORT0_TYPE {Low Latency} \
-    CONFIG.PSU__DDR_QOS_PORT1_VN1_TYPE {Low Latency} \
-    CONFIG.PSU__DDR_QOS_PORT1_VN2_TYPE {Best Effort} \
-    CONFIG.PSU__DDR_QOS_PORT2_VN1_TYPE {Low Latency} \
-    CONFIG.PSU__DDR_QOS_PORT2_VN2_TYPE {Best Effort} \
-    CONFIG.PSU__DDR_QOS_PORT3_TYPE {Video Traffic} \
-    CONFIG.PSU__DDR_QOS_PORT4_TYPE {Best Effort} \
-    CONFIG.PSU__DDR_QOS_PORT5_TYPE {Best Effort} \
-    CONFIG.PSU__DDR_QOS_RD_HPR_THRSHLD {0} \
-    CONFIG.PSU__DDR_QOS_RD_LPR_THRSHLD {16} \
-    CONFIG.PSU__DDR_QOS_WR_THRSHLD {16} \
-    CONFIG.PSU__DDR__INTERFACE__FREQMHZ {266.500} \
-    CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \
-    CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \
-    CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \
-    CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \
-    CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \
-    CONFIG.PSU__DLL__ISUSED {1} \
-    CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \
-    CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \
-    CONFIG.PSU__DP__LANE_SEL {Dual Lower} \
-    CONFIG.PSU__DP__REF_CLK_FREQ {27} \
-    CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk1} \
-    CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {0} \
-    CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100.000000} \
-    CONFIG.PSU__FPGA_PL0_ENABLE {1} \
-    CONFIG.PSU__FPGA_PL1_ENABLE {0} \
-    CONFIG.PSU__FPGA_PL2_ENABLE {0} \
-    CONFIG.PSU__FPGA_PL3_ENABLE {0} \
-    CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \
-    CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \
-    CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \
-    CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \
-    CONFIG.PSU__GPIO2_MIO__IO {MIO 52 .. 77} \
-    CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {1} \
-    CONFIG.PSU__GT__LINK_SPEED {HBR} \
-    CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \
-    CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \
-    CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {0} \
-    CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
-    CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 4 .. 5} \
-    CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \
-    CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \
-    CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \
-    CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \
-    CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \
-    CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \
-    CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \
-    CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \
-    CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100.000000} \
-    CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100.000000} \
-    CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \
-    CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \
-    CONFIG.PSU__OVERRIDE__BASIC_CLOCK {1} \
-    CONFIG.PSU__PL_CLK0_BUF {TRUE} \
-    CONFIG.PSU__PMU_COHERENCY {0} \
-    CONFIG.PSU__PMU__AIBACK__ENABLE {0} \
-    CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \
-    CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \
-    CONFIG.PSU__PMU__GPI0__ENABLE {1} \
-    CONFIG.PSU__PMU__GPI0__IO {MIO 26} \
-    CONFIG.PSU__PMU__GPI1__ENABLE {0} \
-    CONFIG.PSU__PMU__GPI2__ENABLE {0} \
-    CONFIG.PSU__PMU__GPI3__ENABLE {0} \
-    CONFIG.PSU__PMU__GPI4__ENABLE {0} \
-    CONFIG.PSU__PMU__GPI5__ENABLE {0} \
-    CONFIG.PSU__PMU__GPO0__ENABLE {1} \
-    CONFIG.PSU__PMU__GPO0__IO {MIO 32} \
-    CONFIG.PSU__PMU__GPO1__ENABLE {1} \
-    CONFIG.PSU__PMU__GPO1__IO {MIO 33} \
-    CONFIG.PSU__PMU__GPO2__ENABLE {1} \
-    CONFIG.PSU__PMU__GPO2__IO {MIO 34} \
-    CONFIG.PSU__PMU__GPO2__POLARITY {high} \
-    CONFIG.PSU__PMU__GPO3__ENABLE {0} \
-    CONFIG.PSU__PMU__GPO4__ENABLE {0} \
-    CONFIG.PSU__PMU__GPO5__ENABLE {0} \
-    CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \
-    CONFIG.PSU__PMU__PLERROR__ENABLE {0} \
-    CONFIG.PSU__PRESET_APPLIED {1} \
-    CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;1|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;1|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;1|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;0|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;0|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1}\
-\
-    CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;1|LPD;USB3_1;FF9E0000;FF9EFFFF;1|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;0|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;1|LPD;SPI0;FF040000;FF04FFFF;1|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;1|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;0|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;0|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;0|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display\
-Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;800000000;0|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1}\
-\
-    CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333333} \
-    CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {0} \
-    CONFIG.PSU__SATA__PERIPHERAL__ENABLE {0} \
-    CONFIG.PSU__SAXIGP2__DATA_WIDTH {128} \
-    CONFIG.PSU__SD0_COHERENCY {0} \
-    CONFIG.PSU__SD0_ROUTE_THROUGH_FPD {0} \
-    CONFIG.PSU__SD0__CLK_50_SDR_ITAP_DLY {0x15} \
-    CONFIG.PSU__SD0__CLK_50_SDR_OTAP_DLY {0x5} \
-    CONFIG.PSU__SD0__DATA_TRANSFER_MODE {4Bit} \
-    CONFIG.PSU__SD0__GRP_CD__ENABLE {1} \
-    CONFIG.PSU__SD0__GRP_CD__IO {MIO 24} \
-    CONFIG.PSU__SD0__GRP_POW__ENABLE {0} \
-    CONFIG.PSU__SD0__GRP_WP__ENABLE {0} \
-    CONFIG.PSU__SD0__PERIPHERAL__ENABLE {1} \
-    CONFIG.PSU__SD0__PERIPHERAL__IO {MIO 13 .. 16 21 22} \
-    CONFIG.PSU__SD0__SLOT_TYPE {SD 2.0} \
-    CONFIG.PSU__SD1_COHERENCY {0} \
-    CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \
-    CONFIG.PSU__SD1__CLK_50_SDR_ITAP_DLY {0x15} \
-    CONFIG.PSU__SD1__CLK_50_SDR_OTAP_DLY {0x5} \
-    CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \
-    CONFIG.PSU__SD1__GRP_CD__ENABLE {0} \
-    CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \
-    CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \
-    CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
-    CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \
-    CONFIG.PSU__SD1__SLOT_TYPE {SD 2.0} \
-    CONFIG.PSU__SPI0__GRP_SS0__IO {MIO 41} \
-    CONFIG.PSU__SPI0__GRP_SS1__ENABLE {0} \
-    CONFIG.PSU__SPI0__GRP_SS2__ENABLE {0} \
-    CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {1} \
-    CONFIG.PSU__SPI0__PERIPHERAL__IO {MIO 38 .. 43} \
-    CONFIG.PSU__SPI1__GRP_SS0__IO {MIO 9} \
-    CONFIG.PSU__SPI1__GRP_SS1__ENABLE {0} \
-    CONFIG.PSU__SPI1__GRP_SS2__ENABLE {0} \
-    CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {1} \
-    CONFIG.PSU__SPI1__PERIPHERAL__IO {MIO 6 .. 11} \
-    CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \
-    CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \
-    CONFIG.PSU__SWDT0__RESET__ENABLE {0} \
-    CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \
-    CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \
-    CONFIG.PSU__SWDT1__RESET__ENABLE {0} \
-    CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \
-    CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
-    CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \
-    CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \
-    CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \
-    CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \
-    CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \
-    CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \
-    CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \
-    CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \
-    CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \
-    CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \
-    CONFIG.PSU__UART0__PERIPHERAL__ENABLE {0} \
-    CONFIG.PSU__UART1__BAUD_RATE {115200} \
-    CONFIG.PSU__UART1__MODEM__ENABLE {0} \
-    CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \
-    CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 0 .. 1} \
-    CONFIG.PSU__USB0_COHERENCY {0} \
-    CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
-    CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \
-    CONFIG.PSU__USB0__REF_CLK_FREQ {26} \
-    CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk0} \
-    CONFIG.PSU__USB1_COHERENCY {0} \
-    CONFIG.PSU__USB1__PERIPHERAL__ENABLE {1} \
-    CONFIG.PSU__USB1__PERIPHERAL__IO {MIO 64 .. 75} \
-    CONFIG.PSU__USB1__REF_CLK_FREQ {26} \
-    CONFIG.PSU__USB1__REF_CLK_SEL {Ref Clk0} \
-    CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \
-    CONFIG.PSU__USB2_1__EMIO__ENABLE {0} \
-    CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \
-    CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
-    CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \
-    CONFIG.PSU__USB3_1__EMIO__ENABLE {0} \
-    CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE {1} \
-    CONFIG.PSU__USB3_1__PERIPHERAL__IO {GT Lane3} \
-    CONFIG.PSU__USB__RESET__MODE {Boot Pin} \
-    CONFIG.PSU__USB__RESET__POLARITY {Active Low} \
-    CONFIG.PSU__USE__IRQ0 {1} \
-    CONFIG.PSU__USE__M_AXI_GP0 {1} \
-    CONFIG.PSU__USE__M_AXI_GP1 {1} \
-    CONFIG.PSU__USE__M_AXI_GP2 {0} \
-    CONFIG.PSU__USE__S_AXI_GP2 {1} \
-  ] $zynq_ultra_ps_e_0
-
-
-  # Create interface connections
-  connect_bd_intf_net -intf_net axi_dma_0_M_AXIS_MM2S [get_bd_intf_pins axi_dma_0/M_AXIS_MM2S] [get_bd_intf_pins axis_data_fifo_0/S_AXIS]
-  connect_bd_intf_net -intf_net axi_dma_0_M_AXI_MM2S [get_bd_intf_pins axi_dma_0/M_AXI_MM2S] [get_bd_intf_pins axi_smc/S00_AXI]
-  connect_bd_intf_net -intf_net axi_dma_0_M_AXI_S2MM [get_bd_intf_pins axi_dma_0/M_AXI_S2MM] [get_bd_intf_pins axi_smc/S01_AXI]
-  connect_bd_intf_net -intf_net axi_dma_0_M_AXI_SG [get_bd_intf_pins axi_dma_0/M_AXI_SG] [get_bd_intf_pins axi_smc/S02_AXI]
-  connect_bd_intf_net -intf_net axi_smc_M00_AXI [get_bd_intf_pins axi_smc/M00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP0_FPD]
-  connect_bd_intf_net -intf_net axis_data_fifo_0_M_AXIS [get_bd_intf_pins axi_dma_0/S_AXIS_S2MM] [get_bd_intf_pins axis_data_fifo_0/M_AXIS]
-  connect_bd_intf_net -intf_net ps8_0_axi_periph_M00_AXI [get_bd_intf_pins axi_dma_0/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M00_AXI]
-  connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_FPD [get_bd_intf_pins ps8_0_axi_periph/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_FPD]
-  connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM1_FPD [get_bd_intf_pins ps8_0_axi_periph/S01_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM1_FPD]
-
-  # Create port connections
-  connect_bd_net -net rst_ps8_0_100M_peripheral_aresetn [get_bd_pins axi_dma_0/axi_resetn] [get_bd_pins axi_smc/aresetn] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins ps8_0_axi_periph/ARESETN] [get_bd_pins ps8_0_axi_periph/M00_ARESETN] [get_bd_pins ps8_0_axi_periph/S00_ARESETN] [get_bd_pins ps8_0_axi_periph/S01_ARESETN] [get_bd_pins rst_ps8_0_100M/peripheral_aresetn]
-  connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins axi_dma_0/m_axi_mm2s_aclk] [get_bd_pins axi_dma_0/m_axi_s2mm_aclk] [get_bd_pins axi_dma_0/m_axi_sg_aclk] [get_bd_pins axi_dma_0/s_axi_lite_aclk] [get_bd_pins axi_smc/aclk] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins ps8_0_axi_periph/ACLK] [get_bd_pins ps8_0_axi_periph/M00_ACLK] [get_bd_pins ps8_0_axi_periph/S00_ACLK] [get_bd_pins ps8_0_axi_periph/S01_ACLK] [get_bd_pins rst_ps8_0_100M/slowest_sync_clk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm1_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] [get_bd_pins zynq_ultra_ps_e_0/saxihp0_fpd_aclk]
-  connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins rst_ps8_0_100M/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0]
-
-  # Create address segments
-  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_0/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP2/HP0_DDR_LOW] -force
-  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_0/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP2/HP0_DDR_LOW] -force
-  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_0/Data_SG] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP2/HP0_DDR_LOW] -force
-  assign_bd_address -offset 0xA0000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_0/S_AXI_LITE/Reg] -force
-
-  # Exclude Address Segments
-  exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma_0/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP2/HP0_LPS_OCM]
-  exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma_0/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP2/HP0_LPS_OCM]
-  exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma_0/Data_SG] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP2/HP0_LPS_OCM]
-
-
-  # Restore current instance
-  current_bd_instance $oldCurInst
-
-  validate_bd_design
-  save_bd_design
-}
-# End of create_root_design()
-
-
-##################################################################
-# MAIN FLOW
-##################################################################
-
-create_root_design ""
diff --git a/benchmarks/vivado_flow/vck5000_dfx/tcl/impl.tcl b/benchmarks/vivado_flow/vck5000_dfx/tcl/impl.tcl
index 8837d701..667da669 100644
--- a/benchmarks/vivado_flow/vck5000_dfx/tcl/impl.tcl
+++ b/benchmarks/vivado_flow/vck5000_dfx/tcl/impl.tcl
@@ -1,4 +1,10 @@
+
+open_checkpoint overlay.dcp
+read_checkpoint -cell design_1_i/vadd_bw_0/inst ./vadd_bw.dcp
 opt_design
 place_design
 phys_opt_design
 route_design
+write_checkpoint -force routed.dcp
+update_design -cell design_1/vadd_bw_0/inst -black_box
+write_checkpoint -force pr_overlay.dcp
diff --git a/benchmarks/vivado_flow/vck5000_dfx/tcl/ooc_syn.tcl b/benchmarks/vivado_flow/vck5000_dfx/tcl/ooc_syn.tcl
index 55e3c00c..c8a3de5b 100644
--- a/benchmarks/vivado_flow/vck5000_dfx/tcl/ooc_syn.tcl
+++ b/benchmarks/vivado_flow/vck5000_dfx/tcl/ooc_syn.tcl
@@ -1,6 +1,6 @@
 set top_name vadd_bw
 
-set dir "../vadd_bandwidth1r1w2"
+set dir "../v/vadd_bandwidth28r28w"
 set contents [glob -nocomplain -directory $dir *]
 foreach item $contents {
   if { [regexp {.*\.tcl} $item] } {
@@ -16,7 +16,7 @@ set logFileId [open ./runOOC.log "w"]
 set start_time [clock seconds]
 set_param general.maxThreads  8
 synth_design -top $top_name -part xcvc1902-vsvd1760-2MP-e-S -mode out_of_context
-write_checkpoint -force ./checkpoint/$top_name.dcp
+write_checkpoint -force $top_name.dcp
 set end_time [clock seconds]
 set total_seconds [expr $end_time - $start_time]
 puts $logFileId "syn: $total_seconds seconds"
diff --git a/benchmarks/vivado_flow/vck5000_dfx/tcl/prj_gen.tcl b/benchmarks/vivado_flow/vck5000_dfx/tcl/prj_gen.tcl
index 9bfa3e6a..f36a0497 100644
--- a/benchmarks/vivado_flow/vck5000_dfx/tcl/prj_gen.tcl
+++ b/benchmarks/vivado_flow/vck5000_dfx/tcl/prj_gen.tcl
@@ -12,13 +12,20 @@ proc add_src_to_project { dir } {
 set _prj_name_ "project_1"
 create_project -force ${_prj_name_} ${_prj_name_} -part xcvc1902-vsvd1760-2MP-e-S
 set_property board_part xilinx.com:vck5000:part0:1.0 [current_project]
-add_src_to_project ../v/vadd_bandwidth1r1w_placeholder
+add_src_to_project ../v/vadd_bandwidth28r28w_placeholder
 source ../tcl/design_1.tcl
 update_compile_order -fileset sources_1
 make_wrapper -files [get_files ${_prj_name_}/${_prj_name_}.srcs/sources_1/bd/design_1/design_1.bd] -top
 add_files -norecurse ${_prj_name_}/${_prj_name_}.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
 update_compile_order -fileset sources_1
 set_property top design_1_wrapper [current_fileset]
+add_files -fileset constrs_1 ../xdc/pdef1.xdc
+set_property target_constrs_file ../xdc/pdef1.xdc [current_fileset -constrset]
+
+launch_runs synth_1 -jobs 16
+wait_on_run synth_1
+open_run synth_1 -name synth_1
+write_checkpoint -force overlay.dcp
 
 #launch_runs impl_1 -to_step write_device_image -jobs 16
 #wait_on_run impl_1
diff --git a/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/Mmap2Stream.v b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/Mmap2Stream.v
new file mode 100644
index 00000000..b485de6c
--- /dev/null
+++ b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/Mmap2Stream.v
@@ -0,0 +1,589 @@
+// ==============================================================
+// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit)
+// Version: 2022.2
+// Copyright (C) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+//
+// ===========================================================
+
+`timescale 1 ns / 1 ps
+
+(* CORE_GENERATION_INFO="Mmap2Stream_Mmap2Stream,hls_ip_2022_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xcu50-fsvh2104-2-e,HLS_INPUT_CLOCK=3.330000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.430900,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=5218,HLS_SYN_LUT=8284,HLS_VERSION=2022_2}" *)
+
+module Mmap2Stream (
+        ap_clk,
+        ap_rst_n,
+        ap_start,
+        ap_done,
+        ap_idle,
+        ap_ready,
+        m_axi_mmap_AWVALID,
+        m_axi_mmap_AWREADY,
+        m_axi_mmap_AWADDR,
+        m_axi_mmap_AWID,
+        m_axi_mmap_AWLEN,
+        m_axi_mmap_AWSIZE,
+        m_axi_mmap_AWBURST,
+        m_axi_mmap_AWLOCK,
+        m_axi_mmap_AWCACHE,
+        m_axi_mmap_AWPROT,
+        m_axi_mmap_AWQOS,
+        m_axi_mmap_AWREGION,
+        m_axi_mmap_AWUSER,
+        m_axi_mmap_WVALID,
+        m_axi_mmap_WREADY,
+        m_axi_mmap_WDATA,
+        m_axi_mmap_WSTRB,
+        m_axi_mmap_WLAST,
+        m_axi_mmap_WID,
+        m_axi_mmap_WUSER,
+        m_axi_mmap_ARVALID,
+        m_axi_mmap_ARREADY,
+        m_axi_mmap_ARADDR,
+        m_axi_mmap_ARID,
+        m_axi_mmap_ARLEN,
+        m_axi_mmap_ARSIZE,
+        m_axi_mmap_ARBURST,
+        m_axi_mmap_ARLOCK,
+        m_axi_mmap_ARCACHE,
+        m_axi_mmap_ARPROT,
+        m_axi_mmap_ARQOS,
+        m_axi_mmap_ARREGION,
+        m_axi_mmap_ARUSER,
+        m_axi_mmap_RVALID,
+        m_axi_mmap_RREADY,
+        m_axi_mmap_RDATA,
+        m_axi_mmap_RLAST,
+        m_axi_mmap_RID,
+        m_axi_mmap_RUSER,
+        m_axi_mmap_RRESP,
+        m_axi_mmap_BVALID,
+        m_axi_mmap_BREADY,
+        m_axi_mmap_BRESP,
+        m_axi_mmap_BID,
+        m_axi_mmap_BUSER,
+        mmap_offset,
+        n,
+        stream_din,
+        stream_full_n,
+        stream_write
+);
+
+parameter    ap_ST_fsm_state1 = 9'd1;
+parameter    ap_ST_fsm_state2 = 9'd2;
+parameter    ap_ST_fsm_state3 = 9'd4;
+parameter    ap_ST_fsm_state4 = 9'd8;
+parameter    ap_ST_fsm_state5 = 9'd16;
+parameter    ap_ST_fsm_state6 = 9'd32;
+parameter    ap_ST_fsm_state7 = 9'd64;
+parameter    ap_ST_fsm_state8 = 9'd128;
+parameter    ap_ST_fsm_state9 = 9'd256;
+parameter    C_M_AXI_MMAP_ID_WIDTH = 1;
+parameter    C_M_AXI_MMAP_ADDR_WIDTH = 64;
+parameter    C_M_AXI_MMAP_DATA_WIDTH = 512;
+parameter    C_M_AXI_MMAP_AWUSER_WIDTH = 1;
+parameter    C_M_AXI_MMAP_ARUSER_WIDTH = 1;
+parameter    C_M_AXI_MMAP_WUSER_WIDTH = 1;
+parameter    C_M_AXI_MMAP_RUSER_WIDTH = 1;
+parameter    C_M_AXI_MMAP_BUSER_WIDTH = 1;
+parameter    C_M_AXI_MMAP_USER_VALUE = 0;
+parameter    C_M_AXI_MMAP_PROT_VALUE = 0;
+parameter    C_M_AXI_MMAP_CACHE_VALUE = 3;
+parameter    C_M_AXI_DATA_WIDTH = 32;
+
+parameter C_M_AXI_MMAP_WSTRB_WIDTH = (512 / 8);
+parameter C_M_AXI_WSTRB_WIDTH = (32 / 8);
+
+input   ap_clk;
+input   ap_rst_n;
+input   ap_start;
+output   ap_done;
+output   ap_idle;
+output   ap_ready;
+output   m_axi_mmap_AWVALID;
+input   m_axi_mmap_AWREADY;
+output  [C_M_AXI_MMAP_ADDR_WIDTH - 1:0] m_axi_mmap_AWADDR;
+output  [C_M_AXI_MMAP_ID_WIDTH - 1:0] m_axi_mmap_AWID;
+output  [7:0] m_axi_mmap_AWLEN;
+output  [2:0] m_axi_mmap_AWSIZE;
+output  [1:0] m_axi_mmap_AWBURST;
+output  [1:0] m_axi_mmap_AWLOCK;
+output  [3:0] m_axi_mmap_AWCACHE;
+output  [2:0] m_axi_mmap_AWPROT;
+output  [3:0] m_axi_mmap_AWQOS;
+output  [3:0] m_axi_mmap_AWREGION;
+output  [C_M_AXI_MMAP_AWUSER_WIDTH - 1:0] m_axi_mmap_AWUSER;
+output   m_axi_mmap_WVALID;
+input   m_axi_mmap_WREADY;
+output  [C_M_AXI_MMAP_DATA_WIDTH - 1:0] m_axi_mmap_WDATA;
+output  [C_M_AXI_MMAP_WSTRB_WIDTH - 1:0] m_axi_mmap_WSTRB;
+output   m_axi_mmap_WLAST;
+output  [C_M_AXI_MMAP_ID_WIDTH - 1:0] m_axi_mmap_WID;
+output  [C_M_AXI_MMAP_WUSER_WIDTH - 1:0] m_axi_mmap_WUSER;
+output   m_axi_mmap_ARVALID;
+input   m_axi_mmap_ARREADY;
+output  [C_M_AXI_MMAP_ADDR_WIDTH - 1:0] m_axi_mmap_ARADDR;
+output  [C_M_AXI_MMAP_ID_WIDTH - 1:0] m_axi_mmap_ARID;
+output  [7:0] m_axi_mmap_ARLEN;
+output  [2:0] m_axi_mmap_ARSIZE;
+output  [1:0] m_axi_mmap_ARBURST;
+output  [1:0] m_axi_mmap_ARLOCK;
+output  [3:0] m_axi_mmap_ARCACHE;
+output  [2:0] m_axi_mmap_ARPROT;
+output  [3:0] m_axi_mmap_ARQOS;
+output  [3:0] m_axi_mmap_ARREGION;
+output  [C_M_AXI_MMAP_ARUSER_WIDTH - 1:0] m_axi_mmap_ARUSER;
+input   m_axi_mmap_RVALID;
+output   m_axi_mmap_RREADY;
+input  [C_M_AXI_MMAP_DATA_WIDTH - 1:0] m_axi_mmap_RDATA;
+input   m_axi_mmap_RLAST;
+input  [C_M_AXI_MMAP_ID_WIDTH - 1:0] m_axi_mmap_RID;
+input  [C_M_AXI_MMAP_RUSER_WIDTH - 1:0] m_axi_mmap_RUSER;
+input  [1:0] m_axi_mmap_RRESP;
+input   m_axi_mmap_BVALID;
+output   m_axi_mmap_BREADY;
+input  [1:0] m_axi_mmap_BRESP;
+input  [C_M_AXI_MMAP_ID_WIDTH - 1:0] m_axi_mmap_BID;
+input  [C_M_AXI_MMAP_BUSER_WIDTH - 1:0] m_axi_mmap_BUSER;
+input  [63:0] mmap_offset;
+input  [63:0] n;
+output  [512:0] stream_din;
+input   stream_full_n;
+output   stream_write;
+
+reg ap_done;
+reg ap_idle;
+reg ap_ready;
+reg stream_write;
+
+ reg    ap_rst_n_inv;
+(* fsm_encoding = "none" *) reg   [8:0] ap_CS_fsm;
+wire    ap_CS_fsm_state1;
+reg    mmap_blk_n_AR;
+wire  signed [57:0] trunc_ln59_1_fu_90_p4;
+reg   [57:0] trunc_ln59_1_reg_121;
+wire   [31:0] trunc_ln59_fu_111_p1;
+wire    grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_ap_start;
+wire    grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_ap_done;
+wire    grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_ap_idle;
+wire    grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_ap_ready;
+wire    grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_AWVALID;
+wire   [63:0] grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_AWADDR;
+wire   [0:0] grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_AWID;
+wire   [31:0] grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_AWLEN;
+wire   [2:0] grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_AWSIZE;
+wire   [1:0] grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_AWBURST;
+wire   [1:0] grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_AWLOCK;
+wire   [3:0] grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_AWCACHE;
+wire   [2:0] grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_AWPROT;
+wire   [3:0] grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_AWQOS;
+wire   [3:0] grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_AWREGION;
+wire   [0:0] grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_AWUSER;
+wire    grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_WVALID;
+wire   [511:0] grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_WDATA;
+wire   [63:0] grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_WSTRB;
+wire    grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_WLAST;
+wire   [0:0] grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_WID;
+wire   [0:0] grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_WUSER;
+wire    grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_ARVALID;
+wire   [63:0] grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_ARADDR;
+wire   [0:0] grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_ARID;
+wire   [31:0] grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_ARLEN;
+wire   [2:0] grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_ARSIZE;
+wire   [1:0] grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_ARBURST;
+wire   [1:0] grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_ARLOCK;
+wire   [3:0] grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_ARCACHE;
+wire   [2:0] grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_ARPROT;
+wire   [3:0] grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_ARQOS;
+wire   [3:0] grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_ARREGION;
+wire   [0:0] grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_ARUSER;
+wire    grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_RREADY;
+wire    grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_BREADY;
+wire   [512:0] grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_stream_din;
+wire    grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_stream_write;
+wire    mmap_AWREADY;
+wire    mmap_WREADY;
+reg    mmap_ARVALID;
+wire    mmap_ARREADY;
+reg   [63:0] mmap_ARADDR;
+reg   [31:0] mmap_ARLEN;
+wire    mmap_RVALID;
+reg    mmap_RREADY;
+wire   [511:0] mmap_RDATA;
+wire   [8:0] mmap_RFIFONUM;
+wire    mmap_BVALID;
+reg    grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_ap_start_reg;
+wire    ap_CS_fsm_state7;
+reg   [8:0] ap_NS_fsm;
+wire    ap_NS_fsm_state8;
+wire    ap_CS_fsm_state8;
+wire    ap_CS_fsm_state9;
+wire  signed [63:0] sext_ln59_fu_100_p1;
+reg    ap_ST_fsm_state1_blk;
+wire    ap_ST_fsm_state2_blk;
+wire    ap_ST_fsm_state3_blk;
+wire    ap_ST_fsm_state4_blk;
+wire    ap_ST_fsm_state5_blk;
+wire    ap_ST_fsm_state6_blk;
+wire    ap_ST_fsm_state7_blk;
+wire    ap_ST_fsm_state8_blk;
+reg    ap_ST_fsm_state9_blk;
+wire    ap_ce_reg;
+
+// power-on initialization
+initial begin
+#0 ap_CS_fsm = 9'd1;
+#0 grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_ap_start_reg = 1'b0;
+end
+
+Mmap2Stream_Mmap2Stream_Pipeline_VITIS_LOOP_59_1 grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80(
+    .ap_clk(ap_clk),
+    .ap_rst(ap_rst_n_inv),
+    .ap_start(grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_ap_start),
+    .ap_done(grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_ap_done),
+    .ap_idle(grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_ap_idle),
+    .ap_ready(grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_ap_ready),
+    .m_axi_mmap_AWVALID(grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_AWVALID),
+    .m_axi_mmap_AWREADY(1'b0),
+    .m_axi_mmap_AWADDR(grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_AWADDR),
+    .m_axi_mmap_AWID(grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_AWID),
+    .m_axi_mmap_AWLEN(grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_AWLEN),
+    .m_axi_mmap_AWSIZE(grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_AWSIZE),
+    .m_axi_mmap_AWBURST(grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_AWBURST),
+    .m_axi_mmap_AWLOCK(grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_AWLOCK),
+    .m_axi_mmap_AWCACHE(grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_AWCACHE),
+    .m_axi_mmap_AWPROT(grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_AWPROT),
+    .m_axi_mmap_AWQOS(grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_AWQOS),
+    .m_axi_mmap_AWREGION(grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_AWREGION),
+    .m_axi_mmap_AWUSER(grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_AWUSER),
+    .m_axi_mmap_WVALID(grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_WVALID),
+    .m_axi_mmap_WREADY(1'b0),
+    .m_axi_mmap_WDATA(grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_WDATA),
+    .m_axi_mmap_WSTRB(grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_WSTRB),
+    .m_axi_mmap_WLAST(grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_WLAST),
+    .m_axi_mmap_WID(grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_WID),
+    .m_axi_mmap_WUSER(grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_WUSER),
+    .m_axi_mmap_ARVALID(grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_ARVALID),
+    .m_axi_mmap_ARREADY(mmap_ARREADY),
+    .m_axi_mmap_ARADDR(grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_ARADDR),
+    .m_axi_mmap_ARID(grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_ARID),
+    .m_axi_mmap_ARLEN(grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_ARLEN),
+    .m_axi_mmap_ARSIZE(grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_ARSIZE),
+    .m_axi_mmap_ARBURST(grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_ARBURST),
+    .m_axi_mmap_ARLOCK(grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_ARLOCK),
+    .m_axi_mmap_ARCACHE(grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_ARCACHE),
+    .m_axi_mmap_ARPROT(grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_ARPROT),
+    .m_axi_mmap_ARQOS(grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_ARQOS),
+    .m_axi_mmap_ARREGION(grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_ARREGION),
+    .m_axi_mmap_ARUSER(grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_ARUSER),
+    .m_axi_mmap_RVALID(mmap_RVALID),
+    .m_axi_mmap_RREADY(grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_RREADY),
+    .m_axi_mmap_RDATA(mmap_RDATA),
+    .m_axi_mmap_RLAST(1'b0),
+    .m_axi_mmap_RID(1'd0),
+    .m_axi_mmap_RFIFONUM(mmap_RFIFONUM),
+    .m_axi_mmap_RUSER(1'd0),
+    .m_axi_mmap_RRESP(2'd0),
+    .m_axi_mmap_BVALID(1'b0),
+    .m_axi_mmap_BREADY(grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_BREADY),
+    .m_axi_mmap_BRESP(2'd0),
+    .m_axi_mmap_BID(1'd0),
+    .m_axi_mmap_BUSER(1'd0),
+    .stream_din(grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_stream_din),
+    .stream_full_n(stream_full_n),
+    .stream_write(grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_stream_write),
+    .sext_ln59(trunc_ln59_1_reg_121),
+    .n(n)
+);
+
+Mmap2Stream_mmap_m_axi #(
+    .CONSERVATIVE( 1 ),
+    .USER_MAXREQS( 5 ),
+    .MAX_READ_BURST_LENGTH( 16 ),
+    .MAX_WRITE_BURST_LENGTH( 16 ),
+    .C_M_AXI_ID_WIDTH( C_M_AXI_MMAP_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH( C_M_AXI_MMAP_ADDR_WIDTH ),
+    .C_M_AXI_DATA_WIDTH( C_M_AXI_MMAP_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH( C_M_AXI_MMAP_AWUSER_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH( C_M_AXI_MMAP_ARUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH( C_M_AXI_MMAP_WUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH( C_M_AXI_MMAP_RUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH( C_M_AXI_MMAP_BUSER_WIDTH ),
+    .C_USER_VALUE( C_M_AXI_MMAP_USER_VALUE ),
+    .C_PROT_VALUE( C_M_AXI_MMAP_PROT_VALUE ),
+    .C_CACHE_VALUE( C_M_AXI_MMAP_CACHE_VALUE ),
+    .USER_RFIFONUM_WIDTH( 9 ),
+    .USER_DW( 512 ),
+    .USER_AW( 64 ),
+    .NUM_READ_OUTSTANDING( 16 ),
+    .NUM_WRITE_OUTSTANDING( 16 ))
+mmap_m_axi_U(
+    .AWVALID(m_axi_mmap_AWVALID),
+    .AWREADY(m_axi_mmap_AWREADY),
+    .AWADDR(m_axi_mmap_AWADDR),
+    .AWID(m_axi_mmap_AWID),
+    .AWLEN(m_axi_mmap_AWLEN),
+    .AWSIZE(m_axi_mmap_AWSIZE),
+    .AWBURST(m_axi_mmap_AWBURST),
+    .AWLOCK(m_axi_mmap_AWLOCK),
+    .AWCACHE(m_axi_mmap_AWCACHE),
+    .AWPROT(m_axi_mmap_AWPROT),
+    .AWQOS(m_axi_mmap_AWQOS),
+    .AWREGION(m_axi_mmap_AWREGION),
+    .AWUSER(m_axi_mmap_AWUSER),
+    .WVALID(m_axi_mmap_WVALID),
+    .WREADY(m_axi_mmap_WREADY),
+    .WDATA(m_axi_mmap_WDATA),
+    .WSTRB(m_axi_mmap_WSTRB),
+    .WLAST(m_axi_mmap_WLAST),
+    .WID(m_axi_mmap_WID),
+    .WUSER(m_axi_mmap_WUSER),
+    .ARVALID(m_axi_mmap_ARVALID),
+    .ARREADY(m_axi_mmap_ARREADY),
+    .ARADDR(m_axi_mmap_ARADDR),
+    .ARID(m_axi_mmap_ARID),
+    .ARLEN(m_axi_mmap_ARLEN),
+    .ARSIZE(m_axi_mmap_ARSIZE),
+    .ARBURST(m_axi_mmap_ARBURST),
+    .ARLOCK(m_axi_mmap_ARLOCK),
+    .ARCACHE(m_axi_mmap_ARCACHE),
+    .ARPROT(m_axi_mmap_ARPROT),
+    .ARQOS(m_axi_mmap_ARQOS),
+    .ARREGION(m_axi_mmap_ARREGION),
+    .ARUSER(m_axi_mmap_ARUSER),
+    .RVALID(m_axi_mmap_RVALID),
+    .RREADY(m_axi_mmap_RREADY),
+    .RDATA(m_axi_mmap_RDATA),
+    .RLAST(m_axi_mmap_RLAST),
+    .RID(m_axi_mmap_RID),
+    .RUSER(m_axi_mmap_RUSER),
+    .RRESP(m_axi_mmap_RRESP),
+    .BVALID(m_axi_mmap_BVALID),
+    .BREADY(m_axi_mmap_BREADY),
+    .BRESP(m_axi_mmap_BRESP),
+    .BID(m_axi_mmap_BID),
+    .BUSER(m_axi_mmap_BUSER),
+    .ACLK(ap_clk),
+    .ARESET(ap_rst_n_inv),
+    .ACLK_EN(1'b1),
+    .I_ARVALID(mmap_ARVALID),
+    .I_ARREADY(mmap_ARREADY),
+    .I_ARADDR(mmap_ARADDR),
+    .I_ARLEN(mmap_ARLEN),
+    .I_RVALID(mmap_RVALID),
+    .I_RREADY(mmap_RREADY),
+    .I_RDATA(mmap_RDATA),
+    .I_RFIFONUM(mmap_RFIFONUM),
+    .I_AWVALID(1'b0),
+    .I_AWREADY(mmap_AWREADY),
+    .I_AWADDR(64'd0),
+    .I_AWLEN(32'd0),
+    .I_WVALID(1'b0),
+    .I_WREADY(mmap_WREADY),
+    .I_WDATA(512'd0),
+    .I_WSTRB(64'd0),
+    .I_BVALID(mmap_BVALID),
+    .I_BREADY(1'b0)
+);
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_CS_fsm <= ap_ST_fsm_state1;
+    end else begin
+        ap_CS_fsm <= ap_NS_fsm;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_ap_start_reg <= 1'b0;
+    end else begin
+        if (((1'b1 == ap_NS_fsm_state8) & (1'b1 == ap_CS_fsm_state7))) begin
+            grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_ap_start_reg <= 1'b1;
+        end else if ((grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_ap_ready == 1'b1)) begin
+            grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_ap_start_reg <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state1)) begin
+        trunc_ln59_1_reg_121 <= {{mmap_offset[63:6]}};
+    end
+end
+
+always @ (*) begin
+    if (((mmap_ARREADY == 1'b0) | (ap_start == 1'b0))) begin
+        ap_ST_fsm_state1_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state1_blk = 1'b0;
+    end
+end
+
+assign ap_ST_fsm_state2_blk = 1'b0;
+
+assign ap_ST_fsm_state3_blk = 1'b0;
+
+assign ap_ST_fsm_state4_blk = 1'b0;
+
+assign ap_ST_fsm_state5_blk = 1'b0;
+
+assign ap_ST_fsm_state6_blk = 1'b0;
+
+assign ap_ST_fsm_state7_blk = 1'b0;
+
+assign ap_ST_fsm_state8_blk = 1'b0;
+
+always @ (*) begin
+    if ((grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_ap_done == 1'b0)) begin
+        ap_ST_fsm_state9_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state9_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state9) & (grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_ap_done == 1'b1))) begin
+        ap_done = 1'b1;
+    end else begin
+        ap_done = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin
+        ap_idle = 1'b1;
+    end else begin
+        ap_idle = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state9) & (grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_ap_done == 1'b1))) begin
+        ap_ready = 1'b1;
+    end else begin
+        ap_ready = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((~((mmap_ARREADY == 1'b0) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin
+        mmap_ARADDR = sext_ln59_fu_100_p1;
+    end else if (((1'b1 == ap_CS_fsm_state9) | (1'b1 == ap_CS_fsm_state8))) begin
+        mmap_ARADDR = grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_ARADDR;
+    end else begin
+        mmap_ARADDR = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((~((mmap_ARREADY == 1'b0) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin
+        mmap_ARLEN = trunc_ln59_fu_111_p1;
+    end else if (((1'b1 == ap_CS_fsm_state9) | (1'b1 == ap_CS_fsm_state8))) begin
+        mmap_ARLEN = grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_ARLEN;
+    end else begin
+        mmap_ARLEN = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((~((mmap_ARREADY == 1'b0) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin
+        mmap_ARVALID = 1'b1;
+    end else if (((1'b1 == ap_CS_fsm_state9) | (1'b1 == ap_CS_fsm_state8))) begin
+        mmap_ARVALID = grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_ARVALID;
+    end else begin
+        mmap_ARVALID = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state9) | (1'b1 == ap_CS_fsm_state8))) begin
+        mmap_RREADY = grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_m_axi_mmap_RREADY;
+    end else begin
+        mmap_RREADY = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
+        mmap_blk_n_AR = m_axi_mmap_ARREADY;
+    end else begin
+        mmap_blk_n_AR = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state9)) begin
+        stream_write = grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_stream_write;
+    end else begin
+        stream_write = 1'b0;
+    end
+end
+
+always @ (*) begin
+    case (ap_CS_fsm)
+        ap_ST_fsm_state1 : begin
+            if ((~((mmap_ARREADY == 1'b0) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end
+        end
+        ap_ST_fsm_state2 : begin
+            ap_NS_fsm = ap_ST_fsm_state3;
+        end
+        ap_ST_fsm_state3 : begin
+            ap_NS_fsm = ap_ST_fsm_state4;
+        end
+        ap_ST_fsm_state4 : begin
+            ap_NS_fsm = ap_ST_fsm_state5;
+        end
+        ap_ST_fsm_state5 : begin
+            ap_NS_fsm = ap_ST_fsm_state6;
+        end
+        ap_ST_fsm_state6 : begin
+            ap_NS_fsm = ap_ST_fsm_state7;
+        end
+        ap_ST_fsm_state7 : begin
+            ap_NS_fsm = ap_ST_fsm_state8;
+        end
+        ap_ST_fsm_state8 : begin
+            ap_NS_fsm = ap_ST_fsm_state9;
+        end
+        ap_ST_fsm_state9 : begin
+            if (((1'b1 == ap_CS_fsm_state9) & (grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_ap_done == 1'b1))) begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state9;
+            end
+        end
+        default : begin
+            ap_NS_fsm = 'bx;
+        end
+    endcase
+end
+
+assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
+
+assign ap_CS_fsm_state7 = ap_CS_fsm[32'd6];
+
+assign ap_CS_fsm_state8 = ap_CS_fsm[32'd7];
+
+assign ap_CS_fsm_state9 = ap_CS_fsm[32'd8];
+
+assign ap_NS_fsm_state8 = ap_NS_fsm[32'd7];
+
+always @ (*) begin
+    ap_rst_n_inv = ~ap_rst_n;
+end
+
+assign grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_ap_start = grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_ap_start_reg;
+
+assign sext_ln59_fu_100_p1 = trunc_ln59_1_fu_90_p4;
+
+assign stream_din = grp_Mmap2Stream_Pipeline_VITIS_LOOP_59_1_fu_80_stream_din;
+
+assign trunc_ln59_1_fu_90_p4 = {{mmap_offset[63:6]}};
+
+assign trunc_ln59_fu_111_p1 = n[31:0];
+
+endmodule //Mmap2Stream
diff --git a/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/Mmap2Stream_Mmap2Stream_Pipeline_VITIS_LOOP_59_1.v b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/Mmap2Stream_Mmap2Stream_Pipeline_VITIS_LOOP_59_1.v
new file mode 100644
index 00000000..02bbb064
--- /dev/null
+++ b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/Mmap2Stream_Mmap2Stream_Pipeline_VITIS_LOOP_59_1.v
@@ -0,0 +1,464 @@
+// ==============================================================
+// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit)
+// Version: 2022.2
+// Copyright (C) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+//
+// ===========================================================
+
+`timescale 1 ns / 1 ps
+
+module Mmap2Stream_Mmap2Stream_Pipeline_VITIS_LOOP_59_1 (
+        ap_clk,
+        ap_rst,
+        ap_start,
+        ap_done,
+        ap_idle,
+        ap_ready,
+        m_axi_mmap_AWVALID,
+        m_axi_mmap_AWREADY,
+        m_axi_mmap_AWADDR,
+        m_axi_mmap_AWID,
+        m_axi_mmap_AWLEN,
+        m_axi_mmap_AWSIZE,
+        m_axi_mmap_AWBURST,
+        m_axi_mmap_AWLOCK,
+        m_axi_mmap_AWCACHE,
+        m_axi_mmap_AWPROT,
+        m_axi_mmap_AWQOS,
+        m_axi_mmap_AWREGION,
+        m_axi_mmap_AWUSER,
+        m_axi_mmap_WVALID,
+        m_axi_mmap_WREADY,
+        m_axi_mmap_WDATA,
+        m_axi_mmap_WSTRB,
+        m_axi_mmap_WLAST,
+        m_axi_mmap_WID,
+        m_axi_mmap_WUSER,
+        m_axi_mmap_ARVALID,
+        m_axi_mmap_ARREADY,
+        m_axi_mmap_ARADDR,
+        m_axi_mmap_ARID,
+        m_axi_mmap_ARLEN,
+        m_axi_mmap_ARSIZE,
+        m_axi_mmap_ARBURST,
+        m_axi_mmap_ARLOCK,
+        m_axi_mmap_ARCACHE,
+        m_axi_mmap_ARPROT,
+        m_axi_mmap_ARQOS,
+        m_axi_mmap_ARREGION,
+        m_axi_mmap_ARUSER,
+        m_axi_mmap_RVALID,
+        m_axi_mmap_RREADY,
+        m_axi_mmap_RDATA,
+        m_axi_mmap_RLAST,
+        m_axi_mmap_RID,
+        m_axi_mmap_RFIFONUM,
+        m_axi_mmap_RUSER,
+        m_axi_mmap_RRESP,
+        m_axi_mmap_BVALID,
+        m_axi_mmap_BREADY,
+        m_axi_mmap_BRESP,
+        m_axi_mmap_BID,
+        m_axi_mmap_BUSER,
+        stream_din,
+        stream_full_n,
+        stream_write,
+        sext_ln59,
+        n
+);
+
+parameter    ap_ST_fsm_pp0_stage0 = 1'd1;
+
+input   ap_clk;
+input   ap_rst;
+input   ap_start;
+output   ap_done;
+output   ap_idle;
+output   ap_ready;
+output   m_axi_mmap_AWVALID;
+input   m_axi_mmap_AWREADY;
+output  [63:0] m_axi_mmap_AWADDR;
+output  [0:0] m_axi_mmap_AWID;
+output  [31:0] m_axi_mmap_AWLEN;
+output  [2:0] m_axi_mmap_AWSIZE;
+output  [1:0] m_axi_mmap_AWBURST;
+output  [1:0] m_axi_mmap_AWLOCK;
+output  [3:0] m_axi_mmap_AWCACHE;
+output  [2:0] m_axi_mmap_AWPROT;
+output  [3:0] m_axi_mmap_AWQOS;
+output  [3:0] m_axi_mmap_AWREGION;
+output  [0:0] m_axi_mmap_AWUSER;
+output   m_axi_mmap_WVALID;
+input   m_axi_mmap_WREADY;
+output  [511:0] m_axi_mmap_WDATA;
+output  [63:0] m_axi_mmap_WSTRB;
+output   m_axi_mmap_WLAST;
+output  [0:0] m_axi_mmap_WID;
+output  [0:0] m_axi_mmap_WUSER;
+output   m_axi_mmap_ARVALID;
+input   m_axi_mmap_ARREADY;
+output  [63:0] m_axi_mmap_ARADDR;
+output  [0:0] m_axi_mmap_ARID;
+output  [31:0] m_axi_mmap_ARLEN;
+output  [2:0] m_axi_mmap_ARSIZE;
+output  [1:0] m_axi_mmap_ARBURST;
+output  [1:0] m_axi_mmap_ARLOCK;
+output  [3:0] m_axi_mmap_ARCACHE;
+output  [2:0] m_axi_mmap_ARPROT;
+output  [3:0] m_axi_mmap_ARQOS;
+output  [3:0] m_axi_mmap_ARREGION;
+output  [0:0] m_axi_mmap_ARUSER;
+input   m_axi_mmap_RVALID;
+output   m_axi_mmap_RREADY;
+input  [511:0] m_axi_mmap_RDATA;
+input   m_axi_mmap_RLAST;
+input  [0:0] m_axi_mmap_RID;
+input  [8:0] m_axi_mmap_RFIFONUM;
+input  [0:0] m_axi_mmap_RUSER;
+input  [1:0] m_axi_mmap_RRESP;
+input   m_axi_mmap_BVALID;
+output   m_axi_mmap_BREADY;
+input  [1:0] m_axi_mmap_BRESP;
+input  [0:0] m_axi_mmap_BID;
+input  [0:0] m_axi_mmap_BUSER;
+output  [512:0] stream_din;
+input   stream_full_n;
+output   stream_write;
+input  [57:0] sext_ln59;
+input  [63:0] n;
+
+reg ap_idle;
+reg m_axi_mmap_RREADY;
+reg stream_write;
+
+(* fsm_encoding = "none" *) reg   [0:0] ap_CS_fsm;
+wire    ap_CS_fsm_pp0_stage0;
+wire    ap_enable_reg_pp0_iter0;
+reg    ap_enable_reg_pp0_iter1;
+reg    ap_enable_reg_pp0_iter2;
+reg    ap_enable_reg_pp0_iter3;
+reg    ap_idle_pp0;
+wire    ap_block_state1_pp0_stage0_iter0;
+wire    ap_block_state2_pp0_stage0_iter1;
+reg   [0:0] icmp_ln59_reg_141;
+reg    ap_block_state3_pp0_stage0_iter2;
+reg    ap_block_state4_pp0_stage0_iter3;
+reg    ap_block_pp0_stage0_subdone;
+wire   [0:0] icmp_ln59_fu_94_p2;
+reg    ap_condition_exit_pp0_iter1_stage0;
+wire    ap_loop_exit_ready;
+reg    ap_ready_int;
+reg    mmap_blk_n_R;
+wire    ap_block_pp0_stage0;
+reg    stream_blk_n;
+reg    ap_block_pp0_stage0_11001;
+reg   [511:0] mmap_addr_read_reg_145;
+reg    ap_condition_exit_pp0_iter2_stage0;
+reg   [63:0] i_fu_54;
+wire   [63:0] i_2_fu_99_p2;
+wire    ap_loop_init;
+reg    ap_block_pp0_stage0_01001;
+reg    ap_done_reg;
+wire    ap_continue_int;
+reg    ap_done_int;
+reg    ap_loop_exit_ready_pp0_iter2_reg;
+reg   [0:0] ap_NS_fsm;
+wire    ap_enable_pp0;
+wire    ap_start_int;
+wire    ap_ce_reg;
+
+// power-on initialization
+initial begin
+#0 ap_CS_fsm = 1'd1;
+#0 ap_enable_reg_pp0_iter1 = 1'b0;
+#0 ap_enable_reg_pp0_iter2 = 1'b0;
+#0 ap_enable_reg_pp0_iter3 = 1'b0;
+#0 ap_done_reg = 1'b0;
+end
+
+Mmap2Stream_flow_control_loop_pipe_sequential_init flow_control_loop_pipe_sequential_init_U(
+    .ap_clk(ap_clk),
+    .ap_rst(ap_rst),
+    .ap_start(ap_start),
+    .ap_ready(ap_ready),
+    .ap_done(ap_done),
+    .ap_start_int(ap_start_int),
+    .ap_loop_init(ap_loop_init),
+    .ap_ready_int(ap_ready_int),
+    .ap_loop_exit_ready(ap_condition_exit_pp0_iter1_stage0),
+    .ap_loop_exit_done(ap_done_int),
+    .ap_continue_int(ap_continue_int),
+    .ap_done_int(ap_done_int)
+);
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_CS_fsm <= ap_ST_fsm_pp0_stage0;
+    end else begin
+        ap_CS_fsm <= ap_NS_fsm;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_done_reg <= 1'b0;
+    end else begin
+        if ((ap_continue_int == 1'b1)) begin
+            ap_done_reg <= 1'b0;
+        end else if (((ap_loop_exit_ready_pp0_iter2_reg == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone))) begin
+            ap_done_reg <= 1'b1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_enable_reg_pp0_iter1 <= 1'b0;
+    end else begin
+        if ((1'b1 == ap_condition_exit_pp0_iter1_stage0)) begin
+            ap_enable_reg_pp0_iter1 <= 1'b0;
+        end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_subdone))) begin
+            ap_enable_reg_pp0_iter1 <= ap_start_int;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_enable_reg_pp0_iter2 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
+            ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_enable_reg_pp0_iter3 <= 1'b0;
+    end else begin
+        if ((1'b1 == ap_condition_exit_pp0_iter2_stage0)) begin
+            ap_enable_reg_pp0_iter3 <= 1'b0;
+        end else if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
+            ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin
+        if ((ap_loop_init == 1'b1)) begin
+            i_fu_54 <= 64'd0;
+        end else if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln59_fu_94_p2 == 1'd0))) begin
+            i_fu_54 <= i_2_fu_99_p2;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin
+        ap_loop_exit_ready_pp0_iter2_reg <= ap_loop_exit_ready;
+        icmp_ln59_reg_141 <= icmp_ln59_fu_94_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((icmp_ln59_reg_141 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin
+        mmap_addr_read_reg_145 <= m_axi_mmap_RDATA;
+    end
+end
+
+always @ (*) begin
+    if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln59_fu_94_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone))) begin
+        ap_condition_exit_pp0_iter1_stage0 = 1'b1;
+    end else begin
+        ap_condition_exit_pp0_iter1_stage0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((icmp_ln59_reg_141 == 1'd1) & (ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone))) begin
+        ap_condition_exit_pp0_iter2_stage0 = 1'b1;
+    end else begin
+        ap_condition_exit_pp0_iter2_stage0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_loop_exit_ready_pp0_iter2_reg == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone))) begin
+        ap_done_int = 1'b1;
+    end else begin
+        ap_done_int = ap_done_reg;
+    end
+end
+
+always @ (*) begin
+    if (((ap_idle_pp0 == 1'b1) & (ap_start_int == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        ap_idle = 1'b1;
+    end else begin
+        ap_idle = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin
+        ap_idle_pp0 = 1'b1;
+    end else begin
+        ap_idle_pp0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_subdone))) begin
+        ap_ready_int = 1'b1;
+    end else begin
+        ap_ready_int = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((icmp_ln59_reg_141 == 1'd0) & (ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin
+        m_axi_mmap_RREADY = 1'b1;
+    end else begin
+        m_axi_mmap_RREADY = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((icmp_ln59_reg_141 == 1'd0) & (ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage0))) begin
+        mmap_blk_n_R = m_axi_mmap_RVALID;
+    end else begin
+        mmap_blk_n_R = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0))) begin
+        stream_blk_n = stream_full_n;
+    end else begin
+        stream_blk_n = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin
+        stream_write = 1'b1;
+    end else begin
+        stream_write = 1'b0;
+    end
+end
+
+always @ (*) begin
+    case (ap_CS_fsm)
+        ap_ST_fsm_pp0_stage0 : begin
+            ap_NS_fsm = ap_ST_fsm_pp0_stage0;
+        end
+        default : begin
+            ap_NS_fsm = 'bx;
+        end
+    endcase
+end
+
+assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd0];
+
+assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_block_pp0_stage0_01001 = (((icmp_ln59_reg_141 == 1'd0) & (m_axi_mmap_RVALID == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((stream_full_n == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b1)));
+end
+
+always @ (*) begin
+    ap_block_pp0_stage0_11001 = (((icmp_ln59_reg_141 == 1'd0) & (m_axi_mmap_RVALID == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((stream_full_n == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b1)));
+end
+
+always @ (*) begin
+    ap_block_pp0_stage0_subdone = (((icmp_ln59_reg_141 == 1'd0) & (m_axi_mmap_RVALID == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((stream_full_n == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b1)));
+end
+
+assign ap_block_state1_pp0_stage0_iter0 = ~(1'b1 == 1'b1);
+
+assign ap_block_state2_pp0_stage0_iter1 = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_block_state3_pp0_stage0_iter2 = ((icmp_ln59_reg_141 == 1'd0) & (m_axi_mmap_RVALID == 1'b0));
+end
+
+always @ (*) begin
+    ap_block_state4_pp0_stage0_iter3 = (stream_full_n == 1'b0);
+end
+
+assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1);
+
+assign ap_enable_reg_pp0_iter0 = ap_start_int;
+
+assign ap_loop_exit_ready = ap_condition_exit_pp0_iter1_stage0;
+
+assign i_2_fu_99_p2 = (i_fu_54 + 64'd1);
+
+assign icmp_ln59_fu_94_p2 = ((i_fu_54 == n) ? 1'b1 : 1'b0);
+
+assign m_axi_mmap_ARADDR = 64'd0;
+
+assign m_axi_mmap_ARBURST = 2'd0;
+
+assign m_axi_mmap_ARCACHE = 4'd0;
+
+assign m_axi_mmap_ARID = 1'd0;
+
+assign m_axi_mmap_ARLEN = 32'd0;
+
+assign m_axi_mmap_ARLOCK = 2'd0;
+
+assign m_axi_mmap_ARPROT = 3'd0;
+
+assign m_axi_mmap_ARQOS = 4'd0;
+
+assign m_axi_mmap_ARREGION = 4'd0;
+
+assign m_axi_mmap_ARSIZE = 3'd0;
+
+assign m_axi_mmap_ARUSER = 1'd0;
+
+assign m_axi_mmap_ARVALID = 1'b0;
+
+assign m_axi_mmap_AWADDR = 64'd0;
+
+assign m_axi_mmap_AWBURST = 2'd0;
+
+assign m_axi_mmap_AWCACHE = 4'd0;
+
+assign m_axi_mmap_AWID = 1'd0;
+
+assign m_axi_mmap_AWLEN = 32'd0;
+
+assign m_axi_mmap_AWLOCK = 2'd0;
+
+assign m_axi_mmap_AWPROT = 3'd0;
+
+assign m_axi_mmap_AWQOS = 4'd0;
+
+assign m_axi_mmap_AWREGION = 4'd0;
+
+assign m_axi_mmap_AWSIZE = 3'd0;
+
+assign m_axi_mmap_AWUSER = 1'd0;
+
+assign m_axi_mmap_AWVALID = 1'b0;
+
+assign m_axi_mmap_BREADY = 1'b0;
+
+assign m_axi_mmap_WDATA = 512'd0;
+
+assign m_axi_mmap_WID = 1'd0;
+
+assign m_axi_mmap_WLAST = 1'b0;
+
+assign m_axi_mmap_WSTRB = 64'd0;
+
+assign m_axi_mmap_WUSER = 1'd0;
+
+assign m_axi_mmap_WVALID = 1'b0;
+
+assign stream_din = {{1'd0}, {mmap_addr_read_reg_145}};
+
+endmodule //Mmap2Stream_Mmap2Stream_Pipeline_VITIS_LOOP_59_1
diff --git a/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/Mmap2Stream_flow_control_loop_pipe_sequential_init.v b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/Mmap2Stream_flow_control_loop_pipe_sequential_init.v
new file mode 100644
index 00000000..ed4feea3
--- /dev/null
+++ b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/Mmap2Stream_flow_control_loop_pipe_sequential_init.v
@@ -0,0 +1,104 @@
+// ==============================================================
+// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit)
+// Tool Version Limit: 2019.12
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+
+`timescale 1 ns / 1 ps
+
+module Mmap2Stream_flow_control_loop_pipe_sequential_init(
+        ap_clk,
+        ap_rst,
+        ap_start,
+        ap_ready,
+        ap_done,
+        ap_start_int,
+        ap_ready_int,
+        ap_done_int,
+        ap_continue_int,
+        ap_loop_init,
+        ap_loop_exit_ready,
+        ap_loop_exit_done
+);
+
+input   ap_clk;
+input   ap_rst;
+
+//Block level handshake with outside loop
+input   ap_start;
+output  ap_ready;
+output  ap_done;
+
+//Block level handshake with loop body
+output  ap_start_int;
+input   ap_ready_int;
+input   ap_done_int;
+output  ap_continue_int;
+
+//Init live in variables
+output   ap_loop_init;
+wire     ap_loop_init;
+reg ap_loop_init_int;
+reg ap_done;
+reg ap_done_cache;
+
+//Exit signal from loop body
+input   ap_loop_exit_ready;
+input   ap_loop_exit_done;
+
+// power-on initialization
+initial begin
+#0 ap_loop_init_int = 1'b1;
+#0 ap_done_cache = 1'b0;
+end
+
+assign ap_start_int = ap_start;
+
+assign ap_continue_int = 1'b1;
+
+assign ap_ready = ap_loop_exit_ready;
+
+//ap_loop_init is valid for the first II
+//of the first loop run so as to enable
+//the init block ops which are pushed into
+//the first state of the pipeline region
+always @ (posedge ap_clk)
+begin
+    if (ap_rst == 1'b1) begin
+        ap_loop_init_int <= 1'b1;
+    end else if(ap_loop_exit_done == 1'b1) begin
+        ap_loop_init_int <= 1'b1;
+    end else if(ap_ready_int == 1'b1) begin
+        ap_loop_init_int <= 1'b0;
+    end
+end
+
+assign ap_loop_init = ap_loop_init_int & ap_start;
+
+// if no ap_continue port and current module is not top module,
+// ap_done handshakes with ap_start. Internally, flow control sends out
+// ap_conintue_int = 1'b1 so the ap_done_int is asserted high for 1 clock cycle.
+// ap_done_cache is used to record ap_done_int, and de-assert if ap_start_int
+// is asserted, so DUT can start the next run
+always @(posedge ap_clk)
+begin
+    if (ap_rst == 1'b1) begin
+        ap_done_cache <= 1'b0;
+    end else if (ap_done_int == 1'b1) begin
+        ap_done_cache <= 1'b1;
+    end else if (ap_start_int == 1'b1) begin
+        ap_done_cache <= 1'b0;
+    end
+end
+
+// if no ap_continue port and current module is not top module, ap_done handshakes with ap_start
+always @(*)
+begin
+    if ((ap_done_int == 1'b1) || ((ap_done_cache == 1'b1) && (ap_start_int == 1'b0))) begin
+        ap_done = 1'b1;
+    end else begin
+        ap_done = 1'b0;
+    end
+end
+
+endmodule
diff --git a/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/Mmap2Stream_mmap_m_axi.v b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/Mmap2Stream_mmap_m_axi.v
new file mode 100644
index 00000000..ec155b7f
--- /dev/null
+++ b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/Mmap2Stream_mmap_m_axi.v
@@ -0,0 +1,2823 @@
+// ==============================================================
+// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit)
+// Version: 2022.2
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+`timescale 1ns/1ps
+`default_nettype none
+
+module Mmap2Stream_mmap_m_axi
+#(parameter
+    CONSERVATIVE            = 0,
+    NUM_READ_OUTSTANDING    = 2,
+    NUM_WRITE_OUTSTANDING   = 2,
+    MAX_READ_BURST_LENGTH   = 16,
+    MAX_WRITE_BURST_LENGTH  = 16,
+    C_M_AXI_ID_WIDTH        = 1,
+    C_M_AXI_ADDR_WIDTH      = 32,
+    C_M_AXI_DATA_WIDTH      = 32, // power of 2 & range: 2 to 1024
+    C_M_AXI_AWUSER_WIDTH    = 1,
+    C_M_AXI_ARUSER_WIDTH    = 1,
+    C_M_AXI_WUSER_WIDTH     = 1,
+    C_M_AXI_RUSER_WIDTH     = 1,
+    C_M_AXI_BUSER_WIDTH     = 1,
+    C_TARGET_ADDR           = 32'h00000000,
+    C_USER_VALUE            = 1'b0,
+    C_PROT_VALUE            = 3'b000,
+    C_CACHE_VALUE           = 4'b0011,
+    USER_DW                 = 32, // multiple of 8
+    USER_AW                 = 32,
+    USER_MAXREQS            = 16,
+    USER_RFIFONUM_WIDTH     = 6,
+    MAXI_BUFFER_IMPL        = "block"
+)(
+
+    // system signal
+    input  wire                               ACLK,
+    input  wire                               ARESET,
+    input  wire                               ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                         AWLEN,
+    output wire [2:0]                         AWSIZE,
+    output wire [1:0]                         AWBURST,
+    output wire [1:0]                         AWLOCK,
+    output wire [3:0]                         AWCACHE,
+    output wire [2:0]                         AWPROT,
+    output wire [3:0]                         AWQOS,
+    output wire [3:0]                         AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                               AWVALID,
+    input  wire                               AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                               WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                               WVALID,
+    input  wire                               WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                         BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                               BVALID,
+    output wire                               BREADY,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                         ARLEN,
+    output wire [2:0]                         ARSIZE,
+    output wire [1:0]                         ARBURST,
+    output wire [1:0]                         ARLOCK,
+    output wire [3:0]                         ARCACHE,
+    output wire [2:0]                         ARPROT,
+    output wire [3:0]                         ARQOS,
+    output wire [3:0]                         ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                               ARVALID,
+    input  wire                               ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                         RRESP,
+    input  wire                               RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                               RVALID,
+    output wire                               RREADY,
+
+    // internal bus ports
+    // write address
+    input  wire [USER_AW-1:0]                 I_AWADDR,
+    input  wire [31:0]                        I_AWLEN,
+    input  wire                               I_AWVALID,
+    output wire                               I_AWREADY,
+    // write data
+    input  wire [USER_DW-1:0]                 I_WDATA,
+    input  wire [USER_DW/8-1:0]               I_WSTRB,
+    input  wire                               I_WVALID,
+    output wire                               I_WREADY,
+    // write response
+    output wire                               I_BVALID,
+    input  wire                               I_BREADY,
+    // read address
+    input  wire [USER_AW-1:0]                 I_ARADDR,
+    input  wire [31:0]                        I_ARLEN,
+    input  wire                               I_ARVALID,
+    output wire                               I_ARREADY,
+    // read data
+    output wire [USER_DW-1:0]                 I_RDATA,
+    output wire                               I_RVALID,
+    input  wire                               I_RREADY,
+    output wire [USER_RFIFONUM_WIDTH-1:0]     I_RFIFONUM);
+//------------------------Local signal-------------------
+
+    wire [C_M_AXI_ADDR_WIDTH-1:0]   AWADDR_Dummy;
+    wire [31:0]                     AWLEN_Dummy;
+    wire                            AWVALID_Dummy;
+    wire                            AWREADY_Dummy;
+    wire [C_M_AXI_DATA_WIDTH-1:0]   WDATA_Dummy;
+    wire [C_M_AXI_DATA_WIDTH/8-1:0] WSTRB_Dummy;
+    wire                            WVALID_Dummy;
+    wire                            WREADY_Dummy;
+    wire                            BVALID_Dummy;
+    wire                            BREADY_Dummy;
+    wire [C_M_AXI_ADDR_WIDTH-1:0]   ARADDR_Dummy;
+    wire [31:0]                     ARLEN_Dummy;
+    wire                            ARVALID_Dummy;
+    wire                            ARREADY_Dummy;
+    wire [C_M_AXI_DATA_WIDTH-1:0]   RDATA_Dummy;
+    wire [1:0]                      RLAST_Dummy;
+    wire                            RVALID_Dummy;
+    wire                            RREADY_Dummy;
+    wire                            RBURST_READY_Dummy;
+
+//------------------------Instantiation------------------
+    // Mmap2Stream_mmap_m_axi_store
+    Mmap2Stream_mmap_m_axi_store #(
+        .C_TARGET_ADDR           ( C_TARGET_ADDR ),
+        .NUM_WRITE_OUTSTANDING   ( NUM_WRITE_OUTSTANDING ),
+        .MAX_WRITE_BURST_LENGTH  ( MAX_WRITE_BURST_LENGTH ),
+        .BUS_ADDR_WIDTH          ( C_M_AXI_ADDR_WIDTH ),
+        .BUS_DATA_WIDTH          ( C_M_AXI_DATA_WIDTH ),
+        .USER_DW                 ( USER_DW ),
+        .USER_AW                 ( USER_AW ),
+        .USER_MAXREQS            ( USER_MAXREQS ),
+        .BUFFER_IMPL             ( MAXI_BUFFER_IMPL )
+    ) store_unit (
+        .ACLK                    ( ACLK ),
+        .ARESET                  ( ARESET ),
+        .ACLK_EN                 ( ACLK_EN ),
+        .out_AXI_AWADDR          ( AWADDR_Dummy ),
+        .out_AXI_AWLEN           ( AWLEN_Dummy ),
+        .out_AXI_AWVALID         ( AWVALID_Dummy ),
+        .in_AXI_AWREADY          ( AWREADY_Dummy ),
+        .out_AXI_WDATA           ( WDATA_Dummy ),
+        .out_AXI_WSTRB           ( WSTRB_Dummy ),
+        .out_AXI_WVALID          ( WVALID_Dummy ),
+        .in_AXI_WREADY           ( WREADY_Dummy ),
+        .in_AXI_BVALID           ( BVALID_Dummy ),
+        .out_AXI_BREADY          ( BREADY_Dummy ),
+        .in_HLS_AWADDR           ( I_AWADDR ),
+        .in_HLS_AWLEN            ( I_AWLEN ),
+        .in_HLS_AWVALID          ( I_AWVALID ),
+        .out_HLS_AWREADY         ( I_AWREADY ),
+        .in_HLS_WDATA            ( I_WDATA ),
+        .in_HLS_WSTRB            ( I_WSTRB ),
+        .in_HLS_WVALID           ( I_WVALID ),
+        .out_HLS_WREADY          ( I_WREADY ),
+        .out_HLS_BVALID          ( I_BVALID ),
+        .in_HLS_BREADY           ( I_BREADY ));
+
+    // Mmap2Stream_mmap_m_axi_load
+    Mmap2Stream_mmap_m_axi_load #(
+        .C_TARGET_ADDR           ( C_TARGET_ADDR ),
+        .NUM_READ_OUTSTANDING    ( NUM_READ_OUTSTANDING ),
+        .MAX_READ_BURST_LENGTH   ( MAX_READ_BURST_LENGTH ),
+        .BUS_ADDR_WIDTH          ( C_M_AXI_ADDR_WIDTH ),
+        .BUS_DATA_WIDTH          ( C_M_AXI_DATA_WIDTH ),
+        .USER_DW                 ( USER_DW ),
+        .USER_AW                 ( USER_AW ),
+        .USER_MAXREQS            ( USER_MAXREQS ),
+        .USER_RFIFONUM_WIDTH     ( USER_RFIFONUM_WIDTH ),
+        .BUFFER_IMPL             ( MAXI_BUFFER_IMPL )
+    ) load_unit (
+        .ACLK                    ( ACLK ),
+        .ARESET                  ( ARESET ),
+        .ACLK_EN                 ( ACLK_EN ),
+        .out_AXI_ARADDR          ( ARADDR_Dummy ),
+        .out_AXI_ARLEN           ( ARLEN_Dummy ),
+        .out_AXI_ARVALID         ( ARVALID_Dummy ),
+        .in_AXI_ARREADY          ( ARREADY_Dummy ),
+        .in_AXI_RDATA            ( RDATA_Dummy ),
+        .in_AXI_RLAST            ( RLAST_Dummy ),
+        .in_AXI_RVALID           ( RVALID_Dummy ),
+        .out_AXI_RREADY          ( RREADY_Dummy ),
+        .out_AXI_RBURST_READY    ( RBURST_READY_Dummy),
+        .in_HLS_ARADDR           ( I_ARADDR ),
+        .in_HLS_ARLEN            ( I_ARLEN ),
+        .in_HLS_ARVALID          ( I_ARVALID ),
+        .out_HLS_ARREADY         ( I_ARREADY ),
+        .out_HLS_RDATA           ( I_RDATA ),
+        .out_HLS_RVALID          ( I_RVALID ),
+        .in_HLS_RREADY           ( I_RREADY ),
+        .out_HLS_RFIFONUM        ( I_RFIFONUM ));
+
+    // Mmap2Stream_mmap_m_axi_write
+    Mmap2Stream_mmap_m_axi_write #(
+        .CONSERVATIVE            ( CONSERVATIVE),
+        .C_M_AXI_ID_WIDTH        ( C_M_AXI_ID_WIDTH ),
+        .C_M_AXI_AWUSER_WIDTH    ( C_M_AXI_AWUSER_WIDTH ),
+        .C_M_AXI_WUSER_WIDTH     ( C_M_AXI_WUSER_WIDTH ),
+        .C_M_AXI_BUSER_WIDTH     ( C_M_AXI_BUSER_WIDTH ),
+        .C_USER_VALUE            ( C_USER_VALUE ),
+        .C_PROT_VALUE            ( C_PROT_VALUE ),
+        .C_CACHE_VALUE           ( C_CACHE_VALUE ),
+        .BUS_ADDR_WIDTH          ( C_M_AXI_ADDR_WIDTH ),
+        .BUS_DATA_WIDTH          ( C_M_AXI_DATA_WIDTH ),
+        .NUM_WRITE_OUTSTANDING   ( NUM_WRITE_OUTSTANDING ),
+        .MAX_WRITE_BURST_LENGTH  ( MAX_WRITE_BURST_LENGTH )
+    ) bus_write (
+        .ACLK                    ( ACLK ),
+        .ARESET                  ( ARESET ),
+        .ACLK_EN                 ( ACLK_EN ),
+        .out_BUS_AWID            ( AWID ),
+        .out_BUS_AWSIZE          ( AWSIZE ),
+        .out_BUS_AWBURST         ( AWBURST ),
+        .out_BUS_AWLOCK          ( AWLOCK ),
+        .out_BUS_AWCACHE         ( AWCACHE ),
+        .out_BUS_AWPROT          ( AWPROT ),
+        .out_BUS_AWQOS           ( AWQOS ),
+        .out_BUS_AWREGION        ( AWREGION ),
+        .out_BUS_AWUSER          ( AWUSER ),
+        .out_BUS_AWADDR          ( AWADDR ),
+        .out_BUS_AWLEN           ( AWLEN ),
+
+
+        .out_BUS_AWVALID         ( AWVALID ),
+        .in_BUS_AWREADY          ( AWREADY ),
+        .out_BUS_WID             ( WID),
+        .out_BUS_WUSER           ( WUSER),
+        .out_BUS_WDATA           ( WDATA ),
+        .out_BUS_WSTRB           ( WSTRB ),
+        .out_BUS_WLAST           ( WLAST ),
+
+
+        .out_BUS_WVALID          ( WVALID ),
+        .in_BUS_WREADY           ( WREADY ),
+        .in_BUS_BID              ( BID ),
+        .in_BUS_BRESP            ( BRESP ),
+        .in_BUS_BUSER            ( BUSER ),
+        .in_BUS_BVALID           ( BVALID ),
+
+
+        .out_BUS_BREADY          ( BREADY ),
+        .in_HLS_AWVALID          ( AWVALID_Dummy ),
+        .out_HLS_AWREADY         ( AWREADY_Dummy ),
+        .in_HLS_AWADDR           ( AWADDR_Dummy ),
+        .in_HLS_AWLEN            ( AWLEN_Dummy ),
+        .in_HLS_WVALID           ( WVALID_Dummy ),
+        .out_HLS_WREADY          ( WREADY_Dummy ),
+        .in_HLS_WSTRB            ( WSTRB_Dummy ),
+        .in_HLS_WDATA            ( WDATA_Dummy ),
+        .out_HLS_BVALID          ( BVALID_Dummy ),
+        .in_HLS_BREADY           ( BREADY_Dummy ));
+
+    // Mmap2Stream_mmap_m_axi_read
+    Mmap2Stream_mmap_m_axi_read #(
+        .C_M_AXI_ID_WIDTH         ( C_M_AXI_ID_WIDTH ),
+        .C_M_AXI_ARUSER_WIDTH     ( C_M_AXI_ARUSER_WIDTH ),
+        .C_M_AXI_RUSER_WIDTH      ( C_M_AXI_RUSER_WIDTH ),
+        .C_USER_VALUE             ( C_USER_VALUE ),
+        .C_PROT_VALUE             ( C_PROT_VALUE ),
+        .C_CACHE_VALUE            ( C_CACHE_VALUE ),
+        .BUS_ADDR_WIDTH           ( C_M_AXI_ADDR_WIDTH ),
+        .BUS_DATA_WIDTH           ( C_M_AXI_DATA_WIDTH ),
+        .NUM_READ_OUTSTANDING     ( NUM_READ_OUTSTANDING ),
+        .MAX_READ_BURST_LENGTH    ( MAX_READ_BURST_LENGTH )
+    ) bus_read (
+        .ACLK                     ( ACLK ),
+        .ARESET                   ( ARESET ),
+        .ACLK_EN                  ( ACLK_EN ),
+        .out_BUS_ARID             ( ARID ),
+        .out_BUS_ARADDR           ( ARADDR ),
+        .out_BUS_ARLEN            ( ARLEN ),
+        .out_BUS_ARSIZE           ( ARSIZE ),
+        .out_BUS_ARBURST          ( ARBURST ),
+        .out_BUS_ARLOCK           ( ARLOCK ),
+        .out_BUS_ARCACHE          ( ARCACHE ),
+        .out_BUS_ARPROT           ( ARPROT ),
+        .out_BUS_ARQOS            ( ARQOS ),
+        .out_BUS_ARREGION         ( ARREGION ),
+        .out_BUS_ARUSER           ( ARUSER ),
+
+
+        .out_BUS_ARVALID          ( ARVALID ),
+        .in_BUS_ARREADY           ( ARREADY ),
+        .in_BUS_RID               ( RID ),
+        .in_BUS_RDATA             ( RDATA ),
+        .in_BUS_RRESP             ( RRESP ),
+        .in_BUS_RLAST             ( RLAST ),
+        .in_BUS_RUSER             ( RUSER ),
+        .in_BUS_RVALID            ( RVALID ),
+
+
+        .out_BUS_RREADY           ( RREADY ),
+        .in_HLS_ARVALID           ( ARVALID_Dummy ),
+        .out_HLS_ARREADY          ( ARREADY_Dummy ),
+        .in_HLS_ARADDR            ( ARADDR_Dummy ),
+        .in_HLS_ARLEN             ( ARLEN_Dummy ),
+        .out_HLS_RVALID           ( RVALID_Dummy ),
+        .in_HLS_RREADY            ( RREADY_Dummy ),
+        .in_HLS_RBUST_READY       ( RBURST_READY_Dummy),
+        .out_HLS_RDATA            ( RDATA_Dummy ),
+        .out_HLS_RLAST            ( RLAST_Dummy ));
+
+
+endmodule
+`default_nettype wire// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+`timescale 1ns/1ps
+
+module Mmap2Stream_mmap_m_axi_load
+#(parameter
+    C_TARGET_ADDR                         = 32'h00000000,
+    NUM_READ_OUTSTANDING                  = 2,
+    MAX_READ_BURST_LENGTH                 = 16,
+    BUS_ADDR_WIDTH                        = 32,
+    BUS_DATA_WIDTH                        = 32,
+    USER_DW                               = 16,
+    USER_AW                               = 32,
+    USER_MAXREQS                          = 16,
+    USER_RFIFONUM_WIDTH                   = 6,
+    BUFFER_IMPL                           = "auto"
+)(
+    // system signal
+    input  wire                           ACLK,
+    input  wire                           ARESET,
+    input  wire                           ACLK_EN,
+
+    // read address channel
+    output wire [BUS_ADDR_WIDTH-1:0]      out_AXI_ARADDR,
+    output wire [31:0]                    out_AXI_ARLEN,
+    output wire                           out_AXI_ARVALID,
+    input  wire                           in_AXI_ARREADY,
+    // read data channel
+    input  wire [BUS_DATA_WIDTH-1:0]      in_AXI_RDATA,
+    input  wire [1:0]                     in_AXI_RLAST,
+    input  wire                           in_AXI_RVALID,
+    output wire                           out_AXI_RREADY,
+    output wire                           out_AXI_RBURST_READY,
+
+    // internal bus ports
+    // read address
+    input  wire [USER_AW-1:0]             in_HLS_ARADDR,
+    input  wire [31:0]                    in_HLS_ARLEN,
+    input  wire                           in_HLS_ARVALID,
+    output wire                           out_HLS_ARREADY,
+    // read data
+    output wire [USER_DW-1:0]             out_HLS_RDATA,
+    output wire                           out_HLS_RVALID,
+    input  wire                           in_HLS_RREADY,
+    output wire [USER_RFIFONUM_WIDTH-1:0] out_HLS_RFIFONUM);
+
+//------------------------Parameter----------------------
+    localparam
+        USER_DATA_WIDTH = calc_data_width(USER_DW),
+        USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+        USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+        BUS_ADDR_ALIGN  = log2(BUS_DATA_WIDTH/8),
+        RBUFF_DEPTH     = NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH,
+        TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN);
+
+//------------------------Task and function--------------
+    function integer calc_data_width;
+        input integer x;
+        integer y;
+    begin
+        y = 8;
+        while (y < x) y = y * 2;
+        calc_data_width = y;
+    end
+    endfunction
+
+    function integer log2;
+        input integer x;
+        integer n, m;
+    begin
+        n = 0;
+        m = 1;
+        while (m < x) begin
+            n = n + 1;
+            m = m * 2;
+        end
+        log2 = n;
+    end
+    endfunction
+
+//------------------------Local signal-------------------
+
+    wire                           next_rreq;
+    wire                           ready_for_rreq;
+    wire                           rreq_ready;
+
+    wire [USER_AW-1 : 0]           rreq_addr;
+    wire [31:0]                    rreq_len;
+    wire                           rreq_valid;
+
+    wire                           valid_length;
+
+    reg  [BUS_ADDR_WIDTH-1 : 0]    tmp_addr;
+    reg  [31:0]                    tmp_len;
+    reg                            tmp_valid;
+
+    wire                           burst_ready;
+    wire                           beat_valid;
+    wire                           next_beat;
+    wire                           last_beat;
+    wire [BUS_DATA_WIDTH-1 : 0]    beat_data;
+    wire [log2(RBUFF_DEPTH) : 0]   beat_nvalid;
+
+    reg                            ready_for_outstanding;
+
+//------------------------Instantiation------------------
+    Mmap2Stream_mmap_m_axi_fifo #(
+        .DATA_WIDTH        (USER_AW + 32),
+        .ADDR_WIDTH        (log2(USER_MAXREQS)),
+        .DEPTH             (USER_MAXREQS)
+    ) fifo_rreq (
+        .clk               (ACLK),
+        .reset             (ARESET),
+        .clk_en            (ACLK_EN),
+        .if_full_n         (out_HLS_ARREADY),
+        .if_write          (in_HLS_ARVALID),
+        .if_din            ({in_HLS_ARLEN, in_HLS_ARADDR}),
+        .if_empty_n        (rreq_valid),
+        .if_read           (next_rreq),
+        .if_dout           ({rreq_len, rreq_addr}),
+        .if_num_data_valid ());
+
+    // ===================================================================
+    // start of ARADDR PREPROCESSOR
+
+    assign next_rreq       = rreq_valid && ready_for_rreq;
+    assign ready_for_rreq  = ~tmp_valid || (in_AXI_ARREADY && rreq_ready);
+
+    assign valid_length    = (rreq_len != 32'b0) && !rreq_len[31];
+
+    assign out_AXI_ARLEN   = tmp_len;   // Byte length
+    assign out_AXI_ARADDR  = tmp_addr;  // Byte address
+    assign out_AXI_ARVALID = tmp_valid && rreq_ready;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET) begin
+            tmp_len  <= 0;
+            tmp_addr <= 0;
+        end
+        else if (ACLK_EN) begin
+            if(next_rreq) begin
+                tmp_len  <= (rreq_len << USER_ADDR_ALIGN) - 1;            // byte length
+                tmp_addr <= TARGET_ADDR + (rreq_addr << USER_ADDR_ALIGN); // byte address
+            end
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            tmp_valid <= 1'b0;
+        else if (ACLK_EN) begin
+            if (next_rreq && valid_length)
+                tmp_valid <= 1'b1;
+            else if (in_AXI_ARREADY && rreq_ready)
+                tmp_valid <= 1'b0;
+        end
+    end
+
+    // end of ARADDR PREPROCESSOR
+    // ===================================================================
+
+    Mmap2Stream_mmap_m_axi_fifo #(
+        .MEM_STYLE         (BUFFER_IMPL),
+        .DATA_WIDTH        (BUS_DATA_WIDTH + 2),
+        .ADDR_WIDTH        (log2(RBUFF_DEPTH)),
+        .DEPTH             (RBUFF_DEPTH)
+    ) buff_rdata (
+        .clk               (ACLK),
+        .reset             (ARESET),
+        .clk_en            (ACLK_EN),
+        .if_full_n         (out_AXI_RREADY),
+        .if_write          (in_AXI_RVALID),
+        .if_din            ({in_AXI_RLAST, in_AXI_RDATA}),
+        .if_empty_n        (beat_valid),
+        .if_read           (next_beat),
+        .if_dout           ({burst_ready, last_beat, beat_data}),
+        .if_num_data_valid (beat_nvalid));
+
+    assign out_AXI_RBURST_READY = ready_for_outstanding;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            ready_for_outstanding <= 1'b0;
+        else if (ACLK_EN) begin
+            if (next_beat)
+                ready_for_outstanding <= burst_ready;
+            else
+                ready_for_outstanding <= 1'b0;
+        end
+    end
+    // ===================================================================
+    // start of RDATA PREPROCESSOR
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+
+        assign rreq_ready       = 1'b1;
+        assign next_beat        = in_HLS_RREADY;
+
+        assign out_HLS_RDATA    = beat_data[USER_DW-1 : 0];
+        assign out_HLS_RVALID   = beat_valid;
+        assign out_HLS_RFIFONUM = beat_nvalid;
+
+    end
+    else if (USER_DATA_WIDTH < BUS_DATA_WIDTH) begin : bus_wide_gen
+        localparam
+            TOTAL_SPLIT  = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            SPLIT_ALIGN  = log2(TOTAL_SPLIT);
+
+        wire [USER_AW - 1:0]        tmp_addr_end;
+
+        wire                        offset_full_n;
+        wire                        offset_write;
+        wire [SPLIT_ALIGN-1 : 0]    start_offset;
+        wire [SPLIT_ALIGN-1 : 0]    end_offset;
+
+        wire                        offset_valid;
+        wire                        next_offset;
+        wire [SPLIT_ALIGN-1 : 0]    head_offset;
+        wire [SPLIT_ALIGN-1 : 0]    tail_offset;
+
+        reg                         first_beat;
+
+        wire                        first_data;
+        wire                        last_data;
+        wire                        ready_for_data;
+
+        reg  [BUS_DATA_WIDTH-1 : 0] data_buf;
+        reg                         data_valid;
+
+        reg  [USER_RFIFONUM_WIDTH-1:0] rdata_nvalid;
+        reg  [SPLIT_ALIGN : 0]      data_nvalid;
+        wire [SPLIT_ALIGN : 0]      split_nvalid;
+
+        wire [SPLIT_ALIGN-1 : 0]    split_cnt;
+        reg  [SPLIT_ALIGN-1 : 0]    split_cnt_buf;
+
+        wire                        first_split;
+        wire                        next_split;
+        wire                        last_split;
+
+        // Recording the offset of start & end address to extract the expect data from beats when USER_DW < BUS_DW.
+        Mmap2Stream_mmap_m_axi_fifo #(
+            .DATA_WIDTH         (2*SPLIT_ALIGN),
+            .ADDR_WIDTH         (log2(NUM_READ_OUTSTANDING)),
+            .DEPTH              (NUM_READ_OUTSTANDING)
+        ) rreq_offset (
+            .clk                (ACLK),
+            .reset              (ARESET),
+            .clk_en             (ACLK_EN),
+            .if_full_n          (offset_full_n),
+            .if_write           (offset_write),
+            .if_din             ({start_offset, end_offset}),
+            .if_empty_n         (offset_valid),
+            .if_read            (next_offset),
+            .if_dout            ({head_offset, tail_offset}),
+            .if_num_data_valid  ());
+
+        assign rreq_ready       = offset_full_n | ~offset_write;
+        assign tmp_addr_end     = tmp_addr + tmp_len;
+
+        assign start_offset     = tmp_addr[BUS_ADDR_ALIGN - 1 : 0] >> USER_ADDR_ALIGN;
+        assign end_offset       = tmp_addr_end[BUS_ADDR_ALIGN - 1 : 0] >> USER_ADDR_ALIGN;
+        assign offset_write     = tmp_valid & in_AXI_ARREADY;
+
+        assign next_offset      = (last_beat & beat_valid) & last_split;
+        assign next_beat        = last_split;
+
+        assign out_HLS_RDATA    = data_buf[USER_DW-1 : 0];
+        assign out_HLS_RVALID   = data_valid;
+        assign out_HLS_RFIFONUM = rdata_nvalid + data_nvalid;
+
+        assign ready_for_data   = ~data_valid | in_HLS_RREADY;
+        assign first_data       = first_beat && beat_valid && offset_valid;
+        assign last_data        = last_beat && beat_valid && offset_valid;
+
+        assign first_split      = (~first_data) ? (split_cnt == 0 && beat_valid && ready_for_data) : ((split_cnt == head_offset) && ready_for_data);
+        assign last_split       = (~last_data)  ? (split_cnt == (TOTAL_SPLIT-1) && ready_for_data) : ((split_cnt == tail_offset) && ready_for_data);
+        assign next_split       = (~first_data) ? (split_cnt != 0 && ready_for_data)               : ((split_cnt != head_offset) && ready_for_data);
+
+        assign split_cnt        = (first_data && (split_cnt_buf == 0)) ? head_offset : split_cnt_buf;
+
+        assign split_nvalid     = (first_data && last_data)  ? tail_offset - head_offset + 1 :
+                                   first_data                ? TOTAL_SPLIT - head_offset     :
+                                   last_data                 ? tail_offset + 1               :
+                                   TOTAL_SPLIT;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt_buf <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt_buf <= 0;
+                else if (first_split || next_split)
+                    split_cnt_buf <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_beat <= 1'b1;
+            else if (ACLK_EN) begin
+                if (last_beat && last_split)
+                    first_beat <= 1'b1;
+                else if (first_beat && last_split)
+                    first_beat <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (first_split & first_data)
+                    data_buf <= beat_data >> (head_offset * USER_DATA_WIDTH);
+                else if (first_split)
+                    data_buf <= beat_data;
+                else if (next_split)
+                    data_buf <= data_buf >> USER_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                data_valid <= 1'b0;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    data_valid <= 1'b1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    data_valid <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                data_nvalid <= 0;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    data_nvalid <= split_nvalid;
+                else if (next_split)
+                    data_nvalid <= data_nvalid - 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    data_nvalid <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_nvalid <= 0;
+            else if (ACLK_EN) begin
+                if (!beat_valid)
+                    rdata_nvalid <= 0;
+                else
+                    rdata_nvalid <= ((beat_nvalid - 1) << SPLIT_ALIGN);
+            end
+        end
+
+    end
+    else begin : bus_narrow_gen
+        localparam
+            TOTAL_PADS      = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg [USER_DATA_WIDTH-1 : 0] data_buf;
+        reg                         data_valid;
+        reg [PAD_ALIGN:0]           data_nvalid;
+        wire                        ready_for_data;
+
+        wire [TOTAL_PADS - 1:0]     pad_oh;
+        reg  [TOTAL_PADS - 1:0]     pad_oh_reg;
+
+        reg                         first_pad;
+        wire                        last_pad;
+        wire                        next_pad;
+
+        assign rreq_ready       = 1'b1;
+        assign next_beat        = next_pad;
+
+        assign out_HLS_RDATA    = data_buf[USER_DW-1 : 0];
+        assign out_HLS_RVALID   = data_valid;
+        assign out_HLS_RFIFONUM = beat_nvalid[log2(RBUFF_DEPTH) : PAD_ALIGN] + (beat_nvalid[PAD_ALIGN-1:0] + data_nvalid) >> PAD_ALIGN;
+        assign ready_for_data   = ~data_valid | in_HLS_RREADY;
+
+        assign next_pad         = beat_valid && ready_for_data;
+        assign last_pad         = pad_oh[TOTAL_PADS - 1];
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1'b1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 1'b0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1'b1;
+            end
+        end
+
+        assign pad_oh = (beat_valid == 0)  ?  0 :
+                        (first_pad)        ?  1 :
+                        pad_oh_reg;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 0; i < TOTAL_PADS; i = i + 1) begin : data_gen
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if (pad_oh[i] == 1'b1 && ready_for_data)
+                        data_buf[i*BUS_DATA_WIDTH +: BUS_DATA_WIDTH] <= beat_data;
+                end
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                data_valid <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    data_valid <= 1'b1;
+                else if (ready_for_data)
+                    data_valid <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                data_nvalid <= 0;
+            else if (ACLK_EN) begin
+                if (first_pad)
+                    data_nvalid <= 1;
+                else if (next_pad)
+                    data_nvalid <= data_nvalid + 1;
+            end
+        end
+
+    end
+    endgenerate
+    // end of RDATA PREPROCESSOR
+    // ===================================================================
+
+endmodule
+
+
+module Mmap2Stream_mmap_m_axi_store
+#(parameter
+    C_TARGET_ADDR           = 32'h00000000,
+    NUM_WRITE_OUTSTANDING   = 2,
+    MAX_WRITE_BURST_LENGTH  = 16,
+    BUS_ADDR_WIDTH          = 32,
+    BUS_DATA_WIDTH          = 32,
+    USER_DW                 = 16,
+    USER_AW                 = 32,
+    USER_MAXREQS            = 16,
+    BUFFER_IMPL             = "auto"
+)(
+    // system signal
+    input  wire                        ACLK,
+    input  wire                        ARESET,
+    input  wire                        ACLK_EN,
+    // write address channel
+    output wire [BUS_ADDR_WIDTH-1:0]   out_AXI_AWADDR,
+    output wire [31:0]                 out_AXI_AWLEN,
+    output wire                        out_AXI_AWVALID,
+    input  wire                        in_AXI_AWREADY,
+    // write data channel
+    output wire [BUS_DATA_WIDTH-1:0]   out_AXI_WDATA,
+    output wire [BUS_DATA_WIDTH/8-1:0] out_AXI_WSTRB,
+    output wire                        out_AXI_WVALID,
+    input  wire                        in_AXI_WREADY,
+    // write response channel
+    input  wire                        in_AXI_BVALID,
+    output wire                        out_AXI_BREADY,
+
+    // internal bus ports
+    // write address
+    input  wire [USER_AW-1:0]          in_HLS_AWADDR,
+    input  wire [31:0]                 in_HLS_AWLEN,
+    input  wire                        in_HLS_AWVALID,
+    output wire                        out_HLS_AWREADY,
+    // write data
+    input  wire [USER_DW-1:0]          in_HLS_WDATA,
+    input  wire [USER_DW/8-1:0]        in_HLS_WSTRB,
+    input  wire                        in_HLS_WVALID,
+    output wire                        out_HLS_WREADY,
+    // write response
+    output wire                        out_HLS_BVALID,
+    input  wire                        in_HLS_BREADY);
+
+//------------------------Parameter----------------------
+    localparam
+        USER_DATA_WIDTH = calc_data_width(USER_DW),
+        USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+        USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+        BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+        BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+        // write buffer size
+        WBUFF_DEPTH     = max(MAX_WRITE_BURST_LENGTH * BUS_DATA_WIDTH / USER_DATA_WIDTH, 1),
+        TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN);
+
+//------------------------Task and function--------------
+
+    function integer max;
+        input integer x;
+        input integer y;
+    begin
+        max = (x > y) ? x : y;
+    end
+    endfunction
+
+    function integer calc_data_width;
+        input integer x;
+        integer y;
+    begin
+        y = 8;
+        while (y < x) y = y * 2;
+        calc_data_width = y;
+    end
+    endfunction
+
+    function integer log2;
+        input integer x;
+        integer n, m;
+    begin
+        n = 0;
+        m = 1;
+        while (m < x) begin
+            n = n + 1;
+            m = m * 2;
+        end
+        log2 = n;
+    end
+    endfunction
+
+//------------------------Local signal-------------------
+
+    wire                                next_wreq;
+    wire                                ready_for_wreq;
+    wire                                wreq_ready;
+
+    wire [USER_AW-1 : 0]                wreq_addr;
+    wire [31:0]                         wreq_len;
+    wire                                wreq_valid;
+
+    wire                                valid_length;
+
+    reg  [USER_AW-1 : 0]                tmp_addr;
+    reg  [31:0]                         tmp_len;
+    reg                                 tmp_valid;
+
+    wire                                next_wdata;
+    wire                                wdata_valid;
+    wire [USER_DW-1 : 0]                tmp_wdata;
+    wire [USER_DW/8-1 : 0]              tmp_wstrb;
+
+    wire                                wrsp_ready;
+    wire                                wrsp_valid;
+    wire                                wrsp_read;
+    wire                                wrsp_type;
+
+    wire                                ursp_ready;
+    wire                                ursp_write;
+
+//------------------------Instantiation------------------
+    Mmap2Stream_mmap_m_axi_fifo #(
+        .DATA_WIDTH     (USER_AW + 32),
+        .ADDR_WIDTH     (log2(USER_MAXREQS)),
+        .DEPTH          (USER_MAXREQS)
+    ) fifo_wreq (
+        .clk            (ACLK),
+        .reset          (ARESET),
+        .clk_en         (ACLK_EN),
+        .if_full_n      (out_HLS_AWREADY),
+        .if_write       (in_HLS_AWVALID),
+        .if_din         ({in_HLS_AWLEN, in_HLS_AWADDR}),
+        .if_empty_n     (wreq_valid),
+        .if_read        (next_wreq),
+        .if_dout        ({wreq_len, wreq_addr}),
+        .if_num_data_valid());
+
+    assign next_wreq = wreq_valid && ready_for_wreq && wrsp_ready;
+    assign ready_for_wreq  = ~tmp_valid || (in_AXI_AWREADY && wreq_ready);
+
+    assign valid_length    = (wreq_len != 32'b0) && !wreq_len[31];
+
+    assign out_AXI_AWLEN   = tmp_len;   // Byte length
+    assign out_AXI_AWADDR  = tmp_addr;  // Byte address
+    assign out_AXI_AWVALID = tmp_valid && wreq_ready;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET) begin
+            tmp_len  <= 0;
+            tmp_addr <= 0;
+        end
+        else if (ACLK_EN) begin
+            if(next_wreq) begin
+                tmp_len  <= (wreq_len << USER_ADDR_ALIGN) - 1;
+                tmp_addr <= TARGET_ADDR + (wreq_addr << USER_ADDR_ALIGN);
+            end
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            tmp_valid <= 1'b0;
+        else if (next_wreq && valid_length)
+            tmp_valid <= 1'b1;
+        else if (in_AXI_AWREADY && wreq_ready)
+            tmp_valid <= 1'b0;
+    end
+
+    // ===================================================================
+
+    Mmap2Stream_mmap_m_axi_fifo #(
+        .MEM_STYLE         (BUFFER_IMPL),
+        .DATA_WIDTH        (USER_DW + USER_DW/8),
+        .ADDR_WIDTH        (log2(WBUFF_DEPTH)),
+        .DEPTH             (WBUFF_DEPTH)
+    ) buff_wdata (
+        .clk               (ACLK),
+        .reset             (ARESET),
+        .clk_en            (ACLK_EN),
+        .if_full_n         (out_HLS_WREADY),
+        .if_write          (in_HLS_WVALID),
+        .if_din            ({in_HLS_WSTRB , in_HLS_WDATA}),
+        .if_empty_n        (wdata_valid),
+        .if_read           (next_wdata),
+        .if_dout           ({tmp_wstrb, tmp_wdata}),
+        .if_num_data_valid ());
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        assign next_wdata       = in_AXI_WREADY;
+        assign out_AXI_WVALID   = wdata_valid;
+        assign out_AXI_WDATA    = tmp_wdata;
+        assign out_AXI_WSTRB    = tmp_wstrb;
+
+        assign wreq_ready   = 1'b1;
+
+    end
+    else if (USER_DATA_WIDTH < BUS_DATA_WIDTH) begin : bus_wide_gen
+        localparam
+            TOTAL_PADS      = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS),
+            BEAT_LEN_WIDTH  = 32 - BUS_ADDR_ALIGN;
+
+        function [TOTAL_PADS-1 : 0] decoder;
+            input [PAD_ALIGN-1 : 0] din;
+            reg  [TOTAL_PADS-1 : 0] dout;
+            integer i;
+        begin
+            dout = {TOTAL_PADS{1'b0}};
+            for (i = 0; i < din; i = i + 1)
+                dout[i] = 1'b1;
+            decoder = dout;
+        end
+        endfunction
+
+        wire [USER_AW - 1:0]        tmp_addr_end;
+
+        wire                        offset_full_n;
+        wire                        offset_write;
+        wire [PAD_ALIGN-1 : 0]      start_offset;
+        wire [PAD_ALIGN-1 : 0]      end_offset;
+        wire [BEAT_LEN_WIDTH-1 : 0] beat_total;
+
+        wire                        offset_valid;
+        wire                        next_offset;
+        wire [PAD_ALIGN-1 : 0]      head_offset;
+        wire [PAD_ALIGN-1 : 0]      tail_offset;
+
+        wire [BEAT_LEN_WIDTH-1 : 0] beat_len;
+        reg  [BEAT_LEN_WIDTH-1:0]   len_cnt;
+
+        wire [TOTAL_PADS - 1:0]     add_head;
+        wire [TOTAL_PADS - 1:0]     add_tail;
+        wire [TOTAL_PADS - 1:0]     pad_oh;
+        reg  [TOTAL_PADS - 1:0]     pad_oh_reg;
+
+        wire [TOTAL_PADS-1 : 0]     head_pad_sel;
+        wire [0 : TOTAL_PADS-1]     tail_pad_sel; // reverse
+        wire                        ready_for_data;
+        wire                        next_pad;
+        reg                         first_pad;
+        wire                        last_pad;
+        wire                        first_beat;
+        wire                        last_beat;
+        wire                        next_beat;
+
+        reg  [BUS_DATA_WIDTH - 1:0] data_buf;
+        reg  [BUS_DATA_BYTES - 1:0] strb_buf;
+        reg                         data_valid;
+
+        // Recording the offset of start & end address to align beats from data USER_DW < BUS_DW.
+        Mmap2Stream_mmap_m_axi_fifo #(
+            .DATA_WIDTH             (2*PAD_ALIGN + BEAT_LEN_WIDTH),
+            .ADDR_WIDTH             (log2(NUM_WRITE_OUTSTANDING)),
+            .DEPTH                  (NUM_WRITE_OUTSTANDING)
+        ) wreq_offset (
+            .clk                    (ACLK),
+            .reset                  (ARESET),
+            .clk_en                 (ACLK_EN),
+            .if_full_n              (offset_full_n),
+            .if_write               (offset_write),
+            .if_din                 ({start_offset, end_offset, beat_total}),
+            .if_empty_n             (offset_valid),
+            .if_read                (next_offset),
+            .if_dout                ({head_offset, tail_offset, beat_len}),
+            .if_num_data_valid      ());
+
+        assign wreq_ready   = offset_full_n | ~offset_write;
+        assign tmp_addr_end = tmp_addr + tmp_len;
+
+        assign start_offset   = tmp_addr[BUS_ADDR_ALIGN-1 : 0] >> USER_ADDR_ALIGN;
+        assign end_offset     = ~tmp_addr_end[BUS_ADDR_ALIGN-1 : 0] >> USER_ADDR_ALIGN;
+        assign beat_total     = (tmp_len + tmp_addr[BUS_ADDR_ALIGN-1 : 0]) >> BUS_ADDR_ALIGN;
+
+        assign offset_write   = tmp_valid & in_AXI_AWREADY;
+
+        assign out_AXI_WDATA  = data_buf;
+        assign out_AXI_WSTRB  = strb_buf;
+        assign out_AXI_WVALID = data_valid;
+
+        assign next_wdata     = next_pad;
+        assign next_offset    = last_beat && next_beat;
+        assign ready_for_data = ~data_valid || in_AXI_WREADY;
+
+        assign first_beat     = (len_cnt == 0) && offset_valid;
+        assign last_beat      = (len_cnt == beat_len) && offset_valid;
+        assign next_beat      = offset_valid && last_pad && ready_for_data;
+
+        assign next_pad       = offset_valid && wdata_valid && ready_for_data;
+        assign last_pad       = (last_beat) ? pad_oh[TOTAL_PADS-tail_offset-1] : pad_oh[TOTAL_PADS-1];
+
+        assign head_pad_sel   = decoder(head_offset);
+        assign tail_pad_sel   = decoder(tail_offset);
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_offset)
+                    len_cnt <= 0;
+                else if (next_beat)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1'b1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 1'b0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1'b1;
+            end
+        end
+
+        assign pad_oh = (~wdata_valid)            ? 0                :
+                        (first_pad && first_beat) ? 1 << head_offset :
+                        (first_pad)?                1                :
+                        pad_oh_reg;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 0; i < TOTAL_PADS; i = i + 1) begin : data_gen
+            assign add_head[i] = head_pad_sel[i] && first_beat;
+            assign add_tail[i] = tail_pad_sel[i] && last_beat;
+
+            always @(posedge ACLK)
+            begin
+                if (ARESET)
+                    data_buf[i*USER_DATA_WIDTH +: USER_DATA_WIDTH] <= {USER_DATA_WIDTH{1'b0}};
+                else if (ACLK_EN) begin
+                    if ((add_head[i] || add_tail[i]) && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH +: USER_DATA_WIDTH] <= {USER_DATA_WIDTH{1'b0}};
+                    else if (pad_oh[i] == 1'b1 && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH +: USER_DATA_WIDTH] <= tmp_wdata;
+                end
+            end
+
+            always @(posedge ACLK)
+            begin
+                if (ARESET)
+                    strb_buf[i*USER_DATA_BYTES +: USER_DATA_BYTES] <= {USER_DATA_BYTES{1'b0}};
+                else if (ACLK_EN) begin
+                    if ((add_head[i] || add_tail[i]) && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES +: USER_DATA_BYTES] <= {USER_DATA_BYTES{1'b0}};
+                    else if (pad_oh[i] == 1'b1 && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES +: USER_DATA_BYTES] <= tmp_wstrb;
+                end
+            end
+
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                data_valid <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    data_valid <= 1'b1;
+                else if (ready_for_data)
+                    data_valid <= 1'b0;
+            end
+        end
+
+    end
+    else begin : bus_narrow_gen
+        localparam
+            TOTAL_SPLIT       = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            SPLIT_ALIGN       = log2(TOTAL_SPLIT),
+            BEAT_LEN_WIDTH    = 32 - BUS_ADDR_ALIGN;
+
+
+        wire [USER_AW - 1:0]        tmp_addr_end;
+
+        wire                        offset_full_n;
+        wire                        offset_write;
+        wire  [BEAT_LEN_WIDTH-1 : 0] beat_total;
+
+        wire                        offset_valid;
+        wire                        next_offset;
+
+        wire [BEAT_LEN_WIDTH-1 : 0] beat_len;
+        reg  [BEAT_LEN_WIDTH-1 : 0] len_cnt;
+
+        wire                        ready_for_data;
+        reg  [BUS_DATA_WIDTH - 1:0] data_buf;
+        reg  [BUS_DATA_BYTES - 1:0] strb_buf;
+        reg                         data_valid;
+
+        reg [SPLIT_ALIGN-1 : 0]     split_cnt;
+
+        wire                        first_split;
+        wire                        next_split;
+        wire                        last_split;
+
+        // Recording the offset of start & end address to align beats from data USER_DW < BUS_DW.
+        Mmap2Stream_mmap_m_axi_fifo #(
+            .DATA_WIDTH        (BEAT_LEN_WIDTH),
+            .ADDR_WIDTH        (log2(NUM_WRITE_OUTSTANDING)),
+            .DEPTH             (NUM_WRITE_OUTSTANDING)
+        ) wreq_offset (
+            .clk               (ACLK),
+            .reset             (ARESET),
+            .clk_en            (ACLK_EN),
+            .if_full_n         (offset_full_n),
+            .if_write          (offset_write),
+            .if_din            (beat_total),
+            .if_empty_n        (offset_valid),
+            .if_read           (next_offset),
+            .if_dout           (beat_len),
+            .if_num_data_valid ());
+
+        assign wreq_ready     = offset_full_n | ~offset_write;
+        assign beat_total     = (tmp_len + tmp_addr[BUS_ADDR_ALIGN-1 : 0]) >> BUS_ADDR_ALIGN;
+
+        assign offset_write   = tmp_valid & in_AXI_AWREADY;
+
+        assign out_AXI_WDATA  = data_buf[BUS_DATA_WIDTH - 1:0];
+        assign out_AXI_WSTRB  = strb_buf[BUS_DATA_BYTES - 1:0];
+        assign out_AXI_WVALID = data_valid;
+
+        assign next_wdata     = first_split;
+        assign next_offset    = (len_cnt == beat_len) && offset_valid && last_split;
+        assign ready_for_data = ~data_valid | in_AXI_WREADY;
+
+        assign first_split    = (split_cnt == 0) && wdata_valid && offset_valid && ready_for_data;
+        assign last_split     = (split_cnt == (TOTAL_SPLIT - 1)) && ready_for_data;
+        assign next_split     = (split_cnt != 0) && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt <= 0;
+                else if (first_split || next_split)
+                    split_cnt <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_offset)
+                    len_cnt <= 0;
+                else if (next_wdata || next_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_wdata)
+                    data_buf <= tmp_wdata;
+                else if (next_split)
+                    data_buf <= data_buf >> BUS_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_wdata)
+                    strb_buf <= tmp_wstrb;
+                else if (next_split)
+                    strb_buf <= strb_buf >> BUS_DATA_BYTES;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                data_valid <= 0;
+            else if (ACLK_EN) begin
+                if (next_wdata)
+                    data_valid <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    data_valid <= 0;
+            end
+        end
+    end
+    endgenerate
+
+    // ===================================================================
+
+    // generate response for all request (including request with invalid length)
+    Mmap2Stream_mmap_m_axi_fifo #(
+        .DATA_WIDTH        (1),
+        .ADDR_WIDTH        (log2(NUM_WRITE_OUTSTANDING)),
+        .DEPTH             (NUM_WRITE_OUTSTANDING)
+    ) fifo_wrsp (
+        .clk               (ACLK),
+        .reset             (ARESET),
+        .clk_en            (ACLK_EN),
+        .if_full_n         (wrsp_ready),
+        .if_write          (next_wreq),
+        .if_din            (valid_length),
+        .if_empty_n        (wrsp_valid),
+        .if_read           (wrsp_read),
+        .if_dout           (wrsp_type), // 1 - valid length request, 0 - invalid length request
+        .if_num_data_valid ());
+
+    Mmap2Stream_mmap_m_axi_fifo #(
+        .DATA_WIDTH        (1),
+        .ADDR_WIDTH        (log2(USER_MAXREQS)),
+        .DEPTH             (USER_MAXREQS)
+    ) user_resp (
+        .clk               (ACLK),
+        .reset             (ARESET),
+        .clk_en            (ACLK_EN),
+        .if_full_n         (ursp_ready),
+        .if_write          (ursp_write),
+        .if_din            (1'b1),
+        .if_empty_n        (out_HLS_BVALID),
+        .if_read           (in_HLS_BREADY),
+        .if_dout           (),
+        .if_num_data_valid ());
+
+    assign ursp_write  = wrsp_valid && (!wrsp_type || in_AXI_BVALID);
+    assign wrsp_read   = ursp_ready && ursp_write;
+
+    assign out_AXI_BREADY = wrsp_type && ursp_ready;
+
+endmodule
+
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+`timescale 1ns/1ps
+
+//
+
+
+module Mmap2Stream_mmap_m_axi_read
+#(parameter
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ARUSER_WIDTH      = 1,
+    C_M_AXI_RUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    BUS_ADDR_WIDTH            = 32,
+    BUS_DATA_WIDTH            = 32,
+    NUM_READ_OUTSTANDING      = 2,
+    MAX_READ_BURST_LENGTH     = 16
+)(
+    // system signal
+    input  wire                            ACLK,
+    input  wire                            ARESET,
+    input  wire                            ACLK_EN,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]     out_BUS_ARID,
+    output wire [BUS_ADDR_WIDTH-1:0]       out_BUS_ARADDR,
+    output wire [7:0]                      out_BUS_ARLEN,
+    output wire [2:0]                      out_BUS_ARSIZE,
+    output wire [1:0]                      out_BUS_ARBURST,
+    output wire [1:0]                      out_BUS_ARLOCK,
+    output wire [3:0]                      out_BUS_ARCACHE,
+    output wire [2:0]                      out_BUS_ARPROT,
+    output wire [3:0]                      out_BUS_ARQOS,
+    output wire [3:0]                      out_BUS_ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0] out_BUS_ARUSER,
+    output wire                            out_BUS_ARVALID,
+    input  wire                            in_BUS_ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]     in_BUS_RID,
+    input  wire [BUS_DATA_WIDTH-1:0]       in_BUS_RDATA,
+    input  wire [1:0]                      in_BUS_RRESP,
+    input  wire                            in_BUS_RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]  in_BUS_RUSER,
+    input  wire                            in_BUS_RVALID,
+    output wire                            out_BUS_RREADY,
+
+    // HLS internal read request channel
+    input  wire [BUS_ADDR_WIDTH-1:0]       in_HLS_ARADDR,
+    input  wire [31:0]                     in_HLS_ARLEN,
+    input  wire                            in_HLS_ARVALID,
+    output wire                            out_HLS_ARREADY,
+    output wire [BUS_DATA_WIDTH-1:0]       out_HLS_RDATA,
+    output wire [1:0]                      out_HLS_RLAST,
+    output wire                            out_HLS_RVALID,
+    input  wire                            in_HLS_RREADY,
+    input  wire                            in_HLS_RBUST_READY);
+
+//------------------------Parameter----------------------
+    localparam
+        BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+        BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+        NUM_READ_WIDTH  = log2(MAX_READ_BURST_LENGTH),
+        RBUFFER_AWIDTH  = log2(MAX_READ_BURST_LENGTH*NUM_READ_OUTSTANDING),
+        BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+    function integer calc_data_width;
+        input integer x;
+        integer y;
+    begin
+        y = 8;
+        while (y < x) y = y * 2;
+        calc_data_width = y;
+    end
+    endfunction
+
+    function integer log2;
+        input integer x;
+        integer n, m;
+    begin
+        n = 0;
+        m = 1;
+        while (m < x) begin
+            n = n + 1;
+            m = m * 2;
+        end
+        log2 = n;
+    end
+    endfunction
+
+//------------------------Local signal-------------------
+    // AR channel
+    wire                                rreq_valid;
+    wire [BUS_ADDR_WIDTH - 1:0]         tmp_addr;
+    wire [31:0]                         tmp_len;
+    wire [7:0]                          arlen_tmp;
+    wire [BUS_ADDR_WIDTH - 1:0]         araddr_tmp;
+    reg  [BUS_ADDR_WIDTH - 1:0]         start_addr;
+    reg  [BUS_ADDR_WIDTH - 1:0]         end_addr;
+    wire [BUS_ADDR_WIDTH - 1:0]         sect_addr;
+    reg  [BUS_ADDR_WIDTH - 1:0]         sect_addr_buf;
+    wire [11 - BUS_ADDR_ALIGN:0]        start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]        sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]        sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]        beat_len;
+    reg  [BUS_ADDR_WIDTH - 13:0]        sect_cnt;
+    wire                                ar2r_info;
+    wire                                fifo_rctl_r;
+    wire                                fifo_burst_w;
+    reg                                 ARVALID_Dummy;
+    wire                                ready_for_sect;
+    wire                                next_rreq;
+    wire                                ready_for_rreq;
+    reg                                 rreq_handling;
+    wire                                first_sect;
+    wire                                last_sect;
+    reg                                 last_sect_buf;
+    wire                                next_sect;
+    // R channel
+    wire [BUS_DATA_WIDTH-1:0]           tmp_data;
+    wire                                tmp_last;
+    wire                                data_valid;
+    wire                                data_ready;
+    wire                                next_ctrl;
+    wire                                need_rlast;
+    wire                                burst_valid;
+    wire                                last_burst;
+    wire                                fifo_rctl_ready;
+    wire                                next_burst;
+    wire                                burst_end;
+
+//------------------------AR channel begin---------------
+//------------------------Instantiation------------------
+    Mmap2Stream_mmap_m_axi_reg_slice #(
+        .DATA_WIDTH     (BUS_ADDR_WIDTH + 32)
+    ) rs_rreq (
+        .clk            (ACLK),
+        .reset          (ARESET),
+        .s_data         ({in_HLS_ARLEN, in_HLS_ARADDR}),
+        .s_valid        (in_HLS_ARVALID),
+        .s_ready        (out_HLS_ARREADY),
+        .m_data         ({tmp_len, tmp_addr}),
+        .m_valid        (rreq_valid),
+        .m_ready        (next_rreq));
+
+//------------------------Body---------------------------
+    assign ready_for_rreq = last_sect & next_sect | ~rreq_handling;
+    assign next_rreq      = rreq_valid & ready_for_rreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET) begin
+            start_addr <= 0;
+            end_addr   <= 0;
+            beat_len   <= 0;
+        end
+        else if (ACLK_EN) begin
+            if(next_rreq) begin
+                start_addr <= tmp_addr;
+                end_addr   <= tmp_addr + tmp_len;
+                beat_len   <= (tmp_len[11:0] + tmp_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+            end
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            rreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (rreq_valid && ~rreq_handling)
+                rreq_handling <= 1'b1;
+            else if (~rreq_valid && last_sect && next_sect)
+                rreq_handling <= 1'b0;
+        end
+    end
+
+    assign first_sect = (sect_cnt == start_addr[BUS_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr[BUS_ADDR_WIDTH-1:12]);
+    assign next_sect  = rreq_handling & ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr : {sect_cnt, {12{1'b0}}};
+    assign start_to_4k = BOUNDARY_BEATS - start_addr[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                sect_cnt <= tmp_addr[BUS_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET) begin
+            sect_addr_buf <= 0;
+            sect_len_buf <= 0;
+            last_sect_buf <= 1'b0;
+        end
+        else if (ACLK_EN) begin
+            if (next_sect) begin
+                sect_addr_buf <= sect_addr;
+                sect_len_buf <= sect_len;
+                last_sect_buf <= last_sect;
+            end
+        end
+    end
+
+    assign out_BUS_ARID     = 0;
+    assign out_BUS_ARSIZE   = BUS_ADDR_ALIGN;
+    assign out_BUS_ARBURST  = 2'b01;
+    assign out_BUS_ARLOCK   = 2'b00;
+    assign out_BUS_ARCACHE  = C_CACHE_VALUE;
+    assign out_BUS_ARPROT   = C_PROT_VALUE;
+    assign out_BUS_ARUSER   = C_USER_VALUE;
+    assign out_BUS_ARQOS    = 4'b0000;
+    assign out_BUS_ARREGION = 4'b0000;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) begin : must_one_burst
+        assign out_BUS_ARADDR  = {sect_addr_buf[BUS_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign out_BUS_ARLEN   = sect_len_buf;
+        assign out_BUS_ARVALID = ARVALID_Dummy;
+
+        assign ready_for_sect = ~(ARVALID_Dummy && ~in_BUS_ARREADY) && fifo_rctl_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_sect && in_BUS_ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r  = next_sect;
+        assign ar2r_info    = last_sect;
+
+        assign fifo_burst_w = next_sect;
+        assign araddr_tmp   = sect_addr[BUS_ADDR_WIDTH - 1:0];
+        assign arlen_tmp    = sect_len;
+    end
+    else begin : could_multi_bursts
+        reg  [BUS_ADDR_WIDTH - 1:0]                     araddr_buf;
+        reg  [7:0]                                      arlen_buf;
+        reg  [11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN:0]   loop_cnt;
+        reg                                             sect_handling;
+        wire                                            last_loop;
+        wire                                            next_loop;
+        wire                                            ready_for_loop;
+
+        assign out_BUS_ARADDR  = araddr_buf;
+        assign out_BUS_ARLEN   = arlen_buf;
+        assign out_BUS_ARVALID = ARVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_READ_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(ARVALID_Dummy && ~in_BUS_ARREADY) && fifo_rctl_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (rreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~rreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign araddr_tmp = (loop_cnt == 0)? sect_addr_buf[BUS_ADDR_WIDTH - 1:0] : (araddr_buf + ((arlen_buf + 1) << BUS_ADDR_ALIGN));
+        assign arlen_tmp  = (NUM_READ_WIDTH == 0) ? 0 :
+                            (last_loop)? sect_len_buf[NUM_READ_WIDTH - 1:0] : { NUM_READ_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET) begin
+                araddr_buf <= 0;
+                arlen_buf <= 0;
+            end
+            else if (ACLK_EN) begin
+                if (next_loop) begin
+                    araddr_buf <= {araddr_tmp[BUS_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+                    arlen_buf <= arlen_tmp;
+                end
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_loop && in_BUS_ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r  = next_loop;
+        assign ar2r_info    = last_loop && last_sect_buf;
+
+        assign fifo_burst_w = next_loop;
+    end
+    endgenerate
+//------------------------AR channel end-----------------
+
+//------------------------R channel begin----------------
+//------------------------Instantiation------------------
+    Mmap2Stream_mmap_m_axi_reg_slice #(
+        .DATA_WIDTH     (BUS_DATA_WIDTH + 1)
+    ) rs_rdata (
+        .clk            (ACLK),
+        .reset          (ARESET),
+        .s_data         ({in_BUS_RLAST, in_BUS_RDATA}),
+        .s_valid        (in_BUS_RVALID),
+        .s_ready        (out_BUS_RREADY),
+        .m_data         ({tmp_last, tmp_data}),
+        .m_valid        (data_valid),
+        .m_ready        (data_ready));
+
+    Mmap2Stream_mmap_m_axi_fifo #(
+        .DATA_WIDTH     (1),
+        .ADDR_WIDTH     (log2(NUM_READ_OUTSTANDING)),
+        .DEPTH          (NUM_READ_OUTSTANDING)
+    ) fifo_rctl (
+        .clk            (ACLK),
+        .reset          (ARESET),
+        .clk_en         (ACLK_EN),
+        .if_full_n      (fifo_rctl_ready),
+        .if_write       (fifo_rctl_r),
+        .if_din         (ar2r_info),
+        .if_empty_n     (need_rlast),
+        .if_read        (next_ctrl),
+        .if_dout        (),
+        .if_num_data_valid());
+
+    Mmap2Stream_mmap_m_axi_fifo #(
+        .DATA_WIDTH     (1),
+        .ADDR_WIDTH     (log2(NUM_READ_OUTSTANDING)),
+        .DEPTH          (NUM_READ_OUTSTANDING)
+    ) fifo_burst (
+        .clk            (ACLK),
+        .reset          (ARESET),
+        .clk_en         (ACLK_EN),
+        .if_full_n      (),
+        .if_write       (fifo_rctl_r),
+        .if_din         (ar2r_info),
+        .if_empty_n     (burst_valid),
+        .if_read        (next_burst),
+        .if_dout        (last_burst),
+        .if_num_data_valid());
+
+//------------------------Body---------------------------
+    assign next_ctrl      = in_HLS_RBUST_READY && need_rlast;
+    assign next_burst     = burst_end && data_valid && data_ready;
+
+    assign burst_end      = tmp_last === 1'b1;
+    assign out_HLS_RLAST  = {burst_end, burst_end && last_burst && burst_valid};
+    assign out_HLS_RDATA  = tmp_data;
+    assign out_HLS_RVALID = data_valid;
+    assign data_ready     = in_HLS_RREADY;
+//------------------------R channel end------------------
+endmodule
+
+module Mmap2Stream_mmap_m_axi_write
+#(parameter
+    CONSERVATIVE              = 0,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_AWUSER_WIDTH      = 1,
+    C_M_AXI_WUSER_WIDTH       = 1,
+    C_M_AXI_BUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    BUS_ADDR_WIDTH            = 32,
+    BUS_DATA_WIDTH            = 32,
+    NUM_WRITE_OUTSTANDING     = 2,
+    MAX_WRITE_BURST_LENGTH    = 16
+)(
+    // system signal
+    input  wire                             ACLK,
+    input  wire                             ARESET,
+    input  wire                             ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]      out_BUS_AWID,
+    output wire [2:0]                       out_BUS_AWSIZE,
+    output wire [1:0]                       out_BUS_AWBURST,
+    output wire [1:0]                       out_BUS_AWLOCK,
+    output wire [3:0]                       out_BUS_AWCACHE,
+    output wire [2:0]                       out_BUS_AWPROT,
+    output wire [3:0]                       out_BUS_AWQOS,
+    output wire [3:0]                       out_BUS_AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]  out_BUS_AWUSER,
+    output wire [BUS_ADDR_WIDTH-1:0]        out_BUS_AWADDR,
+    output wire [7:0]                       out_BUS_AWLEN,
+    output wire                             out_BUS_AWVALID,
+    input  wire                             in_BUS_AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]      out_BUS_WID,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]   out_BUS_WUSER,
+    output wire [BUS_DATA_WIDTH-1:0]        out_BUS_WDATA,
+    output wire [BUS_DATA_WIDTH/8-1:0]      out_BUS_WSTRB,
+    output wire                             out_BUS_WLAST,
+    output wire                             out_BUS_WVALID,
+    input  wire                             in_BUS_WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]      in_BUS_BID,
+    input  wire [1:0]                       in_BUS_BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]   in_BUS_BUSER,
+    input  wire                             in_BUS_BVALID,
+    output wire                             out_BUS_BREADY,
+    // write request
+    input  wire [BUS_ADDR_WIDTH-1:0]        in_HLS_AWADDR,
+    input  wire [31:0]                      in_HLS_AWLEN,
+    input  wire                             in_HLS_AWVALID,
+    output wire                             out_HLS_AWREADY,
+
+    input  wire [BUS_DATA_WIDTH-1:0]        in_HLS_WDATA,
+    input  wire [BUS_DATA_WIDTH/8-1:0]      in_HLS_WSTRB,
+    input  wire                             in_HLS_WVALID,
+    output wire                             out_HLS_WREADY,
+    output wire                             out_HLS_BVALID,
+    input  wire                             in_HLS_BREADY);
+
+//------------------------Parameter----------------------
+    localparam
+        BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+        BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+        NUM_WRITE_WIDTH = log2(MAX_WRITE_BURST_LENGTH),
+        BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+    function integer calc_data_width;
+        input integer x;
+        integer y;
+    begin
+        y = 8;
+        while (y < x) y = y * 2;
+        calc_data_width = y;
+    end
+    endfunction
+
+    function integer log2;
+        input integer x;
+        integer n, m;
+    begin
+        n = 0;
+        m = 1;
+        while (m < x) begin
+            n = n + 1;
+            m = m * 2;
+        end
+        log2 = n;
+    end
+    endfunction
+
+//------------------------Local signal-------------------
+    // AW channel
+    wire                                wreq_valid;
+    wire [BUS_ADDR_WIDTH - 1:0]         tmp_addr;
+    wire [31:0]                         tmp_len;
+    wire [7:0]                          awlen_tmp;
+    wire [BUS_ADDR_WIDTH - 1:0]         awaddr_tmp;
+    reg  [BUS_ADDR_WIDTH - 1:0]         start_addr;
+    reg  [BUS_ADDR_WIDTH - 1:0]         end_addr;
+    wire [BUS_ADDR_WIDTH - 1:0]         sect_addr;
+    reg  [BUS_ADDR_WIDTH - 1:0]         sect_addr_buf;
+    wire [11 - BUS_ADDR_ALIGN:0]        start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]        sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]        sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]        beat_len;
+    wire                                aw2b_info;
+    reg  [BUS_ADDR_WIDTH - 13:0]        sect_cnt;
+    wire                                fifo_burst_w;
+    wire                                fifo_resp_w;
+
+    wire [BUS_ADDR_WIDTH - 1:0]         AWADDR_Dummy;
+    wire [7:0]                          AWLEN_Dummy;
+    reg                                 AWVALID_Dummy;
+    wire                                AWREADY_Dummy;
+    wire                                ready_for_sect;
+    wire                                next_wreq;
+    wire                                ready_for_wreq;
+    reg                                 wreq_handling;
+    wire                                first_sect;
+    reg                                 last_sect_buf;
+    wire                                last_sect;
+    wire                                next_sect;
+    // W channel
+    wire                                next_data;
+    wire                                data_valid;
+    wire                                data_ready;
+    reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+    reg  [BUS_DATA_BYTES - 1:0]         strb_buf;
+    wire                                ready_for_data;
+
+    reg  [7:0]                          len_cnt;
+    wire [7:0]                          burst_len;
+    wire                                fifo_burst_ready;
+    wire                                next_burst;
+    wire                                burst_valid;
+    reg                                 WVALID_Dummy;
+    wire                                WREADY_Dummy;
+    reg                                 WLAST_Dummy;
+    //B channel
+    wire                                next_resp;
+    wire                                last_resp;
+    wire                                fifo_resp_ready;
+    wire                                need_wrsp;
+    wire                                resp_valid;
+    wire                                resp_ready;
+
+//------------------------AW channel begin---------------
+//------------------------Instantiation------------------
+    Mmap2Stream_mmap_m_axi_reg_slice #(
+        .DATA_WIDTH     (BUS_ADDR_WIDTH + 32)
+    ) rs_wreq (
+        .clk            (ACLK),
+        .reset          (ARESET),
+        .s_data         ({in_HLS_AWLEN, in_HLS_AWADDR}),
+        .s_valid        (in_HLS_AWVALID),
+        .s_ready        (out_HLS_AWREADY),
+        .m_data         ({tmp_len, tmp_addr}),
+        .m_valid        (wreq_valid),
+        .m_ready        (next_wreq));
+
+//------------------------Body---------------------------
+    assign ready_for_wreq = last_sect & next_sect | ~wreq_handling;
+    assign next_wreq      = wreq_valid & ready_for_wreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET) begin
+            start_addr <= 0;
+            end_addr   <= 0;
+            beat_len   <= 0;
+        end
+        else if (ACLK_EN) begin
+            if (next_wreq) begin
+                start_addr <= tmp_addr;
+                end_addr   <= tmp_addr + tmp_len;
+                beat_len   <= (tmp_len[11:0] + tmp_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+            end
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            wreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (wreq_valid && ~wreq_handling)
+                wreq_handling <= 1'b1;
+            else if (~wreq_valid && last_sect && next_sect)
+                wreq_handling <= 1'b0;
+        end
+    end
+
+    // 4k boundary
+    assign first_sect = (sect_cnt == start_addr[BUS_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr[BUS_ADDR_WIDTH-1:12]);
+    assign next_sect  = wreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr : {sect_cnt, {12{1'b0}}};
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                sect_cnt <= tmp_addr[BUS_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET) begin
+            sect_addr_buf <= 0;
+            sect_len_buf <= 0;
+            last_sect_buf <= 1'b0;
+        end
+        else if (ACLK_EN) begin
+            if (next_sect) begin
+                sect_addr_buf <= sect_addr;
+                sect_len_buf <= sect_len;
+                last_sect_buf <= last_sect;
+            end
+        end
+    end
+
+    // burst converter
+    assign out_BUS_AWID     = 0;
+    assign out_BUS_AWSIZE   = BUS_ADDR_ALIGN;
+    assign out_BUS_AWBURST  = 2'b01;
+    assign out_BUS_AWLOCK   = 2'b00;
+    assign out_BUS_AWCACHE  = C_CACHE_VALUE;
+    assign out_BUS_AWPROT   = C_PROT_VALUE;
+    assign out_BUS_AWUSER   = C_USER_VALUE;
+    assign out_BUS_AWQOS    = 4'b0000;
+    assign out_BUS_AWREGION = 4'b0000;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) begin : must_one_burst
+        assign AWADDR_Dummy   = {sect_addr_buf[BUS_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign AWLEN_Dummy    = sect_len_buf;
+
+        assign ready_for_sect = ~(AWVALID_Dummy && ~AWREADY_Dummy) && fifo_burst_ready && fifo_resp_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_sect && AWREADY_Dummy)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_sect;
+        assign aw2b_info   = last_sect;
+
+        assign fifo_burst_w = next_sect;
+        assign awaddr_tmp   = sect_addr[BUS_ADDR_WIDTH - 1:0];
+        assign awlen_tmp    = sect_len;
+    end
+    else begin : could_multi_bursts
+        reg  [BUS_ADDR_WIDTH - 1:0]                         awaddr_buf;
+        reg  [7:0]                                          awlen_buf;
+        reg  [11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN : 0]    loop_cnt;
+        reg                                                 sect_handling;
+        wire                                                last_loop;
+        wire                                                next_loop;
+        wire                                                ready_for_loop;
+
+        assign AWADDR_Dummy   = awaddr_buf;
+        assign AWLEN_Dummy    = awlen_buf;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_WRITE_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(AWVALID_Dummy && ~AWREADY_Dummy) && fifo_burst_ready && fifo_resp_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (wreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~wreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign awaddr_tmp = (loop_cnt == 0)? sect_addr_buf[BUS_ADDR_WIDTH - 1:0] : (awaddr_buf + ((awlen_buf + 1) << BUS_ADDR_ALIGN));
+        assign awlen_tmp  = (NUM_WRITE_WIDTH == 0)? 0 :
+                    (last_loop)? sect_len_buf[NUM_WRITE_WIDTH - 1:0] : { NUM_WRITE_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET) begin
+                awaddr_buf <= 0;
+                awlen_buf <= 0;
+            end
+            else if (ACLK_EN) begin
+                if (next_loop) begin
+                    awaddr_buf <= {awaddr_tmp[BUS_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+                    awlen_buf <= awlen_tmp;
+                end
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_loop && AWREADY_Dummy)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_loop;
+        assign fifo_burst_w = next_loop;
+        assign aw2b_info = last_loop && last_sect_buf;
+    end
+    endgenerate
+//------------------------AW channel end-----------------
+
+//------------------------W channel begin----------------
+//------------------------Instantiation------------------
+
+    Mmap2Stream_mmap_m_axi_fifo #(
+        .DATA_WIDTH     (8),
+        .ADDR_WIDTH     (log2(NUM_WRITE_OUTSTANDING)),
+        .DEPTH          (NUM_WRITE_OUTSTANDING)
+    ) fifo_burst (
+        .clk            (ACLK),
+        .reset          (ARESET),
+        .clk_en         (ACLK_EN),
+        .if_full_n      (fifo_burst_ready),
+        .if_write       (fifo_burst_w),
+        .if_din         (awlen_tmp),
+        .if_empty_n     (burst_valid),
+        .if_read        (next_burst),
+        .if_dout        (burst_len),
+        .if_num_data_valid());
+
+//------------------------Body---------------------------
+
+    assign out_BUS_WUSER    = C_USER_VALUE;
+    assign out_BUS_WID      = 0;
+    assign out_HLS_WREADY   = data_ready;
+
+    assign data_valid       = in_HLS_WVALID;
+    assign data_ready       = burst_valid && ready_for_data;
+    assign next_data        = data_ready && data_valid;
+    assign next_burst       = (len_cnt == burst_len) && next_data;
+    assign ready_for_data   = ~WVALID_Dummy || WREADY_Dummy;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET) begin
+            strb_buf <= 0;
+            data_buf <= 0;
+        end
+        if (ACLK_EN) begin
+            if (next_data) begin
+                data_buf <= in_HLS_WDATA;
+                strb_buf <= in_HLS_WSTRB;
+            end
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            WVALID_Dummy <= 1'b0;
+        else if (ACLK_EN) begin
+            if (next_data)
+                WVALID_Dummy <= 1'b1;
+            else if (ready_for_data)
+                WVALID_Dummy <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            WLAST_Dummy <= 0;
+        else if (ACLK_EN) begin
+            if (next_burst)
+                WLAST_Dummy <= 1;
+            else if (ready_for_data)
+                WLAST_Dummy <= 0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            len_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_burst)
+                len_cnt <= 0;
+            else if (next_data)
+                len_cnt <= len_cnt + 1;
+        end
+    end
+//------------------------W channel end------------------
+
+    // Write throttling unit
+    Mmap2Stream_mmap_m_axi_throttle #(
+        .CONSERVATIVE(CONSERVATIVE),
+        .USED_FIX(0),
+        .ADDR_WIDTH(BUS_ADDR_WIDTH),
+        .DATA_WIDTH(BUS_DATA_WIDTH),
+        .DEPTH(MAX_WRITE_BURST_LENGTH),
+        .MAXREQS(NUM_WRITE_OUTSTANDING),
+        .AVERAGE_MODE(0)
+    ) wreq_throttle (
+        .clk(ACLK),
+        .reset(ARESET),
+        .clk_en(ACLK_EN),
+        // internal
+        .in_TOP_AWADDR(AWADDR_Dummy),
+        .in_TOP_AWLEN(AWLEN_Dummy),
+        .in_TOP_AWVALID(AWVALID_Dummy),
+        .out_TOP_AWREADY(AWREADY_Dummy),
+
+        .in_TOP_WDATA(data_buf),
+        .in_TOP_WSTRB(strb_buf),
+        .in_TOP_WLAST(WLAST_Dummy),
+        .in_TOP_WVALID(WVALID_Dummy),
+        .out_TOP_WREADY(WREADY_Dummy),
+
+        // AXI BUS
+        .out_BUS_AWADDR(out_BUS_AWADDR),
+        .out_BUS_AWLEN(out_BUS_AWLEN),
+        .out_BUS_AWVALID(out_BUS_AWVALID),
+        .in_BUS_AWREADY(in_BUS_AWREADY),
+
+        .out_BUS_WDATA(out_BUS_WDATA),
+        .out_BUS_WSTRB(out_BUS_WSTRB),
+        .out_BUS_WLAST(out_BUS_WLAST),
+        .out_BUS_WVALID(out_BUS_WVALID),
+        .in_BUS_WREADY(in_BUS_WREADY)
+    );
+
+//------------------------B channel begin----------------
+//------------------------Instantiation------------------
+    Mmap2Stream_mmap_m_axi_reg_slice #(
+        .DATA_WIDTH     (1)
+    ) rs_resp (
+        .clk            (ACLK),
+        .reset          (ARESET),
+        .s_data         (1'b1),
+        .s_valid        (in_BUS_BVALID),
+        .s_ready        (out_BUS_BREADY),
+        .m_data         (),
+        .m_valid        (resp_valid),
+        .m_ready        (resp_ready));
+
+    Mmap2Stream_mmap_m_axi_fifo #(
+        .DATA_WIDTH     (1),
+        .ADDR_WIDTH     (log2(NUM_WRITE_OUTSTANDING)),
+        .DEPTH          (NUM_WRITE_OUTSTANDING)
+    ) fifo_resp (
+        .clk            (ACLK),
+        .reset          (ARESET),
+        .clk_en         (ACLK_EN),
+        .if_full_n      (fifo_resp_ready),
+        .if_write       (fifo_resp_w),
+        .if_din         (aw2b_info),
+        .if_empty_n     (need_wrsp),
+        .if_read        (next_resp),
+        .if_dout        (last_resp),
+        .if_num_data_valid());
+//------------------------Body---------------------------
+
+    assign resp_ready = need_wrsp && (in_HLS_BREADY || (last_resp === 1'b0));
+    assign next_resp  = resp_ready && resp_valid;
+
+    assign out_HLS_BVALID = resp_valid && (last_resp === 1'b1 ) ;
+
+//------------------------B channel end------------------
+endmodule
+
+module Mmap2Stream_mmap_m_axi_throttle
+#(parameter
+    CONSERVATIVE   = 0,
+    USED_FIX       = 0,
+    FIX_VALUE      = 4,
+    ADDR_WIDTH     = 32,
+    DATA_WIDTH     = 32,
+    DEPTH          = 16,
+    MAXREQS        = 16,
+    AVERAGE_MODE   = 0
+)(
+    input  wire                      clk,
+    input  wire                      reset,
+    input  wire                      clk_en,
+
+    input  wire [ADDR_WIDTH-1:0]     in_TOP_AWADDR,
+    input  wire [7:0]                in_TOP_AWLEN,
+    input  wire                      in_TOP_AWVALID,
+    output wire                      out_TOP_AWREADY,
+    input  wire [DATA_WIDTH-1:0]     in_TOP_WDATA,
+    input  wire [DATA_WIDTH/8-1:0]   in_TOP_WSTRB,
+    input  wire                      in_TOP_WLAST,
+    input  wire                      in_TOP_WVALID,
+    output wire                      out_TOP_WREADY,
+
+    output wire [ADDR_WIDTH-1:0]     out_BUS_AWADDR,
+    output wire [7:0]                out_BUS_AWLEN,
+    output wire                      out_BUS_AWVALID,
+    input  wire                      in_BUS_AWREADY,
+    output wire [DATA_WIDTH-1:0]     out_BUS_WDATA,
+    output wire [DATA_WIDTH/8-1:0]   out_BUS_WSTRB,
+    output wire                      out_BUS_WLAST,
+    output wire                      out_BUS_WVALID,
+    input  wire                      in_BUS_WREADY);
+
+    function integer log2;
+        input integer x;
+        integer n, m;
+    begin
+        n = 0;
+        m = 1;
+        while (m < x) begin
+            n = n + 1;
+            m = m * 2;
+        end
+        log2 = n;
+    end
+    endfunction
+// aggressive mode
+    generate
+    if (CONSERVATIVE == 0) begin
+        localparam threshold = (USED_FIX)? FIX_VALUE-1 : 0;
+
+        wire                req_en;
+        wire                handshake;
+        wire  [7:0]         load_init;
+        reg   [8:0]         throttl_cnt;
+
+        // AW Channel
+        assign out_BUS_AWADDR = in_TOP_AWADDR;
+        assign out_BUS_AWLEN  = in_TOP_AWLEN;
+
+        // W Channel
+        assign out_BUS_WDATA  = in_TOP_WDATA;
+        assign out_BUS_WSTRB  = in_TOP_WSTRB;
+        assign out_BUS_WLAST  = in_TOP_WLAST;
+        assign out_BUS_WVALID = in_TOP_WVALID & (throttl_cnt > 0);
+        assign out_TOP_WREADY = in_BUS_WREADY & (throttl_cnt > 0);
+
+        if (USED_FIX) begin
+            assign load_init = FIX_VALUE-1;
+            assign handshake = 1'b1;
+        end else if (AVERAGE_MODE) begin
+            assign load_init = in_TOP_AWLEN;
+            assign handshake = 1'b1;
+        end else begin
+            assign load_init = in_TOP_AWLEN;
+            assign handshake = out_BUS_WVALID & in_BUS_WREADY;
+        end
+
+        assign out_BUS_AWVALID = in_TOP_AWVALID & req_en;
+        assign out_TOP_AWREADY = in_BUS_AWREADY & req_en;
+        assign req_en = (throttl_cnt == 0) | (throttl_cnt == 1 & handshake);
+
+        always @(posedge clk)
+        begin
+            if (reset)
+                throttl_cnt <= 0;
+            else if (clk_en) begin
+                if (in_TOP_AWLEN >= threshold && req_en && in_TOP_AWVALID && in_BUS_AWREADY)
+                    throttl_cnt <= load_init + 1'b1; //load
+                else if (throttl_cnt > 0 && handshake)
+                    throttl_cnt <= throttl_cnt - 1'b1;
+            end
+        end
+
+    end
+// conservative mode
+    else begin
+        localparam CNT_WIDTH = ((DEPTH < 4)? 2 : log2(DEPTH)) + 1;
+
+        // Instantiation for reg slice for AW channel
+        wire                        rs_req_ready;
+        wire                        rs_req_valid;
+        wire [ADDR_WIDTH + 7 : 0]   rs_req_in;
+        wire [ADDR_WIDTH + 7 : 0]   rs_req_out;
+
+        Mmap2Stream_mmap_m_axi_reg_slice #(
+            .DATA_WIDTH     (ADDR_WIDTH + 8)
+        ) rs_req (
+            .clk            (clk),
+            .reset          (reset),
+            .s_data         (rs_req_in),
+            .s_valid        (rs_req_valid),
+            .s_ready        (rs_req_ready),
+            .m_data         (rs_req_out),
+            .m_valid        (out_BUS_AWVALID),
+            .m_ready        (in_BUS_AWREADY));
+
+        wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_in;
+        wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_out;
+        wire  [ADDR_WIDTH + 7 : 0]              req_in;
+        reg                                     req_en;
+        wire                                    data_en;
+        wire                                    fifo_valid;
+        wire                                    read_fifo;
+        wire                                    req_fifo_valid;
+        wire                                    read_req;
+        wire                                    data_push;
+        wire                                    data_pop;
+        reg                                     flying_req;
+        reg   [CNT_WIDTH-1 : 0]                 last_cnt;
+
+        //AW Channel
+        assign req_in   = {in_TOP_AWLEN, in_TOP_AWADDR};
+        assign out_BUS_AWADDR = rs_req_out[ADDR_WIDTH-1 : 0];
+        assign out_BUS_AWLEN  = rs_req_out[ADDR_WIDTH+7 : ADDR_WIDTH];
+        assign rs_req_valid = req_fifo_valid & req_en;
+
+        assign read_req      = rs_req_ready & req_en;
+
+        always @(*)
+        begin
+            if (~flying_req & data_en)
+                req_en <= 1;
+            else if (flying_req & (out_BUS_WLAST & data_pop) & (last_cnt[CNT_WIDTH-1:1] != 0))
+                req_en <= 1;
+            else
+                req_en <= 0;
+        end
+
+        always @(posedge clk)
+        begin
+            if (reset)
+                flying_req <= 0;
+            else if (clk_en) begin
+                if (rs_req_valid & rs_req_ready)
+                    flying_req <= 1;
+                else if (out_BUS_WLAST & data_pop)
+                    flying_req <= 0;
+            end
+        end
+
+        Mmap2Stream_mmap_m_axi_fifo #(
+            .DATA_WIDTH     (ADDR_WIDTH + 8),
+            .ADDR_WIDTH     (log2(MAXREQS)),
+            .DEPTH          (MAXREQS)
+        ) req_fifo (
+            .clk            (clk),
+            .reset          (reset),
+            .clk_en         (clk_en),
+            .if_full_n      (out_TOP_AWREADY),
+            .if_write       (in_TOP_AWVALID),
+            .if_din         (req_in),
+            .if_empty_n     (req_fifo_valid),
+            .if_read        (read_req),
+            .if_dout        (rs_req_in),
+            .if_num_data_valid());
+
+        //W Channel
+        assign data_in  = {in_TOP_WLAST, in_TOP_WSTRB, in_TOP_WDATA};
+        assign out_BUS_WDATA = data_out[DATA_WIDTH-1 : 0];
+        assign out_BUS_WSTRB = data_out[DATA_WIDTH+DATA_WIDTH/8-1 : DATA_WIDTH];
+        assign out_BUS_WLAST = data_out[DATA_WIDTH+DATA_WIDTH/8];
+        assign out_BUS_WVALID = fifo_valid & data_en & flying_req;
+
+        assign data_en   = last_cnt != 0;
+        assign data_push = in_TOP_WVALID & out_TOP_WREADY;
+        assign data_pop  = fifo_valid & read_fifo;
+        assign read_fifo = in_BUS_WREADY & data_en & flying_req;
+
+        always @(posedge clk)
+        begin
+            if (reset)
+                last_cnt <= 0;
+            else if (clk_en) begin
+                if ((in_TOP_WLAST & data_push) && ~(out_BUS_WLAST & data_pop))
+                    last_cnt <= last_cnt + 1;
+                else if (~(in_TOP_WLAST & data_push) && (out_BUS_WLAST & data_pop))
+                    last_cnt <= last_cnt - 1;
+            end
+        end
+
+        Mmap2Stream_mmap_m_axi_fifo #(
+            .DATA_WIDTH     (DATA_WIDTH + DATA_WIDTH/8 + 1),
+            .ADDR_WIDTH     (log2(DEPTH)),
+            .DEPTH          (DEPTH)
+        ) data_fifo (
+            .clk            (clk),
+            .reset          (reset),
+            .clk_en         (clk_en),
+            .if_full_n      (out_TOP_WREADY),
+            .if_write       (in_TOP_WVALID),
+            .if_din         (data_in),
+            .if_empty_n     (fifo_valid),
+            .if_read        (read_fifo),
+            .if_dout        (data_out),
+            .if_num_data_valid());
+
+        end
+    endgenerate
+
+endmodule
+
+
+module Mmap2Stream_mmap_m_axi_reg_slice
+#(parameter
+    DATA_WIDTH = 8
+) (
+    // system signals
+    input  wire                  clk,
+    input  wire                  reset,
+    // slave side
+    input  wire [DATA_WIDTH-1:0] s_data,
+    input  wire                  s_valid,
+    output wire                  s_ready,
+    // master side
+    output wire [DATA_WIDTH-1:0] m_data,
+    output wire                  m_valid,
+    input  wire                  m_ready);
+    //------------------------Parameter----------------------
+    // state
+    localparam [1:0]
+        ZERO = 2'b10,
+        ONE  = 2'b11,
+        TWO  = 2'b01;
+    //------------------------Local signal-------------------
+    reg  [DATA_WIDTH-1:0] data_p1;
+    reg  [DATA_WIDTH-1:0] data_p2;
+    wire         load_p1;
+    wire         load_p2;
+    wire         load_p1_from_p2;
+    reg          s_ready_t;
+    reg  [1:0]   state;
+    reg  [1:0]   next;
+    //------------------------Body---------------------------
+    assign s_ready = s_ready_t;
+    assign m_data  = data_p1;
+    assign m_valid = state[0];
+
+    assign load_p1 = (state == ZERO && s_valid) ||
+                    (state == ONE && s_valid && m_ready) ||
+                    (state == TWO && m_ready);
+    assign load_p2 = s_valid & s_ready;
+    assign load_p1_from_p2 = (state == TWO);
+
+    // data_p1
+    always @(posedge clk) begin
+        if (load_p1) begin
+            if (load_p1_from_p2)
+                data_p1 <= data_p2;
+            else
+                data_p1 <= s_data;
+        end
+    end
+
+    // data_p2
+    always @(posedge clk) begin
+        if (load_p2) data_p2 <= s_data;
+    end
+
+    // s_ready_t
+    always @(posedge clk) begin
+        if (reset)
+            s_ready_t <= 1'b0;
+        else if (state == ZERO)
+            s_ready_t <= 1'b1;
+        else if (state == ONE && next == TWO)
+            s_ready_t <= 1'b0;
+        else if (state == TWO && next == ONE)
+            s_ready_t <= 1'b1;
+    end
+
+    // state
+    always @(posedge clk) begin
+        if (reset)
+            state <= ZERO;
+        else
+            state <= next;
+    end
+
+    // next
+    always @(*) begin
+        case (state)
+            ZERO:
+                if (s_valid & s_ready)
+                    next = ONE;
+                else
+                    next = ZERO;
+            ONE:
+                if (~s_valid & m_ready)
+                    next = ZERO;
+                else if (s_valid & ~m_ready)
+                    next = TWO;
+                else
+                    next = ONE;
+            TWO:
+                if (m_ready)
+                    next = ONE;
+                else
+                    next = TWO;
+            default:
+                next = ZERO;
+        endcase
+    end
+endmodule
+
+module Mmap2Stream_mmap_m_axi_fifo
+#(parameter
+    MEM_STYLE   = "shiftreg",
+    DATA_WIDTH = 32,
+    ADDR_WIDTH = 5,
+    DEPTH      = 32
+) (
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire                  clk_en,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+
+    // read
+    output wire                  if_empty_n,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout,
+    output wire [ADDR_WIDTH:0]   if_num_data_valid);
+
+//------------------------Local signal-------------------
+
+    wire                  push;
+    wire                  pop;
+    reg                   full_n = 1'b1;
+    reg                   empty_n = 1'b0;
+    reg                   dout_vld = 1'b0;
+    reg  [ADDR_WIDTH:0]   mOutPtr = 1'b0;
+
+//------------------------Instantiation------------------
+    generate
+    if ((MEM_STYLE == "shiftreg") || (DEPTH == 1)) begin
+        reg  [ADDR_WIDTH-1:0] raddr = 1'b0;
+
+        Mmap2Stream_mmap_m_axi_srl
+        #(  .DATA_WIDTH     (DATA_WIDTH),
+            .ADDR_WIDTH     (ADDR_WIDTH),
+            .DEPTH          (DEPTH))
+        U_fifo_srl(
+            .clk            (clk),
+            .reset          (reset),
+            .clk_en         (clk_en),
+            .we             (push),
+            .din            (if_din),
+            .raddr          (raddr),
+            .re             (pop),
+            .dout           (if_dout)
+        );
+
+        // raddr
+        always @(posedge clk) begin
+            if (reset == 1'b1)
+                raddr <= 1'b0;
+            else if (clk_en) begin
+                if (push & ~pop & empty_n)
+                    raddr <= raddr + 1'b1;
+                else if (~push & pop && raddr != 0)
+                    raddr <= raddr - 1'b1;
+            end
+        end
+
+    end else begin
+        reg  [ADDR_WIDTH-1:0] waddr = 1'b0;
+        reg  [ADDR_WIDTH-1:0] raddr = 1'b0;
+        wire [ADDR_WIDTH-1:0] wnext;
+        wire [ADDR_WIDTH-1:0] rnext;
+
+        Mmap2Stream_mmap_m_axi_mem
+        #(  .MEM_STYLE      (MEM_STYLE),
+            .DATA_WIDTH     (DATA_WIDTH),
+            .ADDR_WIDTH     (ADDR_WIDTH),
+            .DEPTH          (DEPTH))
+        U_fifo_mem(
+            .clk            (clk),
+            .reset          (reset),
+            .clk_en         (clk_en),
+            .we             (push),
+            .waddr          (waddr),
+            .din            (if_din),
+            .raddr          (rnext),
+            .re             (pop),
+            .dout           (if_dout)
+        );
+
+        assign wnext =  !push                ? waddr :
+                        (waddr == DEPTH - 2) ? 1'b0  :
+                        waddr + 1'b1;
+        assign rnext =  !pop                 ? raddr :
+                        (raddr == DEPTH - 2) ? 1'b0  :
+                        raddr + 1'b1;
+
+        // waddr
+        always @(posedge clk) begin
+            if (reset == 1'b1)
+                waddr <= 1'b0;
+            else if (clk_en)
+                waddr <= wnext;
+        end
+
+        // raddr
+        always @(posedge clk) begin
+            if (reset == 1'b1)
+                raddr <= 1'b0;
+            else if (clk_en)
+                raddr <= rnext;
+        end
+    end
+    endgenerate
+
+//------------------------Body---------------------------
+    assign if_num_data_valid = dout_vld ? mOutPtr + 1'b1 : 'b0;
+
+    generate if (DEPTH == 1) begin
+        assign if_full_n  = !dout_vld;
+        assign if_empty_n = dout_vld;
+        assign push = !dout_vld & if_write;
+        assign pop  = !dout_vld & if_write;
+
+    end else begin
+
+        assign if_full_n  = full_n;
+        assign if_empty_n = dout_vld;
+        assign push = full_n & if_write;
+        assign pop  = empty_n & (if_read | ~dout_vld);
+
+        // mOutPtr
+        always @(posedge clk) begin
+            if (reset == 1'b1)
+                mOutPtr <= 'b0;
+            else if (clk_en)
+                if (push & ~pop)
+                    mOutPtr <= mOutPtr + 1'b1;
+                else if (~push & pop)
+                    mOutPtr <= mOutPtr - 1'b1;
+        end
+
+        // full_n
+        always @(posedge clk) begin
+            if (reset == 1'b1)
+                full_n <= 1'b1;
+            else if (clk_en)
+                if (push & ~pop)
+                    full_n <= (mOutPtr != DEPTH - 2);
+                else if (~push & pop)
+                    full_n <= 1'b1;
+        end
+
+        // empty_n
+        always @(posedge clk)
+        begin
+            if (reset)
+                empty_n <= 1'b0;
+            else if (clk_en) begin
+                if (push & ~pop)
+                    empty_n <= 1'b1;
+                else if (~push & pop)
+                    empty_n <= (mOutPtr != 1'b1);
+            end
+        end
+    end
+    endgenerate
+
+    // dout_vld
+    always @(posedge clk) begin
+        if (reset == 1'b1)
+            dout_vld <= 1'b0;
+        else if (clk_en)
+            if (pop)
+                dout_vld <= 1'b1;
+            else if (if_read)
+                dout_vld <= 1'b0;
+    end
+
+endmodule
+
+module Mmap2Stream_mmap_m_axi_srl
+#(parameter
+        DATA_WIDTH  = 32,
+        ADDR_WIDTH  = 6,
+        DEPTH       = 63
+    )(
+        input  wire                  clk,
+        input  wire                  reset,
+        input  wire                  clk_en,
+        input  wire                  we,
+        input  wire [DATA_WIDTH-1:0] din,
+        input  wire [ADDR_WIDTH-1:0] raddr,
+        input  wire                  re,
+        output reg  [DATA_WIDTH-1:0] dout
+    );
+
+    generate
+    if (DEPTH > 1) begin
+        reg  [DATA_WIDTH-1:0] mem[0:DEPTH-2];
+
+        integer i;
+        always @(posedge clk)
+        begin
+            if (clk_en & we) begin
+                for (i = 0; i < DEPTH - 2; i = i + 1) begin
+                    mem[i+1] <= mem[i];
+                end
+                mem[0] <= din;
+            end
+        end
+
+        always @(posedge clk)
+        begin
+            if (reset)
+                dout <= 0;
+            else if (clk_en & re) begin
+                dout <= mem[raddr];
+            end
+        end
+    end
+    else begin
+        always @(posedge clk)
+        begin
+            if (reset)
+                dout <= 0;
+            else if (clk_en & we) begin
+                dout <= din;
+            end
+        end
+    end
+    endgenerate
+
+endmodule
+
+module Mmap2Stream_mmap_m_axi_mem
+#(parameter
+    MEM_STYLE   = "auto",
+    DATA_WIDTH  = 32,
+    ADDR_WIDTH  = 6,
+    DEPTH       = 63
+)(
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire                  clk_en,
+    input  wire                  we,
+    input  wire [ADDR_WIDTH-1:0] waddr,
+    input  wire [DATA_WIDTH-1:0] din,
+    input  wire [ADDR_WIDTH-1:0] raddr,
+    input  wire                  re,
+    output reg  [DATA_WIDTH-1:0] dout);
+
+    (* ram_style = MEM_STYLE, rw_addr_collision = "yes" *)
+    reg  [DATA_WIDTH-1:0] mem[0:DEPTH-2];
+    reg  [ADDR_WIDTH-1:0] raddr_reg;
+
+    //write to ram
+    always @(posedge clk) begin
+        if (clk_en & we)
+            mem[waddr] <= din;
+    end
+
+    //buffer the raddr
+    always @(posedge clk) begin
+        if (clk_en)
+            raddr_reg <= raddr;
+    end
+
+    //read from ram
+    always @(posedge clk) begin
+        if (reset)
+            dout <= 0;
+        else if (clk_en & re)
+            dout <= mem[raddr_reg];
+    end
+endmodule
diff --git a/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/Stream2Mmap.v b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/Stream2Mmap.v
new file mode 100644
index 00000000..ddbb1e6c
--- /dev/null
+++ b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/Stream2Mmap.v
@@ -0,0 +1,617 @@
+// ==============================================================
+// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit)
+// Version: 2022.2
+// Copyright (C) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+//
+// ===========================================================
+
+`timescale 1 ns / 1 ps
+
+(* CORE_GENERATION_INFO="Stream2Mmap_Stream2Mmap,hls_ip_2022_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xcu50-fsvh2104-2-e,HLS_INPUT_CLOCK=3.330000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.430900,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=5217,HLS_SYN_LUT=8304,HLS_VERSION=2022_2}" *)
+
+module Stream2Mmap (
+        ap_clk,
+        ap_rst_n,
+        ap_start,
+        ap_done,
+        ap_idle,
+        ap_ready,
+        m_axi_mmap_AWVALID,
+        m_axi_mmap_AWREADY,
+        m_axi_mmap_AWADDR,
+        m_axi_mmap_AWID,
+        m_axi_mmap_AWLEN,
+        m_axi_mmap_AWSIZE,
+        m_axi_mmap_AWBURST,
+        m_axi_mmap_AWLOCK,
+        m_axi_mmap_AWCACHE,
+        m_axi_mmap_AWPROT,
+        m_axi_mmap_AWQOS,
+        m_axi_mmap_AWREGION,
+        m_axi_mmap_AWUSER,
+        m_axi_mmap_WVALID,
+        m_axi_mmap_WREADY,
+        m_axi_mmap_WDATA,
+        m_axi_mmap_WSTRB,
+        m_axi_mmap_WLAST,
+        m_axi_mmap_WID,
+        m_axi_mmap_WUSER,
+        m_axi_mmap_ARVALID,
+        m_axi_mmap_ARREADY,
+        m_axi_mmap_ARADDR,
+        m_axi_mmap_ARID,
+        m_axi_mmap_ARLEN,
+        m_axi_mmap_ARSIZE,
+        m_axi_mmap_ARBURST,
+        m_axi_mmap_ARLOCK,
+        m_axi_mmap_ARCACHE,
+        m_axi_mmap_ARPROT,
+        m_axi_mmap_ARQOS,
+        m_axi_mmap_ARREGION,
+        m_axi_mmap_ARUSER,
+        m_axi_mmap_RVALID,
+        m_axi_mmap_RREADY,
+        m_axi_mmap_RDATA,
+        m_axi_mmap_RLAST,
+        m_axi_mmap_RID,
+        m_axi_mmap_RUSER,
+        m_axi_mmap_RRESP,
+        m_axi_mmap_BVALID,
+        m_axi_mmap_BREADY,
+        m_axi_mmap_BRESP,
+        m_axi_mmap_BID,
+        m_axi_mmap_BUSER,
+        stream_s_dout,
+        stream_s_empty_n,
+        stream_s_read,
+        stream_peek_dout,
+        stream_peek_empty_n,
+        stream_peek_read,
+        mmap_offset,
+        n
+);
+
+parameter    ap_ST_fsm_state1 = 8'd1;
+parameter    ap_ST_fsm_state2 = 8'd2;
+parameter    ap_ST_fsm_state3 = 8'd4;
+parameter    ap_ST_fsm_state4 = 8'd8;
+parameter    ap_ST_fsm_state5 = 8'd16;
+parameter    ap_ST_fsm_state6 = 8'd32;
+parameter    ap_ST_fsm_state7 = 8'd64;
+parameter    ap_ST_fsm_state8 = 8'd128;
+parameter    C_M_AXI_MMAP_ID_WIDTH = 1;
+parameter    C_M_AXI_MMAP_ADDR_WIDTH = 64;
+parameter    C_M_AXI_MMAP_DATA_WIDTH = 512;
+parameter    C_M_AXI_MMAP_AWUSER_WIDTH = 1;
+parameter    C_M_AXI_MMAP_ARUSER_WIDTH = 1;
+parameter    C_M_AXI_MMAP_WUSER_WIDTH = 1;
+parameter    C_M_AXI_MMAP_RUSER_WIDTH = 1;
+parameter    C_M_AXI_MMAP_BUSER_WIDTH = 1;
+parameter    C_M_AXI_MMAP_USER_VALUE = 0;
+parameter    C_M_AXI_MMAP_PROT_VALUE = 0;
+parameter    C_M_AXI_MMAP_CACHE_VALUE = 3;
+parameter    C_M_AXI_DATA_WIDTH = 32;
+
+parameter C_M_AXI_MMAP_WSTRB_WIDTH = (512 / 8);
+parameter C_M_AXI_WSTRB_WIDTH = (32 / 8);
+
+input   ap_clk;
+input   ap_rst_n;
+input   ap_start;
+output   ap_done;
+output   ap_idle;
+output   ap_ready;
+output   m_axi_mmap_AWVALID;
+input   m_axi_mmap_AWREADY;
+output  [C_M_AXI_MMAP_ADDR_WIDTH - 1:0] m_axi_mmap_AWADDR;
+output  [C_M_AXI_MMAP_ID_WIDTH - 1:0] m_axi_mmap_AWID;
+output  [7:0] m_axi_mmap_AWLEN;
+output  [2:0] m_axi_mmap_AWSIZE;
+output  [1:0] m_axi_mmap_AWBURST;
+output  [1:0] m_axi_mmap_AWLOCK;
+output  [3:0] m_axi_mmap_AWCACHE;
+output  [2:0] m_axi_mmap_AWPROT;
+output  [3:0] m_axi_mmap_AWQOS;
+output  [3:0] m_axi_mmap_AWREGION;
+output  [C_M_AXI_MMAP_AWUSER_WIDTH - 1:0] m_axi_mmap_AWUSER;
+output   m_axi_mmap_WVALID;
+input   m_axi_mmap_WREADY;
+output  [C_M_AXI_MMAP_DATA_WIDTH - 1:0] m_axi_mmap_WDATA;
+output  [C_M_AXI_MMAP_WSTRB_WIDTH - 1:0] m_axi_mmap_WSTRB;
+output   m_axi_mmap_WLAST;
+output  [C_M_AXI_MMAP_ID_WIDTH - 1:0] m_axi_mmap_WID;
+output  [C_M_AXI_MMAP_WUSER_WIDTH - 1:0] m_axi_mmap_WUSER;
+output   m_axi_mmap_ARVALID;
+input   m_axi_mmap_ARREADY;
+output  [C_M_AXI_MMAP_ADDR_WIDTH - 1:0] m_axi_mmap_ARADDR;
+output  [C_M_AXI_MMAP_ID_WIDTH - 1:0] m_axi_mmap_ARID;
+output  [7:0] m_axi_mmap_ARLEN;
+output  [2:0] m_axi_mmap_ARSIZE;
+output  [1:0] m_axi_mmap_ARBURST;
+output  [1:0] m_axi_mmap_ARLOCK;
+output  [3:0] m_axi_mmap_ARCACHE;
+output  [2:0] m_axi_mmap_ARPROT;
+output  [3:0] m_axi_mmap_ARQOS;
+output  [3:0] m_axi_mmap_ARREGION;
+output  [C_M_AXI_MMAP_ARUSER_WIDTH - 1:0] m_axi_mmap_ARUSER;
+input   m_axi_mmap_RVALID;
+output   m_axi_mmap_RREADY;
+input  [C_M_AXI_MMAP_DATA_WIDTH - 1:0] m_axi_mmap_RDATA;
+input   m_axi_mmap_RLAST;
+input  [C_M_AXI_MMAP_ID_WIDTH - 1:0] m_axi_mmap_RID;
+input  [C_M_AXI_MMAP_RUSER_WIDTH - 1:0] m_axi_mmap_RUSER;
+input  [1:0] m_axi_mmap_RRESP;
+input   m_axi_mmap_BVALID;
+output   m_axi_mmap_BREADY;
+input  [1:0] m_axi_mmap_BRESP;
+input  [C_M_AXI_MMAP_ID_WIDTH - 1:0] m_axi_mmap_BID;
+input  [C_M_AXI_MMAP_BUSER_WIDTH - 1:0] m_axi_mmap_BUSER;
+input  [512:0] stream_s_dout;
+input   stream_s_empty_n;
+output   stream_s_read;
+input  [512:0] stream_peek_dout;
+input   stream_peek_empty_n;
+output   stream_peek_read;
+input  [63:0] mmap_offset;
+input  [63:0] n;
+
+reg ap_done;
+reg ap_idle;
+reg ap_ready;
+reg stream_s_read;
+
+ reg    ap_rst_n_inv;
+(* fsm_encoding = "none" *) reg   [7:0] ap_CS_fsm;
+wire    ap_CS_fsm_state1;
+reg    mmap_blk_n_AW;
+reg    mmap_blk_n_B;
+wire    ap_CS_fsm_state8;
+wire  signed [57:0] trunc_ln64_1_fu_103_p4;
+reg   [57:0] trunc_ln64_1_reg_134;
+wire    grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_ap_start;
+wire    grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_ap_done;
+wire    grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_ap_idle;
+wire    grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_ap_ready;
+wire    grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_stream_s_read;
+wire    grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_AWVALID;
+wire   [63:0] grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_AWADDR;
+wire   [0:0] grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_AWID;
+wire   [31:0] grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_AWLEN;
+wire   [2:0] grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_AWSIZE;
+wire   [1:0] grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_AWBURST;
+wire   [1:0] grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_AWLOCK;
+wire   [3:0] grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_AWCACHE;
+wire   [2:0] grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_AWPROT;
+wire   [3:0] grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_AWQOS;
+wire   [3:0] grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_AWREGION;
+wire   [0:0] grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_AWUSER;
+wire    grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_WVALID;
+wire   [511:0] grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_WDATA;
+wire   [63:0] grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_WSTRB;
+wire    grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_WLAST;
+wire   [0:0] grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_WID;
+wire   [0:0] grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_WUSER;
+wire    grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_ARVALID;
+wire   [63:0] grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_ARADDR;
+wire   [0:0] grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_ARID;
+wire   [31:0] grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_ARLEN;
+wire   [2:0] grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_ARSIZE;
+wire   [1:0] grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_ARBURST;
+wire   [1:0] grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_ARLOCK;
+wire   [3:0] grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_ARCACHE;
+wire   [2:0] grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_ARPROT;
+wire   [3:0] grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_ARQOS;
+wire   [3:0] grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_ARREGION;
+wire   [0:0] grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_ARUSER;
+wire    grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_RREADY;
+wire    grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_BREADY;
+reg    mmap_AWVALID;
+wire    mmap_AWREADY;
+reg   [63:0] mmap_AWADDR;
+reg   [31:0] mmap_AWLEN;
+reg    mmap_WVALID;
+wire    mmap_WREADY;
+wire    mmap_ARREADY;
+wire    mmap_RVALID;
+wire   [511:0] mmap_RDATA;
+wire   [8:0] mmap_RFIFONUM;
+wire    mmap_BVALID;
+reg    mmap_BREADY;
+reg    grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_ap_start_reg;
+reg   [7:0] ap_NS_fsm;
+wire    ap_NS_fsm_state2;
+wire    ap_CS_fsm_state2;
+wire    ap_CS_fsm_state3;
+wire  signed [63:0] sext_ln64_fu_113_p1;
+wire   [31:0] trunc_ln64_fu_124_p1;
+reg    ap_ST_fsm_state1_blk;
+wire    ap_ST_fsm_state2_blk;
+reg    ap_ST_fsm_state3_blk;
+wire    ap_ST_fsm_state4_blk;
+wire    ap_ST_fsm_state5_blk;
+wire    ap_ST_fsm_state6_blk;
+wire    ap_ST_fsm_state7_blk;
+reg    ap_ST_fsm_state8_blk;
+wire    ap_ce_reg;
+
+// power-on initialization
+initial begin
+#0 ap_CS_fsm = 8'd1;
+#0 grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_ap_start_reg = 1'b0;
+end
+
+Stream2Mmap_Stream2Mmap_Pipeline_VITIS_LOOP_64_1 grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93(
+    .ap_clk(ap_clk),
+    .ap_rst(ap_rst_n_inv),
+    .ap_start(grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_ap_start),
+    .ap_done(grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_ap_done),
+    .ap_idle(grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_ap_idle),
+    .ap_ready(grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_ap_ready),
+    .stream_s_dout(stream_s_dout),
+    .stream_s_empty_n(stream_s_empty_n),
+    .stream_s_read(grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_stream_s_read),
+    .m_axi_mmap_AWVALID(grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_AWVALID),
+    .m_axi_mmap_AWREADY(mmap_AWREADY),
+    .m_axi_mmap_AWADDR(grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_AWADDR),
+    .m_axi_mmap_AWID(grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_AWID),
+    .m_axi_mmap_AWLEN(grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_AWLEN),
+    .m_axi_mmap_AWSIZE(grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_AWSIZE),
+    .m_axi_mmap_AWBURST(grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_AWBURST),
+    .m_axi_mmap_AWLOCK(grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_AWLOCK),
+    .m_axi_mmap_AWCACHE(grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_AWCACHE),
+    .m_axi_mmap_AWPROT(grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_AWPROT),
+    .m_axi_mmap_AWQOS(grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_AWQOS),
+    .m_axi_mmap_AWREGION(grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_AWREGION),
+    .m_axi_mmap_AWUSER(grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_AWUSER),
+    .m_axi_mmap_WVALID(grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_WVALID),
+    .m_axi_mmap_WREADY(mmap_WREADY),
+    .m_axi_mmap_WDATA(grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_WDATA),
+    .m_axi_mmap_WSTRB(grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_WSTRB),
+    .m_axi_mmap_WLAST(grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_WLAST),
+    .m_axi_mmap_WID(grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_WID),
+    .m_axi_mmap_WUSER(grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_WUSER),
+    .m_axi_mmap_ARVALID(grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_ARVALID),
+    .m_axi_mmap_ARREADY(1'b0),
+    .m_axi_mmap_ARADDR(grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_ARADDR),
+    .m_axi_mmap_ARID(grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_ARID),
+    .m_axi_mmap_ARLEN(grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_ARLEN),
+    .m_axi_mmap_ARSIZE(grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_ARSIZE),
+    .m_axi_mmap_ARBURST(grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_ARBURST),
+    .m_axi_mmap_ARLOCK(grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_ARLOCK),
+    .m_axi_mmap_ARCACHE(grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_ARCACHE),
+    .m_axi_mmap_ARPROT(grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_ARPROT),
+    .m_axi_mmap_ARQOS(grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_ARQOS),
+    .m_axi_mmap_ARREGION(grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_ARREGION),
+    .m_axi_mmap_ARUSER(grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_ARUSER),
+    .m_axi_mmap_RVALID(1'b0),
+    .m_axi_mmap_RREADY(grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_RREADY),
+    .m_axi_mmap_RDATA(512'd0),
+    .m_axi_mmap_RLAST(1'b0),
+    .m_axi_mmap_RID(1'd0),
+    .m_axi_mmap_RFIFONUM(9'd0),
+    .m_axi_mmap_RUSER(1'd0),
+    .m_axi_mmap_RRESP(2'd0),
+    .m_axi_mmap_BVALID(mmap_BVALID),
+    .m_axi_mmap_BREADY(grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_BREADY),
+    .m_axi_mmap_BRESP(2'd0),
+    .m_axi_mmap_BID(1'd0),
+    .m_axi_mmap_BUSER(1'd0),
+    .sext_ln64(trunc_ln64_1_reg_134),
+    .n(n)
+);
+
+Stream2Mmap_mmap_m_axi #(
+    .CONSERVATIVE( 1 ),
+    .USER_MAXREQS( 5 ),
+    .MAX_READ_BURST_LENGTH( 16 ),
+    .MAX_WRITE_BURST_LENGTH( 16 ),
+    .C_M_AXI_ID_WIDTH( C_M_AXI_MMAP_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH( C_M_AXI_MMAP_ADDR_WIDTH ),
+    .C_M_AXI_DATA_WIDTH( C_M_AXI_MMAP_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH( C_M_AXI_MMAP_AWUSER_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH( C_M_AXI_MMAP_ARUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH( C_M_AXI_MMAP_WUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH( C_M_AXI_MMAP_RUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH( C_M_AXI_MMAP_BUSER_WIDTH ),
+    .C_USER_VALUE( C_M_AXI_MMAP_USER_VALUE ),
+    .C_PROT_VALUE( C_M_AXI_MMAP_PROT_VALUE ),
+    .C_CACHE_VALUE( C_M_AXI_MMAP_CACHE_VALUE ),
+    .USER_RFIFONUM_WIDTH( 9 ),
+    .USER_DW( 512 ),
+    .USER_AW( 64 ),
+    .NUM_READ_OUTSTANDING( 16 ),
+    .NUM_WRITE_OUTSTANDING( 16 ))
+mmap_m_axi_U(
+    .AWVALID(m_axi_mmap_AWVALID),
+    .AWREADY(m_axi_mmap_AWREADY),
+    .AWADDR(m_axi_mmap_AWADDR),
+    .AWID(m_axi_mmap_AWID),
+    .AWLEN(m_axi_mmap_AWLEN),
+    .AWSIZE(m_axi_mmap_AWSIZE),
+    .AWBURST(m_axi_mmap_AWBURST),
+    .AWLOCK(m_axi_mmap_AWLOCK),
+    .AWCACHE(m_axi_mmap_AWCACHE),
+    .AWPROT(m_axi_mmap_AWPROT),
+    .AWQOS(m_axi_mmap_AWQOS),
+    .AWREGION(m_axi_mmap_AWREGION),
+    .AWUSER(m_axi_mmap_AWUSER),
+    .WVALID(m_axi_mmap_WVALID),
+    .WREADY(m_axi_mmap_WREADY),
+    .WDATA(m_axi_mmap_WDATA),
+    .WSTRB(m_axi_mmap_WSTRB),
+    .WLAST(m_axi_mmap_WLAST),
+    .WID(m_axi_mmap_WID),
+    .WUSER(m_axi_mmap_WUSER),
+    .ARVALID(m_axi_mmap_ARVALID),
+    .ARREADY(m_axi_mmap_ARREADY),
+    .ARADDR(m_axi_mmap_ARADDR),
+    .ARID(m_axi_mmap_ARID),
+    .ARLEN(m_axi_mmap_ARLEN),
+    .ARSIZE(m_axi_mmap_ARSIZE),
+    .ARBURST(m_axi_mmap_ARBURST),
+    .ARLOCK(m_axi_mmap_ARLOCK),
+    .ARCACHE(m_axi_mmap_ARCACHE),
+    .ARPROT(m_axi_mmap_ARPROT),
+    .ARQOS(m_axi_mmap_ARQOS),
+    .ARREGION(m_axi_mmap_ARREGION),
+    .ARUSER(m_axi_mmap_ARUSER),
+    .RVALID(m_axi_mmap_RVALID),
+    .RREADY(m_axi_mmap_RREADY),
+    .RDATA(m_axi_mmap_RDATA),
+    .RLAST(m_axi_mmap_RLAST),
+    .RID(m_axi_mmap_RID),
+    .RUSER(m_axi_mmap_RUSER),
+    .RRESP(m_axi_mmap_RRESP),
+    .BVALID(m_axi_mmap_BVALID),
+    .BREADY(m_axi_mmap_BREADY),
+    .BRESP(m_axi_mmap_BRESP),
+    .BID(m_axi_mmap_BID),
+    .BUSER(m_axi_mmap_BUSER),
+    .ACLK(ap_clk),
+    .ARESET(ap_rst_n_inv),
+    .ACLK_EN(1'b1),
+    .I_ARVALID(1'b0),
+    .I_ARREADY(mmap_ARREADY),
+    .I_ARADDR(64'd0),
+    .I_ARLEN(32'd0),
+    .I_RVALID(mmap_RVALID),
+    .I_RREADY(1'b0),
+    .I_RDATA(mmap_RDATA),
+    .I_RFIFONUM(mmap_RFIFONUM),
+    .I_AWVALID(mmap_AWVALID),
+    .I_AWREADY(mmap_AWREADY),
+    .I_AWADDR(mmap_AWADDR),
+    .I_AWLEN(mmap_AWLEN),
+    .I_WVALID(mmap_WVALID),
+    .I_WREADY(mmap_WREADY),
+    .I_WDATA(grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_WDATA),
+    .I_WSTRB(grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_WSTRB),
+    .I_BVALID(mmap_BVALID),
+    .I_BREADY(mmap_BREADY)
+);
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_CS_fsm <= ap_ST_fsm_state1;
+    end else begin
+        ap_CS_fsm <= ap_NS_fsm;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_ap_start_reg <= 1'b0;
+    end else begin
+        if (((1'b1 == ap_NS_fsm_state2) & (1'b1 == ap_CS_fsm_state1))) begin
+            grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_ap_start_reg <= 1'b1;
+        end else if ((grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_ap_ready == 1'b1)) begin
+            grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_ap_start_reg <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state1)) begin
+        trunc_ln64_1_reg_134 <= {{mmap_offset[63:6]}};
+    end
+end
+
+always @ (*) begin
+    if (((mmap_AWREADY == 1'b0) | (ap_start == 1'b0))) begin
+        ap_ST_fsm_state1_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state1_blk = 1'b0;
+    end
+end
+
+assign ap_ST_fsm_state2_blk = 1'b0;
+
+always @ (*) begin
+    if ((grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_ap_done == 1'b0)) begin
+        ap_ST_fsm_state3_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state3_blk = 1'b0;
+    end
+end
+
+assign ap_ST_fsm_state4_blk = 1'b0;
+
+assign ap_ST_fsm_state5_blk = 1'b0;
+
+assign ap_ST_fsm_state6_blk = 1'b0;
+
+assign ap_ST_fsm_state7_blk = 1'b0;
+
+always @ (*) begin
+    if ((mmap_BVALID == 1'b0)) begin
+        ap_ST_fsm_state8_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state8_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((mmap_BVALID == 1'b1) & (1'b1 == ap_CS_fsm_state8))) begin
+        ap_done = 1'b1;
+    end else begin
+        ap_done = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin
+        ap_idle = 1'b1;
+    end else begin
+        ap_idle = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((mmap_BVALID == 1'b1) & (1'b1 == ap_CS_fsm_state8))) begin
+        ap_ready = 1'b1;
+    end else begin
+        ap_ready = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((~((mmap_AWREADY == 1'b0) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin
+        mmap_AWADDR = sext_ln64_fu_113_p1;
+    end else if (((1'b1 == ap_CS_fsm_state3) | (1'b1 == ap_CS_fsm_state2))) begin
+        mmap_AWADDR = grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_AWADDR;
+    end else begin
+        mmap_AWADDR = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((~((mmap_AWREADY == 1'b0) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin
+        mmap_AWLEN = trunc_ln64_fu_124_p1;
+    end else if (((1'b1 == ap_CS_fsm_state3) | (1'b1 == ap_CS_fsm_state2))) begin
+        mmap_AWLEN = grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_AWLEN;
+    end else begin
+        mmap_AWLEN = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((~((mmap_AWREADY == 1'b0) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin
+        mmap_AWVALID = 1'b1;
+    end else if (((1'b1 == ap_CS_fsm_state3) | (1'b1 == ap_CS_fsm_state2))) begin
+        mmap_AWVALID = grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_AWVALID;
+    end else begin
+        mmap_AWVALID = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((mmap_BVALID == 1'b1) & (1'b1 == ap_CS_fsm_state8))) begin
+        mmap_BREADY = 1'b1;
+    end else if (((1'b1 == ap_CS_fsm_state3) | (1'b1 == ap_CS_fsm_state2))) begin
+        mmap_BREADY = grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_BREADY;
+    end else begin
+        mmap_BREADY = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state3) | (1'b1 == ap_CS_fsm_state2))) begin
+        mmap_WVALID = grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_m_axi_mmap_WVALID;
+    end else begin
+        mmap_WVALID = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
+        mmap_blk_n_AW = m_axi_mmap_AWREADY;
+    end else begin
+        mmap_blk_n_AW = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state8)) begin
+        mmap_blk_n_B = m_axi_mmap_BVALID;
+    end else begin
+        mmap_blk_n_B = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state3)) begin
+        stream_s_read = grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_stream_s_read;
+    end else begin
+        stream_s_read = 1'b0;
+    end
+end
+
+always @ (*) begin
+    case (ap_CS_fsm)
+        ap_ST_fsm_state1 : begin
+            if ((~((mmap_AWREADY == 1'b0) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end
+        end
+        ap_ST_fsm_state2 : begin
+            ap_NS_fsm = ap_ST_fsm_state3;
+        end
+        ap_ST_fsm_state3 : begin
+            if (((1'b1 == ap_CS_fsm_state3) & (grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_ap_done == 1'b1))) begin
+                ap_NS_fsm = ap_ST_fsm_state4;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state3;
+            end
+        end
+        ap_ST_fsm_state4 : begin
+            ap_NS_fsm = ap_ST_fsm_state5;
+        end
+        ap_ST_fsm_state5 : begin
+            ap_NS_fsm = ap_ST_fsm_state6;
+        end
+        ap_ST_fsm_state6 : begin
+            ap_NS_fsm = ap_ST_fsm_state7;
+        end
+        ap_ST_fsm_state7 : begin
+            ap_NS_fsm = ap_ST_fsm_state8;
+        end
+        ap_ST_fsm_state8 : begin
+            if (((mmap_BVALID == 1'b1) & (1'b1 == ap_CS_fsm_state8))) begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state8;
+            end
+        end
+        default : begin
+            ap_NS_fsm = 'bx;
+        end
+    endcase
+end
+
+assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
+
+assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
+
+assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2];
+
+assign ap_CS_fsm_state8 = ap_CS_fsm[32'd7];
+
+assign ap_NS_fsm_state2 = ap_NS_fsm[32'd1];
+
+always @ (*) begin
+    ap_rst_n_inv = ~ap_rst_n;
+end
+
+assign grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_ap_start = grp_Stream2Mmap_Pipeline_VITIS_LOOP_64_1_fu_93_ap_start_reg;
+
+assign sext_ln64_fu_113_p1 = trunc_ln64_1_fu_103_p4;
+
+assign stream_peek_read = 1'b0;
+
+assign trunc_ln64_1_fu_103_p4 = {{mmap_offset[63:6]}};
+
+assign trunc_ln64_fu_124_p1 = n[31:0];
+
+endmodule //Stream2Mmap
diff --git a/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/Stream2Mmap_Stream2Mmap_Pipeline_VITIS_LOOP_64_1.v b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/Stream2Mmap_Stream2Mmap_Pipeline_VITIS_LOOP_64_1.v
new file mode 100644
index 00000000..e6ec5e7e
--- /dev/null
+++ b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/Stream2Mmap_Stream2Mmap_Pipeline_VITIS_LOOP_64_1.v
@@ -0,0 +1,463 @@
+// ==============================================================
+// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit)
+// Version: 2022.2
+// Copyright (C) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+//
+// ===========================================================
+
+`timescale 1 ns / 1 ps
+
+module Stream2Mmap_Stream2Mmap_Pipeline_VITIS_LOOP_64_1 (
+        ap_clk,
+        ap_rst,
+        ap_start,
+        ap_done,
+        ap_idle,
+        ap_ready,
+        stream_s_dout,
+        stream_s_empty_n,
+        stream_s_read,
+        m_axi_mmap_AWVALID,
+        m_axi_mmap_AWREADY,
+        m_axi_mmap_AWADDR,
+        m_axi_mmap_AWID,
+        m_axi_mmap_AWLEN,
+        m_axi_mmap_AWSIZE,
+        m_axi_mmap_AWBURST,
+        m_axi_mmap_AWLOCK,
+        m_axi_mmap_AWCACHE,
+        m_axi_mmap_AWPROT,
+        m_axi_mmap_AWQOS,
+        m_axi_mmap_AWREGION,
+        m_axi_mmap_AWUSER,
+        m_axi_mmap_WVALID,
+        m_axi_mmap_WREADY,
+        m_axi_mmap_WDATA,
+        m_axi_mmap_WSTRB,
+        m_axi_mmap_WLAST,
+        m_axi_mmap_WID,
+        m_axi_mmap_WUSER,
+        m_axi_mmap_ARVALID,
+        m_axi_mmap_ARREADY,
+        m_axi_mmap_ARADDR,
+        m_axi_mmap_ARID,
+        m_axi_mmap_ARLEN,
+        m_axi_mmap_ARSIZE,
+        m_axi_mmap_ARBURST,
+        m_axi_mmap_ARLOCK,
+        m_axi_mmap_ARCACHE,
+        m_axi_mmap_ARPROT,
+        m_axi_mmap_ARQOS,
+        m_axi_mmap_ARREGION,
+        m_axi_mmap_ARUSER,
+        m_axi_mmap_RVALID,
+        m_axi_mmap_RREADY,
+        m_axi_mmap_RDATA,
+        m_axi_mmap_RLAST,
+        m_axi_mmap_RID,
+        m_axi_mmap_RFIFONUM,
+        m_axi_mmap_RUSER,
+        m_axi_mmap_RRESP,
+        m_axi_mmap_BVALID,
+        m_axi_mmap_BREADY,
+        m_axi_mmap_BRESP,
+        m_axi_mmap_BID,
+        m_axi_mmap_BUSER,
+        sext_ln64,
+        n
+);
+
+parameter    ap_ST_fsm_pp0_stage0 = 1'd1;
+
+input   ap_clk;
+input   ap_rst;
+input   ap_start;
+output   ap_done;
+output   ap_idle;
+output   ap_ready;
+input  [512:0] stream_s_dout;
+input   stream_s_empty_n;
+output   stream_s_read;
+output   m_axi_mmap_AWVALID;
+input   m_axi_mmap_AWREADY;
+output  [63:0] m_axi_mmap_AWADDR;
+output  [0:0] m_axi_mmap_AWID;
+output  [31:0] m_axi_mmap_AWLEN;
+output  [2:0] m_axi_mmap_AWSIZE;
+output  [1:0] m_axi_mmap_AWBURST;
+output  [1:0] m_axi_mmap_AWLOCK;
+output  [3:0] m_axi_mmap_AWCACHE;
+output  [2:0] m_axi_mmap_AWPROT;
+output  [3:0] m_axi_mmap_AWQOS;
+output  [3:0] m_axi_mmap_AWREGION;
+output  [0:0] m_axi_mmap_AWUSER;
+output   m_axi_mmap_WVALID;
+input   m_axi_mmap_WREADY;
+output  [511:0] m_axi_mmap_WDATA;
+output  [63:0] m_axi_mmap_WSTRB;
+output   m_axi_mmap_WLAST;
+output  [0:0] m_axi_mmap_WID;
+output  [0:0] m_axi_mmap_WUSER;
+output   m_axi_mmap_ARVALID;
+input   m_axi_mmap_ARREADY;
+output  [63:0] m_axi_mmap_ARADDR;
+output  [0:0] m_axi_mmap_ARID;
+output  [31:0] m_axi_mmap_ARLEN;
+output  [2:0] m_axi_mmap_ARSIZE;
+output  [1:0] m_axi_mmap_ARBURST;
+output  [1:0] m_axi_mmap_ARLOCK;
+output  [3:0] m_axi_mmap_ARCACHE;
+output  [2:0] m_axi_mmap_ARPROT;
+output  [3:0] m_axi_mmap_ARQOS;
+output  [3:0] m_axi_mmap_ARREGION;
+output  [0:0] m_axi_mmap_ARUSER;
+input   m_axi_mmap_RVALID;
+output   m_axi_mmap_RREADY;
+input  [511:0] m_axi_mmap_RDATA;
+input   m_axi_mmap_RLAST;
+input  [0:0] m_axi_mmap_RID;
+input  [8:0] m_axi_mmap_RFIFONUM;
+input  [0:0] m_axi_mmap_RUSER;
+input  [1:0] m_axi_mmap_RRESP;
+input   m_axi_mmap_BVALID;
+output   m_axi_mmap_BREADY;
+input  [1:0] m_axi_mmap_BRESP;
+input  [0:0] m_axi_mmap_BID;
+input  [0:0] m_axi_mmap_BUSER;
+input  [57:0] sext_ln64;
+input  [63:0] n;
+
+reg ap_idle;
+reg stream_s_read;
+reg m_axi_mmap_WVALID;
+
+(* fsm_encoding = "none" *) reg   [0:0] ap_CS_fsm;
+wire    ap_CS_fsm_pp0_stage0;
+wire    ap_enable_reg_pp0_iter0;
+reg    ap_enable_reg_pp0_iter1;
+reg    ap_enable_reg_pp0_iter2;
+reg    ap_enable_reg_pp0_iter3;
+reg    ap_idle_pp0;
+wire    ap_block_state1_pp0_stage0_iter0;
+wire    ap_block_state2_pp0_stage0_iter1;
+reg   [0:0] icmp_ln64_reg_136;
+reg    ap_block_state3_pp0_stage0_iter2;
+wire    ap_block_state4_pp0_stage0_iter3;
+reg    ap_block_pp0_stage0_subdone;
+wire   [0:0] icmp_ln64_fu_94_p2;
+reg    ap_condition_exit_pp0_iter1_stage0;
+wire    ap_loop_exit_ready;
+reg    ap_ready_int;
+reg    mmap_blk_n_W;
+wire    ap_block_pp0_stage0;
+reg    stream_s_blk_n;
+reg    ap_block_pp0_stage0_11001;
+wire   [511:0] trunc_ln85_fu_115_p1;
+reg   [511:0] trunc_ln85_reg_145;
+reg    ap_condition_exit_pp0_iter2_stage0;
+reg    ap_block_pp0_stage0_01001;
+reg   [63:0] i_fu_52;
+wire   [63:0] i_2_fu_99_p2;
+wire    ap_loop_init;
+reg    ap_done_reg;
+wire    ap_continue_int;
+reg    ap_done_int;
+reg    ap_loop_exit_ready_pp0_iter2_reg;
+reg   [0:0] ap_NS_fsm;
+wire    ap_enable_pp0;
+wire    ap_start_int;
+wire    ap_ce_reg;
+
+// power-on initialization
+initial begin
+#0 ap_CS_fsm = 1'd1;
+#0 ap_enable_reg_pp0_iter1 = 1'b0;
+#0 ap_enable_reg_pp0_iter2 = 1'b0;
+#0 ap_enable_reg_pp0_iter3 = 1'b0;
+#0 ap_done_reg = 1'b0;
+end
+
+Stream2Mmap_flow_control_loop_pipe_sequential_init flow_control_loop_pipe_sequential_init_U(
+    .ap_clk(ap_clk),
+    .ap_rst(ap_rst),
+    .ap_start(ap_start),
+    .ap_ready(ap_ready),
+    .ap_done(ap_done),
+    .ap_start_int(ap_start_int),
+    .ap_loop_init(ap_loop_init),
+    .ap_ready_int(ap_ready_int),
+    .ap_loop_exit_ready(ap_condition_exit_pp0_iter1_stage0),
+    .ap_loop_exit_done(ap_done_int),
+    .ap_continue_int(ap_continue_int),
+    .ap_done_int(ap_done_int)
+);
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_CS_fsm <= ap_ST_fsm_pp0_stage0;
+    end else begin
+        ap_CS_fsm <= ap_NS_fsm;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_done_reg <= 1'b0;
+    end else begin
+        if ((ap_continue_int == 1'b1)) begin
+            ap_done_reg <= 1'b0;
+        end else if (((ap_loop_exit_ready_pp0_iter2_reg == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone))) begin
+            ap_done_reg <= 1'b1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_enable_reg_pp0_iter1 <= 1'b0;
+    end else begin
+        if ((1'b1 == ap_condition_exit_pp0_iter1_stage0)) begin
+            ap_enable_reg_pp0_iter1 <= 1'b0;
+        end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_subdone))) begin
+            ap_enable_reg_pp0_iter1 <= ap_start_int;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_enable_reg_pp0_iter2 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
+            ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_enable_reg_pp0_iter3 <= 1'b0;
+    end else begin
+        if ((1'b1 == ap_condition_exit_pp0_iter2_stage0)) begin
+            ap_enable_reg_pp0_iter3 <= 1'b0;
+        end else if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
+            ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin
+        if ((ap_loop_init == 1'b1)) begin
+            i_fu_52 <= 64'd0;
+        end else if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln64_fu_94_p2 == 1'd0))) begin
+            i_fu_52 <= i_2_fu_99_p2;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin
+        ap_loop_exit_ready_pp0_iter2_reg <= ap_loop_exit_ready;
+        icmp_ln64_reg_136 <= icmp_ln64_fu_94_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((icmp_ln64_reg_136 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin
+        trunc_ln85_reg_145 <= trunc_ln85_fu_115_p1;
+    end
+end
+
+always @ (*) begin
+    if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln64_fu_94_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone))) begin
+        ap_condition_exit_pp0_iter1_stage0 = 1'b1;
+    end else begin
+        ap_condition_exit_pp0_iter1_stage0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((icmp_ln64_reg_136 == 1'd1) & (ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone))) begin
+        ap_condition_exit_pp0_iter2_stage0 = 1'b1;
+    end else begin
+        ap_condition_exit_pp0_iter2_stage0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_loop_exit_ready_pp0_iter2_reg == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone))) begin
+        ap_done_int = 1'b1;
+    end else begin
+        ap_done_int = ap_done_reg;
+    end
+end
+
+always @ (*) begin
+    if (((ap_idle_pp0 == 1'b1) & (ap_start_int == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        ap_idle = 1'b1;
+    end else begin
+        ap_idle = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin
+        ap_idle_pp0 = 1'b1;
+    end else begin
+        ap_idle_pp0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_subdone))) begin
+        ap_ready_int = 1'b1;
+    end else begin
+        ap_ready_int = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin
+        m_axi_mmap_WVALID = 1'b1;
+    end else begin
+        m_axi_mmap_WVALID = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0))) begin
+        mmap_blk_n_W = m_axi_mmap_WREADY;
+    end else begin
+        mmap_blk_n_W = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((icmp_ln64_reg_136 == 1'd0) & (ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage0))) begin
+        stream_s_blk_n = stream_s_empty_n;
+    end else begin
+        stream_s_blk_n = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((icmp_ln64_reg_136 == 1'd0) & (ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin
+        stream_s_read = 1'b1;
+    end else begin
+        stream_s_read = 1'b0;
+    end
+end
+
+always @ (*) begin
+    case (ap_CS_fsm)
+        ap_ST_fsm_pp0_stage0 : begin
+            ap_NS_fsm = ap_ST_fsm_pp0_stage0;
+        end
+        default : begin
+            ap_NS_fsm = 'bx;
+        end
+    endcase
+end
+
+assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd0];
+
+assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_block_pp0_stage0_01001 = ((icmp_ln64_reg_136 == 1'd0) & (stream_s_empty_n == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b1));
+end
+
+always @ (*) begin
+    ap_block_pp0_stage0_11001 = (((icmp_ln64_reg_136 == 1'd0) & (stream_s_empty_n == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((m_axi_mmap_WREADY == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b1)));
+end
+
+always @ (*) begin
+    ap_block_pp0_stage0_subdone = (((icmp_ln64_reg_136 == 1'd0) & (stream_s_empty_n == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((m_axi_mmap_WREADY == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b1)));
+end
+
+assign ap_block_state1_pp0_stage0_iter0 = ~(1'b1 == 1'b1);
+
+assign ap_block_state2_pp0_stage0_iter1 = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_block_state3_pp0_stage0_iter2 = ((icmp_ln64_reg_136 == 1'd0) & (stream_s_empty_n == 1'b0));
+end
+
+assign ap_block_state4_pp0_stage0_iter3 = ~(1'b1 == 1'b1);
+
+assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1);
+
+assign ap_enable_reg_pp0_iter0 = ap_start_int;
+
+assign ap_loop_exit_ready = ap_condition_exit_pp0_iter1_stage0;
+
+assign i_2_fu_99_p2 = (i_fu_52 + 64'd1);
+
+assign icmp_ln64_fu_94_p2 = ((i_fu_52 == n) ? 1'b1 : 1'b0);
+
+assign m_axi_mmap_ARADDR = 64'd0;
+
+assign m_axi_mmap_ARBURST = 2'd0;
+
+assign m_axi_mmap_ARCACHE = 4'd0;
+
+assign m_axi_mmap_ARID = 1'd0;
+
+assign m_axi_mmap_ARLEN = 32'd0;
+
+assign m_axi_mmap_ARLOCK = 2'd0;
+
+assign m_axi_mmap_ARPROT = 3'd0;
+
+assign m_axi_mmap_ARQOS = 4'd0;
+
+assign m_axi_mmap_ARREGION = 4'd0;
+
+assign m_axi_mmap_ARSIZE = 3'd0;
+
+assign m_axi_mmap_ARUSER = 1'd0;
+
+assign m_axi_mmap_ARVALID = 1'b0;
+
+assign m_axi_mmap_AWADDR = 64'd0;
+
+assign m_axi_mmap_AWBURST = 2'd0;
+
+assign m_axi_mmap_AWCACHE = 4'd0;
+
+assign m_axi_mmap_AWID = 1'd0;
+
+assign m_axi_mmap_AWLEN = 32'd0;
+
+assign m_axi_mmap_AWLOCK = 2'd0;
+
+assign m_axi_mmap_AWPROT = 3'd0;
+
+assign m_axi_mmap_AWQOS = 4'd0;
+
+assign m_axi_mmap_AWREGION = 4'd0;
+
+assign m_axi_mmap_AWSIZE = 3'd0;
+
+assign m_axi_mmap_AWUSER = 1'd0;
+
+assign m_axi_mmap_AWVALID = 1'b0;
+
+assign m_axi_mmap_BREADY = 1'b0;
+
+assign m_axi_mmap_RREADY = 1'b0;
+
+assign m_axi_mmap_WDATA = trunc_ln85_reg_145;
+
+assign m_axi_mmap_WID = 1'd0;
+
+assign m_axi_mmap_WLAST = 1'b0;
+
+assign m_axi_mmap_WSTRB = 64'd18446744073709551615;
+
+assign m_axi_mmap_WUSER = 1'd0;
+
+assign trunc_ln85_fu_115_p1 = stream_s_dout[511:0];
+
+endmodule //Stream2Mmap_Stream2Mmap_Pipeline_VITIS_LOOP_64_1
diff --git a/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/Stream2Mmap_flow_control_loop_pipe_sequential_init.v b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/Stream2Mmap_flow_control_loop_pipe_sequential_init.v
new file mode 100644
index 00000000..bf8b1736
--- /dev/null
+++ b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/Stream2Mmap_flow_control_loop_pipe_sequential_init.v
@@ -0,0 +1,104 @@
+// ==============================================================
+// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit)
+// Tool Version Limit: 2019.12
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+
+`timescale 1 ns / 1 ps
+
+module Stream2Mmap_flow_control_loop_pipe_sequential_init(
+        ap_clk,
+        ap_rst,
+        ap_start,
+        ap_ready,
+        ap_done,
+        ap_start_int,
+        ap_ready_int,
+        ap_done_int,
+        ap_continue_int,
+        ap_loop_init,
+        ap_loop_exit_ready,
+        ap_loop_exit_done
+);
+
+input   ap_clk;
+input   ap_rst;
+
+//Block level handshake with outside loop
+input   ap_start;
+output  ap_ready;
+output  ap_done;
+
+//Block level handshake with loop body
+output  ap_start_int;
+input   ap_ready_int;
+input   ap_done_int;
+output  ap_continue_int;
+
+//Init live in variables
+output   ap_loop_init;
+wire     ap_loop_init;
+reg ap_loop_init_int;
+reg ap_done;
+reg ap_done_cache;
+
+//Exit signal from loop body
+input   ap_loop_exit_ready;
+input   ap_loop_exit_done;
+
+// power-on initialization
+initial begin
+#0 ap_loop_init_int = 1'b1;
+#0 ap_done_cache = 1'b0;
+end
+
+assign ap_start_int = ap_start;
+
+assign ap_continue_int = 1'b1;
+
+assign ap_ready = ap_loop_exit_ready;
+
+//ap_loop_init is valid for the first II
+//of the first loop run so as to enable
+//the init block ops which are pushed into
+//the first state of the pipeline region
+always @ (posedge ap_clk)
+begin
+    if (ap_rst == 1'b1) begin
+        ap_loop_init_int <= 1'b1;
+    end else if(ap_loop_exit_done == 1'b1) begin
+        ap_loop_init_int <= 1'b1;
+    end else if(ap_ready_int == 1'b1) begin
+        ap_loop_init_int <= 1'b0;
+    end
+end
+
+assign ap_loop_init = ap_loop_init_int & ap_start;
+
+// if no ap_continue port and current module is not top module,
+// ap_done handshakes with ap_start. Internally, flow control sends out
+// ap_conintue_int = 1'b1 so the ap_done_int is asserted high for 1 clock cycle.
+// ap_done_cache is used to record ap_done_int, and de-assert if ap_start_int
+// is asserted, so DUT can start the next run
+always @(posedge ap_clk)
+begin
+    if (ap_rst == 1'b1) begin
+        ap_done_cache <= 1'b0;
+    end else if (ap_done_int == 1'b1) begin
+        ap_done_cache <= 1'b1;
+    end else if (ap_start_int == 1'b1) begin
+        ap_done_cache <= 1'b0;
+    end
+end
+
+// if no ap_continue port and current module is not top module, ap_done handshakes with ap_start
+always @(*)
+begin
+    if ((ap_done_int == 1'b1) || ((ap_done_cache == 1'b1) && (ap_start_int == 1'b0))) begin
+        ap_done = 1'b1;
+    end else begin
+        ap_done = 1'b0;
+    end
+end
+
+endmodule
diff --git a/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/Stream2Mmap_mmap_m_axi.v b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/Stream2Mmap_mmap_m_axi.v
new file mode 100644
index 00000000..1ee3c3ed
--- /dev/null
+++ b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/Stream2Mmap_mmap_m_axi.v
@@ -0,0 +1,2823 @@
+// ==============================================================
+// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit)
+// Version: 2022.2
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+`timescale 1ns/1ps
+`default_nettype none
+
+module Stream2Mmap_mmap_m_axi
+#(parameter
+    CONSERVATIVE            = 0,
+    NUM_READ_OUTSTANDING    = 2,
+    NUM_WRITE_OUTSTANDING   = 2,
+    MAX_READ_BURST_LENGTH   = 16,
+    MAX_WRITE_BURST_LENGTH  = 16,
+    C_M_AXI_ID_WIDTH        = 1,
+    C_M_AXI_ADDR_WIDTH      = 32,
+    C_M_AXI_DATA_WIDTH      = 32, // power of 2 & range: 2 to 1024
+    C_M_AXI_AWUSER_WIDTH    = 1,
+    C_M_AXI_ARUSER_WIDTH    = 1,
+    C_M_AXI_WUSER_WIDTH     = 1,
+    C_M_AXI_RUSER_WIDTH     = 1,
+    C_M_AXI_BUSER_WIDTH     = 1,
+    C_TARGET_ADDR           = 32'h00000000,
+    C_USER_VALUE            = 1'b0,
+    C_PROT_VALUE            = 3'b000,
+    C_CACHE_VALUE           = 4'b0011,
+    USER_DW                 = 32, // multiple of 8
+    USER_AW                 = 32,
+    USER_MAXREQS            = 16,
+    USER_RFIFONUM_WIDTH     = 6,
+    MAXI_BUFFER_IMPL        = "block"
+)(
+
+    // system signal
+    input  wire                               ACLK,
+    input  wire                               ARESET,
+    input  wire                               ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                         AWLEN,
+    output wire [2:0]                         AWSIZE,
+    output wire [1:0]                         AWBURST,
+    output wire [1:0]                         AWLOCK,
+    output wire [3:0]                         AWCACHE,
+    output wire [2:0]                         AWPROT,
+    output wire [3:0]                         AWQOS,
+    output wire [3:0]                         AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                               AWVALID,
+    input  wire                               AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                               WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                               WVALID,
+    input  wire                               WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                         BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                               BVALID,
+    output wire                               BREADY,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                         ARLEN,
+    output wire [2:0]                         ARSIZE,
+    output wire [1:0]                         ARBURST,
+    output wire [1:0]                         ARLOCK,
+    output wire [3:0]                         ARCACHE,
+    output wire [2:0]                         ARPROT,
+    output wire [3:0]                         ARQOS,
+    output wire [3:0]                         ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                               ARVALID,
+    input  wire                               ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                         RRESP,
+    input  wire                               RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                               RVALID,
+    output wire                               RREADY,
+
+    // internal bus ports
+    // write address
+    input  wire [USER_AW-1:0]                 I_AWADDR,
+    input  wire [31:0]                        I_AWLEN,
+    input  wire                               I_AWVALID,
+    output wire                               I_AWREADY,
+    // write data
+    input  wire [USER_DW-1:0]                 I_WDATA,
+    input  wire [USER_DW/8-1:0]               I_WSTRB,
+    input  wire                               I_WVALID,
+    output wire                               I_WREADY,
+    // write response
+    output wire                               I_BVALID,
+    input  wire                               I_BREADY,
+    // read address
+    input  wire [USER_AW-1:0]                 I_ARADDR,
+    input  wire [31:0]                        I_ARLEN,
+    input  wire                               I_ARVALID,
+    output wire                               I_ARREADY,
+    // read data
+    output wire [USER_DW-1:0]                 I_RDATA,
+    output wire                               I_RVALID,
+    input  wire                               I_RREADY,
+    output wire [USER_RFIFONUM_WIDTH-1:0]     I_RFIFONUM);
+//------------------------Local signal-------------------
+
+    wire [C_M_AXI_ADDR_WIDTH-1:0]   AWADDR_Dummy;
+    wire [31:0]                     AWLEN_Dummy;
+    wire                            AWVALID_Dummy;
+    wire                            AWREADY_Dummy;
+    wire [C_M_AXI_DATA_WIDTH-1:0]   WDATA_Dummy;
+    wire [C_M_AXI_DATA_WIDTH/8-1:0] WSTRB_Dummy;
+    wire                            WVALID_Dummy;
+    wire                            WREADY_Dummy;
+    wire                            BVALID_Dummy;
+    wire                            BREADY_Dummy;
+    wire [C_M_AXI_ADDR_WIDTH-1:0]   ARADDR_Dummy;
+    wire [31:0]                     ARLEN_Dummy;
+    wire                            ARVALID_Dummy;
+    wire                            ARREADY_Dummy;
+    wire [C_M_AXI_DATA_WIDTH-1:0]   RDATA_Dummy;
+    wire [1:0]                      RLAST_Dummy;
+    wire                            RVALID_Dummy;
+    wire                            RREADY_Dummy;
+    wire                            RBURST_READY_Dummy;
+
+//------------------------Instantiation------------------
+    // Stream2Mmap_mmap_m_axi_store
+    Stream2Mmap_mmap_m_axi_store #(
+        .C_TARGET_ADDR           ( C_TARGET_ADDR ),
+        .NUM_WRITE_OUTSTANDING   ( NUM_WRITE_OUTSTANDING ),
+        .MAX_WRITE_BURST_LENGTH  ( MAX_WRITE_BURST_LENGTH ),
+        .BUS_ADDR_WIDTH          ( C_M_AXI_ADDR_WIDTH ),
+        .BUS_DATA_WIDTH          ( C_M_AXI_DATA_WIDTH ),
+        .USER_DW                 ( USER_DW ),
+        .USER_AW                 ( USER_AW ),
+        .USER_MAXREQS            ( USER_MAXREQS ),
+        .BUFFER_IMPL             ( MAXI_BUFFER_IMPL )
+    ) store_unit (
+        .ACLK                    ( ACLK ),
+        .ARESET                  ( ARESET ),
+        .ACLK_EN                 ( ACLK_EN ),
+        .out_AXI_AWADDR          ( AWADDR_Dummy ),
+        .out_AXI_AWLEN           ( AWLEN_Dummy ),
+        .out_AXI_AWVALID         ( AWVALID_Dummy ),
+        .in_AXI_AWREADY          ( AWREADY_Dummy ),
+        .out_AXI_WDATA           ( WDATA_Dummy ),
+        .out_AXI_WSTRB           ( WSTRB_Dummy ),
+        .out_AXI_WVALID          ( WVALID_Dummy ),
+        .in_AXI_WREADY           ( WREADY_Dummy ),
+        .in_AXI_BVALID           ( BVALID_Dummy ),
+        .out_AXI_BREADY          ( BREADY_Dummy ),
+        .in_HLS_AWADDR           ( I_AWADDR ),
+        .in_HLS_AWLEN            ( I_AWLEN ),
+        .in_HLS_AWVALID          ( I_AWVALID ),
+        .out_HLS_AWREADY         ( I_AWREADY ),
+        .in_HLS_WDATA            ( I_WDATA ),
+        .in_HLS_WSTRB            ( I_WSTRB ),
+        .in_HLS_WVALID           ( I_WVALID ),
+        .out_HLS_WREADY          ( I_WREADY ),
+        .out_HLS_BVALID          ( I_BVALID ),
+        .in_HLS_BREADY           ( I_BREADY ));
+
+    // Stream2Mmap_mmap_m_axi_load
+    Stream2Mmap_mmap_m_axi_load #(
+        .C_TARGET_ADDR           ( C_TARGET_ADDR ),
+        .NUM_READ_OUTSTANDING    ( NUM_READ_OUTSTANDING ),
+        .MAX_READ_BURST_LENGTH   ( MAX_READ_BURST_LENGTH ),
+        .BUS_ADDR_WIDTH          ( C_M_AXI_ADDR_WIDTH ),
+        .BUS_DATA_WIDTH          ( C_M_AXI_DATA_WIDTH ),
+        .USER_DW                 ( USER_DW ),
+        .USER_AW                 ( USER_AW ),
+        .USER_MAXREQS            ( USER_MAXREQS ),
+        .USER_RFIFONUM_WIDTH     ( USER_RFIFONUM_WIDTH ),
+        .BUFFER_IMPL             ( MAXI_BUFFER_IMPL )
+    ) load_unit (
+        .ACLK                    ( ACLK ),
+        .ARESET                  ( ARESET ),
+        .ACLK_EN                 ( ACLK_EN ),
+        .out_AXI_ARADDR          ( ARADDR_Dummy ),
+        .out_AXI_ARLEN           ( ARLEN_Dummy ),
+        .out_AXI_ARVALID         ( ARVALID_Dummy ),
+        .in_AXI_ARREADY          ( ARREADY_Dummy ),
+        .in_AXI_RDATA            ( RDATA_Dummy ),
+        .in_AXI_RLAST            ( RLAST_Dummy ),
+        .in_AXI_RVALID           ( RVALID_Dummy ),
+        .out_AXI_RREADY          ( RREADY_Dummy ),
+        .out_AXI_RBURST_READY    ( RBURST_READY_Dummy),
+        .in_HLS_ARADDR           ( I_ARADDR ),
+        .in_HLS_ARLEN            ( I_ARLEN ),
+        .in_HLS_ARVALID          ( I_ARVALID ),
+        .out_HLS_ARREADY         ( I_ARREADY ),
+        .out_HLS_RDATA           ( I_RDATA ),
+        .out_HLS_RVALID          ( I_RVALID ),
+        .in_HLS_RREADY           ( I_RREADY ),
+        .out_HLS_RFIFONUM        ( I_RFIFONUM ));
+
+    // Stream2Mmap_mmap_m_axi_write
+    Stream2Mmap_mmap_m_axi_write #(
+        .CONSERVATIVE            ( CONSERVATIVE),
+        .C_M_AXI_ID_WIDTH        ( C_M_AXI_ID_WIDTH ),
+        .C_M_AXI_AWUSER_WIDTH    ( C_M_AXI_AWUSER_WIDTH ),
+        .C_M_AXI_WUSER_WIDTH     ( C_M_AXI_WUSER_WIDTH ),
+        .C_M_AXI_BUSER_WIDTH     ( C_M_AXI_BUSER_WIDTH ),
+        .C_USER_VALUE            ( C_USER_VALUE ),
+        .C_PROT_VALUE            ( C_PROT_VALUE ),
+        .C_CACHE_VALUE           ( C_CACHE_VALUE ),
+        .BUS_ADDR_WIDTH          ( C_M_AXI_ADDR_WIDTH ),
+        .BUS_DATA_WIDTH          ( C_M_AXI_DATA_WIDTH ),
+        .NUM_WRITE_OUTSTANDING   ( NUM_WRITE_OUTSTANDING ),
+        .MAX_WRITE_BURST_LENGTH  ( MAX_WRITE_BURST_LENGTH )
+    ) bus_write (
+        .ACLK                    ( ACLK ),
+        .ARESET                  ( ARESET ),
+        .ACLK_EN                 ( ACLK_EN ),
+        .out_BUS_AWID            ( AWID ),
+        .out_BUS_AWSIZE          ( AWSIZE ),
+        .out_BUS_AWBURST         ( AWBURST ),
+        .out_BUS_AWLOCK          ( AWLOCK ),
+        .out_BUS_AWCACHE         ( AWCACHE ),
+        .out_BUS_AWPROT          ( AWPROT ),
+        .out_BUS_AWQOS           ( AWQOS ),
+        .out_BUS_AWREGION        ( AWREGION ),
+        .out_BUS_AWUSER          ( AWUSER ),
+        .out_BUS_AWADDR          ( AWADDR ),
+        .out_BUS_AWLEN           ( AWLEN ),
+
+
+        .out_BUS_AWVALID         ( AWVALID ),
+        .in_BUS_AWREADY          ( AWREADY ),
+        .out_BUS_WID             ( WID),
+        .out_BUS_WUSER           ( WUSER),
+        .out_BUS_WDATA           ( WDATA ),
+        .out_BUS_WSTRB           ( WSTRB ),
+        .out_BUS_WLAST           ( WLAST ),
+
+
+        .out_BUS_WVALID          ( WVALID ),
+        .in_BUS_WREADY           ( WREADY ),
+        .in_BUS_BID              ( BID ),
+        .in_BUS_BRESP            ( BRESP ),
+        .in_BUS_BUSER            ( BUSER ),
+        .in_BUS_BVALID           ( BVALID ),
+
+
+        .out_BUS_BREADY          ( BREADY ),
+        .in_HLS_AWVALID          ( AWVALID_Dummy ),
+        .out_HLS_AWREADY         ( AWREADY_Dummy ),
+        .in_HLS_AWADDR           ( AWADDR_Dummy ),
+        .in_HLS_AWLEN            ( AWLEN_Dummy ),
+        .in_HLS_WVALID           ( WVALID_Dummy ),
+        .out_HLS_WREADY          ( WREADY_Dummy ),
+        .in_HLS_WSTRB            ( WSTRB_Dummy ),
+        .in_HLS_WDATA            ( WDATA_Dummy ),
+        .out_HLS_BVALID          ( BVALID_Dummy ),
+        .in_HLS_BREADY           ( BREADY_Dummy ));
+
+    // Stream2Mmap_mmap_m_axi_read
+    Stream2Mmap_mmap_m_axi_read #(
+        .C_M_AXI_ID_WIDTH         ( C_M_AXI_ID_WIDTH ),
+        .C_M_AXI_ARUSER_WIDTH     ( C_M_AXI_ARUSER_WIDTH ),
+        .C_M_AXI_RUSER_WIDTH      ( C_M_AXI_RUSER_WIDTH ),
+        .C_USER_VALUE             ( C_USER_VALUE ),
+        .C_PROT_VALUE             ( C_PROT_VALUE ),
+        .C_CACHE_VALUE            ( C_CACHE_VALUE ),
+        .BUS_ADDR_WIDTH           ( C_M_AXI_ADDR_WIDTH ),
+        .BUS_DATA_WIDTH           ( C_M_AXI_DATA_WIDTH ),
+        .NUM_READ_OUTSTANDING     ( NUM_READ_OUTSTANDING ),
+        .MAX_READ_BURST_LENGTH    ( MAX_READ_BURST_LENGTH )
+    ) bus_read (
+        .ACLK                     ( ACLK ),
+        .ARESET                   ( ARESET ),
+        .ACLK_EN                  ( ACLK_EN ),
+        .out_BUS_ARID             ( ARID ),
+        .out_BUS_ARADDR           ( ARADDR ),
+        .out_BUS_ARLEN            ( ARLEN ),
+        .out_BUS_ARSIZE           ( ARSIZE ),
+        .out_BUS_ARBURST          ( ARBURST ),
+        .out_BUS_ARLOCK           ( ARLOCK ),
+        .out_BUS_ARCACHE          ( ARCACHE ),
+        .out_BUS_ARPROT           ( ARPROT ),
+        .out_BUS_ARQOS            ( ARQOS ),
+        .out_BUS_ARREGION         ( ARREGION ),
+        .out_BUS_ARUSER           ( ARUSER ),
+
+
+        .out_BUS_ARVALID          ( ARVALID ),
+        .in_BUS_ARREADY           ( ARREADY ),
+        .in_BUS_RID               ( RID ),
+        .in_BUS_RDATA             ( RDATA ),
+        .in_BUS_RRESP             ( RRESP ),
+        .in_BUS_RLAST             ( RLAST ),
+        .in_BUS_RUSER             ( RUSER ),
+        .in_BUS_RVALID            ( RVALID ),
+
+
+        .out_BUS_RREADY           ( RREADY ),
+        .in_HLS_ARVALID           ( ARVALID_Dummy ),
+        .out_HLS_ARREADY          ( ARREADY_Dummy ),
+        .in_HLS_ARADDR            ( ARADDR_Dummy ),
+        .in_HLS_ARLEN             ( ARLEN_Dummy ),
+        .out_HLS_RVALID           ( RVALID_Dummy ),
+        .in_HLS_RREADY            ( RREADY_Dummy ),
+        .in_HLS_RBUST_READY       ( RBURST_READY_Dummy),
+        .out_HLS_RDATA            ( RDATA_Dummy ),
+        .out_HLS_RLAST            ( RLAST_Dummy ));
+
+
+endmodule
+`default_nettype wire// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+`timescale 1ns/1ps
+
+module Stream2Mmap_mmap_m_axi_load
+#(parameter
+    C_TARGET_ADDR                         = 32'h00000000,
+    NUM_READ_OUTSTANDING                  = 2,
+    MAX_READ_BURST_LENGTH                 = 16,
+    BUS_ADDR_WIDTH                        = 32,
+    BUS_DATA_WIDTH                        = 32,
+    USER_DW                               = 16,
+    USER_AW                               = 32,
+    USER_MAXREQS                          = 16,
+    USER_RFIFONUM_WIDTH                   = 6,
+    BUFFER_IMPL                           = "auto"
+)(
+    // system signal
+    input  wire                           ACLK,
+    input  wire                           ARESET,
+    input  wire                           ACLK_EN,
+
+    // read address channel
+    output wire [BUS_ADDR_WIDTH-1:0]      out_AXI_ARADDR,
+    output wire [31:0]                    out_AXI_ARLEN,
+    output wire                           out_AXI_ARVALID,
+    input  wire                           in_AXI_ARREADY,
+    // read data channel
+    input  wire [BUS_DATA_WIDTH-1:0]      in_AXI_RDATA,
+    input  wire [1:0]                     in_AXI_RLAST,
+    input  wire                           in_AXI_RVALID,
+    output wire                           out_AXI_RREADY,
+    output wire                           out_AXI_RBURST_READY,
+
+    // internal bus ports
+    // read address
+    input  wire [USER_AW-1:0]             in_HLS_ARADDR,
+    input  wire [31:0]                    in_HLS_ARLEN,
+    input  wire                           in_HLS_ARVALID,
+    output wire                           out_HLS_ARREADY,
+    // read data
+    output wire [USER_DW-1:0]             out_HLS_RDATA,
+    output wire                           out_HLS_RVALID,
+    input  wire                           in_HLS_RREADY,
+    output wire [USER_RFIFONUM_WIDTH-1:0] out_HLS_RFIFONUM);
+
+//------------------------Parameter----------------------
+    localparam
+        USER_DATA_WIDTH = calc_data_width(USER_DW),
+        USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+        USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+        BUS_ADDR_ALIGN  = log2(BUS_DATA_WIDTH/8),
+        RBUFF_DEPTH     = NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH,
+        TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN);
+
+//------------------------Task and function--------------
+    function integer calc_data_width;
+        input integer x;
+        integer y;
+    begin
+        y = 8;
+        while (y < x) y = y * 2;
+        calc_data_width = y;
+    end
+    endfunction
+
+    function integer log2;
+        input integer x;
+        integer n, m;
+    begin
+        n = 0;
+        m = 1;
+        while (m < x) begin
+            n = n + 1;
+            m = m * 2;
+        end
+        log2 = n;
+    end
+    endfunction
+
+//------------------------Local signal-------------------
+
+    wire                           next_rreq;
+    wire                           ready_for_rreq;
+    wire                           rreq_ready;
+
+    wire [USER_AW-1 : 0]           rreq_addr;
+    wire [31:0]                    rreq_len;
+    wire                           rreq_valid;
+
+    wire                           valid_length;
+
+    reg  [BUS_ADDR_WIDTH-1 : 0]    tmp_addr;
+    reg  [31:0]                    tmp_len;
+    reg                            tmp_valid;
+
+    wire                           burst_ready;
+    wire                           beat_valid;
+    wire                           next_beat;
+    wire                           last_beat;
+    wire [BUS_DATA_WIDTH-1 : 0]    beat_data;
+    wire [log2(RBUFF_DEPTH) : 0]   beat_nvalid;
+
+    reg                            ready_for_outstanding;
+
+//------------------------Instantiation------------------
+    Stream2Mmap_mmap_m_axi_fifo #(
+        .DATA_WIDTH        (USER_AW + 32),
+        .ADDR_WIDTH        (log2(USER_MAXREQS)),
+        .DEPTH             (USER_MAXREQS)
+    ) fifo_rreq (
+        .clk               (ACLK),
+        .reset             (ARESET),
+        .clk_en            (ACLK_EN),
+        .if_full_n         (out_HLS_ARREADY),
+        .if_write          (in_HLS_ARVALID),
+        .if_din            ({in_HLS_ARLEN, in_HLS_ARADDR}),
+        .if_empty_n        (rreq_valid),
+        .if_read           (next_rreq),
+        .if_dout           ({rreq_len, rreq_addr}),
+        .if_num_data_valid ());
+
+    // ===================================================================
+    // start of ARADDR PREPROCESSOR
+
+    assign next_rreq       = rreq_valid && ready_for_rreq;
+    assign ready_for_rreq  = ~tmp_valid || (in_AXI_ARREADY && rreq_ready);
+
+    assign valid_length    = (rreq_len != 32'b0) && !rreq_len[31];
+
+    assign out_AXI_ARLEN   = tmp_len;   // Byte length
+    assign out_AXI_ARADDR  = tmp_addr;  // Byte address
+    assign out_AXI_ARVALID = tmp_valid && rreq_ready;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET) begin
+            tmp_len  <= 0;
+            tmp_addr <= 0;
+        end
+        else if (ACLK_EN) begin
+            if(next_rreq) begin
+                tmp_len  <= (rreq_len << USER_ADDR_ALIGN) - 1;            // byte length
+                tmp_addr <= TARGET_ADDR + (rreq_addr << USER_ADDR_ALIGN); // byte address
+            end
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            tmp_valid <= 1'b0;
+        else if (ACLK_EN) begin
+            if (next_rreq && valid_length)
+                tmp_valid <= 1'b1;
+            else if (in_AXI_ARREADY && rreq_ready)
+                tmp_valid <= 1'b0;
+        end
+    end
+
+    // end of ARADDR PREPROCESSOR
+    // ===================================================================
+
+    Stream2Mmap_mmap_m_axi_fifo #(
+        .MEM_STYLE         (BUFFER_IMPL),
+        .DATA_WIDTH        (BUS_DATA_WIDTH + 2),
+        .ADDR_WIDTH        (log2(RBUFF_DEPTH)),
+        .DEPTH             (RBUFF_DEPTH)
+    ) buff_rdata (
+        .clk               (ACLK),
+        .reset             (ARESET),
+        .clk_en            (ACLK_EN),
+        .if_full_n         (out_AXI_RREADY),
+        .if_write          (in_AXI_RVALID),
+        .if_din            ({in_AXI_RLAST, in_AXI_RDATA}),
+        .if_empty_n        (beat_valid),
+        .if_read           (next_beat),
+        .if_dout           ({burst_ready, last_beat, beat_data}),
+        .if_num_data_valid (beat_nvalid));
+
+    assign out_AXI_RBURST_READY = ready_for_outstanding;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            ready_for_outstanding <= 1'b0;
+        else if (ACLK_EN) begin
+            if (next_beat)
+                ready_for_outstanding <= burst_ready;
+            else
+                ready_for_outstanding <= 1'b0;
+        end
+    end
+    // ===================================================================
+    // start of RDATA PREPROCESSOR
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+
+        assign rreq_ready       = 1'b1;
+        assign next_beat        = in_HLS_RREADY;
+
+        assign out_HLS_RDATA    = beat_data[USER_DW-1 : 0];
+        assign out_HLS_RVALID   = beat_valid;
+        assign out_HLS_RFIFONUM = beat_nvalid;
+
+    end
+    else if (USER_DATA_WIDTH < BUS_DATA_WIDTH) begin : bus_wide_gen
+        localparam
+            TOTAL_SPLIT  = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            SPLIT_ALIGN  = log2(TOTAL_SPLIT);
+
+        wire [USER_AW - 1:0]        tmp_addr_end;
+
+        wire                        offset_full_n;
+        wire                        offset_write;
+        wire [SPLIT_ALIGN-1 : 0]    start_offset;
+        wire [SPLIT_ALIGN-1 : 0]    end_offset;
+
+        wire                        offset_valid;
+        wire                        next_offset;
+        wire [SPLIT_ALIGN-1 : 0]    head_offset;
+        wire [SPLIT_ALIGN-1 : 0]    tail_offset;
+
+        reg                         first_beat;
+
+        wire                        first_data;
+        wire                        last_data;
+        wire                        ready_for_data;
+
+        reg  [BUS_DATA_WIDTH-1 : 0] data_buf;
+        reg                         data_valid;
+
+        reg  [USER_RFIFONUM_WIDTH-1:0] rdata_nvalid;
+        reg  [SPLIT_ALIGN : 0]      data_nvalid;
+        wire [SPLIT_ALIGN : 0]      split_nvalid;
+
+        wire [SPLIT_ALIGN-1 : 0]    split_cnt;
+        reg  [SPLIT_ALIGN-1 : 0]    split_cnt_buf;
+
+        wire                        first_split;
+        wire                        next_split;
+        wire                        last_split;
+
+        // Recording the offset of start & end address to extract the expect data from beats when USER_DW < BUS_DW.
+        Stream2Mmap_mmap_m_axi_fifo #(
+            .DATA_WIDTH         (2*SPLIT_ALIGN),
+            .ADDR_WIDTH         (log2(NUM_READ_OUTSTANDING)),
+            .DEPTH              (NUM_READ_OUTSTANDING)
+        ) rreq_offset (
+            .clk                (ACLK),
+            .reset              (ARESET),
+            .clk_en             (ACLK_EN),
+            .if_full_n          (offset_full_n),
+            .if_write           (offset_write),
+            .if_din             ({start_offset, end_offset}),
+            .if_empty_n         (offset_valid),
+            .if_read            (next_offset),
+            .if_dout            ({head_offset, tail_offset}),
+            .if_num_data_valid  ());
+
+        assign rreq_ready       = offset_full_n | ~offset_write;
+        assign tmp_addr_end     = tmp_addr + tmp_len;
+
+        assign start_offset     = tmp_addr[BUS_ADDR_ALIGN - 1 : 0] >> USER_ADDR_ALIGN;
+        assign end_offset       = tmp_addr_end[BUS_ADDR_ALIGN - 1 : 0] >> USER_ADDR_ALIGN;
+        assign offset_write     = tmp_valid & in_AXI_ARREADY;
+
+        assign next_offset      = (last_beat & beat_valid) & last_split;
+        assign next_beat        = last_split;
+
+        assign out_HLS_RDATA    = data_buf[USER_DW-1 : 0];
+        assign out_HLS_RVALID   = data_valid;
+        assign out_HLS_RFIFONUM = rdata_nvalid + data_nvalid;
+
+        assign ready_for_data   = ~data_valid | in_HLS_RREADY;
+        assign first_data       = first_beat && beat_valid && offset_valid;
+        assign last_data        = last_beat && beat_valid && offset_valid;
+
+        assign first_split      = (~first_data) ? (split_cnt == 0 && beat_valid && ready_for_data) : ((split_cnt == head_offset) && ready_for_data);
+        assign last_split       = (~last_data)  ? (split_cnt == (TOTAL_SPLIT-1) && ready_for_data) : ((split_cnt == tail_offset) && ready_for_data);
+        assign next_split       = (~first_data) ? (split_cnt != 0 && ready_for_data)               : ((split_cnt != head_offset) && ready_for_data);
+
+        assign split_cnt        = (first_data && (split_cnt_buf == 0)) ? head_offset : split_cnt_buf;
+
+        assign split_nvalid     = (first_data && last_data)  ? tail_offset - head_offset + 1 :
+                                   first_data                ? TOTAL_SPLIT - head_offset     :
+                                   last_data                 ? tail_offset + 1               :
+                                   TOTAL_SPLIT;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt_buf <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt_buf <= 0;
+                else if (first_split || next_split)
+                    split_cnt_buf <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_beat <= 1'b1;
+            else if (ACLK_EN) begin
+                if (last_beat && last_split)
+                    first_beat <= 1'b1;
+                else if (first_beat && last_split)
+                    first_beat <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (first_split & first_data)
+                    data_buf <= beat_data >> (head_offset * USER_DATA_WIDTH);
+                else if (first_split)
+                    data_buf <= beat_data;
+                else if (next_split)
+                    data_buf <= data_buf >> USER_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                data_valid <= 1'b0;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    data_valid <= 1'b1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    data_valid <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                data_nvalid <= 0;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    data_nvalid <= split_nvalid;
+                else if (next_split)
+                    data_nvalid <= data_nvalid - 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    data_nvalid <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_nvalid <= 0;
+            else if (ACLK_EN) begin
+                if (!beat_valid)
+                    rdata_nvalid <= 0;
+                else
+                    rdata_nvalid <= ((beat_nvalid - 1) << SPLIT_ALIGN);
+            end
+        end
+
+    end
+    else begin : bus_narrow_gen
+        localparam
+            TOTAL_PADS      = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg [USER_DATA_WIDTH-1 : 0] data_buf;
+        reg                         data_valid;
+        reg [PAD_ALIGN:0]           data_nvalid;
+        wire                        ready_for_data;
+
+        wire [TOTAL_PADS - 1:0]     pad_oh;
+        reg  [TOTAL_PADS - 1:0]     pad_oh_reg;
+
+        reg                         first_pad;
+        wire                        last_pad;
+        wire                        next_pad;
+
+        assign rreq_ready       = 1'b1;
+        assign next_beat        = next_pad;
+
+        assign out_HLS_RDATA    = data_buf[USER_DW-1 : 0];
+        assign out_HLS_RVALID   = data_valid;
+        assign out_HLS_RFIFONUM = beat_nvalid[log2(RBUFF_DEPTH) : PAD_ALIGN] + (beat_nvalid[PAD_ALIGN-1:0] + data_nvalid) >> PAD_ALIGN;
+        assign ready_for_data   = ~data_valid | in_HLS_RREADY;
+
+        assign next_pad         = beat_valid && ready_for_data;
+        assign last_pad         = pad_oh[TOTAL_PADS - 1];
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1'b1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 1'b0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1'b1;
+            end
+        end
+
+        assign pad_oh = (beat_valid == 0)  ?  0 :
+                        (first_pad)        ?  1 :
+                        pad_oh_reg;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 0; i < TOTAL_PADS; i = i + 1) begin : data_gen
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if (pad_oh[i] == 1'b1 && ready_for_data)
+                        data_buf[i*BUS_DATA_WIDTH +: BUS_DATA_WIDTH] <= beat_data;
+                end
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                data_valid <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    data_valid <= 1'b1;
+                else if (ready_for_data)
+                    data_valid <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                data_nvalid <= 0;
+            else if (ACLK_EN) begin
+                if (first_pad)
+                    data_nvalid <= 1;
+                else if (next_pad)
+                    data_nvalid <= data_nvalid + 1;
+            end
+        end
+
+    end
+    endgenerate
+    // end of RDATA PREPROCESSOR
+    // ===================================================================
+
+endmodule
+
+
+module Stream2Mmap_mmap_m_axi_store
+#(parameter
+    C_TARGET_ADDR           = 32'h00000000,
+    NUM_WRITE_OUTSTANDING   = 2,
+    MAX_WRITE_BURST_LENGTH  = 16,
+    BUS_ADDR_WIDTH          = 32,
+    BUS_DATA_WIDTH          = 32,
+    USER_DW                 = 16,
+    USER_AW                 = 32,
+    USER_MAXREQS            = 16,
+    BUFFER_IMPL             = "auto"
+)(
+    // system signal
+    input  wire                        ACLK,
+    input  wire                        ARESET,
+    input  wire                        ACLK_EN,
+    // write address channel
+    output wire [BUS_ADDR_WIDTH-1:0]   out_AXI_AWADDR,
+    output wire [31:0]                 out_AXI_AWLEN,
+    output wire                        out_AXI_AWVALID,
+    input  wire                        in_AXI_AWREADY,
+    // write data channel
+    output wire [BUS_DATA_WIDTH-1:0]   out_AXI_WDATA,
+    output wire [BUS_DATA_WIDTH/8-1:0] out_AXI_WSTRB,
+    output wire                        out_AXI_WVALID,
+    input  wire                        in_AXI_WREADY,
+    // write response channel
+    input  wire                        in_AXI_BVALID,
+    output wire                        out_AXI_BREADY,
+
+    // internal bus ports
+    // write address
+    input  wire [USER_AW-1:0]          in_HLS_AWADDR,
+    input  wire [31:0]                 in_HLS_AWLEN,
+    input  wire                        in_HLS_AWVALID,
+    output wire                        out_HLS_AWREADY,
+    // write data
+    input  wire [USER_DW-1:0]          in_HLS_WDATA,
+    input  wire [USER_DW/8-1:0]        in_HLS_WSTRB,
+    input  wire                        in_HLS_WVALID,
+    output wire                        out_HLS_WREADY,
+    // write response
+    output wire                        out_HLS_BVALID,
+    input  wire                        in_HLS_BREADY);
+
+//------------------------Parameter----------------------
+    localparam
+        USER_DATA_WIDTH = calc_data_width(USER_DW),
+        USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+        USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+        BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+        BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+        // write buffer size
+        WBUFF_DEPTH     = max(MAX_WRITE_BURST_LENGTH * BUS_DATA_WIDTH / USER_DATA_WIDTH, 1),
+        TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN);
+
+//------------------------Task and function--------------
+
+    function integer max;
+        input integer x;
+        input integer y;
+    begin
+        max = (x > y) ? x : y;
+    end
+    endfunction
+
+    function integer calc_data_width;
+        input integer x;
+        integer y;
+    begin
+        y = 8;
+        while (y < x) y = y * 2;
+        calc_data_width = y;
+    end
+    endfunction
+
+    function integer log2;
+        input integer x;
+        integer n, m;
+    begin
+        n = 0;
+        m = 1;
+        while (m < x) begin
+            n = n + 1;
+            m = m * 2;
+        end
+        log2 = n;
+    end
+    endfunction
+
+//------------------------Local signal-------------------
+
+    wire                                next_wreq;
+    wire                                ready_for_wreq;
+    wire                                wreq_ready;
+
+    wire [USER_AW-1 : 0]                wreq_addr;
+    wire [31:0]                         wreq_len;
+    wire                                wreq_valid;
+
+    wire                                valid_length;
+
+    reg  [USER_AW-1 : 0]                tmp_addr;
+    reg  [31:0]                         tmp_len;
+    reg                                 tmp_valid;
+
+    wire                                next_wdata;
+    wire                                wdata_valid;
+    wire [USER_DW-1 : 0]                tmp_wdata;
+    wire [USER_DW/8-1 : 0]              tmp_wstrb;
+
+    wire                                wrsp_ready;
+    wire                                wrsp_valid;
+    wire                                wrsp_read;
+    wire                                wrsp_type;
+
+    wire                                ursp_ready;
+    wire                                ursp_write;
+
+//------------------------Instantiation------------------
+    Stream2Mmap_mmap_m_axi_fifo #(
+        .DATA_WIDTH     (USER_AW + 32),
+        .ADDR_WIDTH     (log2(USER_MAXREQS)),
+        .DEPTH          (USER_MAXREQS)
+    ) fifo_wreq (
+        .clk            (ACLK),
+        .reset          (ARESET),
+        .clk_en         (ACLK_EN),
+        .if_full_n      (out_HLS_AWREADY),
+        .if_write       (in_HLS_AWVALID),
+        .if_din         ({in_HLS_AWLEN, in_HLS_AWADDR}),
+        .if_empty_n     (wreq_valid),
+        .if_read        (next_wreq),
+        .if_dout        ({wreq_len, wreq_addr}),
+        .if_num_data_valid());
+
+    assign next_wreq = wreq_valid && ready_for_wreq && wrsp_ready;
+    assign ready_for_wreq  = ~tmp_valid || (in_AXI_AWREADY && wreq_ready);
+
+    assign valid_length    = (wreq_len != 32'b0) && !wreq_len[31];
+
+    assign out_AXI_AWLEN   = tmp_len;   // Byte length
+    assign out_AXI_AWADDR  = tmp_addr;  // Byte address
+    assign out_AXI_AWVALID = tmp_valid && wreq_ready;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET) begin
+            tmp_len  <= 0;
+            tmp_addr <= 0;
+        end
+        else if (ACLK_EN) begin
+            if(next_wreq) begin
+                tmp_len  <= (wreq_len << USER_ADDR_ALIGN) - 1;
+                tmp_addr <= TARGET_ADDR + (wreq_addr << USER_ADDR_ALIGN);
+            end
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            tmp_valid <= 1'b0;
+        else if (next_wreq && valid_length)
+            tmp_valid <= 1'b1;
+        else if (in_AXI_AWREADY && wreq_ready)
+            tmp_valid <= 1'b0;
+    end
+
+    // ===================================================================
+
+    Stream2Mmap_mmap_m_axi_fifo #(
+        .MEM_STYLE         (BUFFER_IMPL),
+        .DATA_WIDTH        (USER_DW + USER_DW/8),
+        .ADDR_WIDTH        (log2(WBUFF_DEPTH)),
+        .DEPTH             (WBUFF_DEPTH)
+    ) buff_wdata (
+        .clk               (ACLK),
+        .reset             (ARESET),
+        .clk_en            (ACLK_EN),
+        .if_full_n         (out_HLS_WREADY),
+        .if_write          (in_HLS_WVALID),
+        .if_din            ({in_HLS_WSTRB , in_HLS_WDATA}),
+        .if_empty_n        (wdata_valid),
+        .if_read           (next_wdata),
+        .if_dout           ({tmp_wstrb, tmp_wdata}),
+        .if_num_data_valid ());
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        assign next_wdata       = in_AXI_WREADY;
+        assign out_AXI_WVALID   = wdata_valid;
+        assign out_AXI_WDATA    = tmp_wdata;
+        assign out_AXI_WSTRB    = tmp_wstrb;
+
+        assign wreq_ready   = 1'b1;
+
+    end
+    else if (USER_DATA_WIDTH < BUS_DATA_WIDTH) begin : bus_wide_gen
+        localparam
+            TOTAL_PADS      = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS),
+            BEAT_LEN_WIDTH  = 32 - BUS_ADDR_ALIGN;
+
+        function [TOTAL_PADS-1 : 0] decoder;
+            input [PAD_ALIGN-1 : 0] din;
+            reg  [TOTAL_PADS-1 : 0] dout;
+            integer i;
+        begin
+            dout = {TOTAL_PADS{1'b0}};
+            for (i = 0; i < din; i = i + 1)
+                dout[i] = 1'b1;
+            decoder = dout;
+        end
+        endfunction
+
+        wire [USER_AW - 1:0]        tmp_addr_end;
+
+        wire                        offset_full_n;
+        wire                        offset_write;
+        wire [PAD_ALIGN-1 : 0]      start_offset;
+        wire [PAD_ALIGN-1 : 0]      end_offset;
+        wire [BEAT_LEN_WIDTH-1 : 0] beat_total;
+
+        wire                        offset_valid;
+        wire                        next_offset;
+        wire [PAD_ALIGN-1 : 0]      head_offset;
+        wire [PAD_ALIGN-1 : 0]      tail_offset;
+
+        wire [BEAT_LEN_WIDTH-1 : 0] beat_len;
+        reg  [BEAT_LEN_WIDTH-1:0]   len_cnt;
+
+        wire [TOTAL_PADS - 1:0]     add_head;
+        wire [TOTAL_PADS - 1:0]     add_tail;
+        wire [TOTAL_PADS - 1:0]     pad_oh;
+        reg  [TOTAL_PADS - 1:0]     pad_oh_reg;
+
+        wire [TOTAL_PADS-1 : 0]     head_pad_sel;
+        wire [0 : TOTAL_PADS-1]     tail_pad_sel; // reverse
+        wire                        ready_for_data;
+        wire                        next_pad;
+        reg                         first_pad;
+        wire                        last_pad;
+        wire                        first_beat;
+        wire                        last_beat;
+        wire                        next_beat;
+
+        reg  [BUS_DATA_WIDTH - 1:0] data_buf;
+        reg  [BUS_DATA_BYTES - 1:0] strb_buf;
+        reg                         data_valid;
+
+        // Recording the offset of start & end address to align beats from data USER_DW < BUS_DW.
+        Stream2Mmap_mmap_m_axi_fifo #(
+            .DATA_WIDTH             (2*PAD_ALIGN + BEAT_LEN_WIDTH),
+            .ADDR_WIDTH             (log2(NUM_WRITE_OUTSTANDING)),
+            .DEPTH                  (NUM_WRITE_OUTSTANDING)
+        ) wreq_offset (
+            .clk                    (ACLK),
+            .reset                  (ARESET),
+            .clk_en                 (ACLK_EN),
+            .if_full_n              (offset_full_n),
+            .if_write               (offset_write),
+            .if_din                 ({start_offset, end_offset, beat_total}),
+            .if_empty_n             (offset_valid),
+            .if_read                (next_offset),
+            .if_dout                ({head_offset, tail_offset, beat_len}),
+            .if_num_data_valid      ());
+
+        assign wreq_ready   = offset_full_n | ~offset_write;
+        assign tmp_addr_end = tmp_addr + tmp_len;
+
+        assign start_offset   = tmp_addr[BUS_ADDR_ALIGN-1 : 0] >> USER_ADDR_ALIGN;
+        assign end_offset     = ~tmp_addr_end[BUS_ADDR_ALIGN-1 : 0] >> USER_ADDR_ALIGN;
+        assign beat_total     = (tmp_len + tmp_addr[BUS_ADDR_ALIGN-1 : 0]) >> BUS_ADDR_ALIGN;
+
+        assign offset_write   = tmp_valid & in_AXI_AWREADY;
+
+        assign out_AXI_WDATA  = data_buf;
+        assign out_AXI_WSTRB  = strb_buf;
+        assign out_AXI_WVALID = data_valid;
+
+        assign next_wdata     = next_pad;
+        assign next_offset    = last_beat && next_beat;
+        assign ready_for_data = ~data_valid || in_AXI_WREADY;
+
+        assign first_beat     = (len_cnt == 0) && offset_valid;
+        assign last_beat      = (len_cnt == beat_len) && offset_valid;
+        assign next_beat      = offset_valid && last_pad && ready_for_data;
+
+        assign next_pad       = offset_valid && wdata_valid && ready_for_data;
+        assign last_pad       = (last_beat) ? pad_oh[TOTAL_PADS-tail_offset-1] : pad_oh[TOTAL_PADS-1];
+
+        assign head_pad_sel   = decoder(head_offset);
+        assign tail_pad_sel   = decoder(tail_offset);
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_offset)
+                    len_cnt <= 0;
+                else if (next_beat)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1'b1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 1'b0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1'b1;
+            end
+        end
+
+        assign pad_oh = (~wdata_valid)            ? 0                :
+                        (first_pad && first_beat) ? 1 << head_offset :
+                        (first_pad)?                1                :
+                        pad_oh_reg;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 0; i < TOTAL_PADS; i = i + 1) begin : data_gen
+            assign add_head[i] = head_pad_sel[i] && first_beat;
+            assign add_tail[i] = tail_pad_sel[i] && last_beat;
+
+            always @(posedge ACLK)
+            begin
+                if (ARESET)
+                    data_buf[i*USER_DATA_WIDTH +: USER_DATA_WIDTH] <= {USER_DATA_WIDTH{1'b0}};
+                else if (ACLK_EN) begin
+                    if ((add_head[i] || add_tail[i]) && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH +: USER_DATA_WIDTH] <= {USER_DATA_WIDTH{1'b0}};
+                    else if (pad_oh[i] == 1'b1 && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH +: USER_DATA_WIDTH] <= tmp_wdata;
+                end
+            end
+
+            always @(posedge ACLK)
+            begin
+                if (ARESET)
+                    strb_buf[i*USER_DATA_BYTES +: USER_DATA_BYTES] <= {USER_DATA_BYTES{1'b0}};
+                else if (ACLK_EN) begin
+                    if ((add_head[i] || add_tail[i]) && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES +: USER_DATA_BYTES] <= {USER_DATA_BYTES{1'b0}};
+                    else if (pad_oh[i] == 1'b1 && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES +: USER_DATA_BYTES] <= tmp_wstrb;
+                end
+            end
+
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                data_valid <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    data_valid <= 1'b1;
+                else if (ready_for_data)
+                    data_valid <= 1'b0;
+            end
+        end
+
+    end
+    else begin : bus_narrow_gen
+        localparam
+            TOTAL_SPLIT       = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            SPLIT_ALIGN       = log2(TOTAL_SPLIT),
+            BEAT_LEN_WIDTH    = 32 - BUS_ADDR_ALIGN;
+
+
+        wire [USER_AW - 1:0]        tmp_addr_end;
+
+        wire                        offset_full_n;
+        wire                        offset_write;
+        wire  [BEAT_LEN_WIDTH-1 : 0] beat_total;
+
+        wire                        offset_valid;
+        wire                        next_offset;
+
+        wire [BEAT_LEN_WIDTH-1 : 0] beat_len;
+        reg  [BEAT_LEN_WIDTH-1 : 0] len_cnt;
+
+        wire                        ready_for_data;
+        reg  [BUS_DATA_WIDTH - 1:0] data_buf;
+        reg  [BUS_DATA_BYTES - 1:0] strb_buf;
+        reg                         data_valid;
+
+        reg [SPLIT_ALIGN-1 : 0]     split_cnt;
+
+        wire                        first_split;
+        wire                        next_split;
+        wire                        last_split;
+
+        // Recording the offset of start & end address to align beats from data USER_DW < BUS_DW.
+        Stream2Mmap_mmap_m_axi_fifo #(
+            .DATA_WIDTH        (BEAT_LEN_WIDTH),
+            .ADDR_WIDTH        (log2(NUM_WRITE_OUTSTANDING)),
+            .DEPTH             (NUM_WRITE_OUTSTANDING)
+        ) wreq_offset (
+            .clk               (ACLK),
+            .reset             (ARESET),
+            .clk_en            (ACLK_EN),
+            .if_full_n         (offset_full_n),
+            .if_write          (offset_write),
+            .if_din            (beat_total),
+            .if_empty_n        (offset_valid),
+            .if_read           (next_offset),
+            .if_dout           (beat_len),
+            .if_num_data_valid ());
+
+        assign wreq_ready     = offset_full_n | ~offset_write;
+        assign beat_total     = (tmp_len + tmp_addr[BUS_ADDR_ALIGN-1 : 0]) >> BUS_ADDR_ALIGN;
+
+        assign offset_write   = tmp_valid & in_AXI_AWREADY;
+
+        assign out_AXI_WDATA  = data_buf[BUS_DATA_WIDTH - 1:0];
+        assign out_AXI_WSTRB  = strb_buf[BUS_DATA_BYTES - 1:0];
+        assign out_AXI_WVALID = data_valid;
+
+        assign next_wdata     = first_split;
+        assign next_offset    = (len_cnt == beat_len) && offset_valid && last_split;
+        assign ready_for_data = ~data_valid | in_AXI_WREADY;
+
+        assign first_split    = (split_cnt == 0) && wdata_valid && offset_valid && ready_for_data;
+        assign last_split     = (split_cnt == (TOTAL_SPLIT - 1)) && ready_for_data;
+        assign next_split     = (split_cnt != 0) && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt <= 0;
+                else if (first_split || next_split)
+                    split_cnt <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_offset)
+                    len_cnt <= 0;
+                else if (next_wdata || next_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_wdata)
+                    data_buf <= tmp_wdata;
+                else if (next_split)
+                    data_buf <= data_buf >> BUS_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_wdata)
+                    strb_buf <= tmp_wstrb;
+                else if (next_split)
+                    strb_buf <= strb_buf >> BUS_DATA_BYTES;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                data_valid <= 0;
+            else if (ACLK_EN) begin
+                if (next_wdata)
+                    data_valid <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    data_valid <= 0;
+            end
+        end
+    end
+    endgenerate
+
+    // ===================================================================
+
+    // generate response for all request (including request with invalid length)
+    Stream2Mmap_mmap_m_axi_fifo #(
+        .DATA_WIDTH        (1),
+        .ADDR_WIDTH        (log2(NUM_WRITE_OUTSTANDING)),
+        .DEPTH             (NUM_WRITE_OUTSTANDING)
+    ) fifo_wrsp (
+        .clk               (ACLK),
+        .reset             (ARESET),
+        .clk_en            (ACLK_EN),
+        .if_full_n         (wrsp_ready),
+        .if_write          (next_wreq),
+        .if_din            (valid_length),
+        .if_empty_n        (wrsp_valid),
+        .if_read           (wrsp_read),
+        .if_dout           (wrsp_type), // 1 - valid length request, 0 - invalid length request
+        .if_num_data_valid ());
+
+    Stream2Mmap_mmap_m_axi_fifo #(
+        .DATA_WIDTH        (1),
+        .ADDR_WIDTH        (log2(USER_MAXREQS)),
+        .DEPTH             (USER_MAXREQS)
+    ) user_resp (
+        .clk               (ACLK),
+        .reset             (ARESET),
+        .clk_en            (ACLK_EN),
+        .if_full_n         (ursp_ready),
+        .if_write          (ursp_write),
+        .if_din            (1'b1),
+        .if_empty_n        (out_HLS_BVALID),
+        .if_read           (in_HLS_BREADY),
+        .if_dout           (),
+        .if_num_data_valid ());
+
+    assign ursp_write  = wrsp_valid && (!wrsp_type || in_AXI_BVALID);
+    assign wrsp_read   = ursp_ready && ursp_write;
+
+    assign out_AXI_BREADY = wrsp_type && ursp_ready;
+
+endmodule
+
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+`timescale 1ns/1ps
+
+//
+
+
+module Stream2Mmap_mmap_m_axi_read
+#(parameter
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ARUSER_WIDTH      = 1,
+    C_M_AXI_RUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    BUS_ADDR_WIDTH            = 32,
+    BUS_DATA_WIDTH            = 32,
+    NUM_READ_OUTSTANDING      = 2,
+    MAX_READ_BURST_LENGTH     = 16
+)(
+    // system signal
+    input  wire                            ACLK,
+    input  wire                            ARESET,
+    input  wire                            ACLK_EN,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]     out_BUS_ARID,
+    output wire [BUS_ADDR_WIDTH-1:0]       out_BUS_ARADDR,
+    output wire [7:0]                      out_BUS_ARLEN,
+    output wire [2:0]                      out_BUS_ARSIZE,
+    output wire [1:0]                      out_BUS_ARBURST,
+    output wire [1:0]                      out_BUS_ARLOCK,
+    output wire [3:0]                      out_BUS_ARCACHE,
+    output wire [2:0]                      out_BUS_ARPROT,
+    output wire [3:0]                      out_BUS_ARQOS,
+    output wire [3:0]                      out_BUS_ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0] out_BUS_ARUSER,
+    output wire                            out_BUS_ARVALID,
+    input  wire                            in_BUS_ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]     in_BUS_RID,
+    input  wire [BUS_DATA_WIDTH-1:0]       in_BUS_RDATA,
+    input  wire [1:0]                      in_BUS_RRESP,
+    input  wire                            in_BUS_RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]  in_BUS_RUSER,
+    input  wire                            in_BUS_RVALID,
+    output wire                            out_BUS_RREADY,
+
+    // HLS internal read request channel
+    input  wire [BUS_ADDR_WIDTH-1:0]       in_HLS_ARADDR,
+    input  wire [31:0]                     in_HLS_ARLEN,
+    input  wire                            in_HLS_ARVALID,
+    output wire                            out_HLS_ARREADY,
+    output wire [BUS_DATA_WIDTH-1:0]       out_HLS_RDATA,
+    output wire [1:0]                      out_HLS_RLAST,
+    output wire                            out_HLS_RVALID,
+    input  wire                            in_HLS_RREADY,
+    input  wire                            in_HLS_RBUST_READY);
+
+//------------------------Parameter----------------------
+    localparam
+        BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+        BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+        NUM_READ_WIDTH  = log2(MAX_READ_BURST_LENGTH),
+        RBUFFER_AWIDTH  = log2(MAX_READ_BURST_LENGTH*NUM_READ_OUTSTANDING),
+        BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+    function integer calc_data_width;
+        input integer x;
+        integer y;
+    begin
+        y = 8;
+        while (y < x) y = y * 2;
+        calc_data_width = y;
+    end
+    endfunction
+
+    function integer log2;
+        input integer x;
+        integer n, m;
+    begin
+        n = 0;
+        m = 1;
+        while (m < x) begin
+            n = n + 1;
+            m = m * 2;
+        end
+        log2 = n;
+    end
+    endfunction
+
+//------------------------Local signal-------------------
+    // AR channel
+    wire                                rreq_valid;
+    wire [BUS_ADDR_WIDTH - 1:0]         tmp_addr;
+    wire [31:0]                         tmp_len;
+    wire [7:0]                          arlen_tmp;
+    wire [BUS_ADDR_WIDTH - 1:0]         araddr_tmp;
+    reg  [BUS_ADDR_WIDTH - 1:0]         start_addr;
+    reg  [BUS_ADDR_WIDTH - 1:0]         end_addr;
+    wire [BUS_ADDR_WIDTH - 1:0]         sect_addr;
+    reg  [BUS_ADDR_WIDTH - 1:0]         sect_addr_buf;
+    wire [11 - BUS_ADDR_ALIGN:0]        start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]        sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]        sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]        beat_len;
+    reg  [BUS_ADDR_WIDTH - 13:0]        sect_cnt;
+    wire                                ar2r_info;
+    wire                                fifo_rctl_r;
+    wire                                fifo_burst_w;
+    reg                                 ARVALID_Dummy;
+    wire                                ready_for_sect;
+    wire                                next_rreq;
+    wire                                ready_for_rreq;
+    reg                                 rreq_handling;
+    wire                                first_sect;
+    wire                                last_sect;
+    reg                                 last_sect_buf;
+    wire                                next_sect;
+    // R channel
+    wire [BUS_DATA_WIDTH-1:0]           tmp_data;
+    wire                                tmp_last;
+    wire                                data_valid;
+    wire                                data_ready;
+    wire                                next_ctrl;
+    wire                                need_rlast;
+    wire                                burst_valid;
+    wire                                last_burst;
+    wire                                fifo_rctl_ready;
+    wire                                next_burst;
+    wire                                burst_end;
+
+//------------------------AR channel begin---------------
+//------------------------Instantiation------------------
+    Stream2Mmap_mmap_m_axi_reg_slice #(
+        .DATA_WIDTH     (BUS_ADDR_WIDTH + 32)
+    ) rs_rreq (
+        .clk            (ACLK),
+        .reset          (ARESET),
+        .s_data         ({in_HLS_ARLEN, in_HLS_ARADDR}),
+        .s_valid        (in_HLS_ARVALID),
+        .s_ready        (out_HLS_ARREADY),
+        .m_data         ({tmp_len, tmp_addr}),
+        .m_valid        (rreq_valid),
+        .m_ready        (next_rreq));
+
+//------------------------Body---------------------------
+    assign ready_for_rreq = last_sect & next_sect | ~rreq_handling;
+    assign next_rreq      = rreq_valid & ready_for_rreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET) begin
+            start_addr <= 0;
+            end_addr   <= 0;
+            beat_len   <= 0;
+        end
+        else if (ACLK_EN) begin
+            if(next_rreq) begin
+                start_addr <= tmp_addr;
+                end_addr   <= tmp_addr + tmp_len;
+                beat_len   <= (tmp_len[11:0] + tmp_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+            end
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            rreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (rreq_valid && ~rreq_handling)
+                rreq_handling <= 1'b1;
+            else if (~rreq_valid && last_sect && next_sect)
+                rreq_handling <= 1'b0;
+        end
+    end
+
+    assign first_sect = (sect_cnt == start_addr[BUS_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr[BUS_ADDR_WIDTH-1:12]);
+    assign next_sect  = rreq_handling & ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr : {sect_cnt, {12{1'b0}}};
+    assign start_to_4k = BOUNDARY_BEATS - start_addr[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                sect_cnt <= tmp_addr[BUS_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET) begin
+            sect_addr_buf <= 0;
+            sect_len_buf <= 0;
+            last_sect_buf <= 1'b0;
+        end
+        else if (ACLK_EN) begin
+            if (next_sect) begin
+                sect_addr_buf <= sect_addr;
+                sect_len_buf <= sect_len;
+                last_sect_buf <= last_sect;
+            end
+        end
+    end
+
+    assign out_BUS_ARID     = 0;
+    assign out_BUS_ARSIZE   = BUS_ADDR_ALIGN;
+    assign out_BUS_ARBURST  = 2'b01;
+    assign out_BUS_ARLOCK   = 2'b00;
+    assign out_BUS_ARCACHE  = C_CACHE_VALUE;
+    assign out_BUS_ARPROT   = C_PROT_VALUE;
+    assign out_BUS_ARUSER   = C_USER_VALUE;
+    assign out_BUS_ARQOS    = 4'b0000;
+    assign out_BUS_ARREGION = 4'b0000;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) begin : must_one_burst
+        assign out_BUS_ARADDR  = {sect_addr_buf[BUS_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign out_BUS_ARLEN   = sect_len_buf;
+        assign out_BUS_ARVALID = ARVALID_Dummy;
+
+        assign ready_for_sect = ~(ARVALID_Dummy && ~in_BUS_ARREADY) && fifo_rctl_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_sect && in_BUS_ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r  = next_sect;
+        assign ar2r_info    = last_sect;
+
+        assign fifo_burst_w = next_sect;
+        assign araddr_tmp   = sect_addr[BUS_ADDR_WIDTH - 1:0];
+        assign arlen_tmp    = sect_len;
+    end
+    else begin : could_multi_bursts
+        reg  [BUS_ADDR_WIDTH - 1:0]                     araddr_buf;
+        reg  [7:0]                                      arlen_buf;
+        reg  [11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN:0]   loop_cnt;
+        reg                                             sect_handling;
+        wire                                            last_loop;
+        wire                                            next_loop;
+        wire                                            ready_for_loop;
+
+        assign out_BUS_ARADDR  = araddr_buf;
+        assign out_BUS_ARLEN   = arlen_buf;
+        assign out_BUS_ARVALID = ARVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_READ_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(ARVALID_Dummy && ~in_BUS_ARREADY) && fifo_rctl_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (rreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~rreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign araddr_tmp = (loop_cnt == 0)? sect_addr_buf[BUS_ADDR_WIDTH - 1:0] : (araddr_buf + ((arlen_buf + 1) << BUS_ADDR_ALIGN));
+        assign arlen_tmp  = (NUM_READ_WIDTH == 0) ? 0 :
+                            (last_loop)? sect_len_buf[NUM_READ_WIDTH - 1:0] : { NUM_READ_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET) begin
+                araddr_buf <= 0;
+                arlen_buf <= 0;
+            end
+            else if (ACLK_EN) begin
+                if (next_loop) begin
+                    araddr_buf <= {araddr_tmp[BUS_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+                    arlen_buf <= arlen_tmp;
+                end
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_loop && in_BUS_ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r  = next_loop;
+        assign ar2r_info    = last_loop && last_sect_buf;
+
+        assign fifo_burst_w = next_loop;
+    end
+    endgenerate
+//------------------------AR channel end-----------------
+
+//------------------------R channel begin----------------
+//------------------------Instantiation------------------
+    Stream2Mmap_mmap_m_axi_reg_slice #(
+        .DATA_WIDTH     (BUS_DATA_WIDTH + 1)
+    ) rs_rdata (
+        .clk            (ACLK),
+        .reset          (ARESET),
+        .s_data         ({in_BUS_RLAST, in_BUS_RDATA}),
+        .s_valid        (in_BUS_RVALID),
+        .s_ready        (out_BUS_RREADY),
+        .m_data         ({tmp_last, tmp_data}),
+        .m_valid        (data_valid),
+        .m_ready        (data_ready));
+
+    Stream2Mmap_mmap_m_axi_fifo #(
+        .DATA_WIDTH     (1),
+        .ADDR_WIDTH     (log2(NUM_READ_OUTSTANDING)),
+        .DEPTH          (NUM_READ_OUTSTANDING)
+    ) fifo_rctl (
+        .clk            (ACLK),
+        .reset          (ARESET),
+        .clk_en         (ACLK_EN),
+        .if_full_n      (fifo_rctl_ready),
+        .if_write       (fifo_rctl_r),
+        .if_din         (ar2r_info),
+        .if_empty_n     (need_rlast),
+        .if_read        (next_ctrl),
+        .if_dout        (),
+        .if_num_data_valid());
+
+    Stream2Mmap_mmap_m_axi_fifo #(
+        .DATA_WIDTH     (1),
+        .ADDR_WIDTH     (log2(NUM_READ_OUTSTANDING)),
+        .DEPTH          (NUM_READ_OUTSTANDING)
+    ) fifo_burst (
+        .clk            (ACLK),
+        .reset          (ARESET),
+        .clk_en         (ACLK_EN),
+        .if_full_n      (),
+        .if_write       (fifo_rctl_r),
+        .if_din         (ar2r_info),
+        .if_empty_n     (burst_valid),
+        .if_read        (next_burst),
+        .if_dout        (last_burst),
+        .if_num_data_valid());
+
+//------------------------Body---------------------------
+    assign next_ctrl      = in_HLS_RBUST_READY && need_rlast;
+    assign next_burst     = burst_end && data_valid && data_ready;
+
+    assign burst_end      = tmp_last === 1'b1;
+    assign out_HLS_RLAST  = {burst_end, burst_end && last_burst && burst_valid};
+    assign out_HLS_RDATA  = tmp_data;
+    assign out_HLS_RVALID = data_valid;
+    assign data_ready     = in_HLS_RREADY;
+//------------------------R channel end------------------
+endmodule
+
+module Stream2Mmap_mmap_m_axi_write
+#(parameter
+    CONSERVATIVE              = 0,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_AWUSER_WIDTH      = 1,
+    C_M_AXI_WUSER_WIDTH       = 1,
+    C_M_AXI_BUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    BUS_ADDR_WIDTH            = 32,
+    BUS_DATA_WIDTH            = 32,
+    NUM_WRITE_OUTSTANDING     = 2,
+    MAX_WRITE_BURST_LENGTH    = 16
+)(
+    // system signal
+    input  wire                             ACLK,
+    input  wire                             ARESET,
+    input  wire                             ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]      out_BUS_AWID,
+    output wire [2:0]                       out_BUS_AWSIZE,
+    output wire [1:0]                       out_BUS_AWBURST,
+    output wire [1:0]                       out_BUS_AWLOCK,
+    output wire [3:0]                       out_BUS_AWCACHE,
+    output wire [2:0]                       out_BUS_AWPROT,
+    output wire [3:0]                       out_BUS_AWQOS,
+    output wire [3:0]                       out_BUS_AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]  out_BUS_AWUSER,
+    output wire [BUS_ADDR_WIDTH-1:0]        out_BUS_AWADDR,
+    output wire [7:0]                       out_BUS_AWLEN,
+    output wire                             out_BUS_AWVALID,
+    input  wire                             in_BUS_AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]      out_BUS_WID,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]   out_BUS_WUSER,
+    output wire [BUS_DATA_WIDTH-1:0]        out_BUS_WDATA,
+    output wire [BUS_DATA_WIDTH/8-1:0]      out_BUS_WSTRB,
+    output wire                             out_BUS_WLAST,
+    output wire                             out_BUS_WVALID,
+    input  wire                             in_BUS_WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]      in_BUS_BID,
+    input  wire [1:0]                       in_BUS_BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]   in_BUS_BUSER,
+    input  wire                             in_BUS_BVALID,
+    output wire                             out_BUS_BREADY,
+    // write request
+    input  wire [BUS_ADDR_WIDTH-1:0]        in_HLS_AWADDR,
+    input  wire [31:0]                      in_HLS_AWLEN,
+    input  wire                             in_HLS_AWVALID,
+    output wire                             out_HLS_AWREADY,
+
+    input  wire [BUS_DATA_WIDTH-1:0]        in_HLS_WDATA,
+    input  wire [BUS_DATA_WIDTH/8-1:0]      in_HLS_WSTRB,
+    input  wire                             in_HLS_WVALID,
+    output wire                             out_HLS_WREADY,
+    output wire                             out_HLS_BVALID,
+    input  wire                             in_HLS_BREADY);
+
+//------------------------Parameter----------------------
+    localparam
+        BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+        BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+        NUM_WRITE_WIDTH = log2(MAX_WRITE_BURST_LENGTH),
+        BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+    function integer calc_data_width;
+        input integer x;
+        integer y;
+    begin
+        y = 8;
+        while (y < x) y = y * 2;
+        calc_data_width = y;
+    end
+    endfunction
+
+    function integer log2;
+        input integer x;
+        integer n, m;
+    begin
+        n = 0;
+        m = 1;
+        while (m < x) begin
+            n = n + 1;
+            m = m * 2;
+        end
+        log2 = n;
+    end
+    endfunction
+
+//------------------------Local signal-------------------
+    // AW channel
+    wire                                wreq_valid;
+    wire [BUS_ADDR_WIDTH - 1:0]         tmp_addr;
+    wire [31:0]                         tmp_len;
+    wire [7:0]                          awlen_tmp;
+    wire [BUS_ADDR_WIDTH - 1:0]         awaddr_tmp;
+    reg  [BUS_ADDR_WIDTH - 1:0]         start_addr;
+    reg  [BUS_ADDR_WIDTH - 1:0]         end_addr;
+    wire [BUS_ADDR_WIDTH - 1:0]         sect_addr;
+    reg  [BUS_ADDR_WIDTH - 1:0]         sect_addr_buf;
+    wire [11 - BUS_ADDR_ALIGN:0]        start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]        sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]        sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]        beat_len;
+    wire                                aw2b_info;
+    reg  [BUS_ADDR_WIDTH - 13:0]        sect_cnt;
+    wire                                fifo_burst_w;
+    wire                                fifo_resp_w;
+
+    wire [BUS_ADDR_WIDTH - 1:0]         AWADDR_Dummy;
+    wire [7:0]                          AWLEN_Dummy;
+    reg                                 AWVALID_Dummy;
+    wire                                AWREADY_Dummy;
+    wire                                ready_for_sect;
+    wire                                next_wreq;
+    wire                                ready_for_wreq;
+    reg                                 wreq_handling;
+    wire                                first_sect;
+    reg                                 last_sect_buf;
+    wire                                last_sect;
+    wire                                next_sect;
+    // W channel
+    wire                                next_data;
+    wire                                data_valid;
+    wire                                data_ready;
+    reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+    reg  [BUS_DATA_BYTES - 1:0]         strb_buf;
+    wire                                ready_for_data;
+
+    reg  [7:0]                          len_cnt;
+    wire [7:0]                          burst_len;
+    wire                                fifo_burst_ready;
+    wire                                next_burst;
+    wire                                burst_valid;
+    reg                                 WVALID_Dummy;
+    wire                                WREADY_Dummy;
+    reg                                 WLAST_Dummy;
+    //B channel
+    wire                                next_resp;
+    wire                                last_resp;
+    wire                                fifo_resp_ready;
+    wire                                need_wrsp;
+    wire                                resp_valid;
+    wire                                resp_ready;
+
+//------------------------AW channel begin---------------
+//------------------------Instantiation------------------
+    Stream2Mmap_mmap_m_axi_reg_slice #(
+        .DATA_WIDTH     (BUS_ADDR_WIDTH + 32)
+    ) rs_wreq (
+        .clk            (ACLK),
+        .reset          (ARESET),
+        .s_data         ({in_HLS_AWLEN, in_HLS_AWADDR}),
+        .s_valid        (in_HLS_AWVALID),
+        .s_ready        (out_HLS_AWREADY),
+        .m_data         ({tmp_len, tmp_addr}),
+        .m_valid        (wreq_valid),
+        .m_ready        (next_wreq));
+
+//------------------------Body---------------------------
+    assign ready_for_wreq = last_sect & next_sect | ~wreq_handling;
+    assign next_wreq      = wreq_valid & ready_for_wreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET) begin
+            start_addr <= 0;
+            end_addr   <= 0;
+            beat_len   <= 0;
+        end
+        else if (ACLK_EN) begin
+            if (next_wreq) begin
+                start_addr <= tmp_addr;
+                end_addr   <= tmp_addr + tmp_len;
+                beat_len   <= (tmp_len[11:0] + tmp_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+            end
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            wreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (wreq_valid && ~wreq_handling)
+                wreq_handling <= 1'b1;
+            else if (~wreq_valid && last_sect && next_sect)
+                wreq_handling <= 1'b0;
+        end
+    end
+
+    // 4k boundary
+    assign first_sect = (sect_cnt == start_addr[BUS_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr[BUS_ADDR_WIDTH-1:12]);
+    assign next_sect  = wreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr : {sect_cnt, {12{1'b0}}};
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                sect_cnt <= tmp_addr[BUS_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET) begin
+            sect_addr_buf <= 0;
+            sect_len_buf <= 0;
+            last_sect_buf <= 1'b0;
+        end
+        else if (ACLK_EN) begin
+            if (next_sect) begin
+                sect_addr_buf <= sect_addr;
+                sect_len_buf <= sect_len;
+                last_sect_buf <= last_sect;
+            end
+        end
+    end
+
+    // burst converter
+    assign out_BUS_AWID     = 0;
+    assign out_BUS_AWSIZE   = BUS_ADDR_ALIGN;
+    assign out_BUS_AWBURST  = 2'b01;
+    assign out_BUS_AWLOCK   = 2'b00;
+    assign out_BUS_AWCACHE  = C_CACHE_VALUE;
+    assign out_BUS_AWPROT   = C_PROT_VALUE;
+    assign out_BUS_AWUSER   = C_USER_VALUE;
+    assign out_BUS_AWQOS    = 4'b0000;
+    assign out_BUS_AWREGION = 4'b0000;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) begin : must_one_burst
+        assign AWADDR_Dummy   = {sect_addr_buf[BUS_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign AWLEN_Dummy    = sect_len_buf;
+
+        assign ready_for_sect = ~(AWVALID_Dummy && ~AWREADY_Dummy) && fifo_burst_ready && fifo_resp_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_sect && AWREADY_Dummy)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_sect;
+        assign aw2b_info   = last_sect;
+
+        assign fifo_burst_w = next_sect;
+        assign awaddr_tmp   = sect_addr[BUS_ADDR_WIDTH - 1:0];
+        assign awlen_tmp    = sect_len;
+    end
+    else begin : could_multi_bursts
+        reg  [BUS_ADDR_WIDTH - 1:0]                         awaddr_buf;
+        reg  [7:0]                                          awlen_buf;
+        reg  [11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN : 0]    loop_cnt;
+        reg                                                 sect_handling;
+        wire                                                last_loop;
+        wire                                                next_loop;
+        wire                                                ready_for_loop;
+
+        assign AWADDR_Dummy   = awaddr_buf;
+        assign AWLEN_Dummy    = awlen_buf;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_WRITE_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(AWVALID_Dummy && ~AWREADY_Dummy) && fifo_burst_ready && fifo_resp_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (wreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~wreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign awaddr_tmp = (loop_cnt == 0)? sect_addr_buf[BUS_ADDR_WIDTH - 1:0] : (awaddr_buf + ((awlen_buf + 1) << BUS_ADDR_ALIGN));
+        assign awlen_tmp  = (NUM_WRITE_WIDTH == 0)? 0 :
+                    (last_loop)? sect_len_buf[NUM_WRITE_WIDTH - 1:0] : { NUM_WRITE_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET) begin
+                awaddr_buf <= 0;
+                awlen_buf <= 0;
+            end
+            else if (ACLK_EN) begin
+                if (next_loop) begin
+                    awaddr_buf <= {awaddr_tmp[BUS_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+                    awlen_buf <= awlen_tmp;
+                end
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_loop && AWREADY_Dummy)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_loop;
+        assign fifo_burst_w = next_loop;
+        assign aw2b_info = last_loop && last_sect_buf;
+    end
+    endgenerate
+//------------------------AW channel end-----------------
+
+//------------------------W channel begin----------------
+//------------------------Instantiation------------------
+
+    Stream2Mmap_mmap_m_axi_fifo #(
+        .DATA_WIDTH     (8),
+        .ADDR_WIDTH     (log2(NUM_WRITE_OUTSTANDING)),
+        .DEPTH          (NUM_WRITE_OUTSTANDING)
+    ) fifo_burst (
+        .clk            (ACLK),
+        .reset          (ARESET),
+        .clk_en         (ACLK_EN),
+        .if_full_n      (fifo_burst_ready),
+        .if_write       (fifo_burst_w),
+        .if_din         (awlen_tmp),
+        .if_empty_n     (burst_valid),
+        .if_read        (next_burst),
+        .if_dout        (burst_len),
+        .if_num_data_valid());
+
+//------------------------Body---------------------------
+
+    assign out_BUS_WUSER    = C_USER_VALUE;
+    assign out_BUS_WID      = 0;
+    assign out_HLS_WREADY   = data_ready;
+
+    assign data_valid       = in_HLS_WVALID;
+    assign data_ready       = burst_valid && ready_for_data;
+    assign next_data        = data_ready && data_valid;
+    assign next_burst       = (len_cnt == burst_len) && next_data;
+    assign ready_for_data   = ~WVALID_Dummy || WREADY_Dummy;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET) begin
+            strb_buf <= 0;
+            data_buf <= 0;
+        end
+        if (ACLK_EN) begin
+            if (next_data) begin
+                data_buf <= in_HLS_WDATA;
+                strb_buf <= in_HLS_WSTRB;
+            end
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            WVALID_Dummy <= 1'b0;
+        else if (ACLK_EN) begin
+            if (next_data)
+                WVALID_Dummy <= 1'b1;
+            else if (ready_for_data)
+                WVALID_Dummy <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            WLAST_Dummy <= 0;
+        else if (ACLK_EN) begin
+            if (next_burst)
+                WLAST_Dummy <= 1;
+            else if (ready_for_data)
+                WLAST_Dummy <= 0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            len_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_burst)
+                len_cnt <= 0;
+            else if (next_data)
+                len_cnt <= len_cnt + 1;
+        end
+    end
+//------------------------W channel end------------------
+
+    // Write throttling unit
+    Stream2Mmap_mmap_m_axi_throttle #(
+        .CONSERVATIVE(CONSERVATIVE),
+        .USED_FIX(0),
+        .ADDR_WIDTH(BUS_ADDR_WIDTH),
+        .DATA_WIDTH(BUS_DATA_WIDTH),
+        .DEPTH(MAX_WRITE_BURST_LENGTH),
+        .MAXREQS(NUM_WRITE_OUTSTANDING),
+        .AVERAGE_MODE(0)
+    ) wreq_throttle (
+        .clk(ACLK),
+        .reset(ARESET),
+        .clk_en(ACLK_EN),
+        // internal
+        .in_TOP_AWADDR(AWADDR_Dummy),
+        .in_TOP_AWLEN(AWLEN_Dummy),
+        .in_TOP_AWVALID(AWVALID_Dummy),
+        .out_TOP_AWREADY(AWREADY_Dummy),
+
+        .in_TOP_WDATA(data_buf),
+        .in_TOP_WSTRB(strb_buf),
+        .in_TOP_WLAST(WLAST_Dummy),
+        .in_TOP_WVALID(WVALID_Dummy),
+        .out_TOP_WREADY(WREADY_Dummy),
+
+        // AXI BUS
+        .out_BUS_AWADDR(out_BUS_AWADDR),
+        .out_BUS_AWLEN(out_BUS_AWLEN),
+        .out_BUS_AWVALID(out_BUS_AWVALID),
+        .in_BUS_AWREADY(in_BUS_AWREADY),
+
+        .out_BUS_WDATA(out_BUS_WDATA),
+        .out_BUS_WSTRB(out_BUS_WSTRB),
+        .out_BUS_WLAST(out_BUS_WLAST),
+        .out_BUS_WVALID(out_BUS_WVALID),
+        .in_BUS_WREADY(in_BUS_WREADY)
+    );
+
+//------------------------B channel begin----------------
+//------------------------Instantiation------------------
+    Stream2Mmap_mmap_m_axi_reg_slice #(
+        .DATA_WIDTH     (1)
+    ) rs_resp (
+        .clk            (ACLK),
+        .reset          (ARESET),
+        .s_data         (1'b1),
+        .s_valid        (in_BUS_BVALID),
+        .s_ready        (out_BUS_BREADY),
+        .m_data         (),
+        .m_valid        (resp_valid),
+        .m_ready        (resp_ready));
+
+    Stream2Mmap_mmap_m_axi_fifo #(
+        .DATA_WIDTH     (1),
+        .ADDR_WIDTH     (log2(NUM_WRITE_OUTSTANDING)),
+        .DEPTH          (NUM_WRITE_OUTSTANDING)
+    ) fifo_resp (
+        .clk            (ACLK),
+        .reset          (ARESET),
+        .clk_en         (ACLK_EN),
+        .if_full_n      (fifo_resp_ready),
+        .if_write       (fifo_resp_w),
+        .if_din         (aw2b_info),
+        .if_empty_n     (need_wrsp),
+        .if_read        (next_resp),
+        .if_dout        (last_resp),
+        .if_num_data_valid());
+//------------------------Body---------------------------
+
+    assign resp_ready = need_wrsp && (in_HLS_BREADY || (last_resp === 1'b0));
+    assign next_resp  = resp_ready && resp_valid;
+
+    assign out_HLS_BVALID = resp_valid && (last_resp === 1'b1 ) ;
+
+//------------------------B channel end------------------
+endmodule
+
+module Stream2Mmap_mmap_m_axi_throttle
+#(parameter
+    CONSERVATIVE   = 0,
+    USED_FIX       = 0,
+    FIX_VALUE      = 4,
+    ADDR_WIDTH     = 32,
+    DATA_WIDTH     = 32,
+    DEPTH          = 16,
+    MAXREQS        = 16,
+    AVERAGE_MODE   = 0
+)(
+    input  wire                      clk,
+    input  wire                      reset,
+    input  wire                      clk_en,
+
+    input  wire [ADDR_WIDTH-1:0]     in_TOP_AWADDR,
+    input  wire [7:0]                in_TOP_AWLEN,
+    input  wire                      in_TOP_AWVALID,
+    output wire                      out_TOP_AWREADY,
+    input  wire [DATA_WIDTH-1:0]     in_TOP_WDATA,
+    input  wire [DATA_WIDTH/8-1:0]   in_TOP_WSTRB,
+    input  wire                      in_TOP_WLAST,
+    input  wire                      in_TOP_WVALID,
+    output wire                      out_TOP_WREADY,
+
+    output wire [ADDR_WIDTH-1:0]     out_BUS_AWADDR,
+    output wire [7:0]                out_BUS_AWLEN,
+    output wire                      out_BUS_AWVALID,
+    input  wire                      in_BUS_AWREADY,
+    output wire [DATA_WIDTH-1:0]     out_BUS_WDATA,
+    output wire [DATA_WIDTH/8-1:0]   out_BUS_WSTRB,
+    output wire                      out_BUS_WLAST,
+    output wire                      out_BUS_WVALID,
+    input  wire                      in_BUS_WREADY);
+
+    function integer log2;
+        input integer x;
+        integer n, m;
+    begin
+        n = 0;
+        m = 1;
+        while (m < x) begin
+            n = n + 1;
+            m = m * 2;
+        end
+        log2 = n;
+    end
+    endfunction
+// aggressive mode
+    generate
+    if (CONSERVATIVE == 0) begin
+        localparam threshold = (USED_FIX)? FIX_VALUE-1 : 0;
+
+        wire                req_en;
+        wire                handshake;
+        wire  [7:0]         load_init;
+        reg   [8:0]         throttl_cnt;
+
+        // AW Channel
+        assign out_BUS_AWADDR = in_TOP_AWADDR;
+        assign out_BUS_AWLEN  = in_TOP_AWLEN;
+
+        // W Channel
+        assign out_BUS_WDATA  = in_TOP_WDATA;
+        assign out_BUS_WSTRB  = in_TOP_WSTRB;
+        assign out_BUS_WLAST  = in_TOP_WLAST;
+        assign out_BUS_WVALID = in_TOP_WVALID & (throttl_cnt > 0);
+        assign out_TOP_WREADY = in_BUS_WREADY & (throttl_cnt > 0);
+
+        if (USED_FIX) begin
+            assign load_init = FIX_VALUE-1;
+            assign handshake = 1'b1;
+        end else if (AVERAGE_MODE) begin
+            assign load_init = in_TOP_AWLEN;
+            assign handshake = 1'b1;
+        end else begin
+            assign load_init = in_TOP_AWLEN;
+            assign handshake = out_BUS_WVALID & in_BUS_WREADY;
+        end
+
+        assign out_BUS_AWVALID = in_TOP_AWVALID & req_en;
+        assign out_TOP_AWREADY = in_BUS_AWREADY & req_en;
+        assign req_en = (throttl_cnt == 0) | (throttl_cnt == 1 & handshake);
+
+        always @(posedge clk)
+        begin
+            if (reset)
+                throttl_cnt <= 0;
+            else if (clk_en) begin
+                if (in_TOP_AWLEN >= threshold && req_en && in_TOP_AWVALID && in_BUS_AWREADY)
+                    throttl_cnt <= load_init + 1'b1; //load
+                else if (throttl_cnt > 0 && handshake)
+                    throttl_cnt <= throttl_cnt - 1'b1;
+            end
+        end
+
+    end
+// conservative mode
+    else begin
+        localparam CNT_WIDTH = ((DEPTH < 4)? 2 : log2(DEPTH)) + 1;
+
+        // Instantiation for reg slice for AW channel
+        wire                        rs_req_ready;
+        wire                        rs_req_valid;
+        wire [ADDR_WIDTH + 7 : 0]   rs_req_in;
+        wire [ADDR_WIDTH + 7 : 0]   rs_req_out;
+
+        Stream2Mmap_mmap_m_axi_reg_slice #(
+            .DATA_WIDTH     (ADDR_WIDTH + 8)
+        ) rs_req (
+            .clk            (clk),
+            .reset          (reset),
+            .s_data         (rs_req_in),
+            .s_valid        (rs_req_valid),
+            .s_ready        (rs_req_ready),
+            .m_data         (rs_req_out),
+            .m_valid        (out_BUS_AWVALID),
+            .m_ready        (in_BUS_AWREADY));
+
+        wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_in;
+        wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_out;
+        wire  [ADDR_WIDTH + 7 : 0]              req_in;
+        reg                                     req_en;
+        wire                                    data_en;
+        wire                                    fifo_valid;
+        wire                                    read_fifo;
+        wire                                    req_fifo_valid;
+        wire                                    read_req;
+        wire                                    data_push;
+        wire                                    data_pop;
+        reg                                     flying_req;
+        reg   [CNT_WIDTH-1 : 0]                 last_cnt;
+
+        //AW Channel
+        assign req_in   = {in_TOP_AWLEN, in_TOP_AWADDR};
+        assign out_BUS_AWADDR = rs_req_out[ADDR_WIDTH-1 : 0];
+        assign out_BUS_AWLEN  = rs_req_out[ADDR_WIDTH+7 : ADDR_WIDTH];
+        assign rs_req_valid = req_fifo_valid & req_en;
+
+        assign read_req      = rs_req_ready & req_en;
+
+        always @(*)
+        begin
+            if (~flying_req & data_en)
+                req_en <= 1;
+            else if (flying_req & (out_BUS_WLAST & data_pop) & (last_cnt[CNT_WIDTH-1:1] != 0))
+                req_en <= 1;
+            else
+                req_en <= 0;
+        end
+
+        always @(posedge clk)
+        begin
+            if (reset)
+                flying_req <= 0;
+            else if (clk_en) begin
+                if (rs_req_valid & rs_req_ready)
+                    flying_req <= 1;
+                else if (out_BUS_WLAST & data_pop)
+                    flying_req <= 0;
+            end
+        end
+
+        Stream2Mmap_mmap_m_axi_fifo #(
+            .DATA_WIDTH     (ADDR_WIDTH + 8),
+            .ADDR_WIDTH     (log2(MAXREQS)),
+            .DEPTH          (MAXREQS)
+        ) req_fifo (
+            .clk            (clk),
+            .reset          (reset),
+            .clk_en         (clk_en),
+            .if_full_n      (out_TOP_AWREADY),
+            .if_write       (in_TOP_AWVALID),
+            .if_din         (req_in),
+            .if_empty_n     (req_fifo_valid),
+            .if_read        (read_req),
+            .if_dout        (rs_req_in),
+            .if_num_data_valid());
+
+        //W Channel
+        assign data_in  = {in_TOP_WLAST, in_TOP_WSTRB, in_TOP_WDATA};
+        assign out_BUS_WDATA = data_out[DATA_WIDTH-1 : 0];
+        assign out_BUS_WSTRB = data_out[DATA_WIDTH+DATA_WIDTH/8-1 : DATA_WIDTH];
+        assign out_BUS_WLAST = data_out[DATA_WIDTH+DATA_WIDTH/8];
+        assign out_BUS_WVALID = fifo_valid & data_en & flying_req;
+
+        assign data_en   = last_cnt != 0;
+        assign data_push = in_TOP_WVALID & out_TOP_WREADY;
+        assign data_pop  = fifo_valid & read_fifo;
+        assign read_fifo = in_BUS_WREADY & data_en & flying_req;
+
+        always @(posedge clk)
+        begin
+            if (reset)
+                last_cnt <= 0;
+            else if (clk_en) begin
+                if ((in_TOP_WLAST & data_push) && ~(out_BUS_WLAST & data_pop))
+                    last_cnt <= last_cnt + 1;
+                else if (~(in_TOP_WLAST & data_push) && (out_BUS_WLAST & data_pop))
+                    last_cnt <= last_cnt - 1;
+            end
+        end
+
+        Stream2Mmap_mmap_m_axi_fifo #(
+            .DATA_WIDTH     (DATA_WIDTH + DATA_WIDTH/8 + 1),
+            .ADDR_WIDTH     (log2(DEPTH)),
+            .DEPTH          (DEPTH)
+        ) data_fifo (
+            .clk            (clk),
+            .reset          (reset),
+            .clk_en         (clk_en),
+            .if_full_n      (out_TOP_WREADY),
+            .if_write       (in_TOP_WVALID),
+            .if_din         (data_in),
+            .if_empty_n     (fifo_valid),
+            .if_read        (read_fifo),
+            .if_dout        (data_out),
+            .if_num_data_valid());
+
+        end
+    endgenerate
+
+endmodule
+
+
+module Stream2Mmap_mmap_m_axi_reg_slice
+#(parameter
+    DATA_WIDTH = 8
+) (
+    // system signals
+    input  wire                  clk,
+    input  wire                  reset,
+    // slave side
+    input  wire [DATA_WIDTH-1:0] s_data,
+    input  wire                  s_valid,
+    output wire                  s_ready,
+    // master side
+    output wire [DATA_WIDTH-1:0] m_data,
+    output wire                  m_valid,
+    input  wire                  m_ready);
+    //------------------------Parameter----------------------
+    // state
+    localparam [1:0]
+        ZERO = 2'b10,
+        ONE  = 2'b11,
+        TWO  = 2'b01;
+    //------------------------Local signal-------------------
+    reg  [DATA_WIDTH-1:0] data_p1;
+    reg  [DATA_WIDTH-1:0] data_p2;
+    wire         load_p1;
+    wire         load_p2;
+    wire         load_p1_from_p2;
+    reg          s_ready_t;
+    reg  [1:0]   state;
+    reg  [1:0]   next;
+    //------------------------Body---------------------------
+    assign s_ready = s_ready_t;
+    assign m_data  = data_p1;
+    assign m_valid = state[0];
+
+    assign load_p1 = (state == ZERO && s_valid) ||
+                    (state == ONE && s_valid && m_ready) ||
+                    (state == TWO && m_ready);
+    assign load_p2 = s_valid & s_ready;
+    assign load_p1_from_p2 = (state == TWO);
+
+    // data_p1
+    always @(posedge clk) begin
+        if (load_p1) begin
+            if (load_p1_from_p2)
+                data_p1 <= data_p2;
+            else
+                data_p1 <= s_data;
+        end
+    end
+
+    // data_p2
+    always @(posedge clk) begin
+        if (load_p2) data_p2 <= s_data;
+    end
+
+    // s_ready_t
+    always @(posedge clk) begin
+        if (reset)
+            s_ready_t <= 1'b0;
+        else if (state == ZERO)
+            s_ready_t <= 1'b1;
+        else if (state == ONE && next == TWO)
+            s_ready_t <= 1'b0;
+        else if (state == TWO && next == ONE)
+            s_ready_t <= 1'b1;
+    end
+
+    // state
+    always @(posedge clk) begin
+        if (reset)
+            state <= ZERO;
+        else
+            state <= next;
+    end
+
+    // next
+    always @(*) begin
+        case (state)
+            ZERO:
+                if (s_valid & s_ready)
+                    next = ONE;
+                else
+                    next = ZERO;
+            ONE:
+                if (~s_valid & m_ready)
+                    next = ZERO;
+                else if (s_valid & ~m_ready)
+                    next = TWO;
+                else
+                    next = ONE;
+            TWO:
+                if (m_ready)
+                    next = ONE;
+                else
+                    next = TWO;
+            default:
+                next = ZERO;
+        endcase
+    end
+endmodule
+
+module Stream2Mmap_mmap_m_axi_fifo
+#(parameter
+    MEM_STYLE   = "shiftreg",
+    DATA_WIDTH = 32,
+    ADDR_WIDTH = 5,
+    DEPTH      = 32
+) (
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire                  clk_en,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+
+    // read
+    output wire                  if_empty_n,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout,
+    output wire [ADDR_WIDTH:0]   if_num_data_valid);
+
+//------------------------Local signal-------------------
+
+    wire                  push;
+    wire                  pop;
+    reg                   full_n = 1'b1;
+    reg                   empty_n = 1'b0;
+    reg                   dout_vld = 1'b0;
+    reg  [ADDR_WIDTH:0]   mOutPtr = 1'b0;
+
+//------------------------Instantiation------------------
+    generate
+    if ((MEM_STYLE == "shiftreg") || (DEPTH == 1)) begin
+        reg  [ADDR_WIDTH-1:0] raddr = 1'b0;
+
+        Stream2Mmap_mmap_m_axi_srl
+        #(  .DATA_WIDTH     (DATA_WIDTH),
+            .ADDR_WIDTH     (ADDR_WIDTH),
+            .DEPTH          (DEPTH))
+        U_fifo_srl(
+            .clk            (clk),
+            .reset          (reset),
+            .clk_en         (clk_en),
+            .we             (push),
+            .din            (if_din),
+            .raddr          (raddr),
+            .re             (pop),
+            .dout           (if_dout)
+        );
+
+        // raddr
+        always @(posedge clk) begin
+            if (reset == 1'b1)
+                raddr <= 1'b0;
+            else if (clk_en) begin
+                if (push & ~pop & empty_n)
+                    raddr <= raddr + 1'b1;
+                else if (~push & pop && raddr != 0)
+                    raddr <= raddr - 1'b1;
+            end
+        end
+
+    end else begin
+        reg  [ADDR_WIDTH-1:0] waddr = 1'b0;
+        reg  [ADDR_WIDTH-1:0] raddr = 1'b0;
+        wire [ADDR_WIDTH-1:0] wnext;
+        wire [ADDR_WIDTH-1:0] rnext;
+
+        Stream2Mmap_mmap_m_axi_mem
+        #(  .MEM_STYLE      (MEM_STYLE),
+            .DATA_WIDTH     (DATA_WIDTH),
+            .ADDR_WIDTH     (ADDR_WIDTH),
+            .DEPTH          (DEPTH))
+        U_fifo_mem(
+            .clk            (clk),
+            .reset          (reset),
+            .clk_en         (clk_en),
+            .we             (push),
+            .waddr          (waddr),
+            .din            (if_din),
+            .raddr          (rnext),
+            .re             (pop),
+            .dout           (if_dout)
+        );
+
+        assign wnext =  !push                ? waddr :
+                        (waddr == DEPTH - 2) ? 1'b0  :
+                        waddr + 1'b1;
+        assign rnext =  !pop                 ? raddr :
+                        (raddr == DEPTH - 2) ? 1'b0  :
+                        raddr + 1'b1;
+
+        // waddr
+        always @(posedge clk) begin
+            if (reset == 1'b1)
+                waddr <= 1'b0;
+            else if (clk_en)
+                waddr <= wnext;
+        end
+
+        // raddr
+        always @(posedge clk) begin
+            if (reset == 1'b1)
+                raddr <= 1'b0;
+            else if (clk_en)
+                raddr <= rnext;
+        end
+    end
+    endgenerate
+
+//------------------------Body---------------------------
+    assign if_num_data_valid = dout_vld ? mOutPtr + 1'b1 : 'b0;
+
+    generate if (DEPTH == 1) begin
+        assign if_full_n  = !dout_vld;
+        assign if_empty_n = dout_vld;
+        assign push = !dout_vld & if_write;
+        assign pop  = !dout_vld & if_write;
+
+    end else begin
+
+        assign if_full_n  = full_n;
+        assign if_empty_n = dout_vld;
+        assign push = full_n & if_write;
+        assign pop  = empty_n & (if_read | ~dout_vld);
+
+        // mOutPtr
+        always @(posedge clk) begin
+            if (reset == 1'b1)
+                mOutPtr <= 'b0;
+            else if (clk_en)
+                if (push & ~pop)
+                    mOutPtr <= mOutPtr + 1'b1;
+                else if (~push & pop)
+                    mOutPtr <= mOutPtr - 1'b1;
+        end
+
+        // full_n
+        always @(posedge clk) begin
+            if (reset == 1'b1)
+                full_n <= 1'b1;
+            else if (clk_en)
+                if (push & ~pop)
+                    full_n <= (mOutPtr != DEPTH - 2);
+                else if (~push & pop)
+                    full_n <= 1'b1;
+        end
+
+        // empty_n
+        always @(posedge clk)
+        begin
+            if (reset)
+                empty_n <= 1'b0;
+            else if (clk_en) begin
+                if (push & ~pop)
+                    empty_n <= 1'b1;
+                else if (~push & pop)
+                    empty_n <= (mOutPtr != 1'b1);
+            end
+        end
+    end
+    endgenerate
+
+    // dout_vld
+    always @(posedge clk) begin
+        if (reset == 1'b1)
+            dout_vld <= 1'b0;
+        else if (clk_en)
+            if (pop)
+                dout_vld <= 1'b1;
+            else if (if_read)
+                dout_vld <= 1'b0;
+    end
+
+endmodule
+
+module Stream2Mmap_mmap_m_axi_srl
+#(parameter
+        DATA_WIDTH  = 32,
+        ADDR_WIDTH  = 6,
+        DEPTH       = 63
+    )(
+        input  wire                  clk,
+        input  wire                  reset,
+        input  wire                  clk_en,
+        input  wire                  we,
+        input  wire [DATA_WIDTH-1:0] din,
+        input  wire [ADDR_WIDTH-1:0] raddr,
+        input  wire                  re,
+        output reg  [DATA_WIDTH-1:0] dout
+    );
+
+    generate
+    if (DEPTH > 1) begin
+        reg  [DATA_WIDTH-1:0] mem[0:DEPTH-2];
+
+        integer i;
+        always @(posedge clk)
+        begin
+            if (clk_en & we) begin
+                for (i = 0; i < DEPTH - 2; i = i + 1) begin
+                    mem[i+1] <= mem[i];
+                end
+                mem[0] <= din;
+            end
+        end
+
+        always @(posedge clk)
+        begin
+            if (reset)
+                dout <= 0;
+            else if (clk_en & re) begin
+                dout <= mem[raddr];
+            end
+        end
+    end
+    else begin
+        always @(posedge clk)
+        begin
+            if (reset)
+                dout <= 0;
+            else if (clk_en & we) begin
+                dout <= din;
+            end
+        end
+    end
+    endgenerate
+
+endmodule
+
+module Stream2Mmap_mmap_m_axi_mem
+#(parameter
+    MEM_STYLE   = "auto",
+    DATA_WIDTH  = 32,
+    ADDR_WIDTH  = 6,
+    DEPTH       = 63
+)(
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire                  clk_en,
+    input  wire                  we,
+    input  wire [ADDR_WIDTH-1:0] waddr,
+    input  wire [DATA_WIDTH-1:0] din,
+    input  wire [ADDR_WIDTH-1:0] raddr,
+    input  wire                  re,
+    output reg  [DATA_WIDTH-1:0] dout);
+
+    (* ram_style = MEM_STYLE, rw_addr_collision = "yes" *)
+    reg  [DATA_WIDTH-1:0] mem[0:DEPTH-2];
+    reg  [ADDR_WIDTH-1:0] raddr_reg;
+
+    //write to ram
+    always @(posedge clk) begin
+        if (clk_en & we)
+            mem[waddr] <= din;
+    end
+
+    //buffer the raddr
+    always @(posedge clk) begin
+        if (clk_en)
+            raddr_reg <= raddr;
+    end
+
+    //read from ram
+    always @(posedge clk) begin
+        if (reset)
+            dout <= 0;
+        else if (clk_en & re)
+            dout <= mem[raddr_reg];
+    end
+endmodule
diff --git a/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/a_axi_write_broadcastor_1_to_3.v b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/a_axi_write_broadcastor_1_to_3.v
new file mode 100644
index 00000000..d84fe57e
--- /dev/null
+++ b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/a_axi_write_broadcastor_1_to_3.v
@@ -0,0 +1,269 @@
+
+module a_axi_write_broadcastor_1_to_3 (
+  ap_clk,
+
+  s_axi_control_AWVALID_slr_0,
+  s_axi_control_AWREADY_slr_0,
+  s_axi_control_AWADDR_slr_0,
+  s_axi_control_WVALID_slr_0,
+  s_axi_control_WREADY_slr_0,
+  s_axi_control_WDATA_slr_0,
+  s_axi_control_WSTRB_slr_0,
+  s_axi_control_AWVALID_slr_1,
+  s_axi_control_AWREADY_slr_1,
+  s_axi_control_AWADDR_slr_1,
+  s_axi_control_WVALID_slr_1,
+  s_axi_control_WREADY_slr_1,
+  s_axi_control_WDATA_slr_1,
+  s_axi_control_WSTRB_slr_1,
+  s_axi_control_AWVALID_slr_2,
+  s_axi_control_AWREADY_slr_2,
+  s_axi_control_AWADDR_slr_2,
+  s_axi_control_WVALID_slr_2,
+  s_axi_control_WREADY_slr_2,
+  s_axi_control_WDATA_slr_2,
+  s_axi_control_WSTRB_slr_2,
+  s_axi_control_AWVALID,
+  s_axi_control_AWREADY,
+  s_axi_control_AWADDR,
+  s_axi_control_WVALID,
+  s_axi_control_WREADY,
+  s_axi_control_WDATA,
+  s_axi_control_WSTRB
+);
+  parameter C_S_AXI_CONTROL_DATA_WIDTH = 32;
+  parameter C_S_AXI_CONTROL_ADDR_WIDTH = 9;
+  parameter C_S_AXI_DATA_WIDTH = 32;
+  parameter C_S_AXI_CONTROL_WSTRB_WIDTH = 32 / 8;
+  parameter C_S_AXI_WSTRB_WIDTH = 32 / 8;
+
+  input ap_clk;
+
+  input s_axi_control_AWVALID;
+  output s_axi_control_AWREADY;
+  input [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR;
+  input s_axi_control_WVALID;
+  output s_axi_control_WREADY;
+  input [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA;
+  input [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB;
+
+  output s_axi_control_AWVALID_slr_0;
+  input s_axi_control_AWREADY_slr_0;
+  output [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR_slr_0;
+  output s_axi_control_WVALID_slr_0;
+  input s_axi_control_WREADY_slr_0;
+  output [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA_slr_0;
+  output [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB_slr_0;
+
+  output s_axi_control_AWVALID_slr_1;
+  input s_axi_control_AWREADY_slr_1;
+  output [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR_slr_1;
+  output s_axi_control_WVALID_slr_1;
+  input s_axi_control_WREADY_slr_1;
+  output [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA_slr_1;
+  output [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB_slr_1;
+
+  output s_axi_control_AWVALID_slr_2;
+  input s_axi_control_AWREADY_slr_2;
+  output [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR_slr_2;
+  output s_axi_control_WVALID_slr_2;
+  input s_axi_control_WREADY_slr_2;
+  output [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA_slr_2;
+  output [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB_slr_2;
+
+  wire s_axi_control_AWVALID_slr_0_inner;
+  wire s_axi_control_AWREADY_slr_0_inner;
+  wire [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR_slr_0_inner;
+  wire s_axi_control_WVALID_slr_0_inner;
+  wire s_axi_control_WREADY_slr_0_inner;
+  wire [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA_slr_0_inner;
+  wire [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB_slr_0_inner;
+
+  wire s_axi_control_AWVALID_slr_1_inner;
+  wire s_axi_control_AWREADY_slr_1_inner;
+  wire [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR_slr_1_inner;
+  wire s_axi_control_WVALID_slr_1_inner;
+  wire s_axi_control_WREADY_slr_1_inner;
+  wire [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA_slr_1_inner;
+  wire [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB_slr_1_inner;
+
+  wire s_axi_control_AWVALID_slr_2_inner;
+  wire s_axi_control_AWREADY_slr_2_inner;
+  wire [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR_slr_2_inner;
+  wire s_axi_control_WVALID_slr_2_inner;
+  wire s_axi_control_WREADY_slr_2_inner;
+  wire [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA_slr_2_inner;
+  wire [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB_slr_2_inner;
+
+  // broadcast the AW channel
+  assign s_axi_control_AWADDR_slr_0_inner = s_axi_control_AWADDR;
+  assign s_axi_control_AWADDR_slr_1_inner = s_axi_control_AWADDR;
+  assign s_axi_control_AWADDR_slr_2_inner = s_axi_control_AWADDR;
+
+  assign s_axi_control_AWVALID_slr_0_inner = s_axi_control_AWVALID;
+  assign s_axi_control_AWVALID_slr_1_inner = s_axi_control_AWVALID;
+  assign s_axi_control_AWVALID_slr_2_inner = s_axi_control_AWVALID;
+
+  assign s_axi_control_AWREADY =  s_axi_control_AWREADY_slr_0_inner &
+                                  s_axi_control_AWREADY_slr_1_inner &
+                                  s_axi_control_AWREADY_slr_2_inner;
+
+  // broadcast the W channel
+  assign s_axi_control_WDATA_slr_0_inner = s_axi_control_WDATA;
+  assign s_axi_control_WDATA_slr_1_inner = s_axi_control_WDATA;
+  assign s_axi_control_WDATA_slr_2_inner = s_axi_control_WDATA;
+
+  assign s_axi_control_WSTRB_slr_0_inner = s_axi_control_WSTRB;
+  assign s_axi_control_WSTRB_slr_1_inner = s_axi_control_WSTRB;
+  assign s_axi_control_WSTRB_slr_2_inner = s_axi_control_WSTRB;
+
+  assign s_axi_control_WVALID_slr_0_inner = s_axi_control_WVALID;
+  assign s_axi_control_WVALID_slr_1_inner = s_axi_control_WVALID;
+  assign s_axi_control_WVALID_slr_2_inner = s_axi_control_WVALID;
+
+  assign s_axi_control_WREADY = s_axi_control_WREADY_slr_0_inner &
+                                s_axi_control_WREADY_slr_1_inner &
+                                s_axi_control_WREADY_slr_2_inner;
+
+  relay_station
+  #(
+    .DATA_WIDTH(C_S_AXI_CONTROL_ADDR_WIDTH),
+    .DEPTH(24),
+    .ADDR_WIDTH(1),
+    .LEVEL( 3 )
+  )
+  AW_pipeline_slr_0
+  (
+    .clk        (ap_clk),
+    .reset      (1'b0),
+    .if_read_ce (1'b1),
+    .if_write_ce(1'b1),
+
+    .if_din     (s_axi_control_AWADDR_slr_0_inner),
+    .if_full_n  (s_axi_control_AWREADY_slr_0_inner),
+    .if_write   (s_axi_control_AWVALID_slr_0_inner),
+
+    .if_dout    (s_axi_control_AWADDR_slr_0),
+    .if_empty_n (s_axi_control_AWVALID_slr_0),
+    .if_read    (s_axi_control_AWREADY_slr_0)
+  );
+
+  relay_station
+  #(
+    .DATA_WIDTH(C_S_AXI_CONTROL_DATA_WIDTH + C_S_AXI_CONTROL_WSTRB_WIDTH),
+    .DEPTH(24),
+    .ADDR_WIDTH(1),
+    .LEVEL( 3 )
+  )
+  W_pipeline_slr_0
+  (
+    .clk        (ap_clk),
+    .reset      (1'b0),
+    .if_read_ce (1'b1),
+    .if_write_ce(1'b1),
+
+    .if_din     ({s_axi_control_WDATA_slr_0_inner, s_axi_control_WSTRB_slr_0_inner}),
+    .if_full_n  (s_axi_control_WREADY_slr_0_inner),
+    .if_write   (s_axi_control_WVALID_slr_0_inner),
+
+    .if_dout    ({s_axi_control_WDATA_slr_0, s_axi_control_WSTRB_slr_0}),
+    .if_empty_n (s_axi_control_WVALID_slr_0),
+    .if_read    (s_axi_control_WREADY_slr_0)
+  );
+
+
+  relay_station
+  #(
+    .DATA_WIDTH(C_S_AXI_CONTROL_ADDR_WIDTH),
+    .DEPTH(24),
+    .ADDR_WIDTH(1),
+    .LEVEL( 3 )
+  )
+  AW_pipeline_slr_1
+  (
+    .clk        (ap_clk),
+    .reset      (1'b0),
+    .if_read_ce (1'b1),
+    .if_write_ce(1'b1),
+
+    .if_din     (s_axi_control_AWADDR_slr_1_inner),
+    .if_full_n  (s_axi_control_AWREADY_slr_1_inner),
+    .if_write   (s_axi_control_AWVALID_slr_1_inner),
+
+    .if_dout    (s_axi_control_AWADDR_slr_1),
+    .if_empty_n (s_axi_control_AWVALID_slr_1),
+    .if_read    (s_axi_control_AWREADY_slr_1)
+  );
+
+  relay_station
+  #(
+    .DATA_WIDTH(C_S_AXI_CONTROL_DATA_WIDTH + C_S_AXI_CONTROL_WSTRB_WIDTH),
+    .DEPTH(24),
+    .ADDR_WIDTH(1),
+    .LEVEL( 3 )
+  )
+  W_pipeline_slr_1
+  (
+    .clk        (ap_clk),
+    .reset      (1'b0),
+    .if_read_ce (1'b1),
+    .if_write_ce(1'b1),
+
+    .if_din     ({s_axi_control_WDATA_slr_1_inner, s_axi_control_WSTRB_slr_1_inner}),
+    .if_full_n  (s_axi_control_WREADY_slr_1_inner),
+    .if_write   (s_axi_control_WVALID_slr_1_inner),
+
+    .if_dout    ({s_axi_control_WDATA_slr_1, s_axi_control_WSTRB_slr_1}),
+    .if_empty_n (s_axi_control_WVALID_slr_1),
+    .if_read    (s_axi_control_WREADY_slr_1)
+  );
+
+
+  relay_station
+  #(
+    .DATA_WIDTH(C_S_AXI_CONTROL_ADDR_WIDTH),
+    .DEPTH(24),
+    .ADDR_WIDTH(1),
+    .LEVEL( 3 )
+  )
+  AW_pipeline_slr_2
+  (
+    .clk        (ap_clk),
+    .reset      (1'b0),
+    .if_read_ce (1'b1),
+    .if_write_ce(1'b1),
+
+    .if_din     (s_axi_control_AWADDR_slr_2_inner),
+    .if_full_n  (s_axi_control_AWREADY_slr_2_inner),
+    .if_write   (s_axi_control_AWVALID_slr_2_inner),
+
+    .if_dout    (s_axi_control_AWADDR_slr_2),
+    .if_empty_n (s_axi_control_AWVALID_slr_2),
+    .if_read    (s_axi_control_AWREADY_slr_2)
+  );
+
+  relay_station
+  #(
+    .DATA_WIDTH(C_S_AXI_CONTROL_DATA_WIDTH + C_S_AXI_CONTROL_WSTRB_WIDTH),
+    .DEPTH(24),
+    .ADDR_WIDTH(1),
+    .LEVEL( 3 )
+  )
+  W_pipeline_slr_2
+  (
+    .clk        (ap_clk),
+    .reset      (1'b0),
+    .if_read_ce (1'b1),
+    .if_write_ce(1'b1),
+
+    .if_din     ({s_axi_control_WDATA_slr_2_inner, s_axi_control_WSTRB_slr_2_inner}),
+    .if_full_n  (s_axi_control_WREADY_slr_2_inner),
+    .if_write   (s_axi_control_WVALID_slr_2_inner),
+
+    .if_dout    ({s_axi_control_WDATA_slr_2, s_axi_control_WSTRB_slr_2}),
+    .if_empty_n (s_axi_control_WVALID_slr_2),
+    .if_read    (s_axi_control_WREADY_slr_2)
+  );
+
+
+endmodule
diff --git a/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/a_axi_write_broadcastor_1_to_4.v b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/a_axi_write_broadcastor_1_to_4.v
new file mode 100644
index 00000000..055ed0bd
--- /dev/null
+++ b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/a_axi_write_broadcastor_1_to_4.v
@@ -0,0 +1,346 @@
+
+module a_axi_write_broadcastor_1_to_4 (
+  ap_clk,
+
+  s_axi_control_AWVALID_slr_0,
+  s_axi_control_AWREADY_slr_0,
+  s_axi_control_AWADDR_slr_0,
+  s_axi_control_WVALID_slr_0,
+  s_axi_control_WREADY_slr_0,
+  s_axi_control_WDATA_slr_0,
+  s_axi_control_WSTRB_slr_0,
+  s_axi_control_AWVALID_slr_1,
+  s_axi_control_AWREADY_slr_1,
+  s_axi_control_AWADDR_slr_1,
+  s_axi_control_WVALID_slr_1,
+  s_axi_control_WREADY_slr_1,
+  s_axi_control_WDATA_slr_1,
+  s_axi_control_WSTRB_slr_1,
+  s_axi_control_AWVALID_slr_2,
+  s_axi_control_AWREADY_slr_2,
+  s_axi_control_AWADDR_slr_2,
+  s_axi_control_WVALID_slr_2,
+  s_axi_control_WREADY_slr_2,
+  s_axi_control_WDATA_slr_2,
+  s_axi_control_WSTRB_slr_2,
+  s_axi_control_AWVALID_slr_3,
+  s_axi_control_AWREADY_slr_3,
+  s_axi_control_AWADDR_slr_3,
+  s_axi_control_WVALID_slr_3,
+  s_axi_control_WREADY_slr_3,
+  s_axi_control_WDATA_slr_3,
+  s_axi_control_WSTRB_slr_3,
+  s_axi_control_AWVALID,
+  s_axi_control_AWREADY,
+  s_axi_control_AWADDR,
+  s_axi_control_WVALID,
+  s_axi_control_WREADY,
+  s_axi_control_WDATA,
+  s_axi_control_WSTRB
+);
+  parameter C_S_AXI_CONTROL_DATA_WIDTH = 32;
+  parameter C_S_AXI_CONTROL_ADDR_WIDTH = 9;
+  parameter C_S_AXI_DATA_WIDTH = 32;
+  parameter C_S_AXI_CONTROL_WSTRB_WIDTH = 32 / 8;
+  parameter C_S_AXI_WSTRB_WIDTH = 32 / 8;
+
+  input ap_clk;
+  input s_axi_control_AWVALID;
+  output s_axi_control_AWREADY;
+  input [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR;
+  input s_axi_control_WVALID;
+  output s_axi_control_WREADY;
+  input [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA;
+  input [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB;
+
+  output s_axi_control_AWVALID_slr_0;
+  input s_axi_control_AWREADY_slr_0;
+  output [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR_slr_0;
+  output s_axi_control_WVALID_slr_0;
+  input s_axi_control_WREADY_slr_0;
+  output [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA_slr_0;
+  output [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB_slr_0;
+
+  output s_axi_control_AWVALID_slr_1;
+  input s_axi_control_AWREADY_slr_1;
+  output [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR_slr_1;
+  output s_axi_control_WVALID_slr_1;
+  input s_axi_control_WREADY_slr_1;
+  output [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA_slr_1;
+  output [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB_slr_1;
+
+  output s_axi_control_AWVALID_slr_2;
+  input s_axi_control_AWREADY_slr_2;
+  output [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR_slr_2;
+  output s_axi_control_WVALID_slr_2;
+  input s_axi_control_WREADY_slr_2;
+  output [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA_slr_2;
+  output [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB_slr_2;
+
+  output s_axi_control_AWVALID_slr_3;
+  input s_axi_control_AWREADY_slr_3;
+  output [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR_slr_3;
+  output s_axi_control_WVALID_slr_3;
+  input s_axi_control_WREADY_slr_3;
+  output [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA_slr_3;
+  output [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB_slr_3;
+
+  wire s_axi_control_AWVALID_slr_0_inner;
+  wire s_axi_control_AWREADY_slr_0_inner;
+  wire [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR_slr_0_inner;
+  wire s_axi_control_WVALID_slr_0_inner;
+  wire s_axi_control_WREADY_slr_0_inner;
+  wire [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA_slr_0_inner;
+  wire [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB_slr_0_inner;
+
+  wire s_axi_control_AWVALID_slr_1_inner;
+  wire s_axi_control_AWREADY_slr_1_inner;
+  wire [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR_slr_1_inner;
+  wire s_axi_control_WVALID_slr_1_inner;
+  wire s_axi_control_WREADY_slr_1_inner;
+  wire [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA_slr_1_inner;
+  wire [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB_slr_1_inner;
+
+  wire s_axi_control_AWVALID_slr_2_inner;
+  wire s_axi_control_AWREADY_slr_2_inner;
+  wire [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR_slr_2_inner;
+  wire s_axi_control_WVALID_slr_2_inner;
+  wire s_axi_control_WREADY_slr_2_inner;
+  wire [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA_slr_2_inner;
+  wire [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB_slr_2_inner;
+
+  wire s_axi_control_AWVALID_slr_3_inner;
+  wire s_axi_control_AWREADY_slr_3_inner;
+  wire [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR_slr_3_inner;
+  wire s_axi_control_WVALID_slr_3_inner;
+  wire s_axi_control_WREADY_slr_3_inner;
+  wire [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA_slr_3_inner;
+  wire [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB_slr_3_inner;
+
+  // broadcast the AW channel
+  assign s_axi_control_AWADDR_slr_0_inner = s_axi_control_AWADDR;
+  assign s_axi_control_AWADDR_slr_1_inner = s_axi_control_AWADDR;
+  assign s_axi_control_AWADDR_slr_2_inner = s_axi_control_AWADDR;
+  assign s_axi_control_AWADDR_slr_3_inner = s_axi_control_AWADDR;
+
+  assign s_axi_control_AWVALID_slr_0_inner = s_axi_control_AWVALID;
+  assign s_axi_control_AWVALID_slr_1_inner = s_axi_control_AWVALID;
+  assign s_axi_control_AWVALID_slr_2_inner = s_axi_control_AWVALID;
+  assign s_axi_control_AWVALID_slr_3_inner = s_axi_control_AWVALID;
+
+  assign s_axi_control_AWREADY =  s_axi_control_AWREADY_slr_0_inner &
+                                  s_axi_control_AWREADY_slr_1_inner &
+                                  s_axi_control_AWREADY_slr_2_inner &
+                                  s_axi_control_AWREADY_slr_3_inner;
+
+  // broadcast the W channel
+  assign s_axi_control_WDATA_slr_0_inner = s_axi_control_WDATA;
+  assign s_axi_control_WDATA_slr_1_inner = s_axi_control_WDATA;
+  assign s_axi_control_WDATA_slr_2_inner = s_axi_control_WDATA;
+  assign s_axi_control_WDATA_slr_3_inner = s_axi_control_WDATA;
+
+  assign s_axi_control_WSTRB_slr_0_inner = s_axi_control_WSTRB;
+  assign s_axi_control_WSTRB_slr_1_inner = s_axi_control_WSTRB;
+  assign s_axi_control_WSTRB_slr_2_inner = s_axi_control_WSTRB;
+  assign s_axi_control_WSTRB_slr_3_inner = s_axi_control_WSTRB;
+
+  assign s_axi_control_WVALID_slr_0_inner = s_axi_control_WVALID;
+  assign s_axi_control_WVALID_slr_1_inner = s_axi_control_WVALID;
+  assign s_axi_control_WVALID_slr_2_inner = s_axi_control_WVALID;
+  assign s_axi_control_WVALID_slr_3_inner = s_axi_control_WVALID;
+
+  assign s_axi_control_WREADY = s_axi_control_WREADY_slr_0_inner &
+                                s_axi_control_WREADY_slr_1_inner &
+                                s_axi_control_WREADY_slr_2_inner &
+                                s_axi_control_WREADY_slr_3_inner;
+
+  relay_station
+  #(
+    .DATA_WIDTH(C_S_AXI_CONTROL_ADDR_WIDTH),
+    .DEPTH(24),
+    .ADDR_WIDTH(1),
+    .LEVEL( 3 )
+  )
+  AW_pipeline_slr_0
+  (
+    .clk        (ap_clk),
+    .reset      (1'b0),
+    .if_read_ce (1'b1),
+    .if_write_ce(1'b1),
+
+    .if_din     (s_axi_control_AWADDR_slr_0_inner),
+    .if_full_n  (s_axi_control_AWREADY_slr_0_inner),
+    .if_write   (s_axi_control_AWVALID_slr_0_inner),
+
+    .if_dout    (s_axi_control_AWADDR_slr_0),
+    .if_empty_n (s_axi_control_AWVALID_slr_0),
+    .if_read    (s_axi_control_AWREADY_slr_0)
+  );
+
+  relay_station
+  #(
+    .DATA_WIDTH(C_S_AXI_CONTROL_DATA_WIDTH + C_S_AXI_CONTROL_WSTRB_WIDTH),
+    .DEPTH(24),
+    .ADDR_WIDTH(1),
+    .LEVEL( 3 )
+  )
+  W_pipeline_slr_0
+  (
+    .clk        (ap_clk),
+    .reset      (1'b0),
+    .if_read_ce (1'b1),
+    .if_write_ce(1'b1),
+
+    .if_din     ({s_axi_control_WDATA_slr_0_inner, s_axi_control_WSTRB_slr_0_inner}),
+    .if_full_n  (s_axi_control_WREADY_slr_0_inner),
+    .if_write   (s_axi_control_WVALID_slr_0_inner),
+
+    .if_dout    ({s_axi_control_WDATA_slr_0, s_axi_control_WSTRB_slr_0}),
+    .if_empty_n (s_axi_control_WVALID_slr_0),
+    .if_read    (s_axi_control_WREADY_slr_0)
+  );
+
+
+  relay_station
+  #(
+    .DATA_WIDTH(C_S_AXI_CONTROL_ADDR_WIDTH),
+    .DEPTH(24),
+    .ADDR_WIDTH(1),
+    .LEVEL( 3 )
+  )
+  AW_pipeline_slr_1
+  (
+    .clk        (ap_clk),
+    .reset      (1'b0),
+    .if_read_ce (1'b1),
+    .if_write_ce(1'b1),
+
+    .if_din     (s_axi_control_AWADDR_slr_1_inner),
+    .if_full_n  (s_axi_control_AWREADY_slr_1_inner),
+    .if_write   (s_axi_control_AWVALID_slr_1_inner),
+
+    .if_dout    (s_axi_control_AWADDR_slr_1),
+    .if_empty_n (s_axi_control_AWVALID_slr_1),
+    .if_read    (s_axi_control_AWREADY_slr_1)
+  );
+
+  relay_station
+  #(
+    .DATA_WIDTH(C_S_AXI_CONTROL_DATA_WIDTH + C_S_AXI_CONTROL_WSTRB_WIDTH),
+    .DEPTH(24),
+    .ADDR_WIDTH(1),
+    .LEVEL( 3 )
+  )
+  W_pipeline_slr_1
+  (
+    .clk        (ap_clk),
+    .reset      (1'b0),
+    .if_read_ce (1'b1),
+    .if_write_ce(1'b1),
+
+    .if_din     ({s_axi_control_WDATA_slr_1_inner, s_axi_control_WSTRB_slr_1_inner}),
+    .if_full_n  (s_axi_control_WREADY_slr_1_inner),
+    .if_write   (s_axi_control_WVALID_slr_1_inner),
+
+    .if_dout    ({s_axi_control_WDATA_slr_1, s_axi_control_WSTRB_slr_1}),
+    .if_empty_n (s_axi_control_WVALID_slr_1),
+    .if_read    (s_axi_control_WREADY_slr_1)
+  );
+
+
+  relay_station
+  #(
+    .DATA_WIDTH(C_S_AXI_CONTROL_ADDR_WIDTH),
+    .DEPTH(24),
+    .ADDR_WIDTH(1),
+    .LEVEL( 3 )
+  )
+  AW_pipeline_slr_2
+  (
+    .clk        (ap_clk),
+    .reset      (1'b0),
+    .if_read_ce (1'b1),
+    .if_write_ce(1'b1),
+
+    .if_din     (s_axi_control_AWADDR_slr_2_inner),
+    .if_full_n  (s_axi_control_AWREADY_slr_2_inner),
+    .if_write   (s_axi_control_AWVALID_slr_2_inner),
+
+    .if_dout    (s_axi_control_AWADDR_slr_2),
+    .if_empty_n (s_axi_control_AWVALID_slr_2),
+    .if_read    (s_axi_control_AWREADY_slr_2)
+  );
+
+  relay_station
+  #(
+    .DATA_WIDTH(C_S_AXI_CONTROL_DATA_WIDTH + C_S_AXI_CONTROL_WSTRB_WIDTH),
+    .DEPTH(24),
+    .ADDR_WIDTH(1),
+    .LEVEL( 3 )
+  )
+  W_pipeline_slr_2
+  (
+    .clk        (ap_clk),
+    .reset      (1'b0),
+    .if_read_ce (1'b1),
+    .if_write_ce(1'b1),
+
+    .if_din     ({s_axi_control_WDATA_slr_2_inner, s_axi_control_WSTRB_slr_2_inner}),
+    .if_full_n  (s_axi_control_WREADY_slr_2_inner),
+    .if_write   (s_axi_control_WVALID_slr_2_inner),
+
+    .if_dout    ({s_axi_control_WDATA_slr_2, s_axi_control_WSTRB_slr_2}),
+    .if_empty_n (s_axi_control_WVALID_slr_2),
+    .if_read    (s_axi_control_WREADY_slr_2)
+  );
+
+
+  relay_station
+  #(
+    .DATA_WIDTH(C_S_AXI_CONTROL_ADDR_WIDTH),
+    .DEPTH(24),
+    .ADDR_WIDTH(1),
+    .LEVEL( 3 )
+  )
+  AW_pipeline_slr_3
+  (
+    .clk        (ap_clk),
+    .reset      (1'b0),
+    .if_read_ce (1'b1),
+    .if_write_ce(1'b1),
+
+    .if_din     (s_axi_control_AWADDR_slr_3_inner),
+    .if_full_n  (s_axi_control_AWREADY_slr_3_inner),
+    .if_write   (s_axi_control_AWVALID_slr_3_inner),
+
+    .if_dout    (s_axi_control_AWADDR_slr_3),
+    .if_empty_n (s_axi_control_AWVALID_slr_3),
+    .if_read    (s_axi_control_AWREADY_slr_3)
+  );
+
+  relay_station
+  #(
+    .DATA_WIDTH(C_S_AXI_CONTROL_DATA_WIDTH + C_S_AXI_CONTROL_WSTRB_WIDTH),
+    .DEPTH(24),
+    .ADDR_WIDTH(1),
+    .LEVEL( 3 )
+  )
+  W_pipeline_slr_3
+  (
+    .clk        (ap_clk),
+    .reset      (1'b0),
+    .if_read_ce (1'b1),
+    .if_write_ce(1'b1),
+
+    .if_din     ({s_axi_control_WDATA_slr_3_inner, s_axi_control_WSTRB_slr_3_inner}),
+    .if_full_n  (s_axi_control_WREADY_slr_3_inner),
+    .if_write   (s_axi_control_WVALID_slr_3_inner),
+
+    .if_dout    ({s_axi_control_WDATA_slr_3, s_axi_control_WSTRB_slr_3}),
+    .if_empty_n (s_axi_control_WVALID_slr_3),
+    .if_read    (s_axi_control_WREADY_slr_3)
+  );
+
+
+
+endmodule
diff --git a/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/arbiter.v b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/arbiter.v
new file mode 100644
index 00000000..cfac70d1
--- /dev/null
+++ b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/arbiter.v
@@ -0,0 +1,159 @@
+/*
+
+Copyright (c) 2014-2021 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * Arbiter module
+ */
+module arbiter #
+(
+    parameter PORTS = 4,
+    // select round robin arbitration
+    parameter ARB_TYPE_ROUND_ROBIN = 0,
+    // blocking arbiter enable
+    parameter ARB_BLOCK = 0,
+    // block on acknowledge assert when nonzero, request deassert when 0
+    parameter ARB_BLOCK_ACK = 1,
+    // LSB priority selection
+    parameter ARB_LSB_HIGH_PRIORITY = 0
+)
+(
+    input  wire                     clk,
+    input  wire                     rst,
+
+    input  wire [PORTS-1:0]         request,
+    input  wire [PORTS-1:0]         acknowledge,
+
+    output wire [PORTS-1:0]         grant,
+    output wire                     grant_valid,
+    output wire [$clog2(PORTS)-1:0] grant_encoded
+);
+
+reg [PORTS-1:0] grant_reg = 0, grant_next;
+reg grant_valid_reg = 0, grant_valid_next;
+reg [$clog2(PORTS)-1:0] grant_encoded_reg = 0, grant_encoded_next;
+
+assign grant_valid = grant_valid_reg;
+assign grant = grant_reg;
+assign grant_encoded = grant_encoded_reg;
+
+wire request_valid;
+wire [$clog2(PORTS)-1:0] request_index;
+wire [PORTS-1:0] request_mask;
+
+priority_encoder #(
+    .WIDTH(PORTS),
+    .LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
+)
+priority_encoder_inst (
+    .input_unencoded(request),
+    .output_valid(request_valid),
+    .output_encoded(request_index),
+    .output_unencoded(request_mask)
+);
+
+reg [PORTS-1:0] mask_reg = 0, mask_next;
+
+wire masked_request_valid;
+wire [$clog2(PORTS)-1:0] masked_request_index;
+wire [PORTS-1:0] masked_request_mask;
+
+priority_encoder #(
+    .WIDTH(PORTS),
+    .LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
+)
+priority_encoder_masked (
+    .input_unencoded(request & mask_reg),
+    .output_valid(masked_request_valid),
+    .output_encoded(masked_request_index),
+    .output_unencoded(masked_request_mask)
+);
+
+always @* begin
+    grant_next = 0;
+    grant_valid_next = 0;
+    grant_encoded_next = 0;
+    mask_next = mask_reg;
+
+    if (ARB_BLOCK && !ARB_BLOCK_ACK && grant_reg & request) begin
+        // granted request still asserted; hold it
+        grant_valid_next = grant_valid_reg;
+        grant_next = grant_reg;
+        grant_encoded_next = grant_encoded_reg;
+    end else if (ARB_BLOCK && ARB_BLOCK_ACK && grant_valid && !(grant_reg & acknowledge)) begin
+        // granted request not yet acknowledged; hold it
+        grant_valid_next = grant_valid_reg;
+        grant_next = grant_reg;
+        grant_encoded_next = grant_encoded_reg;
+    end else if (request_valid) begin
+        if (ARB_TYPE_ROUND_ROBIN) begin
+            if (masked_request_valid) begin
+                grant_valid_next = 1;
+                grant_next = masked_request_mask;
+                grant_encoded_next = masked_request_index;
+                if (ARB_LSB_HIGH_PRIORITY) begin
+                    mask_next = {PORTS{1'b1}} << (masked_request_index + 1);
+                end else begin
+                    mask_next = {PORTS{1'b1}} >> (PORTS - masked_request_index);
+                end
+            end else begin
+                grant_valid_next = 1;
+                grant_next = request_mask;
+                grant_encoded_next = request_index;
+                if (ARB_LSB_HIGH_PRIORITY) begin
+                    mask_next = {PORTS{1'b1}} << (request_index + 1);
+                end else begin
+                    mask_next = {PORTS{1'b1}} >> (PORTS - request_index);
+                end
+            end
+        end else begin
+            grant_valid_next = 1;
+            grant_next = request_mask;
+            grant_encoded_next = request_index;
+        end
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        grant_reg <= 0;
+        grant_valid_reg <= 0;
+        grant_encoded_reg <= 0;
+        mask_reg <= 0;
+    end else begin
+        grant_reg <= grant_next;
+        grant_valid_reg <= grant_valid_next;
+        grant_encoded_reg <= grant_encoded_next;
+        mask_reg <= mask_next;
+    end
+end
+
+endmodule
+
+`resetall
diff --git a/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/async_mmap.v b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/async_mmap.v
new file mode 100644
index 00000000..283d7664
--- /dev/null
+++ b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/async_mmap.v
@@ -0,0 +1,533 @@
+`default_nettype none
+
+module async_mmap #(
+  parameter BufferSize        = 32,
+  parameter BufferSizeLog     = 5,
+  parameter AddrWidth         = 64,
+  parameter AxiSideAddrWidth  = 64,
+  parameter DataWidth         = 512,
+  parameter DataWidthBytesLog = 6,  // must equal log2(DataWidth/8)
+  parameter WaitTimeWidth     = 4,
+  parameter BurstLenWidth     = 8,
+  // implement the FIFOs for the read channel
+  // if set to 0: disconnect the data link
+  parameter EnableReadChannel = 1,
+  parameter EnableWriteChannel= 1,
+  // for burst inference
+  parameter MaxWaitTime       = 3,
+  parameter MaxBurstLen       = 15
+) (
+  // pragma RS clk port=clk
+  // pragma RS rst port=rst active=high
+  input wire clk,
+  input wire rst, // active high
+
+  // axi write addr channel
+  // pragma RS handshake valid=m_axi_AWVALID ready=m_axi_AWREADY data=m_axi_AW.*
+  output wire                        m_axi_AWVALID,
+  input  wire                        m_axi_AWREADY,
+  output wire [AxiSideAddrWidth-1:0] m_axi_AWADDR,
+  output wire [0:0]                  m_axi_AWID,
+  output wire [7:0]                  m_axi_AWLEN,
+  output wire [2:0]                  m_axi_AWSIZE,
+  output wire [1:0]                  m_axi_AWBURST,
+  output wire [0:0]                  m_axi_AWLOCK,
+  output wire [3:0]                  m_axi_AWCACHE,
+  output wire [2:0]                  m_axi_AWPROT,
+  output wire [3:0]                  m_axi_AWQOS,
+
+  // axi write data channel
+  // pragma RS handshake valid=m_axi_WVALID ready=m_axi_WREADY data=m_axi_W.*
+  output wire                   m_axi_WVALID,
+  input  wire                   m_axi_WREADY,
+  output wire [DataWidth-1:0]   m_axi_WDATA,
+  output wire [DataWidth/8-1:0] m_axi_WSTRB,
+  output wire                   m_axi_WLAST,
+
+  // axi write acknowledge channel
+  // pragma RS handshake valid=m_axi_BVALID ready=m_axi_BREADY data=m_axi_B.*
+  input  wire       m_axi_BVALID,
+  output wire       m_axi_BREADY,
+  input  wire [1:0] m_axi_BRESP,
+  input  wire [0:0] m_axi_BID,
+
+  // axi read addr channel
+  // pragma RS handshake valid=m_axi_ARVALID ready=m_axi_ARREADY data=m_axi_AR.*
+  output wire                        m_axi_ARVALID,
+  input  wire                        m_axi_ARREADY,
+  output wire [AxiSideAddrWidth-1:0] m_axi_ARADDR,
+  output wire [0:0]                  m_axi_ARID,
+  output wire [7:0]                  m_axi_ARLEN,
+  output wire [2:0]                  m_axi_ARSIZE,
+  output wire [1:0]                  m_axi_ARBURST,
+  output wire [0:0]                  m_axi_ARLOCK,
+  output wire [3:0]                  m_axi_ARCACHE,
+  output wire [2:0]                  m_axi_ARPROT,
+  output wire [3:0]                  m_axi_ARQOS,
+
+  // axi read response channel
+  // pragma RS handshake valid=m_axi_RVALID ready=m_axi_RREADY data=m_axi_R.*
+  input  wire                 m_axi_RVALID,
+  output wire                 m_axi_RREADY,
+  input  wire [DataWidth-1:0] m_axi_RDATA,
+  input  wire                 m_axi_RLAST,
+  input  wire [0:0]           m_axi_RID,
+  input  wire [1:0]           m_axi_RRESP,
+
+
+  // push read addr here
+  // pragma RS handshake valid=read_addr_write ready=read_addr_full_n data=read_addr_din
+  input  wire [AddrWidth-1:0] read_addr_din,
+  input  wire                 read_addr_write,
+  output wire                 read_addr_full_n,
+
+  // pop read resp here
+  // pragma RS handshake valid=read_data_empty_n ready=read_data_read data=read_data_dout
+  output wire [DataWidth-1:0] read_data_dout,
+  input  wire                 read_data_read,
+  output wire                 read_data_empty_n,
+
+  // push write addr and data here
+  // pragma RS handshake valid=write_addr_write ready=write_addr_full_n data=write_addr_din
+  // pragma RS handshake valid=write_data_write ready=write_data_full_n data=write_data_din
+  input  wire [AddrWidth-1:0] write_addr_din,
+  input  wire                 write_addr_write,
+  output wire                 write_addr_full_n,
+  input  wire [DataWidth-1:0] write_data_din,
+  input  wire                 write_data_write,
+  output wire                 write_data_full_n,
+
+  // pop write resp here
+  // pragma RS handshake valid=write_resp_empty_n ready=write_resp_read data=write_resp_dout
+  output wire [7:0] write_resp_dout,
+  input  wire       write_resp_read,
+  output wire       write_resp_empty_n
+);
+
+  // write addr buffer, from user to burst detector
+  wire [AddrWidth-1:0] write_addr_dout;
+  wire                 write_addr_empty_n;
+  wire                 write_addr_read;
+
+  relay_station #(
+    .DATA_WIDTH(AddrWidth),
+    .ADDR_WIDTH(BufferSizeLog),
+    .DEPTH     (BufferSize),
+    .LEVEL     (1),
+    .CONNECT   (EnableWriteChannel)
+  ) write_addr (
+    .clk  (clk),
+    .reset(rst),
+
+    // from user
+    .if_full_n  (write_addr_full_n),
+    .if_write_ce(1'b1),
+    .if_write   (write_addr_write),
+    .if_din     (write_addr_din),
+
+    // to burst detector
+    .if_empty_n(write_addr_empty_n),
+    .if_read_ce(1'b1),
+    .if_read   (write_addr_read),
+    .if_dout   (write_addr_dout)
+  );
+
+  // burst write addr buffer, from burst detector to axi
+  wire [BurstLenWidth+AddrWidth-1:0] burst_write_addr_din;
+  wire                               burst_write_addr_full_n;
+  wire                               burst_write_addr_write;
+  wire [AddrWidth-1:0]               burst_write_addr_dout_addr;
+  wire [BurstLenWidth-1:0]           burst_write_addr_dout_burst_len;
+  wire                               burst_write_addr_empty_n;
+  wire                               burst_write_addr_read;
+
+  wire  [BurstLenWidth-1:0] burst_write_len_din;
+  wire                      burst_write_len_full_n;
+  wire                      burst_write_len_write;
+  wire  [BurstLenWidth-1:0] burst_write_len_dout;
+  wire                      burst_write_len_empty_n;
+  wire                      burst_write_len_read;
+
+  wire [BurstLenWidth-1:0] write_req_din;
+  wire                     write_req_write;
+  wire                     write_req_full_n;
+  wire [BurstLenWidth-1:0] write_req_dout;
+  wire                     write_req_read;
+  wire                     write_req_empty_n;
+
+  wire burst_write_last_din;
+  wire burst_write_last_full_n;
+  wire burst_write_last_write;
+  wire burst_write_last_dout;
+  wire burst_write_last_empty_n;
+
+  detect_burst #(
+    .AddrWidth        (AddrWidth),
+    .DataWidthBytesLog(DataWidthBytesLog),
+    .WaitTimeWidth    (WaitTimeWidth),
+    .BurstLenWidth    (BurstLenWidth)
+  ) detect_burst_write (
+    .clk(clk),
+    .rst(rst),
+
+    .max_wait_time(MaxWaitTime[WaitTimeWidth-1:0]),
+    .max_burst_len(MaxBurstLen[BurstLenWidth-1:0]),
+
+    // input: individual addresses
+    .addr_dout   (write_addr_dout),
+    .addr_empty_n(write_addr_empty_n),
+    .addr_read   (write_addr_read),
+
+    // output: inferred burst addresses
+    .addr_din   (burst_write_addr_din),
+    .addr_full_n(burst_write_addr_full_n),
+    .addr_write (burst_write_addr_write),
+
+    // output: used to generate the "last" signals
+    .burst_len_0_din   (burst_write_len_din),
+    .burst_len_0_full_n(burst_write_len_full_n),
+    .burst_len_0_write (burst_write_len_write),
+
+    // output: used to generate write responses
+    .burst_len_1_din   (write_req_din),
+    .burst_len_1_full_n(write_req_full_n),
+    .burst_len_1_write (write_req_write)
+  );
+
+  relay_station #(
+    .DATA_WIDTH(BurstLenWidth + AddrWidth),
+    .ADDR_WIDTH(BufferSizeLog),
+    .DEPTH     (BufferSize),
+    .LEVEL     (1),
+    .CONNECT   (EnableWriteChannel)
+  ) burst_write_addr (
+    .clk  (clk),
+    .reset(rst),
+
+    // from burst detector
+    .if_full_n  (burst_write_addr_full_n),
+    .if_write_ce(1'b1),
+    .if_write   (burst_write_addr_write),
+    .if_din     (burst_write_addr_din),
+
+    // to axi
+    .if_empty_n(burst_write_addr_empty_n),
+    .if_read_ce(1'b1),
+    .if_read   (burst_write_addr_read),
+    .if_dout   ({burst_write_addr_dout_burst_len, burst_write_addr_dout_addr})
+  );
+
+  relay_station #(
+    .DATA_WIDTH(BurstLenWidth),
+    .ADDR_WIDTH(BufferSizeLog),
+    .DEPTH     (BufferSize),
+    .LEVEL     (1),
+    .CONNECT   (EnableWriteChannel)
+  ) burst_write_len (
+    .clk  (clk),
+    .reset(rst),
+
+    // from burst detector
+    .if_full_n  (burst_write_len_full_n),
+    .if_write_ce(1'b1),
+    .if_write   (burst_write_len_write),
+    .if_din     (burst_write_len_din),
+
+    // to last generator
+    .if_empty_n(burst_write_len_empty_n),
+    .if_read_ce(1'b1),
+    .if_read   (burst_write_len_read),
+    .if_dout   (burst_write_len_dout)
+  );
+
+  // generate last signal for W channel
+  generate_last #(
+    .BurstLenWidth(BurstLenWidth)
+  ) generate_last_unit(
+    .clk(clk),
+    .rst(rst),
+
+    .burst_len_dout   (burst_write_len_dout),
+    .burst_len_empty_n(burst_write_len_empty_n),
+    .burst_len_read   (burst_write_len_read),
+
+    .last_din   (burst_write_last_din),
+    .last_full_n(burst_write_last_full_n),
+    .last_write (burst_write_last_write)
+  );
+
+  // write req buffer that remembers the burst length of each write transaction
+  relay_station #(
+    .DATA_WIDTH(BurstLenWidth),
+    .ADDR_WIDTH(BufferSizeLog),
+    .DEPTH     (BufferSize),
+    .LEVEL     (1),
+    .CONNECT   (EnableWriteChannel)
+  ) write_req (
+    .clk  (clk),
+    .reset(rst),
+
+    // from burst detector
+    .if_full_n  (write_req_full_n),
+    .if_write_ce(1'b1),
+    .if_write   (write_req_write),
+    .if_din     (write_req_din),
+
+    // to write resp buffer
+    .if_empty_n(write_req_empty_n),
+    .if_read_ce(1'b1),
+    .if_read   (write_req_read),
+    .if_dout   (write_req_dout)
+  );
+
+  // write data buffer
+  wire [DataWidth-1:0] write_data_dout;
+  wire                 write_data_empty_n;
+  relay_station #(
+    .DATA_WIDTH(DataWidth),
+    .ADDR_WIDTH(BufferSizeLog),
+    .DEPTH     (BufferSize),
+    .LEVEL     (1),
+    .CONNECT   (EnableWriteChannel)
+  ) write_data (
+    .clk  (clk),
+    .reset(rst),
+
+    // from user
+    .if_full_n  (write_data_full_n),
+    .if_write_ce(1'b1),
+    .if_write   (write_data_write),
+    .if_din     (write_data_din),
+
+    // to axi
+    .if_empty_n(write_data_empty_n),
+    .if_read_ce(1'b1),
+    // deal with when data-relay_station is non empty but last-relay_station is empty
+    .if_read   (m_axi_WREADY && burst_write_last_empty_n),
+    .if_dout   (write_data_dout)
+  );
+
+  // this relay_station should be synchronized with the wr_data relay_station
+  relay_station #(
+    .DATA_WIDTH(1),
+    .ADDR_WIDTH(BufferSizeLog),
+    .DEPTH     (BufferSize),
+    .LEVEL     (1),
+    .CONNECT   (EnableWriteChannel)
+  ) burst_write_last (
+    .clk  (clk),
+    .reset(rst),
+
+    // from burst detector
+    .if_full_n  (burst_write_last_full_n),
+    .if_write_ce(1'b1),
+    .if_write   (burst_write_last_write),
+    .if_din     (burst_write_last_din),
+
+    // to axi
+    .if_empty_n(burst_write_last_empty_n),
+    .if_read_ce(1'b1),
+    // deal with when last-relay_station is non-empty while data-relay_station is empty
+    .if_read   (m_axi_WREADY && write_data_empty_n),
+    .if_dout   (burst_write_last_dout)
+  );
+
+  // write resp buffer
+  wire [BurstLenWidth-1:0] write_resp_din   = write_req_dout;
+  wire                     write_resp_write = m_axi_BVALID && write_req_empty_n;
+  wire                     write_resp_full_n;
+  relay_station #(
+    .DATA_WIDTH(BurstLenWidth),
+    .ADDR_WIDTH(BufferSizeLog),
+    .DEPTH     (BufferSize),
+    .LEVEL     (1),
+    .CONNECT   (EnableWriteChannel)
+  ) write_resp (
+    .clk  (clk),
+    .reset(rst),
+
+    // from write req buffer and axi
+    .if_full_n  (write_resp_full_n),
+    .if_write_ce(1'b1),
+    .if_write   (write_resp_write),
+    .if_din     (write_resp_din),
+
+    // to user
+    .if_empty_n(write_resp_empty_n),
+    .if_read_ce(1'b1),
+    .if_read   (write_resp_read),
+    .if_dout   (write_resp_dout)
+  );
+
+  // AW channel
+  assign burst_write_addr_read = m_axi_AWREADY;
+  assign m_axi_AWVALID  = burst_write_addr_empty_n;
+  assign m_axi_AWADDR   = {{(AxiSideAddrWidth - AddrWidth){1'b0}}, burst_write_addr_dout_addr};
+  assign m_axi_AWID     = 0;
+  assign m_axi_AWLEN    = burst_write_addr_dout_burst_len;
+  assign m_axi_AWSIZE   = DataWidthBytesLog;
+  assign m_axi_AWBURST  = 1;        // INCR mode
+  assign m_axi_AWLOCK   = 0;        // Xilinx only supports 0
+  assign m_axi_AWCACHE  = 4'b0011;  // Xilinx only supports 4'b0011
+  assign m_axi_AWPROT   = 0;
+  assign m_axi_AWQOS    = 0;
+
+  // W channel
+  assign m_axi_WVALID = write_data_empty_n && burst_write_last_empty_n;
+  assign m_axi_WDATA  = write_data_dout;
+  assign m_axi_WSTRB  = {(DataWidth/8){1'b1}};  // assume every bit is valid
+  assign m_axi_WLAST  = burst_write_last_dout;
+
+  // B channel
+  assign m_axi_BREADY   = write_resp_full_n && write_req_empty_n;
+  assign write_req_read = write_resp_full_n && m_axi_BVALID;
+
+  // read addr buffer, from user to burst detector
+  wire [AddrWidth-1:0] read_addr_dout;
+  wire                 read_addr_empty_n;
+  wire                 read_addr_read;
+
+  relay_station #(
+    .DATA_WIDTH(AddrWidth),
+    .ADDR_WIDTH(BufferSizeLog),
+    .DEPTH     (BufferSize),
+    .LEVEL     (1),
+    .CONNECT   (EnableReadChannel)
+  ) read_addr (
+    .clk  (clk),
+    .reset(rst),
+
+    // from user
+    .if_full_n  (read_addr_full_n),
+    .if_write_ce(1'b1),
+    .if_write   (read_addr_write),
+    .if_din     (read_addr_din),
+
+    // to axi
+    .if_empty_n(read_addr_empty_n),
+    .if_read_ce(1'b1),
+    .if_read   (read_addr_read),
+    .if_dout   (read_addr_dout)
+  );
+
+  wire [BurstLenWidth+AddrWidth-1:0] burst_read_addr_din;
+  wire                               burst_read_addr_full_n;
+  wire                               burst_read_addr_write;
+  wire [AddrWidth-1:0]               burst_read_addr_dout_addr;
+  wire [BurstLenWidth-1:0]           burst_read_addr_dout_burst_len;
+  wire                               burst_read_addr_empty_n;
+  wire                               burst_read_addr_read;
+
+  relay_station #(
+    .DATA_WIDTH(BurstLenWidth + AddrWidth),
+    .ADDR_WIDTH(BufferSizeLog),
+    .DEPTH     (BufferSize),
+    .LEVEL     (1),
+    .CONNECT   (EnableReadChannel)
+  ) burst_read_addr (
+    .clk  (clk),
+    .reset(rst),
+
+    // from burst detector
+    .if_full_n  (burst_read_addr_full_n),
+    .if_write_ce(1'b1),
+    .if_write   (burst_read_addr_write),
+    .if_din     (burst_read_addr_din),
+
+    // to axi
+    .if_empty_n(burst_read_addr_empty_n),
+    .if_read_ce(1'b1),
+    .if_read   (burst_read_addr_read),
+    .if_dout   ({burst_read_addr_dout_burst_len, burst_read_addr_dout_addr})
+  );
+
+  detect_burst #(
+    .AddrWidth        (AddrWidth),
+    .DataWidthBytesLog(DataWidthBytesLog),
+    .WaitTimeWidth    (WaitTimeWidth),
+    .BurstLenWidth    (BurstLenWidth)
+  ) detect_burst_read (
+    .clk(clk),
+    .rst(rst),
+
+    .max_wait_time(MaxWaitTime[WaitTimeWidth-1:0]),
+    .max_burst_len(MaxBurstLen[BurstLenWidth-1:0]),
+
+    // input: individual addresses
+    .addr_dout   (read_addr_dout),
+    .addr_empty_n(read_addr_empty_n),
+    .addr_read   (read_addr_read),
+
+    // output: inferred burst addresses
+    .addr_din   (burst_read_addr_din),
+    .addr_full_n(burst_read_addr_full_n),
+    .addr_write (burst_read_addr_write),
+
+    // output: used to generate the "last" signals, unused
+    .burst_len_0_din   (),
+    .burst_len_0_full_n(1'b1),
+    .burst_len_0_write (),
+
+    // output: used to generate write responses, unused
+    .burst_len_1_din   (),
+    .burst_len_1_full_n(1'b1),
+    .burst_len_1_write ()
+  );
+
+  // read resp buffer
+  wire [DataWidth-1:0] read_data_din;
+  wire                 read_data_write;
+  wire                 read_data_full_n;
+  relay_station #(
+    .DATA_WIDTH(DataWidth),
+    .ADDR_WIDTH(BufferSizeLog),
+    .DEPTH     (BufferSize),
+    .LEVEL     (1),
+    .CONNECT   (EnableReadChannel)
+  ) read_data (
+    .clk  (clk),
+    .reset(rst),
+
+    // from axi
+    .if_full_n  (read_data_full_n),
+    .if_write_ce(1'b1),
+    .if_write   (read_data_write),
+    .if_din     (read_data_din),
+
+    // to user
+    .if_empty_n(read_data_empty_n),
+    .if_read_ce(1'b1),
+    .if_read   (read_data_read),
+    .if_dout   (read_data_dout)
+  );
+
+  // AR channel
+  assign burst_read_addr_read = m_axi_ARREADY;
+  assign m_axi_ARVALID        = burst_read_addr_empty_n;
+  assign m_axi_ARADDR         = {{(AxiSideAddrWidth - AddrWidth){1'b0}}, burst_read_addr_dout_addr};
+  assign m_axi_ARID           = 0;
+  assign m_axi_ARLEN          = burst_read_addr_dout_burst_len;
+  assign m_axi_ARSIZE         = DataWidthBytesLog;
+  assign m_axi_ARBURST        = 1;        // INCR mode
+  assign m_axi_ARLOCK         = 0;        // Xilinx only supports 0
+  assign m_axi_ARCACHE        = 4'b0011;  // Xilinx only supports 4'b0011
+  assign m_axi_ARPROT         = 0;
+  assign m_axi_ARQOS          = 0;
+
+  // R channel
+  assign m_axi_RREADY    = read_data_full_n;
+  assign read_data_write = m_axi_RVALID;
+  assign read_data_din   = m_axi_RDATA;
+
+  // unused input signals
+  wire _unused = &{1'b0,
+    m_axi_BRESP,
+    m_axi_BID,
+    m_axi_RLAST,
+    m_axi_RID,
+    m_axi_RRESP,
+    1'b0};
+
+endmodule  // async_mmap
+
+`default_nettype wire
diff --git a/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/axi_crossbar.v b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/axi_crossbar.v
new file mode 100644
index 00000000..991d4540
--- /dev/null
+++ b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/axi_crossbar.v
@@ -0,0 +1,391 @@
+/*
+
+Copyright (c) 2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4 crossbar
+ */
+module axi_crossbar #
+(
+    // Number of AXI inputs (slave interfaces)
+    parameter S_COUNT = 4,
+    // Number of AXI outputs (master interfaces)
+    parameter M_COUNT = 4,
+    // Width of data bus in bits
+    parameter DATA_WIDTH = 32,
+    // Width of address bus in bits
+    parameter ADDR_WIDTH = 32,
+    // Width of wstrb (width of data bus in words)
+    parameter STRB_WIDTH = (DATA_WIDTH/8),
+    // Input ID field width (from AXI masters)
+    parameter S_ID_WIDTH = 8,
+    // Output ID field width (towards AXI slaves)
+    // Additional bits required for response routing
+    parameter M_ID_WIDTH = S_ID_WIDTH+$clog2(S_COUNT),
+    // Propagate awuser signal
+    parameter AWUSER_ENABLE = 0,
+    // Width of awuser signal
+    parameter AWUSER_WIDTH = 1,
+    // Propagate wuser signal
+    parameter WUSER_ENABLE = 0,
+    // Width of wuser signal
+    parameter WUSER_WIDTH = 1,
+    // Propagate buser signal
+    parameter BUSER_ENABLE = 0,
+    // Width of buser signal
+    parameter BUSER_WIDTH = 1,
+    // Propagate aruser signal
+    parameter ARUSER_ENABLE = 0,
+    // Width of aruser signal
+    parameter ARUSER_WIDTH = 1,
+    // Propagate ruser signal
+    parameter RUSER_ENABLE = 0,
+    // Width of ruser signal
+    parameter RUSER_WIDTH = 1,
+    // Number of concurrent unique IDs for each slave interface
+    // S_COUNT concatenated fields of 32 bits
+    parameter S_THREADS = {S_COUNT{32'd2}},
+    // Number of concurrent operations for each slave interface
+    // S_COUNT concatenated fields of 32 bits
+    parameter S_ACCEPT = {S_COUNT{32'd16}},
+    // Number of regions per master interface
+    parameter M_REGIONS = 1,
+    // Master interface base addresses
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_WIDTH bits
+    // set to zero for default addressing based on M_ADDR_WIDTH
+    parameter M_BASE_ADDR = 0,
+    // Master interface address widths
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits
+    parameter M_ADDR_WIDTH = {M_COUNT{{M_REGIONS{32'd24}}}},
+    // Read connections between interfaces
+    // M_COUNT concatenated fields of S_COUNT bits
+    parameter M_CONNECT_READ = {M_COUNT{{S_COUNT{1'b1}}}},
+    // Write connections between interfaces
+    // M_COUNT concatenated fields of S_COUNT bits
+    parameter M_CONNECT_WRITE = {M_COUNT{{S_COUNT{1'b1}}}},
+    // Number of concurrent operations for each master interface
+    // M_COUNT concatenated fields of 32 bits
+    parameter M_ISSUE = {M_COUNT{32'd4}},
+    // Secure master (fail operations based on awprot/arprot)
+    // M_COUNT bits
+    parameter M_SECURE = {M_COUNT{1'b0}},
+    // Slave interface AW channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_AW_REG_TYPE = {S_COUNT{2'd0}},
+    // Slave interface W channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_W_REG_TYPE = {S_COUNT{2'd0}},
+    // Slave interface B channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_B_REG_TYPE = {S_COUNT{2'd1}},
+    // Slave interface AR channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_AR_REG_TYPE = {S_COUNT{2'd0}},
+    // Slave interface R channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_R_REG_TYPE = {S_COUNT{2'd2}},
+    // Master interface AW channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_AW_REG_TYPE = {M_COUNT{2'd1}},
+    // Master interface W channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_W_REG_TYPE = {M_COUNT{2'd2}},
+    // Master interface B channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_B_REG_TYPE = {M_COUNT{2'd0}},
+    // Master interface AR channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_AR_REG_TYPE = {M_COUNT{2'd1}},
+    // Master interface R channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_R_REG_TYPE = {M_COUNT{2'd0}}
+)
+(
+    input  wire                             clk,
+    input  wire                             rst,
+
+    /*
+     * AXI slave interfaces
+     */
+    input  wire [S_COUNT*S_ID_WIDTH-1:0]    s_axi_awid,
+    input  wire [S_COUNT*ADDR_WIDTH-1:0]    s_axi_awaddr,
+    input  wire [S_COUNT*8-1:0]             s_axi_awlen,
+    input  wire [S_COUNT*3-1:0]             s_axi_awsize,
+    input  wire [S_COUNT*2-1:0]             s_axi_awburst,
+    input  wire [S_COUNT-1:0]               s_axi_awlock,
+    input  wire [S_COUNT*4-1:0]             s_axi_awcache,
+    input  wire [S_COUNT*3-1:0]             s_axi_awprot,
+    input  wire [S_COUNT*4-1:0]             s_axi_awqos,
+    input  wire [S_COUNT*AWUSER_WIDTH-1:0]  s_axi_awuser,
+    input  wire [S_COUNT-1:0]               s_axi_awvalid,
+    output wire [S_COUNT-1:0]               s_axi_awready,
+    input  wire [S_COUNT*DATA_WIDTH-1:0]    s_axi_wdata,
+    input  wire [S_COUNT*STRB_WIDTH-1:0]    s_axi_wstrb,
+    input  wire [S_COUNT-1:0]               s_axi_wlast,
+    input  wire [S_COUNT*WUSER_WIDTH-1:0]   s_axi_wuser,
+    input  wire [S_COUNT-1:0]               s_axi_wvalid,
+    output wire [S_COUNT-1:0]               s_axi_wready,
+    output wire [S_COUNT*S_ID_WIDTH-1:0]    s_axi_bid,
+    output wire [S_COUNT*2-1:0]             s_axi_bresp,
+    output wire [S_COUNT*BUSER_WIDTH-1:0]   s_axi_buser,
+    output wire [S_COUNT-1:0]               s_axi_bvalid,
+    input  wire [S_COUNT-1:0]               s_axi_bready,
+    input  wire [S_COUNT*S_ID_WIDTH-1:0]    s_axi_arid,
+    input  wire [S_COUNT*ADDR_WIDTH-1:0]    s_axi_araddr,
+    input  wire [S_COUNT*8-1:0]             s_axi_arlen,
+    input  wire [S_COUNT*3-1:0]             s_axi_arsize,
+    input  wire [S_COUNT*2-1:0]             s_axi_arburst,
+    input  wire [S_COUNT-1:0]               s_axi_arlock,
+    input  wire [S_COUNT*4-1:0]             s_axi_arcache,
+    input  wire [S_COUNT*3-1:0]             s_axi_arprot,
+    input  wire [S_COUNT*4-1:0]             s_axi_arqos,
+    input  wire [S_COUNT*ARUSER_WIDTH-1:0]  s_axi_aruser,
+    input  wire [S_COUNT-1:0]               s_axi_arvalid,
+    output wire [S_COUNT-1:0]               s_axi_arready,
+    output wire [S_COUNT*S_ID_WIDTH-1:0]    s_axi_rid,
+    output wire [S_COUNT*DATA_WIDTH-1:0]    s_axi_rdata,
+    output wire [S_COUNT*2-1:0]             s_axi_rresp,
+    output wire [S_COUNT-1:0]               s_axi_rlast,
+    output wire [S_COUNT*RUSER_WIDTH-1:0]   s_axi_ruser,
+    output wire [S_COUNT-1:0]               s_axi_rvalid,
+    input  wire [S_COUNT-1:0]               s_axi_rready,
+
+    /*
+     * AXI master interfaces
+     */
+    output wire [M_COUNT*M_ID_WIDTH-1:0]    m_axi_awid,
+    output wire [M_COUNT*ADDR_WIDTH-1:0]    m_axi_awaddr,
+    output wire [M_COUNT*8-1:0]             m_axi_awlen,
+    output wire [M_COUNT*3-1:0]             m_axi_awsize,
+    output wire [M_COUNT*2-1:0]             m_axi_awburst,
+    output wire [M_COUNT-1:0]               m_axi_awlock,
+    output wire [M_COUNT*4-1:0]             m_axi_awcache,
+    output wire [M_COUNT*3-1:0]             m_axi_awprot,
+    output wire [M_COUNT*4-1:0]             m_axi_awqos,
+    output wire [M_COUNT*4-1:0]             m_axi_awregion,
+    output wire [M_COUNT*AWUSER_WIDTH-1:0]  m_axi_awuser,
+    output wire [M_COUNT-1:0]               m_axi_awvalid,
+    input  wire [M_COUNT-1:0]               m_axi_awready,
+    output wire [M_COUNT*DATA_WIDTH-1:0]    m_axi_wdata,
+    output wire [M_COUNT*STRB_WIDTH-1:0]    m_axi_wstrb,
+    output wire [M_COUNT-1:0]               m_axi_wlast,
+    output wire [M_COUNT*WUSER_WIDTH-1:0]   m_axi_wuser,
+    output wire [M_COUNT-1:0]               m_axi_wvalid,
+    input  wire [M_COUNT-1:0]               m_axi_wready,
+    input  wire [M_COUNT*M_ID_WIDTH-1:0]    m_axi_bid,
+    input  wire [M_COUNT*2-1:0]             m_axi_bresp,
+    input  wire [M_COUNT*BUSER_WIDTH-1:0]   m_axi_buser,
+    input  wire [M_COUNT-1:0]               m_axi_bvalid,
+    output wire [M_COUNT-1:0]               m_axi_bready,
+    output wire [M_COUNT*M_ID_WIDTH-1:0]    m_axi_arid,
+    output wire [M_COUNT*ADDR_WIDTH-1:0]    m_axi_araddr,
+    output wire [M_COUNT*8-1:0]             m_axi_arlen,
+    output wire [M_COUNT*3-1:0]             m_axi_arsize,
+    output wire [M_COUNT*2-1:0]             m_axi_arburst,
+    output wire [M_COUNT-1:0]               m_axi_arlock,
+    output wire [M_COUNT*4-1:0]             m_axi_arcache,
+    output wire [M_COUNT*3-1:0]             m_axi_arprot,
+    output wire [M_COUNT*4-1:0]             m_axi_arqos,
+    output wire [M_COUNT*4-1:0]             m_axi_arregion,
+    output wire [M_COUNT*ARUSER_WIDTH-1:0]  m_axi_aruser,
+    output wire [M_COUNT-1:0]               m_axi_arvalid,
+    input  wire [M_COUNT-1:0]               m_axi_arready,
+    input  wire [M_COUNT*M_ID_WIDTH-1:0]    m_axi_rid,
+    input  wire [M_COUNT*DATA_WIDTH-1:0]    m_axi_rdata,
+    input  wire [M_COUNT*2-1:0]             m_axi_rresp,
+    input  wire [M_COUNT-1:0]               m_axi_rlast,
+    input  wire [M_COUNT*RUSER_WIDTH-1:0]   m_axi_ruser,
+    input  wire [M_COUNT-1:0]               m_axi_rvalid,
+    output wire [M_COUNT-1:0]               m_axi_rready
+);
+
+axi_crossbar_wr #(
+    .S_COUNT(S_COUNT),
+    .M_COUNT(M_COUNT),
+    .DATA_WIDTH(DATA_WIDTH),
+    .ADDR_WIDTH(ADDR_WIDTH),
+    .STRB_WIDTH(STRB_WIDTH),
+    .S_ID_WIDTH(S_ID_WIDTH),
+    .M_ID_WIDTH(M_ID_WIDTH),
+    .AWUSER_ENABLE(AWUSER_ENABLE),
+    .AWUSER_WIDTH(AWUSER_WIDTH),
+    .WUSER_ENABLE(WUSER_ENABLE),
+    .WUSER_WIDTH(WUSER_WIDTH),
+    .BUSER_ENABLE(BUSER_ENABLE),
+    .BUSER_WIDTH(BUSER_WIDTH),
+    .S_THREADS(S_THREADS),
+    .S_ACCEPT(S_ACCEPT),
+    .M_REGIONS(M_REGIONS),
+    .M_BASE_ADDR(M_BASE_ADDR),
+    .M_ADDR_WIDTH(M_ADDR_WIDTH),
+    .M_CONNECT(M_CONNECT_WRITE),
+    .M_ISSUE(M_ISSUE),
+    .M_SECURE(M_SECURE),
+    .S_AW_REG_TYPE(S_AW_REG_TYPE),
+    .S_W_REG_TYPE (S_W_REG_TYPE),
+    .S_B_REG_TYPE (S_B_REG_TYPE)
+)
+axi_crossbar_wr_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI slave interfaces
+     */
+    .s_axi_awid(s_axi_awid),
+    .s_axi_awaddr(s_axi_awaddr),
+    .s_axi_awlen(s_axi_awlen),
+    .s_axi_awsize(s_axi_awsize),
+    .s_axi_awburst(s_axi_awburst),
+    .s_axi_awlock(s_axi_awlock),
+    .s_axi_awcache(s_axi_awcache),
+    .s_axi_awprot(s_axi_awprot),
+    .s_axi_awqos(s_axi_awqos),
+    .s_axi_awuser(s_axi_awuser),
+    .s_axi_awvalid(s_axi_awvalid),
+    .s_axi_awready(s_axi_awready),
+    .s_axi_wdata(s_axi_wdata),
+    .s_axi_wstrb(s_axi_wstrb),
+    .s_axi_wlast(s_axi_wlast),
+    .s_axi_wuser(s_axi_wuser),
+    .s_axi_wvalid(s_axi_wvalid),
+    .s_axi_wready(s_axi_wready),
+    .s_axi_bid(s_axi_bid),
+    .s_axi_bresp(s_axi_bresp),
+    .s_axi_buser(s_axi_buser),
+    .s_axi_bvalid(s_axi_bvalid),
+    .s_axi_bready(s_axi_bready),
+
+    /*
+     * AXI master interfaces
+     */
+    .m_axi_awid(m_axi_awid),
+    .m_axi_awaddr(m_axi_awaddr),
+    .m_axi_awlen(m_axi_awlen),
+    .m_axi_awsize(m_axi_awsize),
+    .m_axi_awburst(m_axi_awburst),
+    .m_axi_awlock(m_axi_awlock),
+    .m_axi_awcache(m_axi_awcache),
+    .m_axi_awprot(m_axi_awprot),
+    .m_axi_awqos(m_axi_awqos),
+    .m_axi_awregion(m_axi_awregion),
+    .m_axi_awuser(m_axi_awuser),
+    .m_axi_awvalid(m_axi_awvalid),
+    .m_axi_awready(m_axi_awready),
+    .m_axi_wdata(m_axi_wdata),
+    .m_axi_wstrb(m_axi_wstrb),
+    .m_axi_wlast(m_axi_wlast),
+    .m_axi_wuser(m_axi_wuser),
+    .m_axi_wvalid(m_axi_wvalid),
+    .m_axi_wready(m_axi_wready),
+    .m_axi_bid(m_axi_bid),
+    .m_axi_bresp(m_axi_bresp),
+    .m_axi_buser(m_axi_buser),
+    .m_axi_bvalid(m_axi_bvalid),
+    .m_axi_bready(m_axi_bready)
+);
+
+axi_crossbar_rd #(
+    .S_COUNT(S_COUNT),
+    .M_COUNT(M_COUNT),
+    .DATA_WIDTH(DATA_WIDTH),
+    .ADDR_WIDTH(ADDR_WIDTH),
+    .STRB_WIDTH(STRB_WIDTH),
+    .S_ID_WIDTH(S_ID_WIDTH),
+    .M_ID_WIDTH(M_ID_WIDTH),
+    .ARUSER_ENABLE(ARUSER_ENABLE),
+    .ARUSER_WIDTH(ARUSER_WIDTH),
+    .RUSER_ENABLE(RUSER_ENABLE),
+    .RUSER_WIDTH(RUSER_WIDTH),
+    .S_THREADS(S_THREADS),
+    .S_ACCEPT(S_ACCEPT),
+    .M_REGIONS(M_REGIONS),
+    .M_BASE_ADDR(M_BASE_ADDR),
+    .M_ADDR_WIDTH(M_ADDR_WIDTH),
+    .M_CONNECT(M_CONNECT_READ),
+    .M_ISSUE(M_ISSUE),
+    .M_SECURE(M_SECURE),
+    .S_AR_REG_TYPE(S_AR_REG_TYPE),
+    .S_R_REG_TYPE (S_R_REG_TYPE)
+)
+axi_crossbar_rd_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI slave interfaces
+     */
+    .s_axi_arid(s_axi_arid),
+    .s_axi_araddr(s_axi_araddr),
+    .s_axi_arlen(s_axi_arlen),
+    .s_axi_arsize(s_axi_arsize),
+    .s_axi_arburst(s_axi_arburst),
+    .s_axi_arlock(s_axi_arlock),
+    .s_axi_arcache(s_axi_arcache),
+    .s_axi_arprot(s_axi_arprot),
+    .s_axi_arqos(s_axi_arqos),
+    .s_axi_aruser(s_axi_aruser),
+    .s_axi_arvalid(s_axi_arvalid),
+    .s_axi_arready(s_axi_arready),
+    .s_axi_rid(s_axi_rid),
+    .s_axi_rdata(s_axi_rdata),
+    .s_axi_rresp(s_axi_rresp),
+    .s_axi_rlast(s_axi_rlast),
+    .s_axi_ruser(s_axi_ruser),
+    .s_axi_rvalid(s_axi_rvalid),
+    .s_axi_rready(s_axi_rready),
+
+    /*
+     * AXI master interfaces
+     */
+    .m_axi_arid(m_axi_arid),
+    .m_axi_araddr(m_axi_araddr),
+    .m_axi_arlen(m_axi_arlen),
+    .m_axi_arsize(m_axi_arsize),
+    .m_axi_arburst(m_axi_arburst),
+    .m_axi_arlock(m_axi_arlock),
+    .m_axi_arcache(m_axi_arcache),
+    .m_axi_arprot(m_axi_arprot),
+    .m_axi_arqos(m_axi_arqos),
+    .m_axi_arregion(m_axi_arregion),
+    .m_axi_aruser(m_axi_aruser),
+    .m_axi_arvalid(m_axi_arvalid),
+    .m_axi_arready(m_axi_arready),
+    .m_axi_rid(m_axi_rid),
+    .m_axi_rdata(m_axi_rdata),
+    .m_axi_rresp(m_axi_rresp),
+    .m_axi_rlast(m_axi_rlast),
+    .m_axi_ruser(m_axi_ruser),
+    .m_axi_rvalid(m_axi_rvalid),
+    .m_axi_rready(m_axi_rready)
+);
+
+endmodule
+
+`resetall
diff --git a/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/axi_crossbar_2x1.v b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/axi_crossbar_2x1.v
new file mode 100644
index 00000000..8d37b678
--- /dev/null
+++ b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/axi_crossbar_2x1.v
@@ -0,0 +1,440 @@
+/*
+
+Copyright (c) 2020 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4 2x1 crossbar (wrapper)
+ */
+module axi_crossbar_2x1 #
+(
+    // Width of data bus in bits
+    parameter DATA_WIDTH = 32,
+    // Width of address bus in bits
+    parameter ADDR_WIDTH = 32,
+    // Width of wstrb (width of data bus in words)
+    parameter STRB_WIDTH = (DATA_WIDTH/8),
+    // Input ID field width (from AXI masters)
+    parameter S_ID_WIDTH = 8,
+    // Output ID field width (towards AXI slaves)
+    // Additional bits required for response routing
+    parameter M_ID_WIDTH = S_ID_WIDTH+$clog2(S_COUNT),
+    // Propagate awuser signal
+    parameter AWUSER_ENABLE = 0,
+    // Width of awuser signal
+    parameter AWUSER_WIDTH = 1,
+    // Propagate wuser signal
+    parameter WUSER_ENABLE = 0,
+    // Width of wuser signal
+    parameter WUSER_WIDTH = 1,
+    // Propagate buser signal
+    parameter BUSER_ENABLE = 0,
+    // Width of buser signal
+    parameter BUSER_WIDTH = 1,
+    // Propagate aruser signal
+    parameter ARUSER_ENABLE = 0,
+    // Width of aruser signal
+    parameter ARUSER_WIDTH = 1,
+    // Propagate ruser signal
+    parameter RUSER_ENABLE = 0,
+    // Width of ruser signal
+    parameter RUSER_WIDTH = 1,
+    // Number of concurrent unique IDs
+    parameter S00_THREADS = 2,
+    // Number of concurrent operations
+    parameter S00_ACCEPT = 16,
+    // Number of concurrent unique IDs
+    parameter S01_THREADS = 2,
+    // Number of concurrent operations
+    parameter S01_ACCEPT = 16,
+    // Number of regions per master interface
+    parameter M_REGIONS = 1,
+    // Master interface base addresses
+    // M_REGIONS concatenated fields of ADDR_WIDTH bits
+    parameter M00_BASE_ADDR = 0,
+    // Master interface address widths
+    // M_REGIONS concatenated fields of 32 bits
+    parameter M00_ADDR_WIDTH = {M_REGIONS{32'd24}},
+    // Read connections between interfaces
+    // S_COUNT bits
+    parameter M00_CONNECT_READ = 2'b11,
+    // Write connections between interfaces
+    // S_COUNT bits
+    parameter M00_CONNECT_WRITE = 2'b11,
+    // Number of concurrent operations for each master interface
+    parameter M00_ISSUE = 4,
+    // Secure master (fail operations based on awprot/arprot)
+    parameter M00_SECURE = 0,
+    // Slave interface AW channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S00_AW_REG_TYPE = 0,
+    // Slave interface W channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S00_W_REG_TYPE = 0,
+    // Slave interface B channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S00_B_REG_TYPE = 1,
+    // Slave interface AR channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S00_AR_REG_TYPE = 0,
+    // Slave interface R channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S00_R_REG_TYPE = 2,
+    // Slave interface AW channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S01_AW_REG_TYPE = 0,
+    // Slave interface W channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S01_W_REG_TYPE = 0,
+    // Slave interface B channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S01_B_REG_TYPE = 1,
+    // Slave interface AR channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S01_AR_REG_TYPE = 0,
+    // Slave interface R channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S01_R_REG_TYPE = 2,
+    // Master interface AW channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M00_AW_REG_TYPE = 1,
+    // Master interface W channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M00_W_REG_TYPE = 2,
+    // Master interface B channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M00_B_REG_TYPE = 0,
+    // Master interface AR channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M00_AR_REG_TYPE = 1,
+    // Master interface R channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M00_R_REG_TYPE = 0
+)
+(
+    input  wire                     clk,
+    input  wire                     rst,
+
+    /*
+     * AXI slave interface
+     */
+    input  wire [S_ID_WIDTH-1:0]    s00_axi_awid,
+    input  wire [ADDR_WIDTH-1:0]    s00_axi_awaddr,
+    input  wire [7:0]               s00_axi_awlen,
+    input  wire [2:0]               s00_axi_awsize,
+    input  wire [1:0]               s00_axi_awburst,
+    input  wire                     s00_axi_awlock,
+    input  wire [3:0]               s00_axi_awcache,
+    input  wire [2:0]               s00_axi_awprot,
+    input  wire [3:0]               s00_axi_awqos,
+    input  wire [AWUSER_WIDTH-1:0]  s00_axi_awuser,
+    input  wire                     s00_axi_awvalid,
+    output wire                     s00_axi_awready,
+    input  wire [DATA_WIDTH-1:0]    s00_axi_wdata,
+    input  wire [STRB_WIDTH-1:0]    s00_axi_wstrb,
+    input  wire                     s00_axi_wlast,
+    input  wire [WUSER_WIDTH-1:0]   s00_axi_wuser,
+    input  wire                     s00_axi_wvalid,
+    output wire                     s00_axi_wready,
+    output wire [S_ID_WIDTH-1:0]    s00_axi_bid,
+    output wire [1:0]               s00_axi_bresp,
+    output wire [BUSER_WIDTH-1:0]   s00_axi_buser,
+    output wire                     s00_axi_bvalid,
+    input  wire                     s00_axi_bready,
+    input  wire [S_ID_WIDTH-1:0]    s00_axi_arid,
+    input  wire [ADDR_WIDTH-1:0]    s00_axi_araddr,
+    input  wire [7:0]               s00_axi_arlen,
+    input  wire [2:0]               s00_axi_arsize,
+    input  wire [1:0]               s00_axi_arburst,
+    input  wire                     s00_axi_arlock,
+    input  wire [3:0]               s00_axi_arcache,
+    input  wire [2:0]               s00_axi_arprot,
+    input  wire [3:0]               s00_axi_arqos,
+    input  wire [ARUSER_WIDTH-1:0]  s00_axi_aruser,
+    input  wire                     s00_axi_arvalid,
+    output wire                     s00_axi_arready,
+    output wire [S_ID_WIDTH-1:0]    s00_axi_rid,
+    output wire [DATA_WIDTH-1:0]    s00_axi_rdata,
+    output wire [1:0]               s00_axi_rresp,
+    output wire                     s00_axi_rlast,
+    output wire [RUSER_WIDTH-1:0]   s00_axi_ruser,
+    output wire                     s00_axi_rvalid,
+    input  wire                     s00_axi_rready,
+
+    input  wire [S_ID_WIDTH-1:0]    s01_axi_awid,
+    input  wire [ADDR_WIDTH-1:0]    s01_axi_awaddr,
+    input  wire [7:0]               s01_axi_awlen,
+    input  wire [2:0]               s01_axi_awsize,
+    input  wire [1:0]               s01_axi_awburst,
+    input  wire                     s01_axi_awlock,
+    input  wire [3:0]               s01_axi_awcache,
+    input  wire [2:0]               s01_axi_awprot,
+    input  wire [3:0]               s01_axi_awqos,
+    input  wire [AWUSER_WIDTH-1:0]  s01_axi_awuser,
+    input  wire                     s01_axi_awvalid,
+    output wire                     s01_axi_awready,
+    input  wire [DATA_WIDTH-1:0]    s01_axi_wdata,
+    input  wire [STRB_WIDTH-1:0]    s01_axi_wstrb,
+    input  wire                     s01_axi_wlast,
+    input  wire [WUSER_WIDTH-1:0]   s01_axi_wuser,
+    input  wire                     s01_axi_wvalid,
+    output wire                     s01_axi_wready,
+    output wire [S_ID_WIDTH-1:0]    s01_axi_bid,
+    output wire [1:0]               s01_axi_bresp,
+    output wire [BUSER_WIDTH-1:0]   s01_axi_buser,
+    output wire                     s01_axi_bvalid,
+    input  wire                     s01_axi_bready,
+    input  wire [S_ID_WIDTH-1:0]    s01_axi_arid,
+    input  wire [ADDR_WIDTH-1:0]    s01_axi_araddr,
+    input  wire [7:0]               s01_axi_arlen,
+    input  wire [2:0]               s01_axi_arsize,
+    input  wire [1:0]               s01_axi_arburst,
+    input  wire                     s01_axi_arlock,
+    input  wire [3:0]               s01_axi_arcache,
+    input  wire [2:0]               s01_axi_arprot,
+    input  wire [3:0]               s01_axi_arqos,
+    input  wire [ARUSER_WIDTH-1:0]  s01_axi_aruser,
+    input  wire                     s01_axi_arvalid,
+    output wire                     s01_axi_arready,
+    output wire [S_ID_WIDTH-1:0]    s01_axi_rid,
+    output wire [DATA_WIDTH-1:0]    s01_axi_rdata,
+    output wire [1:0]               s01_axi_rresp,
+    output wire                     s01_axi_rlast,
+    output wire [RUSER_WIDTH-1:0]   s01_axi_ruser,
+    output wire                     s01_axi_rvalid,
+    input  wire                     s01_axi_rready,
+
+    /*
+     * AXI master interface
+     */
+    output wire [M_ID_WIDTH-1:0]    m00_axi_awid,
+    output wire [ADDR_WIDTH-1:0]    m00_axi_awaddr,
+    output wire [7:0]               m00_axi_awlen,
+    output wire [2:0]               m00_axi_awsize,
+    output wire [1:0]               m00_axi_awburst,
+    output wire                     m00_axi_awlock,
+    output wire [3:0]               m00_axi_awcache,
+    output wire [2:0]               m00_axi_awprot,
+    output wire [3:0]               m00_axi_awqos,
+    output wire [3:0]               m00_axi_awregion,
+    output wire [AWUSER_WIDTH-1:0]  m00_axi_awuser,
+    output wire                     m00_axi_awvalid,
+    input  wire                     m00_axi_awready,
+    output wire [DATA_WIDTH-1:0]    m00_axi_wdata,
+    output wire [STRB_WIDTH-1:0]    m00_axi_wstrb,
+    output wire                     m00_axi_wlast,
+    output wire [WUSER_WIDTH-1:0]   m00_axi_wuser,
+    output wire                     m00_axi_wvalid,
+    input  wire                     m00_axi_wready,
+    input  wire [M_ID_WIDTH-1:0]    m00_axi_bid,
+    input  wire [1:0]               m00_axi_bresp,
+    input  wire [BUSER_WIDTH-1:0]   m00_axi_buser,
+    input  wire                     m00_axi_bvalid,
+    output wire                     m00_axi_bready,
+    output wire [M_ID_WIDTH-1:0]    m00_axi_arid,
+    output wire [ADDR_WIDTH-1:0]    m00_axi_araddr,
+    output wire [7:0]               m00_axi_arlen,
+    output wire [2:0]               m00_axi_arsize,
+    output wire [1:0]               m00_axi_arburst,
+    output wire                     m00_axi_arlock,
+    output wire [3:0]               m00_axi_arcache,
+    output wire [2:0]               m00_axi_arprot,
+    output wire [3:0]               m00_axi_arqos,
+    output wire [3:0]               m00_axi_arregion,
+    output wire [ARUSER_WIDTH-1:0]  m00_axi_aruser,
+    output wire                     m00_axi_arvalid,
+    input  wire                     m00_axi_arready,
+    input  wire [M_ID_WIDTH-1:0]    m00_axi_rid,
+    input  wire [DATA_WIDTH-1:0]    m00_axi_rdata,
+    input  wire [1:0]               m00_axi_rresp,
+    input  wire                     m00_axi_rlast,
+    input  wire [RUSER_WIDTH-1:0]   m00_axi_ruser,
+    input  wire                     m00_axi_rvalid,
+    output wire                     m00_axi_rready
+);
+
+localparam S_COUNT = 2;
+localparam M_COUNT = 1;
+
+// parameter sizing helpers
+function [ADDR_WIDTH*M_REGIONS-1:0] w_a_r(input [ADDR_WIDTH*M_REGIONS-1:0] val);
+    w_a_r = val;
+endfunction
+
+function [32*M_REGIONS-1:0] w_32_r(input [32*M_REGIONS-1:0] val);
+    w_32_r = val;
+endfunction
+
+function [S_COUNT-1:0] w_s(input [S_COUNT-1:0] val);
+    w_s = val;
+endfunction
+
+function [31:0] w_32(input [31:0] val);
+    w_32 = val;
+endfunction
+
+function [1:0] w_2(input [1:0] val);
+    w_2 = val;
+endfunction
+
+function w_1(input val);
+    w_1 = val;
+endfunction
+
+axi_crossbar #(
+    .S_COUNT(S_COUNT),
+    .M_COUNT(M_COUNT),
+    .DATA_WIDTH(DATA_WIDTH),
+    .ADDR_WIDTH(ADDR_WIDTH),
+    .STRB_WIDTH(STRB_WIDTH),
+    .S_ID_WIDTH(S_ID_WIDTH),
+    .M_ID_WIDTH(M_ID_WIDTH),
+    .AWUSER_ENABLE(AWUSER_ENABLE),
+    .AWUSER_WIDTH(AWUSER_WIDTH),
+    .WUSER_ENABLE(WUSER_ENABLE),
+    .WUSER_WIDTH(WUSER_WIDTH),
+    .BUSER_ENABLE(BUSER_ENABLE),
+    .BUSER_WIDTH(BUSER_WIDTH),
+    .ARUSER_ENABLE(ARUSER_ENABLE),
+    .ARUSER_WIDTH(ARUSER_WIDTH),
+    .RUSER_ENABLE(RUSER_ENABLE),
+    .RUSER_WIDTH(RUSER_WIDTH),
+    .S_THREADS({ w_32(S01_THREADS), w_32(S00_THREADS) }),
+    .S_ACCEPT({ w_32(S01_ACCEPT), w_32(S00_ACCEPT) }),
+    .M_REGIONS(M_REGIONS),
+    .M_BASE_ADDR({ w_a_r(M00_BASE_ADDR) }),
+    .M_ADDR_WIDTH({ w_32_r(M00_ADDR_WIDTH) }),
+    .M_CONNECT_READ({ w_s(M00_CONNECT_READ) }),
+    .M_CONNECT_WRITE({ w_s(M00_CONNECT_WRITE) }),
+    .M_ISSUE({ w_32(M00_ISSUE) }),
+    .M_SECURE({ w_1(M00_SECURE) }),
+    .S_AR_REG_TYPE({ w_2(S01_AR_REG_TYPE), w_2(S00_AR_REG_TYPE) }),
+    .S_R_REG_TYPE({ w_2(S01_R_REG_TYPE), w_2(S00_R_REG_TYPE) }),
+    .S_AW_REG_TYPE({ w_2(S01_AW_REG_TYPE), w_2(S00_AW_REG_TYPE) }),
+    .S_W_REG_TYPE({ w_2(S01_W_REG_TYPE), w_2(S00_W_REG_TYPE) }),
+    .S_B_REG_TYPE({ w_2(S01_B_REG_TYPE), w_2(S00_B_REG_TYPE) }),
+    .M_AR_REG_TYPE({ w_2(M00_AR_REG_TYPE) }),
+    .M_R_REG_TYPE({ w_2(M00_R_REG_TYPE) }),
+    .M_AW_REG_TYPE({ w_2(M00_AW_REG_TYPE) }),
+    .M_W_REG_TYPE({ w_2(M00_W_REG_TYPE) }),
+    .M_B_REG_TYPE({ w_2(M00_B_REG_TYPE) })
+)
+axi_crossbar_inst (
+    .clk(clk),
+    .rst(rst),
+    .s_axi_awid({ s01_axi_awid, s00_axi_awid }),
+    .s_axi_awaddr({ s01_axi_awaddr, s00_axi_awaddr }),
+    .s_axi_awlen({ s01_axi_awlen, s00_axi_awlen }),
+    .s_axi_awsize({ s01_axi_awsize, s00_axi_awsize }),
+    .s_axi_awburst({ s01_axi_awburst, s00_axi_awburst }),
+    .s_axi_awlock({ s01_axi_awlock, s00_axi_awlock }),
+    .s_axi_awcache({ s01_axi_awcache, s00_axi_awcache }),
+    .s_axi_awprot({ s01_axi_awprot, s00_axi_awprot }),
+    .s_axi_awqos({ s01_axi_awqos, s00_axi_awqos }),
+    .s_axi_awuser({ s01_axi_awuser, s00_axi_awuser }),
+    .s_axi_awvalid({ s01_axi_awvalid, s00_axi_awvalid }),
+    .s_axi_awready({ s01_axi_awready, s00_axi_awready }),
+    .s_axi_wdata({ s01_axi_wdata, s00_axi_wdata }),
+    .s_axi_wstrb({ s01_axi_wstrb, s00_axi_wstrb }),
+    .s_axi_wlast({ s01_axi_wlast, s00_axi_wlast }),
+    .s_axi_wuser({ s01_axi_wuser, s00_axi_wuser }),
+    .s_axi_wvalid({ s01_axi_wvalid, s00_axi_wvalid }),
+    .s_axi_wready({ s01_axi_wready, s00_axi_wready }),
+    .s_axi_bid({ s01_axi_bid, s00_axi_bid }),
+    .s_axi_bresp({ s01_axi_bresp, s00_axi_bresp }),
+    .s_axi_buser({ s01_axi_buser, s00_axi_buser }),
+    .s_axi_bvalid({ s01_axi_bvalid, s00_axi_bvalid }),
+    .s_axi_bready({ s01_axi_bready, s00_axi_bready }),
+    .s_axi_arid({ s01_axi_arid, s00_axi_arid }),
+    .s_axi_araddr({ s01_axi_araddr, s00_axi_araddr }),
+    .s_axi_arlen({ s01_axi_arlen, s00_axi_arlen }),
+    .s_axi_arsize({ s01_axi_arsize, s00_axi_arsize }),
+    .s_axi_arburst({ s01_axi_arburst, s00_axi_arburst }),
+    .s_axi_arlock({ s01_axi_arlock, s00_axi_arlock }),
+    .s_axi_arcache({ s01_axi_arcache, s00_axi_arcache }),
+    .s_axi_arprot({ s01_axi_arprot, s00_axi_arprot }),
+    .s_axi_arqos({ s01_axi_arqos, s00_axi_arqos }),
+    .s_axi_aruser({ s01_axi_aruser, s00_axi_aruser }),
+    .s_axi_arvalid({ s01_axi_arvalid, s00_axi_arvalid }),
+    .s_axi_arready({ s01_axi_arready, s00_axi_arready }),
+    .s_axi_rid({ s01_axi_rid, s00_axi_rid }),
+    .s_axi_rdata({ s01_axi_rdata, s00_axi_rdata }),
+    .s_axi_rresp({ s01_axi_rresp, s00_axi_rresp }),
+    .s_axi_rlast({ s01_axi_rlast, s00_axi_rlast }),
+    .s_axi_ruser({ s01_axi_ruser, s00_axi_ruser }),
+    .s_axi_rvalid({ s01_axi_rvalid, s00_axi_rvalid }),
+    .s_axi_rready({ s01_axi_rready, s00_axi_rready }),
+    .m_axi_awid({ m00_axi_awid }),
+    .m_axi_awaddr({ m00_axi_awaddr }),
+    .m_axi_awlen({ m00_axi_awlen }),
+    .m_axi_awsize({ m00_axi_awsize }),
+    .m_axi_awburst({ m00_axi_awburst }),
+    .m_axi_awlock({ m00_axi_awlock }),
+    .m_axi_awcache({ m00_axi_awcache }),
+    .m_axi_awprot({ m00_axi_awprot }),
+    .m_axi_awqos({ m00_axi_awqos }),
+    .m_axi_awregion({ m00_axi_awregion }),
+    .m_axi_awuser({ m00_axi_awuser }),
+    .m_axi_awvalid({ m00_axi_awvalid }),
+    .m_axi_awready({ m00_axi_awready }),
+    .m_axi_wdata({ m00_axi_wdata }),
+    .m_axi_wstrb({ m00_axi_wstrb }),
+    .m_axi_wlast({ m00_axi_wlast }),
+    .m_axi_wuser({ m00_axi_wuser }),
+    .m_axi_wvalid({ m00_axi_wvalid }),
+    .m_axi_wready({ m00_axi_wready }),
+    .m_axi_bid({ m00_axi_bid }),
+    .m_axi_bresp({ m00_axi_bresp }),
+    .m_axi_buser({ m00_axi_buser }),
+    .m_axi_bvalid({ m00_axi_bvalid }),
+    .m_axi_bready({ m00_axi_bready }),
+    .m_axi_arid({ m00_axi_arid }),
+    .m_axi_araddr({ m00_axi_araddr }),
+    .m_axi_arlen({ m00_axi_arlen }),
+    .m_axi_arsize({ m00_axi_arsize }),
+    .m_axi_arburst({ m00_axi_arburst }),
+    .m_axi_arlock({ m00_axi_arlock }),
+    .m_axi_arcache({ m00_axi_arcache }),
+    .m_axi_arprot({ m00_axi_arprot }),
+    .m_axi_arqos({ m00_axi_arqos }),
+    .m_axi_arregion({ m00_axi_arregion }),
+    .m_axi_aruser({ m00_axi_aruser }),
+    .m_axi_arvalid({ m00_axi_arvalid }),
+    .m_axi_arready({ m00_axi_arready }),
+    .m_axi_rid({ m00_axi_rid }),
+    .m_axi_rdata({ m00_axi_rdata }),
+    .m_axi_rresp({ m00_axi_rresp }),
+    .m_axi_rlast({ m00_axi_rlast }),
+    .m_axi_ruser({ m00_axi_ruser }),
+    .m_axi_rvalid({ m00_axi_rvalid }),
+    .m_axi_rready({ m00_axi_rready })
+);
+
+endmodule
+
+`resetall
diff --git a/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/axi_crossbar_addr.v b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/axi_crossbar_addr.v
new file mode 100644
index 00000000..7b784652
--- /dev/null
+++ b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/axi_crossbar_addr.v
@@ -0,0 +1,418 @@
+/*
+
+Copyright (c) 2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4 crossbar address decode and admission control
+ */
+module axi_crossbar_addr #
+(
+    // Slave interface index
+    parameter S = 0,
+    // Number of AXI inputs (slave interfaces)
+    parameter S_COUNT = 4,
+    // Number of AXI outputs (master interfaces)
+    parameter M_COUNT = 4,
+    // Width of address bus in bits
+    parameter ADDR_WIDTH = 32,
+    // ID field width
+    parameter ID_WIDTH = 8,
+    // Number of concurrent unique IDs
+    parameter S_THREADS = 32'd2,
+    // Number of concurrent operations
+    parameter S_ACCEPT = 32'd16,
+    // Number of regions per master interface
+    parameter M_REGIONS = 1,
+    // Master interface base addresses
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_WIDTH bits
+    // set to zero for default addressing based on M_ADDR_WIDTH
+    parameter M_BASE_ADDR = 0,
+    // Master interface address widths
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits
+    parameter M_ADDR_WIDTH = {M_COUNT{{M_REGIONS{32'd24}}}},
+    // Connections between interfaces
+    // M_COUNT concatenated fields of S_COUNT bits
+    parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}},
+    // Secure master (fail operations based on awprot/arprot)
+    // M_COUNT bits
+    parameter M_SECURE = {M_COUNT{1'b0}},
+    // Enable write command output
+    parameter WC_OUTPUT = 0
+)
+(
+    input  wire                       clk,
+    input  wire                       rst,
+
+    /*
+     * Address input
+     */
+    input  wire [ID_WIDTH-1:0]        s_axi_aid,
+    input  wire [ADDR_WIDTH-1:0]      s_axi_aaddr,
+    input  wire [2:0]                 s_axi_aprot,
+    input  wire [3:0]                 s_axi_aqos,
+    input  wire                       s_axi_avalid,
+    output wire                       s_axi_aready,
+
+    /*
+     * Address output
+     */
+    output wire [3:0]                 m_axi_aregion,
+    output wire [$clog2(M_COUNT)-1:0] m_select,
+    output wire                       m_axi_avalid,
+    input  wire                       m_axi_aready,
+
+    /*
+     * Write command output
+     */
+    output wire [$clog2(M_COUNT)-1:0] m_wc_select,
+    output wire                       m_wc_decerr,
+    output wire                       m_wc_valid,
+    input  wire                       m_wc_ready,
+
+    /*
+     * Reply command output
+     */
+    output wire                       m_rc_decerr,
+    output wire                       m_rc_valid,
+    input  wire                       m_rc_ready,
+
+    /*
+     * Completion input
+     */
+    input  wire [ID_WIDTH-1:0]        s_cpl_id,
+    input  wire                       s_cpl_valid
+);
+
+parameter CL_S_COUNT = $clog2(S_COUNT);
+parameter CL_M_COUNT = $clog2(M_COUNT);
+
+parameter S_INT_THREADS = S_THREADS > S_ACCEPT ? S_ACCEPT : S_THREADS;
+parameter CL_S_INT_THREADS = $clog2(S_INT_THREADS);
+parameter CL_S_ACCEPT = $clog2(S_ACCEPT);
+
+// default address computation
+function [M_COUNT*M_REGIONS*ADDR_WIDTH-1:0] calcBaseAddrs(input [31:0] dummy);
+    integer i;
+    reg [ADDR_WIDTH-1:0] base;
+    reg [ADDR_WIDTH-1:0] width;
+    reg [ADDR_WIDTH-1:0] size;
+    reg [ADDR_WIDTH-1:0] mask;
+    begin
+        calcBaseAddrs = {M_COUNT*M_REGIONS*ADDR_WIDTH{1'b0}};
+        base = 0;
+        for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+            width = M_ADDR_WIDTH[i*32 +: 32];
+            mask = {ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - width);
+            size = mask + 1;
+            if (width > 0) begin
+                if ((base & mask) != 0) begin
+                   base = base + size - (base & mask); // align
+                end
+                calcBaseAddrs[i * ADDR_WIDTH +: ADDR_WIDTH] = base;
+                base = base + size; // increment
+            end
+        end
+    end
+endfunction
+
+parameter M_BASE_ADDR_INT = M_BASE_ADDR ? M_BASE_ADDR : calcBaseAddrs(0);
+
+integer i, j;
+
+// check configuration
+initial begin
+    if (S_ACCEPT < 1) begin
+        $error("Error: need at least 1 accept (instance %m)");
+        $finish;
+    end
+
+    if (S_THREADS < 1) begin
+        $error("Error: need at least 1 thread (instance %m)");
+        $finish;
+    end
+
+    if (S_THREADS > S_ACCEPT) begin
+        $warning("Warning: requested thread count larger than accept count; limiting thread count to accept count (instance %m)");
+    end
+
+    if (M_REGIONS < 1) begin
+        $error("Error: need at least 1 region (instance %m)");
+        $finish;
+    end
+
+    for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        if (M_ADDR_WIDTH[i*32 +: 32] && (M_ADDR_WIDTH[i*32 +: 32] < 12 || M_ADDR_WIDTH[i*32 +: 32] > ADDR_WIDTH)) begin
+            $error("Error: address width out of range (instance %m)");
+            $finish;
+        end
+    end
+
+    $display("Addressing configuration for axi_crossbar_addr instance %m");
+    for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        if (M_ADDR_WIDTH[i*32 +: 32]) begin
+            $display("%2d (%2d): %x / %02d -- %x-%x",
+                i/M_REGIONS, i%M_REGIONS,
+                M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH],
+                M_ADDR_WIDTH[i*32 +: 32],
+                M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[i*32 +: 32]),
+                M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[i*32 +: 32]))
+            );
+        end
+    end
+
+    for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        if ((M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] & (2**M_ADDR_WIDTH[i*32 +: 32]-1)) != 0) begin
+            $display("Region not aligned:");
+            $display("%2d (%2d): %x / %2d -- %x-%x",
+                i/M_REGIONS, i%M_REGIONS,
+                M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH],
+                M_ADDR_WIDTH[i*32 +: 32],
+                M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[i*32 +: 32]),
+                M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[i*32 +: 32]))
+            );
+            $error("Error: address range not aligned (instance %m)");
+            $finish;
+        end
+    end
+
+    for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        for (j = i+1; j < M_COUNT*M_REGIONS; j = j + 1) begin
+            if (M_ADDR_WIDTH[i*32 +: 32] && M_ADDR_WIDTH[j*32 +: 32]) begin
+                if (((M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[i*32 +: 32])) <= (M_BASE_ADDR_INT[j*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[j*32 +: 32]))))
+                        && ((M_BASE_ADDR_INT[j*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[j*32 +: 32])) <= (M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[i*32 +: 32]))))) begin
+                    $display("Overlapping regions:");
+                    $display("%2d (%2d): %x / %2d -- %x-%x",
+                        i/M_REGIONS, i%M_REGIONS,
+                        M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH],
+                        M_ADDR_WIDTH[i*32 +: 32],
+                        M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[i*32 +: 32]),
+                        M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[i*32 +: 32]))
+                    );
+                    $display("%2d (%2d): %x / %2d -- %x-%x",
+                        j/M_REGIONS, j%M_REGIONS,
+                        M_BASE_ADDR_INT[j*ADDR_WIDTH +: ADDR_WIDTH],
+                        M_ADDR_WIDTH[j*32 +: 32],
+                        M_BASE_ADDR_INT[j*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[j*32 +: 32]),
+                        M_BASE_ADDR_INT[j*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[j*32 +: 32]))
+                    );
+                    $error("Error: address ranges overlap (instance %m)");
+                    $finish;
+                end
+            end
+        end
+    end
+end
+
+localparam [2:0]
+    STATE_IDLE = 3'd0,
+    STATE_DECODE = 3'd1;
+
+reg [2:0] state_reg = STATE_IDLE, state_next;
+
+reg s_axi_aready_reg = 0, s_axi_aready_next;
+
+reg [3:0] m_axi_aregion_reg = 4'd0, m_axi_aregion_next;
+reg [CL_M_COUNT-1:0] m_select_reg = 0, m_select_next;
+reg m_axi_avalid_reg = 1'b0, m_axi_avalid_next;
+reg m_decerr_reg = 1'b0, m_decerr_next;
+reg m_wc_valid_reg = 1'b0, m_wc_valid_next;
+reg m_rc_valid_reg = 1'b0, m_rc_valid_next;
+
+assign s_axi_aready = s_axi_aready_reg;
+
+assign m_axi_aregion = m_axi_aregion_reg;
+assign m_select = m_select_reg;
+assign m_axi_avalid = m_axi_avalid_reg;
+
+assign m_wc_select = m_select_reg;
+assign m_wc_decerr = m_decerr_reg;
+assign m_wc_valid = m_wc_valid_reg;
+
+assign m_rc_decerr = m_decerr_reg;
+assign m_rc_valid = m_rc_valid_reg;
+
+reg match;
+reg trans_start;
+reg trans_complete;
+
+reg [$clog2(S_ACCEPT+1)-1:0] trans_count_reg = 0;
+wire trans_limit = trans_count_reg >= S_ACCEPT && !trans_complete;
+
+// transfer ID thread tracking
+reg [ID_WIDTH-1:0] thread_id_reg[S_INT_THREADS-1:0];
+reg [CL_M_COUNT-1:0] thread_m_reg[S_INT_THREADS-1:0];
+reg [3:0] thread_region_reg[S_INT_THREADS-1:0];
+reg [$clog2(S_ACCEPT+1)-1:0] thread_count_reg[S_INT_THREADS-1:0];
+
+wire [S_INT_THREADS-1:0] thread_active;
+wire [S_INT_THREADS-1:0] thread_match;
+wire [S_INT_THREADS-1:0] thread_match_dest;
+wire [S_INT_THREADS-1:0] thread_cpl_match;
+wire [S_INT_THREADS-1:0] thread_trans_start;
+wire [S_INT_THREADS-1:0] thread_trans_complete;
+
+generate
+    genvar n;
+
+    for (n = 0; n < S_INT_THREADS; n = n + 1) begin
+        initial begin
+            thread_count_reg[n] <= 0;
+        end
+
+        assign thread_active[n] = thread_count_reg[n] != 0;
+        assign thread_match[n] = thread_active[n] && thread_id_reg[n] == s_axi_aid;
+        assign thread_match_dest[n] = thread_match[n] && thread_m_reg[n] == m_select_next && (M_REGIONS < 2 || thread_region_reg[n] == m_axi_aregion_next);
+        assign thread_cpl_match[n] = thread_active[n] && thread_id_reg[n] == s_cpl_id;
+        assign thread_trans_start[n] = (thread_match[n] || (!thread_active[n] && !thread_match && !(thread_trans_start & ({S_INT_THREADS{1'b1}} >> (S_INT_THREADS-n))))) && trans_start;
+        assign thread_trans_complete[n] = thread_cpl_match[n] && trans_complete;
+
+        always @(posedge clk) begin
+            if (rst) begin
+                thread_count_reg[n] <= 0;
+            end else begin
+                if (thread_trans_start[n] && !thread_trans_complete[n]) begin
+                    thread_count_reg[n] <= thread_count_reg[n] + 1;
+                end else if (!thread_trans_start[n] && thread_trans_complete[n]) begin
+                    thread_count_reg[n] <= thread_count_reg[n] - 1;
+                end
+            end
+
+            if (thread_trans_start[n]) begin
+                thread_id_reg[n] <= s_axi_aid;
+                thread_m_reg[n] <= m_select_next;
+                thread_region_reg[n] <= m_axi_aregion_next;
+            end
+        end
+    end
+endgenerate
+
+always @* begin
+    state_next = STATE_IDLE;
+
+    match = 1'b0;
+    trans_start = 1'b0;
+    trans_complete = 1'b0;
+
+    s_axi_aready_next = 1'b0;
+
+    m_axi_aregion_next = m_axi_aregion_reg;
+    m_select_next = m_select_reg;
+    m_axi_avalid_next = m_axi_avalid_reg && !m_axi_aready;
+    m_decerr_next = m_decerr_reg;
+    m_wc_valid_next = m_wc_valid_reg && !m_wc_ready;
+    m_rc_valid_next = m_rc_valid_reg && !m_rc_ready;
+
+    case (state_reg)
+        STATE_IDLE: begin
+            // idle state, store values
+            s_axi_aready_next = 1'b0;
+
+            if (s_axi_avalid && !s_axi_aready) begin
+                match = 1'b0;
+                for (i = 0; i < M_COUNT; i = i + 1) begin
+                    for (j = 0; j < M_REGIONS; j = j + 1) begin
+                        if (M_ADDR_WIDTH[(i*M_REGIONS+j)*32 +: 32] && (!M_SECURE[i] || !s_axi_aprot[1]) && (M_CONNECT & (1 << (S+i*S_COUNT))) && (s_axi_aaddr >> M_ADDR_WIDTH[(i*M_REGIONS+j)*32 +: 32]) == (M_BASE_ADDR_INT[(i*M_REGIONS+j)*ADDR_WIDTH +: ADDR_WIDTH] >> M_ADDR_WIDTH[(i*M_REGIONS+j)*32 +: 32])) begin
+                            m_select_next = i;
+                            m_axi_aregion_next = j;
+                            match = 1'b1;
+                        end
+                    end
+                end
+
+                if (match) begin
+                    // address decode successful
+                    if (!trans_limit && (thread_match_dest || (!(&thread_active) && !thread_match))) begin
+                        // transaction limit not reached
+                        m_axi_avalid_next = 1'b1;
+                        m_decerr_next = 1'b0;
+                        m_wc_valid_next = WC_OUTPUT;
+                        m_rc_valid_next = 1'b0;
+                        trans_start = 1'b1;
+                        state_next = STATE_DECODE;
+                    end else begin
+                        // transaction limit reached; block in idle
+                        state_next = STATE_IDLE;
+                    end
+                end else begin
+                    // decode error
+                    m_axi_avalid_next = 1'b0;
+                    m_decerr_next = 1'b1;
+                    m_wc_valid_next = WC_OUTPUT;
+                    m_rc_valid_next = 1'b1;
+                    state_next = STATE_DECODE;
+                end
+            end else begin
+                state_next = STATE_IDLE;
+            end
+        end
+        STATE_DECODE: begin
+            if (!m_axi_avalid_next && (!m_wc_valid_next || !WC_OUTPUT) && !m_rc_valid_next) begin
+                s_axi_aready_next = 1'b1;
+                state_next = STATE_IDLE;
+            end else begin
+                state_next = STATE_DECODE;
+            end
+        end
+    endcase
+
+    // manage completions
+    trans_complete = s_cpl_valid;
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        state_reg <= STATE_IDLE;
+        s_axi_aready_reg <= 1'b0;
+        m_axi_avalid_reg <= 1'b0;
+        m_wc_valid_reg <= 1'b0;
+        m_rc_valid_reg <= 1'b0;
+
+        trans_count_reg <= 0;
+    end else begin
+        state_reg <= state_next;
+        s_axi_aready_reg <= s_axi_aready_next;
+        m_axi_avalid_reg <= m_axi_avalid_next;
+        m_wc_valid_reg <= m_wc_valid_next;
+        m_rc_valid_reg <= m_rc_valid_next;
+
+        if (trans_start && !trans_complete) begin
+            trans_count_reg <= trans_count_reg + 1;
+        end else if (!trans_start && trans_complete) begin
+            trans_count_reg <= trans_count_reg - 1;
+        end
+    end
+
+    m_axi_aregion_reg <= m_axi_aregion_next;
+    m_select_reg <= m_select_next;
+    m_decerr_reg <= m_decerr_next;
+end
+
+endmodule
+
+`resetall
diff --git a/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/axi_crossbar_rd.v b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/axi_crossbar_rd.v
new file mode 100644
index 00000000..2b1410ac
--- /dev/null
+++ b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/axi_crossbar_rd.v
@@ -0,0 +1,569 @@
+/*
+
+Copyright (c) 2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4 crossbar (read)
+ */
+module axi_crossbar_rd #
+(
+    // Number of AXI inputs (slave interfaces)
+    parameter S_COUNT = 4,
+    // Number of AXI outputs (master interfaces)
+    parameter M_COUNT = 4,
+    // Width of data bus in bits
+    parameter DATA_WIDTH = 32,
+    // Width of address bus in bits
+    parameter ADDR_WIDTH = 32,
+    // Width of wstrb (width of data bus in words)
+    parameter STRB_WIDTH = (DATA_WIDTH/8),
+    // Input ID field width (from AXI masters)
+    parameter S_ID_WIDTH = 8,
+    // Output ID field width (towards AXI slaves)
+    // Additional bits required for response routing
+    parameter M_ID_WIDTH = S_ID_WIDTH+$clog2(S_COUNT),
+    // Propagate aruser signal
+    parameter ARUSER_ENABLE = 0,
+    // Width of aruser signal
+    parameter ARUSER_WIDTH = 1,
+    // Propagate ruser signal
+    parameter RUSER_ENABLE = 0,
+    // Width of ruser signal
+    parameter RUSER_WIDTH = 1,
+    // Number of concurrent unique IDs for each slave interface
+    // S_COUNT concatenated fields of 32 bits
+    parameter S_THREADS = {S_COUNT{32'd2}},
+    // Number of concurrent operations for each slave interface
+    // S_COUNT concatenated fields of 32 bits
+    parameter S_ACCEPT = {S_COUNT{32'd16}},
+    // Number of regions per master interface
+    parameter M_REGIONS = 1,
+    // Master interface base addresses
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_WIDTH bits
+    // set to zero for default addressing based on M_ADDR_WIDTH
+    parameter M_BASE_ADDR = 0,
+    // Master interface address widths
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits
+    parameter M_ADDR_WIDTH = {M_COUNT{{M_REGIONS{32'd24}}}},
+    // Read connections between interfaces
+    // M_COUNT concatenated fields of S_COUNT bits
+    parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}},
+    // Number of concurrent operations for each master interface
+    // M_COUNT concatenated fields of 32 bits
+    parameter M_ISSUE = {M_COUNT{32'd4}},
+    // Secure master (fail operations based on awprot/arprot)
+    // M_COUNT bits
+    parameter M_SECURE = {M_COUNT{1'b0}},
+    // Slave interface AR channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_AR_REG_TYPE = {S_COUNT{2'd0}},
+    // Slave interface R channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_R_REG_TYPE = {S_COUNT{2'd2}},
+    // Master interface AR channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_AR_REG_TYPE = {M_COUNT{2'd1}},
+    // Master interface R channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_R_REG_TYPE = {M_COUNT{2'd0}}
+)
+(
+    input  wire                             clk,
+    input  wire                             rst,
+
+    /*
+     * AXI slave interfaces
+     */
+    input  wire [S_COUNT*S_ID_WIDTH-1:0]    s_axi_arid,
+    input  wire [S_COUNT*ADDR_WIDTH-1:0]    s_axi_araddr,
+    input  wire [S_COUNT*8-1:0]             s_axi_arlen,
+    input  wire [S_COUNT*3-1:0]             s_axi_arsize,
+    input  wire [S_COUNT*2-1:0]             s_axi_arburst,
+    input  wire [S_COUNT-1:0]               s_axi_arlock,
+    input  wire [S_COUNT*4-1:0]             s_axi_arcache,
+    input  wire [S_COUNT*3-1:0]             s_axi_arprot,
+    input  wire [S_COUNT*4-1:0]             s_axi_arqos,
+    input  wire [S_COUNT*ARUSER_WIDTH-1:0]  s_axi_aruser,
+    input  wire [S_COUNT-1:0]               s_axi_arvalid,
+    output wire [S_COUNT-1:0]               s_axi_arready,
+    output wire [S_COUNT*S_ID_WIDTH-1:0]    s_axi_rid,
+    output wire [S_COUNT*DATA_WIDTH-1:0]    s_axi_rdata,
+    output wire [S_COUNT*2-1:0]             s_axi_rresp,
+    output wire [S_COUNT-1:0]               s_axi_rlast,
+    output wire [S_COUNT*RUSER_WIDTH-1:0]   s_axi_ruser,
+    output wire [S_COUNT-1:0]               s_axi_rvalid,
+    input  wire [S_COUNT-1:0]               s_axi_rready,
+
+    /*
+     * AXI master interfaces
+     */
+    output wire [M_COUNT*M_ID_WIDTH-1:0]    m_axi_arid,
+    output wire [M_COUNT*ADDR_WIDTH-1:0]    m_axi_araddr,
+    output wire [M_COUNT*8-1:0]             m_axi_arlen,
+    output wire [M_COUNT*3-1:0]             m_axi_arsize,
+    output wire [M_COUNT*2-1:0]             m_axi_arburst,
+    output wire [M_COUNT-1:0]               m_axi_arlock,
+    output wire [M_COUNT*4-1:0]             m_axi_arcache,
+    output wire [M_COUNT*3-1:0]             m_axi_arprot,
+    output wire [M_COUNT*4-1:0]             m_axi_arqos,
+    output wire [M_COUNT*4-1:0]             m_axi_arregion,
+    output wire [M_COUNT*ARUSER_WIDTH-1:0]  m_axi_aruser,
+    output wire [M_COUNT-1:0]               m_axi_arvalid,
+    input  wire [M_COUNT-1:0]               m_axi_arready,
+    input  wire [M_COUNT*M_ID_WIDTH-1:0]    m_axi_rid,
+    input  wire [M_COUNT*DATA_WIDTH-1:0]    m_axi_rdata,
+    input  wire [M_COUNT*2-1:0]             m_axi_rresp,
+    input  wire [M_COUNT-1:0]               m_axi_rlast,
+    input  wire [M_COUNT*RUSER_WIDTH-1:0]   m_axi_ruser,
+    input  wire [M_COUNT-1:0]               m_axi_rvalid,
+    output wire [M_COUNT-1:0]               m_axi_rready
+);
+
+parameter CL_S_COUNT = $clog2(S_COUNT);
+parameter CL_M_COUNT = $clog2(M_COUNT);
+parameter M_COUNT_P1 = M_COUNT+1;
+parameter CL_M_COUNT_P1 = $clog2(M_COUNT_P1);
+
+integer i;
+
+// check configuration
+initial begin
+    if (M_ID_WIDTH < S_ID_WIDTH+$clog2(S_COUNT)) begin
+        $error("Error: M_ID_WIDTH must be at least $clog2(S_COUNT) larger than S_ID_WIDTH (instance %m)");
+        $finish;
+    end
+
+    for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        if (M_ADDR_WIDTH[i*32 +: 32] && (M_ADDR_WIDTH[i*32 +: 32] < 12 || M_ADDR_WIDTH[i*32 +: 32] > ADDR_WIDTH)) begin
+            $error("Error: value out of range (instance %m)");
+            $finish;
+        end
+    end
+end
+
+wire [S_COUNT*S_ID_WIDTH-1:0]    int_s_axi_arid;
+wire [S_COUNT*ADDR_WIDTH-1:0]    int_s_axi_araddr;
+wire [S_COUNT*8-1:0]             int_s_axi_arlen;
+wire [S_COUNT*3-1:0]             int_s_axi_arsize;
+wire [S_COUNT*2-1:0]             int_s_axi_arburst;
+wire [S_COUNT-1:0]               int_s_axi_arlock;
+wire [S_COUNT*4-1:0]             int_s_axi_arcache;
+wire [S_COUNT*3-1:0]             int_s_axi_arprot;
+wire [S_COUNT*4-1:0]             int_s_axi_arqos;
+wire [S_COUNT*4-1:0]             int_s_axi_arregion;
+wire [S_COUNT*ARUSER_WIDTH-1:0]  int_s_axi_aruser;
+wire [S_COUNT-1:0]               int_s_axi_arvalid;
+wire [S_COUNT-1:0]               int_s_axi_arready;
+
+wire [S_COUNT*M_COUNT-1:0]       int_axi_arvalid;
+wire [M_COUNT*S_COUNT-1:0]       int_axi_arready;
+
+wire [M_COUNT*M_ID_WIDTH-1:0]    int_m_axi_rid;
+wire [M_COUNT*DATA_WIDTH-1:0]    int_m_axi_rdata;
+wire [M_COUNT*2-1:0]             int_m_axi_rresp;
+wire [M_COUNT-1:0]               int_m_axi_rlast;
+wire [M_COUNT*RUSER_WIDTH-1:0]   int_m_axi_ruser;
+wire [M_COUNT-1:0]               int_m_axi_rvalid;
+wire [M_COUNT-1:0]               int_m_axi_rready;
+
+wire [M_COUNT*S_COUNT-1:0]       int_axi_rvalid;
+wire [S_COUNT*M_COUNT-1:0]       int_axi_rready;
+
+generate
+
+    genvar m, n;
+
+    for (m = 0; m < S_COUNT; m = m + 1) begin : s_ifaces
+        // address decode and admission control
+        wire [CL_M_COUNT-1:0] a_select;
+
+        wire m_axi_avalid;
+        wire m_axi_aready;
+
+        wire m_rc_decerr;
+        wire m_rc_valid;
+        wire m_rc_ready;
+
+        wire [S_ID_WIDTH-1:0] s_cpl_id;
+        wire s_cpl_valid;
+
+        axi_crossbar_addr #(
+            .S(m),
+            .S_COUNT(S_COUNT),
+            .M_COUNT(M_COUNT),
+            .ADDR_WIDTH(ADDR_WIDTH),
+            .ID_WIDTH(S_ID_WIDTH),
+            .S_THREADS(S_THREADS[m*32 +: 32]),
+            .S_ACCEPT(S_ACCEPT[m*32 +: 32]),
+            .M_REGIONS(M_REGIONS),
+            .M_BASE_ADDR(M_BASE_ADDR),
+            .M_ADDR_WIDTH(M_ADDR_WIDTH),
+            .M_CONNECT(M_CONNECT),
+            .M_SECURE(M_SECURE),
+            .WC_OUTPUT(0)
+        )
+        addr_inst (
+            .clk(clk),
+            .rst(rst),
+
+            /*
+             * Address input
+             */
+            .s_axi_aid(int_s_axi_arid[m*S_ID_WIDTH +: S_ID_WIDTH]),
+            .s_axi_aaddr(int_s_axi_araddr[m*ADDR_WIDTH +: ADDR_WIDTH]),
+            .s_axi_aprot(int_s_axi_arprot[m*3 +: 3]),
+            .s_axi_aqos(int_s_axi_arqos[m*4 +: 4]),
+            .s_axi_avalid(int_s_axi_arvalid[m]),
+            .s_axi_aready(int_s_axi_arready[m]),
+
+            /*
+             * Address output
+             */
+            .m_axi_aregion(int_s_axi_arregion[m*4 +: 4]),
+            .m_select(a_select),
+            .m_axi_avalid(m_axi_avalid),
+            .m_axi_aready(m_axi_aready),
+
+            /*
+             * Write command output
+             */
+            .m_wc_select(),
+            .m_wc_decerr(),
+            .m_wc_valid(),
+            .m_wc_ready(1'b1),
+
+            /*
+             * Response command output
+             */
+            .m_rc_decerr(m_rc_decerr),
+            .m_rc_valid(m_rc_valid),
+            .m_rc_ready(m_rc_ready),
+
+            /*
+             * Completion input
+             */
+            .s_cpl_id(s_cpl_id),
+            .s_cpl_valid(s_cpl_valid)
+        );
+
+        assign int_axi_arvalid[m*M_COUNT +: M_COUNT] = m_axi_avalid << a_select;
+        assign m_axi_aready = int_axi_arready[a_select*S_COUNT+m];
+
+        // decode error handling
+        reg [S_ID_WIDTH-1:0]  decerr_m_axi_rid_reg = {S_ID_WIDTH{1'b0}}, decerr_m_axi_rid_next;
+        reg                   decerr_m_axi_rlast_reg = 1'b0, decerr_m_axi_rlast_next;
+        reg                   decerr_m_axi_rvalid_reg = 1'b0, decerr_m_axi_rvalid_next;
+        wire                  decerr_m_axi_rready;
+
+        reg [7:0] decerr_len_reg = 8'd0, decerr_len_next;
+
+        assign m_rc_ready = !decerr_m_axi_rvalid_reg;
+
+        always @* begin
+            decerr_len_next = decerr_len_reg;
+            decerr_m_axi_rid_next = decerr_m_axi_rid_reg;
+            decerr_m_axi_rlast_next = decerr_m_axi_rlast_reg;
+            decerr_m_axi_rvalid_next = decerr_m_axi_rvalid_reg;
+
+            if (decerr_m_axi_rvalid_reg) begin
+                if (decerr_m_axi_rready) begin
+                    if (decerr_len_reg > 0) begin
+                        decerr_len_next = decerr_len_reg-1;
+                        decerr_m_axi_rlast_next = (decerr_len_next == 0);
+                        decerr_m_axi_rvalid_next = 1'b1;
+                    end else begin
+                        decerr_m_axi_rvalid_next = 1'b0;
+                    end
+                end
+            end else if (m_rc_valid && m_rc_ready) begin
+                decerr_len_next = int_s_axi_arlen[m*8 +: 8];
+                decerr_m_axi_rid_next = int_s_axi_arid[m*S_ID_WIDTH +: S_ID_WIDTH];
+                decerr_m_axi_rlast_next = (decerr_len_next == 0);
+                decerr_m_axi_rvalid_next = 1'b1;
+            end
+        end
+
+        always @(posedge clk) begin
+            if (rst) begin
+                decerr_m_axi_rvalid_reg <= 1'b0;
+            end else begin
+                decerr_m_axi_rvalid_reg <= decerr_m_axi_rvalid_next;
+            end
+
+            decerr_m_axi_rid_reg <= decerr_m_axi_rid_next;
+            decerr_m_axi_rlast_reg <= decerr_m_axi_rlast_next;
+            decerr_len_reg <= decerr_len_next;
+        end
+
+        // read response arbitration
+        wire [M_COUNT_P1-1:0] r_request;
+        wire [M_COUNT_P1-1:0] r_acknowledge;
+        wire [M_COUNT_P1-1:0] r_grant;
+        wire r_grant_valid;
+        wire [CL_M_COUNT_P1-1:0] r_grant_encoded;
+
+        arbiter #(
+            .PORTS(M_COUNT_P1),
+            .ARB_TYPE_ROUND_ROBIN(1),
+            .ARB_BLOCK(1),
+            .ARB_BLOCK_ACK(1),
+            .ARB_LSB_HIGH_PRIORITY(1)
+        )
+        r_arb_inst (
+            .clk(clk),
+            .rst(rst),
+            .request(r_request),
+            .acknowledge(r_acknowledge),
+            .grant(r_grant),
+            .grant_valid(r_grant_valid),
+            .grant_encoded(r_grant_encoded)
+        );
+
+        // read response mux
+        wire [S_ID_WIDTH-1:0]  m_axi_rid_mux    = {decerr_m_axi_rid_reg, int_m_axi_rid} >> r_grant_encoded*M_ID_WIDTH;
+        wire [DATA_WIDTH-1:0]  m_axi_rdata_mux  = {{DATA_WIDTH{1'b0}}, int_m_axi_rdata} >> r_grant_encoded*DATA_WIDTH;
+        wire [1:0]             m_axi_rresp_mux  = {2'b11, int_m_axi_rresp} >> r_grant_encoded*2;
+        wire                   m_axi_rlast_mux  = {decerr_m_axi_rlast_reg, int_m_axi_rlast} >> r_grant_encoded;
+        wire [RUSER_WIDTH-1:0] m_axi_ruser_mux  = {{RUSER_WIDTH{1'b0}}, int_m_axi_ruser} >> r_grant_encoded*RUSER_WIDTH;
+        wire                   m_axi_rvalid_mux = ({decerr_m_axi_rvalid_reg, int_m_axi_rvalid} >> r_grant_encoded) & r_grant_valid;
+        wire                   m_axi_rready_mux;
+
+        assign int_axi_rready[m*M_COUNT +: M_COUNT] = (r_grant_valid && m_axi_rready_mux) << r_grant_encoded;
+        assign decerr_m_axi_rready = (r_grant_valid && m_axi_rready_mux) && (r_grant_encoded == M_COUNT_P1-1);
+
+        for (n = 0; n < M_COUNT; n = n + 1) begin
+            assign r_request[n] = int_axi_rvalid[n*S_COUNT+m] && !r_grant[n];
+            assign r_acknowledge[n] = r_grant[n] && int_axi_rvalid[n*S_COUNT+m] && m_axi_rlast_mux && m_axi_rready_mux;
+        end
+
+        assign r_request[M_COUNT_P1-1] = decerr_m_axi_rvalid_reg && !r_grant[M_COUNT_P1-1];
+        assign r_acknowledge[M_COUNT_P1-1] = r_grant[M_COUNT_P1-1] && decerr_m_axi_rvalid_reg && decerr_m_axi_rlast_reg && m_axi_rready_mux;
+
+        assign s_cpl_id = m_axi_rid_mux;
+        assign s_cpl_valid = m_axi_rvalid_mux && m_axi_rready_mux && m_axi_rlast_mux;
+
+        // S side register
+        axi_register_rd #(
+            .DATA_WIDTH(DATA_WIDTH),
+            .ADDR_WIDTH(ADDR_WIDTH),
+            .STRB_WIDTH(STRB_WIDTH),
+            .ID_WIDTH(S_ID_WIDTH),
+            .ARUSER_ENABLE(ARUSER_ENABLE),
+            .ARUSER_WIDTH(ARUSER_WIDTH),
+            .RUSER_ENABLE(RUSER_ENABLE),
+            .RUSER_WIDTH(RUSER_WIDTH),
+            .AR_REG_TYPE(S_AR_REG_TYPE[m*2 +: 2]),
+            .R_REG_TYPE(S_R_REG_TYPE[m*2 +: 2])
+        )
+        reg_inst (
+            .clk(clk),
+            .rst(rst),
+            .s_axi_arid(s_axi_arid[m*S_ID_WIDTH +: S_ID_WIDTH]),
+            .s_axi_araddr(s_axi_araddr[m*ADDR_WIDTH +: ADDR_WIDTH]),
+            .s_axi_arlen(s_axi_arlen[m*8 +: 8]),
+            .s_axi_arsize(s_axi_arsize[m*3 +: 3]),
+            .s_axi_arburst(s_axi_arburst[m*2 +: 2]),
+            .s_axi_arlock(s_axi_arlock[m]),
+            .s_axi_arcache(s_axi_arcache[m*4 +: 4]),
+            .s_axi_arprot(s_axi_arprot[m*3 +: 3]),
+            .s_axi_arqos(s_axi_arqos[m*4 +: 4]),
+            .s_axi_arregion(4'd0),
+            .s_axi_aruser(s_axi_aruser[m*ARUSER_WIDTH +: ARUSER_WIDTH]),
+            .s_axi_arvalid(s_axi_arvalid[m]),
+            .s_axi_arready(s_axi_arready[m]),
+            .s_axi_rid(s_axi_rid[m*S_ID_WIDTH +: S_ID_WIDTH]),
+            .s_axi_rdata(s_axi_rdata[m*DATA_WIDTH +: DATA_WIDTH]),
+            .s_axi_rresp(s_axi_rresp[m*2 +: 2]),
+            .s_axi_rlast(s_axi_rlast[m]),
+            .s_axi_ruser(s_axi_ruser[m*RUSER_WIDTH +: RUSER_WIDTH]),
+            .s_axi_rvalid(s_axi_rvalid[m]),
+            .s_axi_rready(s_axi_rready[m]),
+            .m_axi_arid(int_s_axi_arid[m*S_ID_WIDTH +: S_ID_WIDTH]),
+            .m_axi_araddr(int_s_axi_araddr[m*ADDR_WIDTH +: ADDR_WIDTH]),
+            .m_axi_arlen(int_s_axi_arlen[m*8 +: 8]),
+            .m_axi_arsize(int_s_axi_arsize[m*3 +: 3]),
+            .m_axi_arburst(int_s_axi_arburst[m*2 +: 2]),
+            .m_axi_arlock(int_s_axi_arlock[m]),
+            .m_axi_arcache(int_s_axi_arcache[m*4 +: 4]),
+            .m_axi_arprot(int_s_axi_arprot[m*3 +: 3]),
+            .m_axi_arqos(int_s_axi_arqos[m*4 +: 4]),
+            .m_axi_arregion(),
+            .m_axi_aruser(int_s_axi_aruser[m*ARUSER_WIDTH +: ARUSER_WIDTH]),
+            .m_axi_arvalid(int_s_axi_arvalid[m]),
+            .m_axi_arready(int_s_axi_arready[m]),
+            .m_axi_rid(m_axi_rid_mux),
+            .m_axi_rdata(m_axi_rdata_mux),
+            .m_axi_rresp(m_axi_rresp_mux),
+            .m_axi_rlast(m_axi_rlast_mux),
+            .m_axi_ruser(m_axi_ruser_mux),
+            .m_axi_rvalid(m_axi_rvalid_mux),
+            .m_axi_rready(m_axi_rready_mux)
+        );
+    end // s_ifaces
+
+    for (n = 0; n < M_COUNT; n = n + 1) begin : m_ifaces
+        // in-flight transaction count
+        wire trans_start;
+        wire trans_complete;
+        reg [$clog2(M_ISSUE[n*32 +: 32]+1)-1:0] trans_count_reg = 0;
+
+        wire trans_limit = trans_count_reg >= M_ISSUE[n*32 +: 32] && !trans_complete;
+
+        always @(posedge clk) begin
+            if (rst) begin
+                trans_count_reg <= 0;
+            end else begin
+                if (trans_start && !trans_complete) begin
+                    trans_count_reg <= trans_count_reg + 1;
+                end else if (!trans_start && trans_complete) begin
+                    trans_count_reg <= trans_count_reg - 1;
+                end
+            end
+        end
+
+        // address arbitration
+        wire [S_COUNT-1:0] a_request;
+        wire [S_COUNT-1:0] a_acknowledge;
+        wire [S_COUNT-1:0] a_grant;
+        wire a_grant_valid;
+        wire [CL_S_COUNT-1:0] a_grant_encoded;
+
+        arbiter #(
+            .PORTS(S_COUNT),
+            .ARB_TYPE_ROUND_ROBIN(1),
+            .ARB_BLOCK(1),
+            .ARB_BLOCK_ACK(1),
+            .ARB_LSB_HIGH_PRIORITY(1)
+        )
+        a_arb_inst (
+            .clk(clk),
+            .rst(rst),
+            .request(a_request),
+            .acknowledge(a_acknowledge),
+            .grant(a_grant),
+            .grant_valid(a_grant_valid),
+            .grant_encoded(a_grant_encoded)
+        );
+
+        // address mux
+        wire [M_ID_WIDTH-1:0]   s_axi_arid_mux     = int_s_axi_arid[a_grant_encoded*S_ID_WIDTH +: S_ID_WIDTH] | (a_grant_encoded << S_ID_WIDTH);
+        wire [ADDR_WIDTH-1:0]   s_axi_araddr_mux   = int_s_axi_araddr[a_grant_encoded*ADDR_WIDTH +: ADDR_WIDTH];
+        wire [7:0]              s_axi_arlen_mux    = int_s_axi_arlen[a_grant_encoded*8 +: 8];
+        wire [2:0]              s_axi_arsize_mux   = int_s_axi_arsize[a_grant_encoded*3 +: 3];
+        wire [1:0]              s_axi_arburst_mux  = int_s_axi_arburst[a_grant_encoded*2 +: 2];
+        wire                    s_axi_arlock_mux   = int_s_axi_arlock[a_grant_encoded];
+        wire [3:0]              s_axi_arcache_mux  = int_s_axi_arcache[a_grant_encoded*4 +: 4];
+        wire [2:0]              s_axi_arprot_mux   = int_s_axi_arprot[a_grant_encoded*3 +: 3];
+        wire [3:0]              s_axi_arqos_mux    = int_s_axi_arqos[a_grant_encoded*4 +: 4];
+        wire [3:0]              s_axi_arregion_mux = int_s_axi_arregion[a_grant_encoded*4 +: 4];
+        wire [ARUSER_WIDTH-1:0] s_axi_aruser_mux   = int_s_axi_aruser[a_grant_encoded*ARUSER_WIDTH +: ARUSER_WIDTH];
+        wire                    s_axi_arvalid_mux  = int_axi_arvalid[a_grant_encoded*M_COUNT+n] && a_grant_valid;
+        wire                    s_axi_arready_mux;
+
+        assign int_axi_arready[n*S_COUNT +: S_COUNT] = (a_grant_valid && s_axi_arready_mux) << a_grant_encoded;
+
+        for (m = 0; m < S_COUNT; m = m + 1) begin
+            assign a_request[m] = int_axi_arvalid[m*M_COUNT+n] && !a_grant[m] && !trans_limit;
+            assign a_acknowledge[m] = a_grant[m] && int_axi_arvalid[m*M_COUNT+n] && s_axi_arready_mux;
+        end
+
+        assign trans_start = s_axi_arvalid_mux && s_axi_arready_mux && a_grant_valid;
+
+        // read response forwarding
+        wire [CL_S_COUNT-1:0] r_select = m_axi_rid[n*M_ID_WIDTH +: M_ID_WIDTH] >> S_ID_WIDTH;
+
+        assign int_axi_rvalid[n*S_COUNT +: S_COUNT] = int_m_axi_rvalid[n] << r_select;
+        assign int_m_axi_rready[n] = int_axi_rready[r_select*M_COUNT+n];
+
+        assign trans_complete = int_m_axi_rvalid[n] && int_m_axi_rready[n] && int_m_axi_rlast[n];
+
+        // M side register
+        axi_register_rd #(
+            .DATA_WIDTH(DATA_WIDTH),
+            .ADDR_WIDTH(ADDR_WIDTH),
+            .STRB_WIDTH(STRB_WIDTH),
+            .ID_WIDTH(M_ID_WIDTH),
+            .ARUSER_ENABLE(ARUSER_ENABLE),
+            .ARUSER_WIDTH(ARUSER_WIDTH),
+            .RUSER_ENABLE(RUSER_ENABLE),
+            .RUSER_WIDTH(RUSER_WIDTH),
+            .AR_REG_TYPE(M_AR_REG_TYPE[n*2 +: 2]),
+            .R_REG_TYPE(M_R_REG_TYPE[n*2 +: 2])
+        )
+        reg_inst (
+            .clk(clk),
+            .rst(rst),
+            .s_axi_arid(s_axi_arid_mux),
+            .s_axi_araddr(s_axi_araddr_mux),
+            .s_axi_arlen(s_axi_arlen_mux),
+            .s_axi_arsize(s_axi_arsize_mux),
+            .s_axi_arburst(s_axi_arburst_mux),
+            .s_axi_arlock(s_axi_arlock_mux),
+            .s_axi_arcache(s_axi_arcache_mux),
+            .s_axi_arprot(s_axi_arprot_mux),
+            .s_axi_arqos(s_axi_arqos_mux),
+            .s_axi_arregion(s_axi_arregion_mux),
+            .s_axi_aruser(s_axi_aruser_mux),
+            .s_axi_arvalid(s_axi_arvalid_mux),
+            .s_axi_arready(s_axi_arready_mux),
+            .s_axi_rid(int_m_axi_rid[n*M_ID_WIDTH +: M_ID_WIDTH]),
+            .s_axi_rdata(int_m_axi_rdata[n*DATA_WIDTH +: DATA_WIDTH]),
+            .s_axi_rresp(int_m_axi_rresp[n*2 +: 2]),
+            .s_axi_rlast(int_m_axi_rlast[n]),
+            .s_axi_ruser(int_m_axi_ruser[n*RUSER_WIDTH +: RUSER_WIDTH]),
+            .s_axi_rvalid(int_m_axi_rvalid[n]),
+            .s_axi_rready(int_m_axi_rready[n]),
+            .m_axi_arid(m_axi_arid[n*M_ID_WIDTH +: M_ID_WIDTH]),
+            .m_axi_araddr(m_axi_araddr[n*ADDR_WIDTH +: ADDR_WIDTH]),
+            .m_axi_arlen(m_axi_arlen[n*8 +: 8]),
+            .m_axi_arsize(m_axi_arsize[n*3 +: 3]),
+            .m_axi_arburst(m_axi_arburst[n*2 +: 2]),
+            .m_axi_arlock(m_axi_arlock[n]),
+            .m_axi_arcache(m_axi_arcache[n*4 +: 4]),
+            .m_axi_arprot(m_axi_arprot[n*3 +: 3]),
+            .m_axi_arqos(m_axi_arqos[n*4 +: 4]),
+            .m_axi_arregion(m_axi_arregion[n*4 +: 4]),
+            .m_axi_aruser(m_axi_aruser[n*ARUSER_WIDTH +: ARUSER_WIDTH]),
+            .m_axi_arvalid(m_axi_arvalid[n]),
+            .m_axi_arready(m_axi_arready[n]),
+            .m_axi_rid(m_axi_rid[n*M_ID_WIDTH +: M_ID_WIDTH]),
+            .m_axi_rdata(m_axi_rdata[n*DATA_WIDTH +: DATA_WIDTH]),
+            .m_axi_rresp(m_axi_rresp[n*2 +: 2]),
+            .m_axi_rlast(m_axi_rlast[n]),
+            .m_axi_ruser(m_axi_ruser[n*RUSER_WIDTH +: RUSER_WIDTH]),
+            .m_axi_rvalid(m_axi_rvalid[n]),
+            .m_axi_rready(m_axi_rready[n])
+        );
+    end // m_ifaces
+
+endgenerate
+
+endmodule
+
+`resetall
diff --git a/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/axi_crossbar_wr.v b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/axi_crossbar_wr.v
new file mode 100644
index 00000000..5f556653
--- /dev/null
+++ b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/axi_crossbar_wr.v
@@ -0,0 +1,678 @@
+/*
+
+Copyright (c) 2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4 crossbar (write)
+ */
+module axi_crossbar_wr #
+(
+    // Number of AXI inputs (slave interfaces)
+    parameter S_COUNT = 4,
+    // Number of AXI outputs (master interfaces)
+    parameter M_COUNT = 4,
+    // Width of data bus in bits
+    parameter DATA_WIDTH = 32,
+    // Width of address bus in bits
+    parameter ADDR_WIDTH = 32,
+    // Width of wstrb (width of data bus in words)
+    parameter STRB_WIDTH = (DATA_WIDTH/8),
+    // Input ID field width (from AXI masters)
+    parameter S_ID_WIDTH = 8,
+    // Output ID field width (towards AXI slaves)
+    // Additional bits required for response routing
+    parameter M_ID_WIDTH = S_ID_WIDTH+$clog2(S_COUNT),
+    // Propagate awuser signal
+    parameter AWUSER_ENABLE = 0,
+    // Width of awuser signal
+    parameter AWUSER_WIDTH = 1,
+    // Propagate wuser signal
+    parameter WUSER_ENABLE = 0,
+    // Width of wuser signal
+    parameter WUSER_WIDTH = 1,
+    // Propagate buser signal
+    parameter BUSER_ENABLE = 0,
+    // Width of buser signal
+    parameter BUSER_WIDTH = 1,
+    // Number of concurrent unique IDs for each slave interface
+    // S_COUNT concatenated fields of 32 bits
+    parameter S_THREADS = {S_COUNT{32'd2}},
+    // Number of concurrent operations for each slave interface
+    // S_COUNT concatenated fields of 32 bits
+    parameter S_ACCEPT = {S_COUNT{32'd16}},
+    // Number of regions per master interface
+    parameter M_REGIONS = 1,
+    // Master interface base addresses
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_WIDTH bits
+    // set to zero for default addressing based on M_ADDR_WIDTH
+    parameter M_BASE_ADDR = 0,
+    // Master interface address widths
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits
+    parameter M_ADDR_WIDTH = {M_COUNT{{M_REGIONS{32'd24}}}},
+    // Write connections between interfaces
+    // M_COUNT concatenated fields of S_COUNT bits
+    parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}},
+    // Number of concurrent operations for each master interface
+    // M_COUNT concatenated fields of 32 bits
+    parameter M_ISSUE = {M_COUNT{32'd4}},
+    // Secure master (fail operations based on awprot/arprot)
+    // M_COUNT bits
+    parameter M_SECURE = {M_COUNT{1'b0}},
+    // Slave interface AW channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_AW_REG_TYPE = {S_COUNT{2'd0}},
+    // Slave interface W channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_W_REG_TYPE = {S_COUNT{2'd0}},
+    // Slave interface B channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_B_REG_TYPE = {S_COUNT{2'd1}},
+    // Master interface AW channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_AW_REG_TYPE = {M_COUNT{2'd1}},
+    // Master interface W channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_W_REG_TYPE = {M_COUNT{2'd2}},
+    // Master interface B channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_B_REG_TYPE = {M_COUNT{2'd0}}
+)
+(
+    input  wire                             clk,
+    input  wire                             rst,
+
+    /*
+     * AXI slave interfaces
+     */
+    input  wire [S_COUNT*S_ID_WIDTH-1:0]    s_axi_awid,
+    input  wire [S_COUNT*ADDR_WIDTH-1:0]    s_axi_awaddr,
+    input  wire [S_COUNT*8-1:0]             s_axi_awlen,
+    input  wire [S_COUNT*3-1:0]             s_axi_awsize,
+    input  wire [S_COUNT*2-1:0]             s_axi_awburst,
+    input  wire [S_COUNT-1:0]               s_axi_awlock,
+    input  wire [S_COUNT*4-1:0]             s_axi_awcache,
+    input  wire [S_COUNT*3-1:0]             s_axi_awprot,
+    input  wire [S_COUNT*4-1:0]             s_axi_awqos,
+    input  wire [S_COUNT*AWUSER_WIDTH-1:0]  s_axi_awuser,
+    input  wire [S_COUNT-1:0]               s_axi_awvalid,
+    output wire [S_COUNT-1:0]               s_axi_awready,
+    input  wire [S_COUNT*DATA_WIDTH-1:0]    s_axi_wdata,
+    input  wire [S_COUNT*STRB_WIDTH-1:0]    s_axi_wstrb,
+    input  wire [S_COUNT-1:0]               s_axi_wlast,
+    input  wire [S_COUNT*WUSER_WIDTH-1:0]   s_axi_wuser,
+    input  wire [S_COUNT-1:0]               s_axi_wvalid,
+    output wire [S_COUNT-1:0]               s_axi_wready,
+    output wire [S_COUNT*S_ID_WIDTH-1:0]    s_axi_bid,
+    output wire [S_COUNT*2-1:0]             s_axi_bresp,
+    output wire [S_COUNT*BUSER_WIDTH-1:0]   s_axi_buser,
+    output wire [S_COUNT-1:0]               s_axi_bvalid,
+    input  wire [S_COUNT-1:0]               s_axi_bready,
+
+    /*
+     * AXI master interfaces
+     */
+    output wire [M_COUNT*M_ID_WIDTH-1:0]    m_axi_awid,
+    output wire [M_COUNT*ADDR_WIDTH-1:0]    m_axi_awaddr,
+    output wire [M_COUNT*8-1:0]             m_axi_awlen,
+    output wire [M_COUNT*3-1:0]             m_axi_awsize,
+    output wire [M_COUNT*2-1:0]             m_axi_awburst,
+    output wire [M_COUNT-1:0]               m_axi_awlock,
+    output wire [M_COUNT*4-1:0]             m_axi_awcache,
+    output wire [M_COUNT*3-1:0]             m_axi_awprot,
+    output wire [M_COUNT*4-1:0]             m_axi_awqos,
+    output wire [M_COUNT*4-1:0]             m_axi_awregion,
+    output wire [M_COUNT*AWUSER_WIDTH-1:0]  m_axi_awuser,
+    output wire [M_COUNT-1:0]               m_axi_awvalid,
+    input  wire [M_COUNT-1:0]               m_axi_awready,
+    output wire [M_COUNT*DATA_WIDTH-1:0]    m_axi_wdata,
+    output wire [M_COUNT*STRB_WIDTH-1:0]    m_axi_wstrb,
+    output wire [M_COUNT-1:0]               m_axi_wlast,
+    output wire [M_COUNT*WUSER_WIDTH-1:0]   m_axi_wuser,
+    output wire [M_COUNT-1:0]               m_axi_wvalid,
+    input  wire [M_COUNT-1:0]               m_axi_wready,
+    input  wire [M_COUNT*M_ID_WIDTH-1:0]    m_axi_bid,
+    input  wire [M_COUNT*2-1:0]             m_axi_bresp,
+    input  wire [M_COUNT*BUSER_WIDTH-1:0]   m_axi_buser,
+    input  wire [M_COUNT-1:0]               m_axi_bvalid,
+    output wire [M_COUNT-1:0]               m_axi_bready
+);
+
+parameter CL_S_COUNT = $clog2(S_COUNT);
+parameter CL_M_COUNT = $clog2(M_COUNT);
+parameter M_COUNT_P1 = M_COUNT+1;
+parameter CL_M_COUNT_P1 = $clog2(M_COUNT_P1);
+
+integer i;
+
+// check configuration
+initial begin
+    if (M_ID_WIDTH < S_ID_WIDTH+$clog2(S_COUNT)) begin
+        $error("Error: M_ID_WIDTH must be at least $clog2(S_COUNT) larger than S_ID_WIDTH (instance %m)");
+        $finish;
+    end
+
+    for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        if (M_ADDR_WIDTH[i*32 +: 32] && (M_ADDR_WIDTH[i*32 +: 32] < 12 || M_ADDR_WIDTH[i*32 +: 32] > ADDR_WIDTH)) begin
+            $error("Error: value out of range (instance %m)");
+            $finish;
+        end
+    end
+end
+
+wire [S_COUNT*S_ID_WIDTH-1:0]    int_s_axi_awid;
+wire [S_COUNT*ADDR_WIDTH-1:0]    int_s_axi_awaddr;
+wire [S_COUNT*8-1:0]             int_s_axi_awlen;
+wire [S_COUNT*3-1:0]             int_s_axi_awsize;
+wire [S_COUNT*2-1:0]             int_s_axi_awburst;
+wire [S_COUNT-1:0]               int_s_axi_awlock;
+wire [S_COUNT*4-1:0]             int_s_axi_awcache;
+wire [S_COUNT*3-1:0]             int_s_axi_awprot;
+wire [S_COUNT*4-1:0]             int_s_axi_awqos;
+wire [S_COUNT*4-1:0]             int_s_axi_awregion;
+wire [S_COUNT*AWUSER_WIDTH-1:0]  int_s_axi_awuser;
+wire [S_COUNT-1:0]               int_s_axi_awvalid;
+wire [S_COUNT-1:0]               int_s_axi_awready;
+
+wire [S_COUNT*M_COUNT-1:0]       int_axi_awvalid;
+wire [M_COUNT*S_COUNT-1:0]       int_axi_awready;
+
+wire [S_COUNT*DATA_WIDTH-1:0]    int_s_axi_wdata;
+wire [S_COUNT*STRB_WIDTH-1:0]    int_s_axi_wstrb;
+wire [S_COUNT-1:0]               int_s_axi_wlast;
+wire [S_COUNT*WUSER_WIDTH-1:0]   int_s_axi_wuser;
+wire [S_COUNT-1:0]               int_s_axi_wvalid;
+wire [S_COUNT-1:0]               int_s_axi_wready;
+
+wire [S_COUNT*M_COUNT-1:0]       int_axi_wvalid;
+wire [M_COUNT*S_COUNT-1:0]       int_axi_wready;
+
+wire [M_COUNT*M_ID_WIDTH-1:0]    int_m_axi_bid;
+wire [M_COUNT*2-1:0]             int_m_axi_bresp;
+wire [M_COUNT*BUSER_WIDTH-1:0]   int_m_axi_buser;
+wire [M_COUNT-1:0]               int_m_axi_bvalid;
+wire [M_COUNT-1:0]               int_m_axi_bready;
+
+wire [M_COUNT*S_COUNT-1:0]       int_axi_bvalid;
+wire [S_COUNT*M_COUNT-1:0]       int_axi_bready;
+
+generate
+
+    genvar m, n;
+
+    for (m = 0; m < S_COUNT; m = m + 1) begin : s_ifaces
+        // address decode and admission control
+        wire [CL_M_COUNT-1:0] a_select;
+
+        wire m_axi_avalid;
+        wire m_axi_aready;
+
+        wire [CL_M_COUNT-1:0] m_wc_select;
+        wire m_wc_decerr;
+        wire m_wc_valid;
+        wire m_wc_ready;
+
+        wire m_rc_decerr;
+        wire m_rc_valid;
+        wire m_rc_ready;
+
+        wire [S_ID_WIDTH-1:0] s_cpl_id;
+        wire s_cpl_valid;
+
+        axi_crossbar_addr #(
+            .S(m),
+            .S_COUNT(S_COUNT),
+            .M_COUNT(M_COUNT),
+            .ADDR_WIDTH(ADDR_WIDTH),
+            .ID_WIDTH(S_ID_WIDTH),
+            .S_THREADS(S_THREADS[m*32 +: 32]),
+            .S_ACCEPT(S_ACCEPT[m*32 +: 32]),
+            .M_REGIONS(M_REGIONS),
+            .M_BASE_ADDR(M_BASE_ADDR),
+            .M_ADDR_WIDTH(M_ADDR_WIDTH),
+            .M_CONNECT(M_CONNECT),
+            .M_SECURE(M_SECURE),
+            .WC_OUTPUT(1)
+        )
+        addr_inst (
+            .clk(clk),
+            .rst(rst),
+
+            /*
+             * Address input
+             */
+            .s_axi_aid(int_s_axi_awid[m*S_ID_WIDTH +: S_ID_WIDTH]),
+            .s_axi_aaddr(int_s_axi_awaddr[m*ADDR_WIDTH +: ADDR_WIDTH]),
+            .s_axi_aprot(int_s_axi_awprot[m*3 +: 3]),
+            .s_axi_aqos(int_s_axi_awqos[m*4 +: 4]),
+            .s_axi_avalid(int_s_axi_awvalid[m]),
+            .s_axi_aready(int_s_axi_awready[m]),
+
+            /*
+             * Address output
+             */
+            .m_axi_aregion(int_s_axi_awregion[m*4 +: 4]),
+            .m_select(a_select),
+            .m_axi_avalid(m_axi_avalid),
+            .m_axi_aready(m_axi_aready),
+
+            /*
+             * Write command output
+             */
+            .m_wc_select(m_wc_select),
+            .m_wc_decerr(m_wc_decerr),
+            .m_wc_valid(m_wc_valid),
+            .m_wc_ready(m_wc_ready),
+
+            /*
+             * Response command output
+             */
+            .m_rc_decerr(m_rc_decerr),
+            .m_rc_valid(m_rc_valid),
+            .m_rc_ready(m_rc_ready),
+
+            /*
+             * Completion input
+             */
+            .s_cpl_id(s_cpl_id),
+            .s_cpl_valid(s_cpl_valid)
+        );
+
+        assign int_axi_awvalid[m*M_COUNT +: M_COUNT] = m_axi_avalid << a_select;
+        assign m_axi_aready = int_axi_awready[a_select*S_COUNT+m];
+
+        // write command handling
+        reg [CL_M_COUNT-1:0] w_select_reg = 0, w_select_next;
+        reg w_drop_reg = 1'b0, w_drop_next;
+        reg w_select_valid_reg = 1'b0, w_select_valid_next;
+
+        assign m_wc_ready = !w_select_valid_reg;
+
+        always @* begin
+            w_select_next = w_select_reg;
+            w_drop_next = w_drop_reg && !(int_s_axi_wvalid[m] && int_s_axi_wready[m] && int_s_axi_wlast[m]);
+            w_select_valid_next = w_select_valid_reg && !(int_s_axi_wvalid[m] && int_s_axi_wready[m] && int_s_axi_wlast[m]);
+
+            if (m_wc_valid && !w_select_valid_reg) begin
+                w_select_next = m_wc_select;
+                w_drop_next = m_wc_decerr;
+                w_select_valid_next = m_wc_valid;
+            end
+        end
+
+        always @(posedge clk) begin
+            if (rst) begin
+                w_select_valid_reg <= 1'b0;
+            end else begin
+                w_select_valid_reg <= w_select_valid_next;
+            end
+
+            w_select_reg <= w_select_next;
+            w_drop_reg <= w_drop_next;
+        end
+
+        // write data forwarding
+        assign int_axi_wvalid[m*M_COUNT +: M_COUNT] = (int_s_axi_wvalid[m] && w_select_valid_reg && !w_drop_reg) << w_select_reg;
+        assign int_s_axi_wready[m] = int_axi_wready[w_select_reg*S_COUNT+m] || w_drop_reg;
+
+        // decode error handling
+        reg [S_ID_WIDTH-1:0]  decerr_m_axi_bid_reg = {S_ID_WIDTH{1'b0}}, decerr_m_axi_bid_next;
+        reg                   decerr_m_axi_bvalid_reg = 1'b0, decerr_m_axi_bvalid_next;
+        wire                  decerr_m_axi_bready;
+
+        assign m_rc_ready = !decerr_m_axi_bvalid_reg;
+
+        always @* begin
+            decerr_m_axi_bid_next = decerr_m_axi_bid_reg;
+            decerr_m_axi_bvalid_next = decerr_m_axi_bvalid_reg;
+
+            if (decerr_m_axi_bvalid_reg) begin
+                if (decerr_m_axi_bready) begin
+                    decerr_m_axi_bvalid_next = 1'b0;
+                end
+            end else if (m_rc_valid && m_rc_ready) begin
+                decerr_m_axi_bid_next = int_s_axi_awid[m*S_ID_WIDTH +: S_ID_WIDTH];
+                decerr_m_axi_bvalid_next = 1'b1;
+            end
+        end
+
+        always @(posedge clk) begin
+            if (rst) begin
+                decerr_m_axi_bvalid_reg <= 1'b0;
+            end else begin
+                decerr_m_axi_bvalid_reg <= decerr_m_axi_bvalid_next;
+            end
+
+            decerr_m_axi_bid_reg <= decerr_m_axi_bid_next;
+        end
+
+        // write response arbitration
+        wire [M_COUNT_P1-1:0] b_request;
+        wire [M_COUNT_P1-1:0] b_acknowledge;
+        wire [M_COUNT_P1-1:0] b_grant;
+        wire b_grant_valid;
+        wire [CL_M_COUNT_P1-1:0] b_grant_encoded;
+
+        arbiter #(
+            .PORTS(M_COUNT_P1),
+            .ARB_TYPE_ROUND_ROBIN(1),
+            .ARB_BLOCK(1),
+            .ARB_BLOCK_ACK(1),
+            .ARB_LSB_HIGH_PRIORITY(1)
+        )
+        b_arb_inst (
+            .clk(clk),
+            .rst(rst),
+            .request(b_request),
+            .acknowledge(b_acknowledge),
+            .grant(b_grant),
+            .grant_valid(b_grant_valid),
+            .grant_encoded(b_grant_encoded)
+        );
+
+        // write response mux
+        wire [S_ID_WIDTH-1:0]  m_axi_bid_mux    = {decerr_m_axi_bid_reg, int_m_axi_bid} >> b_grant_encoded*M_ID_WIDTH;
+        wire [1:0]             m_axi_bresp_mux  = {2'b11, int_m_axi_bresp} >> b_grant_encoded*2;
+        wire [BUSER_WIDTH-1:0] m_axi_buser_mux  = {{BUSER_WIDTH{1'b0}}, int_m_axi_buser} >> b_grant_encoded*BUSER_WIDTH;
+        wire                   m_axi_bvalid_mux = ({decerr_m_axi_bvalid_reg, int_m_axi_bvalid} >> b_grant_encoded) & b_grant_valid;
+        wire                   m_axi_bready_mux;
+
+        assign int_axi_bready[m*M_COUNT +: M_COUNT] = (b_grant_valid && m_axi_bready_mux) << b_grant_encoded;
+        assign decerr_m_axi_bready = (b_grant_valid && m_axi_bready_mux) && (b_grant_encoded == M_COUNT_P1-1);
+
+        for (n = 0; n < M_COUNT; n = n + 1) begin
+            assign b_request[n] = int_axi_bvalid[n*S_COUNT+m] && !b_grant[n];
+            assign b_acknowledge[n] = b_grant[n] && int_axi_bvalid[n*S_COUNT+m] && m_axi_bready_mux;
+        end
+
+        assign b_request[M_COUNT_P1-1] = decerr_m_axi_bvalid_reg && !b_grant[M_COUNT_P1-1];
+        assign b_acknowledge[M_COUNT_P1-1] = b_grant[M_COUNT_P1-1] && decerr_m_axi_bvalid_reg && m_axi_bready_mux;
+
+        assign s_cpl_id = m_axi_bid_mux;
+        assign s_cpl_valid = m_axi_bvalid_mux && m_axi_bready_mux;
+
+        // S side register
+        axi_register_wr #(
+            .DATA_WIDTH(DATA_WIDTH),
+            .ADDR_WIDTH(ADDR_WIDTH),
+            .STRB_WIDTH(STRB_WIDTH),
+            .ID_WIDTH(S_ID_WIDTH),
+            .AWUSER_ENABLE(AWUSER_ENABLE),
+            .AWUSER_WIDTH(AWUSER_WIDTH),
+            .WUSER_ENABLE(WUSER_ENABLE),
+            .WUSER_WIDTH(WUSER_WIDTH),
+            .BUSER_ENABLE(BUSER_ENABLE),
+            .BUSER_WIDTH(BUSER_WIDTH),
+            .AW_REG_TYPE(S_AW_REG_TYPE[m*2 +: 2]),
+            .W_REG_TYPE(S_W_REG_TYPE[m*2 +: 2]),
+            .B_REG_TYPE(S_B_REG_TYPE[m*2 +: 2])
+        )
+        reg_inst (
+            .clk(clk),
+            .rst(rst),
+            .s_axi_awid(s_axi_awid[m*S_ID_WIDTH +: S_ID_WIDTH]),
+            .s_axi_awaddr(s_axi_awaddr[m*ADDR_WIDTH +: ADDR_WIDTH]),
+            .s_axi_awlen(s_axi_awlen[m*8 +: 8]),
+            .s_axi_awsize(s_axi_awsize[m*3 +: 3]),
+            .s_axi_awburst(s_axi_awburst[m*2 +: 2]),
+            .s_axi_awlock(s_axi_awlock[m]),
+            .s_axi_awcache(s_axi_awcache[m*4 +: 4]),
+            .s_axi_awprot(s_axi_awprot[m*3 +: 3]),
+            .s_axi_awqos(s_axi_awqos[m*4 +: 4]),
+            .s_axi_awregion(4'd0),
+            .s_axi_awuser(s_axi_awuser[m*AWUSER_WIDTH +: AWUSER_WIDTH]),
+            .s_axi_awvalid(s_axi_awvalid[m]),
+            .s_axi_awready(s_axi_awready[m]),
+            .s_axi_wdata(s_axi_wdata[m*DATA_WIDTH +: DATA_WIDTH]),
+            .s_axi_wstrb(s_axi_wstrb[m*STRB_WIDTH +: STRB_WIDTH]),
+            .s_axi_wlast(s_axi_wlast[m]),
+            .s_axi_wuser(s_axi_wuser[m*WUSER_WIDTH +: WUSER_WIDTH]),
+            .s_axi_wvalid(s_axi_wvalid[m]),
+            .s_axi_wready(s_axi_wready[m]),
+            .s_axi_bid(s_axi_bid[m*S_ID_WIDTH +: S_ID_WIDTH]),
+            .s_axi_bresp(s_axi_bresp[m*2 +: 2]),
+            .s_axi_buser(s_axi_buser[m*BUSER_WIDTH +: BUSER_WIDTH]),
+            .s_axi_bvalid(s_axi_bvalid[m]),
+            .s_axi_bready(s_axi_bready[m]),
+            .m_axi_awid(int_s_axi_awid[m*S_ID_WIDTH +: S_ID_WIDTH]),
+            .m_axi_awaddr(int_s_axi_awaddr[m*ADDR_WIDTH +: ADDR_WIDTH]),
+            .m_axi_awlen(int_s_axi_awlen[m*8 +: 8]),
+            .m_axi_awsize(int_s_axi_awsize[m*3 +: 3]),
+            .m_axi_awburst(int_s_axi_awburst[m*2 +: 2]),
+            .m_axi_awlock(int_s_axi_awlock[m]),
+            .m_axi_awcache(int_s_axi_awcache[m*4 +: 4]),
+            .m_axi_awprot(int_s_axi_awprot[m*3 +: 3]),
+            .m_axi_awqos(int_s_axi_awqos[m*4 +: 4]),
+            .m_axi_awregion(),
+            .m_axi_awuser(int_s_axi_awuser[m*AWUSER_WIDTH +: AWUSER_WIDTH]),
+            .m_axi_awvalid(int_s_axi_awvalid[m]),
+            .m_axi_awready(int_s_axi_awready[m]),
+            .m_axi_wdata(int_s_axi_wdata[m*DATA_WIDTH +: DATA_WIDTH]),
+            .m_axi_wstrb(int_s_axi_wstrb[m*STRB_WIDTH +: STRB_WIDTH]),
+            .m_axi_wlast(int_s_axi_wlast[m]),
+            .m_axi_wuser(int_s_axi_wuser[m*WUSER_WIDTH +: WUSER_WIDTH]),
+            .m_axi_wvalid(int_s_axi_wvalid[m]),
+            .m_axi_wready(int_s_axi_wready[m]),
+            .m_axi_bid(m_axi_bid_mux),
+            .m_axi_bresp(m_axi_bresp_mux),
+            .m_axi_buser(m_axi_buser_mux),
+            .m_axi_bvalid(m_axi_bvalid_mux),
+            .m_axi_bready(m_axi_bready_mux)
+        );
+    end // s_ifaces
+
+    for (n = 0; n < M_COUNT; n = n + 1) begin : m_ifaces
+        // in-flight transaction count
+        wire trans_start;
+        wire trans_complete;
+        reg [$clog2(M_ISSUE[n*32 +: 32]+1)-1:0] trans_count_reg = 0;
+
+        wire trans_limit = trans_count_reg >= M_ISSUE[n*32 +: 32] && !trans_complete;
+
+        always @(posedge clk) begin
+            if (rst) begin
+                trans_count_reg <= 0;
+            end else begin
+                if (trans_start && !trans_complete) begin
+                    trans_count_reg <= trans_count_reg + 1;
+                end else if (!trans_start && trans_complete) begin
+                    trans_count_reg <= trans_count_reg - 1;
+                end
+            end
+        end
+
+        // address arbitration
+        reg [CL_S_COUNT-1:0] w_select_reg = 0, w_select_next;
+        reg w_select_valid_reg = 1'b0, w_select_valid_next;
+        reg w_select_new_reg = 1'b0, w_select_new_next;
+
+        wire [S_COUNT-1:0] a_request;
+        wire [S_COUNT-1:0] a_acknowledge;
+        wire [S_COUNT-1:0] a_grant;
+        wire a_grant_valid;
+        wire [CL_S_COUNT-1:0] a_grant_encoded;
+
+        arbiter #(
+            .PORTS(S_COUNT),
+            .ARB_TYPE_ROUND_ROBIN(1),
+            .ARB_BLOCK(1),
+            .ARB_BLOCK_ACK(1),
+            .ARB_LSB_HIGH_PRIORITY(1)
+        )
+        a_arb_inst (
+            .clk(clk),
+            .rst(rst),
+            .request(a_request),
+            .acknowledge(a_acknowledge),
+            .grant(a_grant),
+            .grant_valid(a_grant_valid),
+            .grant_encoded(a_grant_encoded)
+        );
+
+        // address mux
+        wire [M_ID_WIDTH-1:0]   s_axi_awid_mux     = int_s_axi_awid[a_grant_encoded*S_ID_WIDTH +: S_ID_WIDTH] | (a_grant_encoded << S_ID_WIDTH);
+        wire [ADDR_WIDTH-1:0]   s_axi_awaddr_mux   = int_s_axi_awaddr[a_grant_encoded*ADDR_WIDTH +: ADDR_WIDTH];
+        wire [7:0]              s_axi_awlen_mux    = int_s_axi_awlen[a_grant_encoded*8 +: 8];
+        wire [2:0]              s_axi_awsize_mux   = int_s_axi_awsize[a_grant_encoded*3 +: 3];
+        wire [1:0]              s_axi_awburst_mux  = int_s_axi_awburst[a_grant_encoded*2 +: 2];
+        wire                    s_axi_awlock_mux   = int_s_axi_awlock[a_grant_encoded];
+        wire [3:0]              s_axi_awcache_mux  = int_s_axi_awcache[a_grant_encoded*4 +: 4];
+        wire [2:0]              s_axi_awprot_mux   = int_s_axi_awprot[a_grant_encoded*3 +: 3];
+        wire [3:0]              s_axi_awqos_mux    = int_s_axi_awqos[a_grant_encoded*4 +: 4];
+        wire [3:0]              s_axi_awregion_mux = int_s_axi_awregion[a_grant_encoded*4 +: 4];
+        wire [AWUSER_WIDTH-1:0] s_axi_awuser_mux   = int_s_axi_awuser[a_grant_encoded*AWUSER_WIDTH +: AWUSER_WIDTH];
+        wire                    s_axi_awvalid_mux  = int_axi_awvalid[a_grant_encoded*M_COUNT+n] && a_grant_valid;
+        wire                    s_axi_awready_mux;
+
+        assign int_axi_awready[n*S_COUNT +: S_COUNT] = (a_grant_valid && s_axi_awready_mux) << a_grant_encoded;
+
+        for (m = 0; m < S_COUNT; m = m + 1) begin
+            assign a_request[m] = int_axi_awvalid[m*M_COUNT+n] && !a_grant[m] && !trans_limit && !w_select_valid_next;
+            assign a_acknowledge[m] = a_grant[m] && int_axi_awvalid[m*M_COUNT+n] && s_axi_awready_mux;
+        end
+
+        assign trans_start = s_axi_awvalid_mux && s_axi_awready_mux && a_grant_valid;
+
+        // write data mux
+        wire [DATA_WIDTH-1:0]  s_axi_wdata_mux   = int_s_axi_wdata[w_select_reg*DATA_WIDTH +: DATA_WIDTH];
+        wire [STRB_WIDTH-1:0]  s_axi_wstrb_mux   = int_s_axi_wstrb[w_select_reg*STRB_WIDTH +: STRB_WIDTH];
+        wire                   s_axi_wlast_mux   = int_s_axi_wlast[w_select_reg];
+        wire [WUSER_WIDTH-1:0] s_axi_wuser_mux   = int_s_axi_wuser[w_select_reg*WUSER_WIDTH +: WUSER_WIDTH];
+        wire                   s_axi_wvalid_mux  = int_axi_wvalid[w_select_reg*M_COUNT+n] && w_select_valid_reg;
+        wire                   s_axi_wready_mux;
+
+        assign int_axi_wready[n*S_COUNT +: S_COUNT] = (w_select_valid_reg && s_axi_wready_mux) << w_select_reg;
+
+        // write data routing
+        always @* begin
+            w_select_next = w_select_reg;
+            w_select_valid_next = w_select_valid_reg && !(s_axi_wvalid_mux && s_axi_wready_mux && s_axi_wlast_mux);
+            w_select_new_next = w_select_new_reg || !a_grant_valid || a_acknowledge;
+
+            if (a_grant_valid && !w_select_valid_reg && w_select_new_reg) begin
+                w_select_next = a_grant_encoded;
+                w_select_valid_next = a_grant_valid;
+                w_select_new_next = 1'b0;
+            end
+        end
+
+        always @(posedge clk) begin
+            if (rst) begin
+                w_select_valid_reg <= 1'b0;
+                w_select_new_reg <= 1'b1;
+            end else begin
+                w_select_valid_reg <= w_select_valid_next;
+                w_select_new_reg <= w_select_new_next;
+            end
+
+            w_select_reg <= w_select_next;
+        end
+
+        // write response forwarding
+        wire [CL_S_COUNT-1:0] b_select = m_axi_bid[n*M_ID_WIDTH +: M_ID_WIDTH] >> S_ID_WIDTH;
+
+        assign int_axi_bvalid[n*S_COUNT +: S_COUNT] = int_m_axi_bvalid[n] << b_select;
+        assign int_m_axi_bready[n] = int_axi_bready[b_select*M_COUNT+n];
+
+        assign trans_complete = int_m_axi_bvalid[n] && int_m_axi_bready[n];
+
+        // M side register
+        axi_register_wr #(
+            .DATA_WIDTH(DATA_WIDTH),
+            .ADDR_WIDTH(ADDR_WIDTH),
+            .STRB_WIDTH(STRB_WIDTH),
+            .ID_WIDTH(M_ID_WIDTH),
+            .AWUSER_ENABLE(AWUSER_ENABLE),
+            .AWUSER_WIDTH(AWUSER_WIDTH),
+            .WUSER_ENABLE(WUSER_ENABLE),
+            .WUSER_WIDTH(WUSER_WIDTH),
+            .BUSER_ENABLE(BUSER_ENABLE),
+            .BUSER_WIDTH(BUSER_WIDTH),
+            .AW_REG_TYPE(M_AW_REG_TYPE[n*2 +: 2]),
+            .W_REG_TYPE(M_W_REG_TYPE[n*2 +: 2]),
+            .B_REG_TYPE(M_B_REG_TYPE[n*2 +: 2])
+        )
+        reg_inst (
+            .clk(clk),
+            .rst(rst),
+            .s_axi_awid(s_axi_awid_mux),
+            .s_axi_awaddr(s_axi_awaddr_mux),
+            .s_axi_awlen(s_axi_awlen_mux),
+            .s_axi_awsize(s_axi_awsize_mux),
+            .s_axi_awburst(s_axi_awburst_mux),
+            .s_axi_awlock(s_axi_awlock_mux),
+            .s_axi_awcache(s_axi_awcache_mux),
+            .s_axi_awprot(s_axi_awprot_mux),
+            .s_axi_awqos(s_axi_awqos_mux),
+            .s_axi_awregion(s_axi_awregion_mux),
+            .s_axi_awuser(s_axi_awuser_mux),
+            .s_axi_awvalid(s_axi_awvalid_mux),
+            .s_axi_awready(s_axi_awready_mux),
+            .s_axi_wdata(s_axi_wdata_mux),
+            .s_axi_wstrb(s_axi_wstrb_mux),
+            .s_axi_wlast(s_axi_wlast_mux),
+            .s_axi_wuser(s_axi_wuser_mux),
+            .s_axi_wvalid(s_axi_wvalid_mux),
+            .s_axi_wready(s_axi_wready_mux),
+            .s_axi_bid(int_m_axi_bid[n*M_ID_WIDTH +: M_ID_WIDTH]),
+            .s_axi_bresp(int_m_axi_bresp[n*2 +: 2]),
+            .s_axi_buser(int_m_axi_buser[n*BUSER_WIDTH +: BUSER_WIDTH]),
+            .s_axi_bvalid(int_m_axi_bvalid[n]),
+            .s_axi_bready(int_m_axi_bready[n]),
+            .m_axi_awid(m_axi_awid[n*M_ID_WIDTH +: M_ID_WIDTH]),
+            .m_axi_awaddr(m_axi_awaddr[n*ADDR_WIDTH +: ADDR_WIDTH]),
+            .m_axi_awlen(m_axi_awlen[n*8 +: 8]),
+            .m_axi_awsize(m_axi_awsize[n*3 +: 3]),
+            .m_axi_awburst(m_axi_awburst[n*2 +: 2]),
+            .m_axi_awlock(m_axi_awlock[n]),
+            .m_axi_awcache(m_axi_awcache[n*4 +: 4]),
+            .m_axi_awprot(m_axi_awprot[n*3 +: 3]),
+            .m_axi_awqos(m_axi_awqos[n*4 +: 4]),
+            .m_axi_awregion(m_axi_awregion[n*4 +: 4]),
+            .m_axi_awuser(m_axi_awuser[n*AWUSER_WIDTH +: AWUSER_WIDTH]),
+            .m_axi_awvalid(m_axi_awvalid[n]),
+            .m_axi_awready(m_axi_awready[n]),
+            .m_axi_wdata(m_axi_wdata[n*DATA_WIDTH +: DATA_WIDTH]),
+            .m_axi_wstrb(m_axi_wstrb[n*STRB_WIDTH +: STRB_WIDTH]),
+            .m_axi_wlast(m_axi_wlast[n]),
+            .m_axi_wuser(m_axi_wuser[n*WUSER_WIDTH +: WUSER_WIDTH]),
+            .m_axi_wvalid(m_axi_wvalid[n]),
+            .m_axi_wready(m_axi_wready[n]),
+            .m_axi_bid(m_axi_bid[n*M_ID_WIDTH +: M_ID_WIDTH]),
+            .m_axi_bresp(m_axi_bresp[n*2 +: 2]),
+            .m_axi_buser(m_axi_buser[n*BUSER_WIDTH +: BUSER_WIDTH]),
+            .m_axi_bvalid(m_axi_bvalid[n]),
+            .m_axi_bready(m_axi_bready[n])
+        );
+    end // m_ifaces
+
+endgenerate
+
+endmodule
+
+`resetall
diff --git a/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/axi_pipeline.v b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/axi_pipeline.v
new file mode 100644
index 00000000..7f3d08fe
--- /dev/null
+++ b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/axi_pipeline.v
@@ -0,0 +1,214 @@
+module axi_pipeline #(
+  parameter
+    C_M_AXI_ID_WIDTH        = 8,
+    C_M_AXI_ADDR_WIDTH      = 32,
+    C_M_AXI_DATA_WIDTH      = 512,
+    C_M_AXI_WSTRB_WIDTH     = (512 / 8),
+
+    PIPELINE_LEVEL          = 3,
+    EnableReadChannel       = 1,
+    EnableWriteChannel      = 1
+)
+(
+  input                                          ap_clk,
+
+  // pipeline in
+  input                                          in_AWVALID,
+  output                                         in_AWREADY,
+  input   [C_M_AXI_ADDR_WIDTH - 1:0]             in_AWADDR,
+  input   [1:0]                                  in_AWBURST,
+  input   [7:0]                                  in_AWLEN,
+  input   [2:0]                                  in_AWSIZE,
+  input   [C_M_AXI_ID_WIDTH - 1:0]               in_AWID,
+
+  input                                          in_WVALID,
+  output                                         in_WREADY,
+  input   [C_M_AXI_DATA_WIDTH - 1:0]             in_WDATA,
+  input   [C_M_AXI_WSTRB_WIDTH - 1:0]            in_WSTRB,
+  input                                          in_WLAST,
+
+  output                                         in_BVALID,
+  input                                          in_BREADY,
+  output   [1:0]                                 in_BRESP,
+  output   [C_M_AXI_ID_WIDTH - 1:0]              in_BID,
+
+  input                                          in_ARVALID,
+  output                                         in_ARREADY,
+  input   [C_M_AXI_ADDR_WIDTH - 1:0]             in_ARADDR,
+  input   [1:0]                                  in_ARBURST,
+  input   [7:0]                                  in_ARLEN,
+  input   [2:0]                                  in_ARSIZE,
+  input   [C_M_AXI_ID_WIDTH - 1:0]               in_ARID,
+
+  output                                         in_RVALID,
+  input                                          in_RREADY,
+  output   [C_M_AXI_DATA_WIDTH - 1:0]            in_RDATA,
+  output                                         in_RLAST,
+  output   [C_M_AXI_ID_WIDTH - 1:0]              in_RID,
+  output   [1:0]                                 in_RRESP,
+
+  // pipeline out
+  output                                         out_AWVALID,
+  input                                          out_AWREADY,
+  output   [C_M_AXI_ADDR_WIDTH - 1:0]            out_AWADDR,
+  output   [1:0]                                 out_AWBURST,
+  output   [7:0]                                 out_AWLEN,
+  output   [2:0]                                 out_AWSIZE,
+  output   [C_M_AXI_ID_WIDTH - 1:0]              out_AWID,
+
+  output                                         out_WVALID,
+  input                                          out_WREADY,
+  output   [C_M_AXI_DATA_WIDTH - 1:0]            out_WDATA,
+  output   [C_M_AXI_WSTRB_WIDTH - 1:0]           out_WSTRB,
+  output                                         out_WLAST,
+
+  input                                          out_BVALID,
+  output                                         out_BREADY,
+  input   [1:0]                                  out_BRESP,
+  input   [C_M_AXI_ID_WIDTH - 1:0]               out_BID,
+
+  output                                         out_ARVALID,
+  input                                          out_ARREADY,
+  output   [C_M_AXI_ADDR_WIDTH - 1:0]            out_ARADDR,
+  output   [1:0]                                 out_ARBURST,
+  output   [7:0]                                 out_ARLEN,
+  output   [2:0]                                 out_ARSIZE,
+  output   [C_M_AXI_ID_WIDTH - 1:0]              out_ARID,
+
+  input                                          out_RVALID,
+  output                                         out_RREADY,
+  input   [C_M_AXI_DATA_WIDTH - 1:0]             out_RDATA,
+  input                                          out_RLAST,
+  input   [C_M_AXI_ID_WIDTH - 1:0]               out_RID,
+  input   [1:0]                                  out_RRESP
+);
+
+  relay_station
+  #(
+    .DATA_WIDTH     ( C_M_AXI_ADDR_WIDTH + C_M_AXI_ID_WIDTH + 8 + 3 + 2           ),
+    .DEPTH          ( 2                                                           ),
+    .ADDR_WIDTH     ( 1                                                           ),
+    .LEVEL          ( PIPELINE_LEVEL                                              ),
+    .CONNECT        ( EnableWriteChannel )
+  )
+  AW_pipeline
+  (
+    .clk            ( ap_clk                                                      ),
+    .reset          ( 1'b0                                                        ),
+    .if_read_ce     ( 1'b1                                                        ),
+    .if_write_ce    ( 1'b1                                                        ),
+
+    .if_din         ( {in_AWADDR,  in_AWID,  in_AWLEN,  in_AWSIZE,  in_AWBURST}   ),
+    .if_full_n      ( in_AWREADY                                                  ),
+    .if_write       ( in_AWVALID                                                  ),
+
+    .if_dout        ( {out_AWADDR, out_AWID, out_AWLEN, out_AWSIZE, out_AWBURST}  ),
+    .if_empty_n     ( out_AWVALID                                                 ),
+    .if_read        ( out_AWREADY                                                 )
+  );
+
+  relay_station
+  #(
+    .DATA_WIDTH(
+      C_M_AXI_DATA_WIDTH + C_M_AXI_WSTRB_WIDTH + 1
+    ),
+    .DEPTH(2),
+    .ADDR_WIDTH(1),
+    .LEVEL( PIPELINE_LEVEL ),
+    .CONNECT        ( EnableWriteChannel )
+  )
+  W_pipeline
+  (
+    .clk        (ap_clk),
+    .reset      ( 1'b0                  ),
+    .if_read_ce (1'b1),
+    .if_write_ce(1'b1),
+
+    .if_din     ({in_WDATA,  in_WSTRB,  in_WLAST}),
+    .if_full_n  ( in_WREADY),
+    .if_write   ( in_WVALID),
+
+    .if_dout    ({out_WDATA, out_WSTRB, out_WLAST}),
+    .if_empty_n (out_WVALID),
+    .if_read    (out_WREADY)
+  );
+
+  relay_station
+  #(
+    .DATA_WIDTH(
+      C_M_AXI_ADDR_WIDTH + C_M_AXI_ID_WIDTH + 8 + 3 + 2
+    ),
+    .DEPTH(2),
+    .ADDR_WIDTH(1),
+    .LEVEL( PIPELINE_LEVEL ),
+    .CONNECT( EnableReadChannel )
+  )
+  AR_pipeline
+  (
+    .clk        (ap_clk),
+    .reset      (1'b0),
+    .if_read_ce (1'b1),
+    .if_write_ce(1'b1),
+
+    .if_din     ({ in_ARADDR,  in_ARID,  in_ARLEN,  in_ARSIZE,  in_ARBURST}),
+    .if_full_n  ( in_ARREADY),
+    .if_write   ( in_ARVALID),
+
+    .if_dout    ({out_ARADDR, out_ARID, out_ARLEN, out_ARSIZE, out_ARBURST}),
+    .if_empty_n (out_ARVALID),
+    .if_read    (out_ARREADY)
+  );
+
+  relay_station
+  #(
+    .DATA_WIDTH(
+      C_M_AXI_DATA_WIDTH + 1 + C_M_AXI_ID_WIDTH + 2
+    ),
+    .DEPTH(2),
+    .ADDR_WIDTH(1),
+    .LEVEL( PIPELINE_LEVEL ),
+    .CONNECT( EnableReadChannel )
+  )
+  R_pipeline
+  (
+    .clk        (ap_clk),
+    .reset      (1'b0),
+    .if_read_ce (1'b1),
+    .if_write_ce(1'b1),
+
+    .if_din     ({out_RDATA, out_RLAST, out_RID, out_RRESP}),
+    .if_full_n  ( out_RREADY),
+    .if_write   ( out_RVALID),
+
+    .if_dout    ({in_RDATA,  in_RLAST,  in_RID, in_RRESP}),
+    .if_empty_n (in_RVALID),
+    .if_read    (in_RREADY)
+  );
+
+  relay_station
+  #(
+    .DATA_WIDTH(
+      2 + C_M_AXI_ID_WIDTH
+    ),
+    .DEPTH(2),
+    .ADDR_WIDTH(1),
+    .LEVEL( PIPELINE_LEVEL ),
+    .CONNECT( EnableWriteChannel )
+  )
+  B_pipeline
+  (
+    .clk        (ap_clk),
+    .reset      (1'b0),
+    .if_read_ce (1'b1),
+    .if_write_ce(1'b1),
+
+    .if_din     ({out_BRESP,  out_BID}),
+    .if_full_n  (out_BREADY),
+    .if_write   (out_BVALID),
+
+    .if_dout    ({ in_BRESP,  in_BID}),
+    .if_empty_n (in_BVALID),
+    .if_read    (in_BREADY)
+  );
+
+endmodule
diff --git a/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/axi_register_rd.v b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/axi_register_rd.v
new file mode 100644
index 00000000..c0df03a0
--- /dev/null
+++ b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/axi_register_rd.v
@@ -0,0 +1,530 @@
+/*
+
+Copyright (c) 2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4 register (read)
+ */
+module axi_register_rd #
+(
+    // Width of data bus in bits
+    parameter DATA_WIDTH = 32,
+    // Width of address bus in bits
+    parameter ADDR_WIDTH = 32,
+    // Width of wstrb (width of data bus in words)
+    parameter STRB_WIDTH = (DATA_WIDTH/8),
+    // Width of ID signal
+    parameter ID_WIDTH = 8,
+    // Propagate aruser signal
+    parameter ARUSER_ENABLE = 0,
+    // Width of aruser signal
+    parameter ARUSER_WIDTH = 1,
+    // Propagate ruser signal
+    parameter RUSER_ENABLE = 0,
+    // Width of ruser signal
+    parameter RUSER_WIDTH = 1,
+    // AR channel register type
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter AR_REG_TYPE = 1,
+    // R channel register type
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter R_REG_TYPE = 2
+)
+(
+    input  wire                     clk,
+    input  wire                     rst,
+
+    /*
+     * AXI slave interface
+     */
+    input  wire [ID_WIDTH-1:0]      s_axi_arid,
+    input  wire [ADDR_WIDTH-1:0]    s_axi_araddr,
+    input  wire [7:0]               s_axi_arlen,
+    input  wire [2:0]               s_axi_arsize,
+    input  wire [1:0]               s_axi_arburst,
+    input  wire                     s_axi_arlock,
+    input  wire [3:0]               s_axi_arcache,
+    input  wire [2:0]               s_axi_arprot,
+    input  wire [3:0]               s_axi_arqos,
+    input  wire [3:0]               s_axi_arregion,
+    input  wire [ARUSER_WIDTH-1:0]  s_axi_aruser,
+    input  wire                     s_axi_arvalid,
+    output wire                     s_axi_arready,
+    output wire [ID_WIDTH-1:0]      s_axi_rid,
+    output wire [DATA_WIDTH-1:0]    s_axi_rdata,
+    output wire [1:0]               s_axi_rresp,
+    output wire                     s_axi_rlast,
+    output wire [RUSER_WIDTH-1:0]   s_axi_ruser,
+    output wire                     s_axi_rvalid,
+    input  wire                     s_axi_rready,
+
+    /*
+     * AXI master interface
+     */
+    output wire [ID_WIDTH-1:0]      m_axi_arid,
+    output wire [ADDR_WIDTH-1:0]    m_axi_araddr,
+    output wire [7:0]               m_axi_arlen,
+    output wire [2:0]               m_axi_arsize,
+    output wire [1:0]               m_axi_arburst,
+    output wire                     m_axi_arlock,
+    output wire [3:0]               m_axi_arcache,
+    output wire [2:0]               m_axi_arprot,
+    output wire [3:0]               m_axi_arqos,
+    output wire [3:0]               m_axi_arregion,
+    output wire [ARUSER_WIDTH-1:0]  m_axi_aruser,
+    output wire                     m_axi_arvalid,
+    input  wire                     m_axi_arready,
+    input  wire [ID_WIDTH-1:0]      m_axi_rid,
+    input  wire [DATA_WIDTH-1:0]    m_axi_rdata,
+    input  wire [1:0]               m_axi_rresp,
+    input  wire                     m_axi_rlast,
+    input  wire [RUSER_WIDTH-1:0]   m_axi_ruser,
+    input  wire                     m_axi_rvalid,
+    output wire                     m_axi_rready
+);
+
+generate
+
+// AR channel
+
+if (AR_REG_TYPE > 1) begin
+// skid buffer, no bubble cycles
+
+// datapath registers
+reg                    s_axi_arready_reg = 1'b0;
+
+reg [ID_WIDTH-1:0]     m_axi_arid_reg     = {ID_WIDTH{1'b0}};
+reg [ADDR_WIDTH-1:0]   m_axi_araddr_reg   = {ADDR_WIDTH{1'b0}};
+reg [7:0]              m_axi_arlen_reg    = 8'd0;
+reg [2:0]              m_axi_arsize_reg   = 3'd0;
+reg [1:0]              m_axi_arburst_reg  = 2'd0;
+reg                    m_axi_arlock_reg   = 1'b0;
+reg [3:0]              m_axi_arcache_reg  = 4'd0;
+reg [2:0]              m_axi_arprot_reg   = 3'd0;
+reg [3:0]              m_axi_arqos_reg    = 4'd0;
+reg [3:0]              m_axi_arregion_reg = 4'd0;
+reg [ARUSER_WIDTH-1:0] m_axi_aruser_reg   = {ARUSER_WIDTH{1'b0}};
+reg                    m_axi_arvalid_reg  = 1'b0, m_axi_arvalid_next;
+
+reg [ID_WIDTH-1:0]     temp_m_axi_arid_reg     = {ID_WIDTH{1'b0}};
+reg [ADDR_WIDTH-1:0]   temp_m_axi_araddr_reg   = {ADDR_WIDTH{1'b0}};
+reg [7:0]              temp_m_axi_arlen_reg    = 8'd0;
+reg [2:0]              temp_m_axi_arsize_reg   = 3'd0;
+reg [1:0]              temp_m_axi_arburst_reg  = 2'd0;
+reg                    temp_m_axi_arlock_reg   = 1'b0;
+reg [3:0]              temp_m_axi_arcache_reg  = 4'd0;
+reg [2:0]              temp_m_axi_arprot_reg   = 3'd0;
+reg [3:0]              temp_m_axi_arqos_reg    = 4'd0;
+reg [3:0]              temp_m_axi_arregion_reg = 4'd0;
+reg [ARUSER_WIDTH-1:0] temp_m_axi_aruser_reg   = {ARUSER_WIDTH{1'b0}};
+reg                    temp_m_axi_arvalid_reg  = 1'b0, temp_m_axi_arvalid_next;
+
+// datapath control
+reg store_axi_ar_input_to_output;
+reg store_axi_ar_input_to_temp;
+reg store_axi_ar_temp_to_output;
+
+assign s_axi_arready  = s_axi_arready_reg;
+
+assign m_axi_arid     = m_axi_arid_reg;
+assign m_axi_araddr   = m_axi_araddr_reg;
+assign m_axi_arlen    = m_axi_arlen_reg;
+assign m_axi_arsize   = m_axi_arsize_reg;
+assign m_axi_arburst  = m_axi_arburst_reg;
+assign m_axi_arlock   = m_axi_arlock_reg;
+assign m_axi_arcache  = m_axi_arcache_reg;
+assign m_axi_arprot   = m_axi_arprot_reg;
+assign m_axi_arqos    = m_axi_arqos_reg;
+assign m_axi_arregion = m_axi_arregion_reg;
+assign m_axi_aruser   = ARUSER_ENABLE ? m_axi_aruser_reg : {ARUSER_WIDTH{1'b0}};
+assign m_axi_arvalid  = m_axi_arvalid_reg;
+
+// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
+wire s_axi_arready_early = m_axi_arready | (~temp_m_axi_arvalid_reg & (~m_axi_arvalid_reg | ~s_axi_arvalid));
+
+always @* begin
+    // transfer sink ready state to source
+    m_axi_arvalid_next = m_axi_arvalid_reg;
+    temp_m_axi_arvalid_next = temp_m_axi_arvalid_reg;
+
+    store_axi_ar_input_to_output = 1'b0;
+    store_axi_ar_input_to_temp = 1'b0;
+    store_axi_ar_temp_to_output = 1'b0;
+
+    if (s_axi_arready_reg) begin
+        // input is ready
+        if (m_axi_arready | ~m_axi_arvalid_reg) begin
+            // output is ready or currently not valid, transfer data to output
+            m_axi_arvalid_next = s_axi_arvalid;
+            store_axi_ar_input_to_output = 1'b1;
+        end else begin
+            // output is not ready, store input in temp
+            temp_m_axi_arvalid_next = s_axi_arvalid;
+            store_axi_ar_input_to_temp = 1'b1;
+        end
+    end else if (m_axi_arready) begin
+        // input is not ready, but output is ready
+        m_axi_arvalid_next = temp_m_axi_arvalid_reg;
+        temp_m_axi_arvalid_next = 1'b0;
+        store_axi_ar_temp_to_output = 1'b1;
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        s_axi_arready_reg <= 1'b0;
+        m_axi_arvalid_reg <= 1'b0;
+        temp_m_axi_arvalid_reg <= 1'b0;
+    end else begin
+        s_axi_arready_reg <= s_axi_arready_early;
+        m_axi_arvalid_reg <= m_axi_arvalid_next;
+        temp_m_axi_arvalid_reg <= temp_m_axi_arvalid_next;
+    end
+
+    // datapath
+    if (store_axi_ar_input_to_output) begin
+        m_axi_arid_reg <= s_axi_arid;
+        m_axi_araddr_reg <= s_axi_araddr;
+        m_axi_arlen_reg <= s_axi_arlen;
+        m_axi_arsize_reg <= s_axi_arsize;
+        m_axi_arburst_reg <= s_axi_arburst;
+        m_axi_arlock_reg <= s_axi_arlock;
+        m_axi_arcache_reg <= s_axi_arcache;
+        m_axi_arprot_reg <= s_axi_arprot;
+        m_axi_arqos_reg <= s_axi_arqos;
+        m_axi_arregion_reg <= s_axi_arregion;
+        m_axi_aruser_reg <= s_axi_aruser;
+    end else if (store_axi_ar_temp_to_output) begin
+        m_axi_arid_reg <= temp_m_axi_arid_reg;
+        m_axi_araddr_reg <= temp_m_axi_araddr_reg;
+        m_axi_arlen_reg <= temp_m_axi_arlen_reg;
+        m_axi_arsize_reg <= temp_m_axi_arsize_reg;
+        m_axi_arburst_reg <= temp_m_axi_arburst_reg;
+        m_axi_arlock_reg <= temp_m_axi_arlock_reg;
+        m_axi_arcache_reg <= temp_m_axi_arcache_reg;
+        m_axi_arprot_reg <= temp_m_axi_arprot_reg;
+        m_axi_arqos_reg <= temp_m_axi_arqos_reg;
+        m_axi_arregion_reg <= temp_m_axi_arregion_reg;
+        m_axi_aruser_reg <= temp_m_axi_aruser_reg;
+    end
+
+    if (store_axi_ar_input_to_temp) begin
+        temp_m_axi_arid_reg <= s_axi_arid;
+        temp_m_axi_araddr_reg <= s_axi_araddr;
+        temp_m_axi_arlen_reg <= s_axi_arlen;
+        temp_m_axi_arsize_reg <= s_axi_arsize;
+        temp_m_axi_arburst_reg <= s_axi_arburst;
+        temp_m_axi_arlock_reg <= s_axi_arlock;
+        temp_m_axi_arcache_reg <= s_axi_arcache;
+        temp_m_axi_arprot_reg <= s_axi_arprot;
+        temp_m_axi_arqos_reg <= s_axi_arqos;
+        temp_m_axi_arregion_reg <= s_axi_arregion;
+        temp_m_axi_aruser_reg <= s_axi_aruser;
+    end
+end
+
+end else if (AR_REG_TYPE == 1) begin
+// simple register, inserts bubble cycles
+
+// datapath registers
+reg                    s_axi_arready_reg = 1'b0;
+
+reg [ID_WIDTH-1:0]     m_axi_arid_reg     = {ID_WIDTH{1'b0}};
+reg [ADDR_WIDTH-1:0]   m_axi_araddr_reg   = {ADDR_WIDTH{1'b0}};
+reg [7:0]              m_axi_arlen_reg    = 8'd0;
+reg [2:0]              m_axi_arsize_reg   = 3'd0;
+reg [1:0]              m_axi_arburst_reg  = 2'd0;
+reg                    m_axi_arlock_reg   = 1'b0;
+reg [3:0]              m_axi_arcache_reg  = 4'd0;
+reg [2:0]              m_axi_arprot_reg   = 3'd0;
+reg [3:0]              m_axi_arqos_reg    = 4'd0;
+reg [3:0]              m_axi_arregion_reg = 4'd0;
+reg [ARUSER_WIDTH-1:0] m_axi_aruser_reg   = {ARUSER_WIDTH{1'b0}};
+reg                    m_axi_arvalid_reg  = 1'b0, m_axi_arvalid_next;
+
+// datapath control
+reg store_axi_ar_input_to_output;
+
+assign s_axi_arready  = s_axi_arready_reg;
+
+assign m_axi_arid     = m_axi_arid_reg;
+assign m_axi_araddr   = m_axi_araddr_reg;
+assign m_axi_arlen    = m_axi_arlen_reg;
+assign m_axi_arsize   = m_axi_arsize_reg;
+assign m_axi_arburst  = m_axi_arburst_reg;
+assign m_axi_arlock   = m_axi_arlock_reg;
+assign m_axi_arcache  = m_axi_arcache_reg;
+assign m_axi_arprot   = m_axi_arprot_reg;
+assign m_axi_arqos    = m_axi_arqos_reg;
+assign m_axi_arregion = m_axi_arregion_reg;
+assign m_axi_aruser   = ARUSER_ENABLE ? m_axi_aruser_reg : {ARUSER_WIDTH{1'b0}};
+assign m_axi_arvalid  = m_axi_arvalid_reg;
+
+// enable ready input next cycle if output buffer will be empty
+wire s_axi_arready_early = !m_axi_arvalid_next;
+
+always @* begin
+    // transfer sink ready state to source
+    m_axi_arvalid_next = m_axi_arvalid_reg;
+
+    store_axi_ar_input_to_output = 1'b0;
+
+    if (s_axi_arready_reg) begin
+        m_axi_arvalid_next = s_axi_arvalid;
+        store_axi_ar_input_to_output = 1'b1;
+    end else if (m_axi_arready) begin
+        m_axi_arvalid_next = 1'b0;
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        s_axi_arready_reg <= 1'b0;
+        m_axi_arvalid_reg <= 1'b0;
+    end else begin
+        s_axi_arready_reg <= s_axi_arready_early;
+        m_axi_arvalid_reg <= m_axi_arvalid_next;
+    end
+
+    // datapath
+    if (store_axi_ar_input_to_output) begin
+        m_axi_arid_reg <= s_axi_arid;
+        m_axi_araddr_reg <= s_axi_araddr;
+        m_axi_arlen_reg <= s_axi_arlen;
+        m_axi_arsize_reg <= s_axi_arsize;
+        m_axi_arburst_reg <= s_axi_arburst;
+        m_axi_arlock_reg <= s_axi_arlock;
+        m_axi_arcache_reg <= s_axi_arcache;
+        m_axi_arprot_reg <= s_axi_arprot;
+        m_axi_arqos_reg <= s_axi_arqos;
+        m_axi_arregion_reg <= s_axi_arregion;
+        m_axi_aruser_reg <= s_axi_aruser;
+    end
+end
+
+end else begin
+
+    // bypass AR channel
+    assign m_axi_arid = s_axi_arid;
+    assign m_axi_araddr = s_axi_araddr;
+    assign m_axi_arlen = s_axi_arlen;
+    assign m_axi_arsize = s_axi_arsize;
+    assign m_axi_arburst = s_axi_arburst;
+    assign m_axi_arlock = s_axi_arlock;
+    assign m_axi_arcache = s_axi_arcache;
+    assign m_axi_arprot = s_axi_arprot;
+    assign m_axi_arqos = s_axi_arqos;
+    assign m_axi_arregion = s_axi_arregion;
+    assign m_axi_aruser = ARUSER_ENABLE ? s_axi_aruser : {ARUSER_WIDTH{1'b0}};
+    assign m_axi_arvalid = s_axi_arvalid;
+    assign s_axi_arready = m_axi_arready;
+
+end
+
+// R channel
+
+if (R_REG_TYPE > 1) begin
+// skid buffer, no bubble cycles
+
+// datapath registers
+reg                   m_axi_rready_reg = 1'b0;
+
+reg [ID_WIDTH-1:0]    s_axi_rid_reg    = {ID_WIDTH{1'b0}};
+reg [DATA_WIDTH-1:0]  s_axi_rdata_reg  = {DATA_WIDTH{1'b0}};
+reg [1:0]             s_axi_rresp_reg  = 2'b0;
+reg                   s_axi_rlast_reg  = 1'b0;
+reg [RUSER_WIDTH-1:0] s_axi_ruser_reg  = {RUSER_WIDTH{1'b0}};
+reg                   s_axi_rvalid_reg = 1'b0, s_axi_rvalid_next;
+
+reg [ID_WIDTH-1:0]    temp_s_axi_rid_reg    = {ID_WIDTH{1'b0}};
+reg [DATA_WIDTH-1:0]  temp_s_axi_rdata_reg  = {DATA_WIDTH{1'b0}};
+reg [1:0]             temp_s_axi_rresp_reg  = 2'b0;
+reg                   temp_s_axi_rlast_reg  = 1'b0;
+reg [RUSER_WIDTH-1:0] temp_s_axi_ruser_reg  = {RUSER_WIDTH{1'b0}};
+reg                   temp_s_axi_rvalid_reg = 1'b0, temp_s_axi_rvalid_next;
+
+// datapath control
+reg store_axi_r_input_to_output;
+reg store_axi_r_input_to_temp;
+reg store_axi_r_temp_to_output;
+
+assign m_axi_rready = m_axi_rready_reg;
+
+assign s_axi_rid    = s_axi_rid_reg;
+assign s_axi_rdata  = s_axi_rdata_reg;
+assign s_axi_rresp  = s_axi_rresp_reg;
+assign s_axi_rlast  = s_axi_rlast_reg;
+assign s_axi_ruser  = RUSER_ENABLE ? s_axi_ruser_reg : {RUSER_WIDTH{1'b0}};
+assign s_axi_rvalid = s_axi_rvalid_reg;
+
+// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
+wire m_axi_rready_early = s_axi_rready | (~temp_s_axi_rvalid_reg & (~s_axi_rvalid_reg | ~m_axi_rvalid));
+
+always @* begin
+    // transfer sink ready state to source
+    s_axi_rvalid_next = s_axi_rvalid_reg;
+    temp_s_axi_rvalid_next = temp_s_axi_rvalid_reg;
+
+    store_axi_r_input_to_output = 1'b0;
+    store_axi_r_input_to_temp = 1'b0;
+    store_axi_r_temp_to_output = 1'b0;
+
+    if (m_axi_rready_reg) begin
+        // input is ready
+        if (s_axi_rready | ~s_axi_rvalid_reg) begin
+            // output is ready or currently not valid, transfer data to output
+            s_axi_rvalid_next = m_axi_rvalid;
+            store_axi_r_input_to_output = 1'b1;
+        end else begin
+            // output is not ready, store input in temp
+            temp_s_axi_rvalid_next = m_axi_rvalid;
+            store_axi_r_input_to_temp = 1'b1;
+        end
+    end else if (s_axi_rready) begin
+        // input is not ready, but output is ready
+        s_axi_rvalid_next = temp_s_axi_rvalid_reg;
+        temp_s_axi_rvalid_next = 1'b0;
+        store_axi_r_temp_to_output = 1'b1;
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        m_axi_rready_reg <= 1'b0;
+        s_axi_rvalid_reg <= 1'b0;
+        temp_s_axi_rvalid_reg <= 1'b0;
+    end else begin
+        m_axi_rready_reg <= m_axi_rready_early;
+        s_axi_rvalid_reg <= s_axi_rvalid_next;
+        temp_s_axi_rvalid_reg <= temp_s_axi_rvalid_next;
+    end
+
+    // datapath
+    if (store_axi_r_input_to_output) begin
+        s_axi_rid_reg   <= m_axi_rid;
+        s_axi_rdata_reg <= m_axi_rdata;
+        s_axi_rresp_reg <= m_axi_rresp;
+        s_axi_rlast_reg <= m_axi_rlast;
+        s_axi_ruser_reg <= m_axi_ruser;
+    end else if (store_axi_r_temp_to_output) begin
+        s_axi_rid_reg   <= temp_s_axi_rid_reg;
+        s_axi_rdata_reg <= temp_s_axi_rdata_reg;
+        s_axi_rresp_reg <= temp_s_axi_rresp_reg;
+        s_axi_rlast_reg <= temp_s_axi_rlast_reg;
+        s_axi_ruser_reg <= temp_s_axi_ruser_reg;
+    end
+
+    if (store_axi_r_input_to_temp) begin
+        temp_s_axi_rid_reg   <= m_axi_rid;
+        temp_s_axi_rdata_reg <= m_axi_rdata;
+        temp_s_axi_rresp_reg <= m_axi_rresp;
+        temp_s_axi_rlast_reg <= m_axi_rlast;
+        temp_s_axi_ruser_reg <= m_axi_ruser;
+    end
+end
+
+end else if (R_REG_TYPE == 1) begin
+// simple register, inserts bubble cycles
+
+// datapath registers
+reg                   m_axi_rready_reg = 1'b0;
+
+reg [ID_WIDTH-1:0]    s_axi_rid_reg    = {ID_WIDTH{1'b0}};
+reg [DATA_WIDTH-1:0]  s_axi_rdata_reg  = {DATA_WIDTH{1'b0}};
+reg [1:0]             s_axi_rresp_reg  = 2'b0;
+reg                   s_axi_rlast_reg  = 1'b0;
+reg [RUSER_WIDTH-1:0] s_axi_ruser_reg  = {RUSER_WIDTH{1'b0}};
+reg                   s_axi_rvalid_reg = 1'b0, s_axi_rvalid_next;
+
+// datapath control
+reg store_axi_r_input_to_output;
+
+assign m_axi_rready = m_axi_rready_reg;
+
+assign s_axi_rid    = s_axi_rid_reg;
+assign s_axi_rdata  = s_axi_rdata_reg;
+assign s_axi_rresp  = s_axi_rresp_reg;
+assign s_axi_rlast  = s_axi_rlast_reg;
+assign s_axi_ruser  = RUSER_ENABLE ? s_axi_ruser_reg : {RUSER_WIDTH{1'b0}};
+assign s_axi_rvalid = s_axi_rvalid_reg;
+
+// enable ready input next cycle if output buffer will be empty
+wire m_axi_rready_early = !s_axi_rvalid_next;
+
+always @* begin
+    // transfer sink ready state to source
+    s_axi_rvalid_next = s_axi_rvalid_reg;
+
+    store_axi_r_input_to_output = 1'b0;
+
+    if (m_axi_rready_reg) begin
+        s_axi_rvalid_next = m_axi_rvalid;
+        store_axi_r_input_to_output = 1'b1;
+    end else if (s_axi_rready) begin
+        s_axi_rvalid_next = 1'b0;
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        m_axi_rready_reg <= 1'b0;
+        s_axi_rvalid_reg <= 1'b0;
+    end else begin
+        m_axi_rready_reg <= m_axi_rready_early;
+        s_axi_rvalid_reg <= s_axi_rvalid_next;
+    end
+
+    // datapath
+    if (store_axi_r_input_to_output) begin
+        s_axi_rid_reg   <= m_axi_rid;
+        s_axi_rdata_reg <= m_axi_rdata;
+        s_axi_rresp_reg <= m_axi_rresp;
+        s_axi_rlast_reg <= m_axi_rlast;
+        s_axi_ruser_reg <= m_axi_ruser;
+    end
+end
+
+end else begin
+
+    // bypass R channel
+    assign s_axi_rid = m_axi_rid;
+    assign s_axi_rdata = m_axi_rdata;
+    assign s_axi_rresp = m_axi_rresp;
+    assign s_axi_rlast = m_axi_rlast;
+    assign s_axi_ruser = RUSER_ENABLE ? m_axi_ruser : {RUSER_WIDTH{1'b0}};
+    assign s_axi_rvalid = m_axi_rvalid;
+    assign m_axi_rready = s_axi_rready;
+
+end
+
+endgenerate
+
+endmodule
+
+`resetall
diff --git a/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/axi_register_wr.v b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/axi_register_wr.v
new file mode 100644
index 00000000..9176d6ba
--- /dev/null
+++ b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/axi_register_wr.v
@@ -0,0 +1,691 @@
+/*
+
+Copyright (c) 2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4 register (write)
+ */
+module axi_register_wr #
+(
+    // Width of data bus in bits
+    parameter DATA_WIDTH = 32,
+    // Width of address bus in bits
+    parameter ADDR_WIDTH = 32,
+    // Width of wstrb (width of data bus in words)
+    parameter STRB_WIDTH = (DATA_WIDTH/8),
+    // Width of ID signal
+    parameter ID_WIDTH = 8,
+    // Propagate awuser signal
+    parameter AWUSER_ENABLE = 0,
+    // Width of awuser signal
+    parameter AWUSER_WIDTH = 1,
+    // Propagate wuser signal
+    parameter WUSER_ENABLE = 0,
+    // Width of wuser signal
+    parameter WUSER_WIDTH = 1,
+    // Propagate buser signal
+    parameter BUSER_ENABLE = 0,
+    // Width of buser signal
+    parameter BUSER_WIDTH = 1,
+    // AW channel register type
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter AW_REG_TYPE = 1,
+    // W channel register type
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter W_REG_TYPE = 2,
+    // B channel register type
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter B_REG_TYPE = 1
+)
+(
+    input  wire                     clk,
+    input  wire                     rst,
+
+    /*
+     * AXI slave interface
+     */
+    input  wire [ID_WIDTH-1:0]      s_axi_awid,
+    input  wire [ADDR_WIDTH-1:0]    s_axi_awaddr,
+    input  wire [7:0]               s_axi_awlen,
+    input  wire [2:0]               s_axi_awsize,
+    input  wire [1:0]               s_axi_awburst,
+    input  wire                     s_axi_awlock,
+    input  wire [3:0]               s_axi_awcache,
+    input  wire [2:0]               s_axi_awprot,
+    input  wire [3:0]               s_axi_awqos,
+    input  wire [3:0]               s_axi_awregion,
+    input  wire [AWUSER_WIDTH-1:0]  s_axi_awuser,
+    input  wire                     s_axi_awvalid,
+    output wire                     s_axi_awready,
+    input  wire [DATA_WIDTH-1:0]    s_axi_wdata,
+    input  wire [STRB_WIDTH-1:0]    s_axi_wstrb,
+    input  wire                     s_axi_wlast,
+    input  wire [WUSER_WIDTH-1:0]   s_axi_wuser,
+    input  wire                     s_axi_wvalid,
+    output wire                     s_axi_wready,
+    output wire [ID_WIDTH-1:0]      s_axi_bid,
+    output wire [1:0]               s_axi_bresp,
+    output wire [BUSER_WIDTH-1:0]   s_axi_buser,
+    output wire                     s_axi_bvalid,
+    input  wire                     s_axi_bready,
+
+    /*
+     * AXI master interface
+     */
+    output wire [ID_WIDTH-1:0]      m_axi_awid,
+    output wire [ADDR_WIDTH-1:0]    m_axi_awaddr,
+    output wire [7:0]               m_axi_awlen,
+    output wire [2:0]               m_axi_awsize,
+    output wire [1:0]               m_axi_awburst,
+    output wire                     m_axi_awlock,
+    output wire [3:0]               m_axi_awcache,
+    output wire [2:0]               m_axi_awprot,
+    output wire [3:0]               m_axi_awqos,
+    output wire [3:0]               m_axi_awregion,
+    output wire [AWUSER_WIDTH-1:0]  m_axi_awuser,
+    output wire                     m_axi_awvalid,
+    input  wire                     m_axi_awready,
+    output wire [DATA_WIDTH-1:0]    m_axi_wdata,
+    output wire [STRB_WIDTH-1:0]    m_axi_wstrb,
+    output wire                     m_axi_wlast,
+    output wire [WUSER_WIDTH-1:0]   m_axi_wuser,
+    output wire                     m_axi_wvalid,
+    input  wire                     m_axi_wready,
+    input  wire [ID_WIDTH-1:0]      m_axi_bid,
+    input  wire [1:0]               m_axi_bresp,
+    input  wire [BUSER_WIDTH-1:0]   m_axi_buser,
+    input  wire                     m_axi_bvalid,
+    output wire                     m_axi_bready
+);
+
+generate
+
+// AW channel
+
+if (AW_REG_TYPE > 1) begin
+// skid buffer, no bubble cycles
+
+// datapath registers
+reg                    s_axi_awready_reg = 1'b0;
+
+reg [ID_WIDTH-1:0]     m_axi_awid_reg     = {ID_WIDTH{1'b0}};
+reg [ADDR_WIDTH-1:0]   m_axi_awaddr_reg   = {ADDR_WIDTH{1'b0}};
+reg [7:0]              m_axi_awlen_reg    = 8'd0;
+reg [2:0]              m_axi_awsize_reg   = 3'd0;
+reg [1:0]              m_axi_awburst_reg  = 2'd0;
+reg                    m_axi_awlock_reg   = 1'b0;
+reg [3:0]              m_axi_awcache_reg  = 4'd0;
+reg [2:0]              m_axi_awprot_reg   = 3'd0;
+reg [3:0]              m_axi_awqos_reg    = 4'd0;
+reg [3:0]              m_axi_awregion_reg = 4'd0;
+reg [AWUSER_WIDTH-1:0] m_axi_awuser_reg   = {AWUSER_WIDTH{1'b0}};
+reg                    m_axi_awvalid_reg  = 1'b0, m_axi_awvalid_next;
+
+reg [ID_WIDTH-1:0]     temp_m_axi_awid_reg     = {ID_WIDTH{1'b0}};
+reg [ADDR_WIDTH-1:0]   temp_m_axi_awaddr_reg   = {ADDR_WIDTH{1'b0}};
+reg [7:0]              temp_m_axi_awlen_reg    = 8'd0;
+reg [2:0]              temp_m_axi_awsize_reg   = 3'd0;
+reg [1:0]              temp_m_axi_awburst_reg  = 2'd0;
+reg                    temp_m_axi_awlock_reg   = 1'b0;
+reg [3:0]              temp_m_axi_awcache_reg  = 4'd0;
+reg [2:0]              temp_m_axi_awprot_reg   = 3'd0;
+reg [3:0]              temp_m_axi_awqos_reg    = 4'd0;
+reg [3:0]              temp_m_axi_awregion_reg = 4'd0;
+reg [AWUSER_WIDTH-1:0] temp_m_axi_awuser_reg   = {AWUSER_WIDTH{1'b0}};
+reg                    temp_m_axi_awvalid_reg  = 1'b0, temp_m_axi_awvalid_next;
+
+// datapath control
+reg store_axi_aw_input_to_output;
+reg store_axi_aw_input_to_temp;
+reg store_axi_aw_temp_to_output;
+
+assign s_axi_awready  = s_axi_awready_reg;
+
+assign m_axi_awid     = m_axi_awid_reg;
+assign m_axi_awaddr   = m_axi_awaddr_reg;
+assign m_axi_awlen    = m_axi_awlen_reg;
+assign m_axi_awsize   = m_axi_awsize_reg;
+assign m_axi_awburst  = m_axi_awburst_reg;
+assign m_axi_awlock   = m_axi_awlock_reg;
+assign m_axi_awcache  = m_axi_awcache_reg;
+assign m_axi_awprot   = m_axi_awprot_reg;
+assign m_axi_awqos    = m_axi_awqos_reg;
+assign m_axi_awregion = m_axi_awregion_reg;
+assign m_axi_awuser   = AWUSER_ENABLE ? m_axi_awuser_reg : {AWUSER_WIDTH{1'b0}};
+assign m_axi_awvalid  = m_axi_awvalid_reg;
+
+// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
+wire s_axi_awready_early = m_axi_awready | (~temp_m_axi_awvalid_reg & (~m_axi_awvalid_reg | ~s_axi_awvalid));
+
+always @* begin
+    // transfer sink ready state to source
+    m_axi_awvalid_next = m_axi_awvalid_reg;
+    temp_m_axi_awvalid_next = temp_m_axi_awvalid_reg;
+
+    store_axi_aw_input_to_output = 1'b0;
+    store_axi_aw_input_to_temp = 1'b0;
+    store_axi_aw_temp_to_output = 1'b0;
+
+    if (s_axi_awready_reg) begin
+        // input is ready
+        if (m_axi_awready | ~m_axi_awvalid_reg) begin
+            // output is ready or currently not valid, transfer data to output
+            m_axi_awvalid_next = s_axi_awvalid;
+            store_axi_aw_input_to_output = 1'b1;
+        end else begin
+            // output is not ready, store input in temp
+            temp_m_axi_awvalid_next = s_axi_awvalid;
+            store_axi_aw_input_to_temp = 1'b1;
+        end
+    end else if (m_axi_awready) begin
+        // input is not ready, but output is ready
+        m_axi_awvalid_next = temp_m_axi_awvalid_reg;
+        temp_m_axi_awvalid_next = 1'b0;
+        store_axi_aw_temp_to_output = 1'b1;
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        s_axi_awready_reg <= 1'b0;
+        m_axi_awvalid_reg <= 1'b0;
+        temp_m_axi_awvalid_reg <= 1'b0;
+    end else begin
+        s_axi_awready_reg <= s_axi_awready_early;
+        m_axi_awvalid_reg <= m_axi_awvalid_next;
+        temp_m_axi_awvalid_reg <= temp_m_axi_awvalid_next;
+    end
+
+    // datapath
+    if (store_axi_aw_input_to_output) begin
+        m_axi_awid_reg <= s_axi_awid;
+        m_axi_awaddr_reg <= s_axi_awaddr;
+        m_axi_awlen_reg <= s_axi_awlen;
+        m_axi_awsize_reg <= s_axi_awsize;
+        m_axi_awburst_reg <= s_axi_awburst;
+        m_axi_awlock_reg <= s_axi_awlock;
+        m_axi_awcache_reg <= s_axi_awcache;
+        m_axi_awprot_reg <= s_axi_awprot;
+        m_axi_awqos_reg <= s_axi_awqos;
+        m_axi_awregion_reg <= s_axi_awregion;
+        m_axi_awuser_reg <= s_axi_awuser;
+    end else if (store_axi_aw_temp_to_output) begin
+        m_axi_awid_reg <= temp_m_axi_awid_reg;
+        m_axi_awaddr_reg <= temp_m_axi_awaddr_reg;
+        m_axi_awlen_reg <= temp_m_axi_awlen_reg;
+        m_axi_awsize_reg <= temp_m_axi_awsize_reg;
+        m_axi_awburst_reg <= temp_m_axi_awburst_reg;
+        m_axi_awlock_reg <= temp_m_axi_awlock_reg;
+        m_axi_awcache_reg <= temp_m_axi_awcache_reg;
+        m_axi_awprot_reg <= temp_m_axi_awprot_reg;
+        m_axi_awqos_reg <= temp_m_axi_awqos_reg;
+        m_axi_awregion_reg <= temp_m_axi_awregion_reg;
+        m_axi_awuser_reg <= temp_m_axi_awuser_reg;
+    end
+
+    if (store_axi_aw_input_to_temp) begin
+        temp_m_axi_awid_reg <= s_axi_awid;
+        temp_m_axi_awaddr_reg <= s_axi_awaddr;
+        temp_m_axi_awlen_reg <= s_axi_awlen;
+        temp_m_axi_awsize_reg <= s_axi_awsize;
+        temp_m_axi_awburst_reg <= s_axi_awburst;
+        temp_m_axi_awlock_reg <= s_axi_awlock;
+        temp_m_axi_awcache_reg <= s_axi_awcache;
+        temp_m_axi_awprot_reg <= s_axi_awprot;
+        temp_m_axi_awqos_reg <= s_axi_awqos;
+        temp_m_axi_awregion_reg <= s_axi_awregion;
+        temp_m_axi_awuser_reg <= s_axi_awuser;
+    end
+end
+
+end else if (AW_REG_TYPE == 1) begin
+// simple register, inserts bubble cycles
+
+// datapath registers
+reg                    s_axi_awready_reg = 1'b0;
+
+reg [ID_WIDTH-1:0]     m_axi_awid_reg     = {ID_WIDTH{1'b0}};
+reg [ADDR_WIDTH-1:0]   m_axi_awaddr_reg   = {ADDR_WIDTH{1'b0}};
+reg [7:0]              m_axi_awlen_reg    = 8'd0;
+reg [2:0]              m_axi_awsize_reg   = 3'd0;
+reg [1:0]              m_axi_awburst_reg  = 2'd0;
+reg                    m_axi_awlock_reg   = 1'b0;
+reg [3:0]              m_axi_awcache_reg  = 4'd0;
+reg [2:0]              m_axi_awprot_reg   = 3'd0;
+reg [3:0]              m_axi_awqos_reg    = 4'd0;
+reg [3:0]              m_axi_awregion_reg = 4'd0;
+reg [AWUSER_WIDTH-1:0] m_axi_awuser_reg   = {AWUSER_WIDTH{1'b0}};
+reg                    m_axi_awvalid_reg  = 1'b0, m_axi_awvalid_next;
+
+// datapath control
+reg store_axi_aw_input_to_output;
+
+assign s_axi_awready  = s_axi_awready_reg;
+
+assign m_axi_awid     = m_axi_awid_reg;
+assign m_axi_awaddr   = m_axi_awaddr_reg;
+assign m_axi_awlen    = m_axi_awlen_reg;
+assign m_axi_awsize   = m_axi_awsize_reg;
+assign m_axi_awburst  = m_axi_awburst_reg;
+assign m_axi_awlock   = m_axi_awlock_reg;
+assign m_axi_awcache  = m_axi_awcache_reg;
+assign m_axi_awprot   = m_axi_awprot_reg;
+assign m_axi_awqos    = m_axi_awqos_reg;
+assign m_axi_awregion = m_axi_awregion_reg;
+assign m_axi_awuser   = AWUSER_ENABLE ? m_axi_awuser_reg : {AWUSER_WIDTH{1'b0}};
+assign m_axi_awvalid  = m_axi_awvalid_reg;
+
+// enable ready input next cycle if output buffer will be empty
+wire s_axi_awready_eawly = !m_axi_awvalid_next;
+
+always @* begin
+    // transfer sink ready state to source
+    m_axi_awvalid_next = m_axi_awvalid_reg;
+
+    store_axi_aw_input_to_output = 1'b0;
+
+    if (s_axi_awready_reg) begin
+        m_axi_awvalid_next = s_axi_awvalid;
+        store_axi_aw_input_to_output = 1'b1;
+    end else if (m_axi_awready) begin
+        m_axi_awvalid_next = 1'b0;
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        s_axi_awready_reg <= 1'b0;
+        m_axi_awvalid_reg <= 1'b0;
+    end else begin
+        s_axi_awready_reg <= s_axi_awready_eawly;
+        m_axi_awvalid_reg <= m_axi_awvalid_next;
+    end
+
+    // datapath
+    if (store_axi_aw_input_to_output) begin
+        m_axi_awid_reg <= s_axi_awid;
+        m_axi_awaddr_reg <= s_axi_awaddr;
+        m_axi_awlen_reg <= s_axi_awlen;
+        m_axi_awsize_reg <= s_axi_awsize;
+        m_axi_awburst_reg <= s_axi_awburst;
+        m_axi_awlock_reg <= s_axi_awlock;
+        m_axi_awcache_reg <= s_axi_awcache;
+        m_axi_awprot_reg <= s_axi_awprot;
+        m_axi_awqos_reg <= s_axi_awqos;
+        m_axi_awregion_reg <= s_axi_awregion;
+        m_axi_awuser_reg <= s_axi_awuser;
+    end
+end
+
+end else begin
+
+    // bypass AW channel
+    assign m_axi_awid = s_axi_awid;
+    assign m_axi_awaddr = s_axi_awaddr;
+    assign m_axi_awlen = s_axi_awlen;
+    assign m_axi_awsize = s_axi_awsize;
+    assign m_axi_awburst = s_axi_awburst;
+    assign m_axi_awlock = s_axi_awlock;
+    assign m_axi_awcache = s_axi_awcache;
+    assign m_axi_awprot = s_axi_awprot;
+    assign m_axi_awqos = s_axi_awqos;
+    assign m_axi_awregion = s_axi_awregion;
+    assign m_axi_awuser = AWUSER_ENABLE ? s_axi_awuser : {AWUSER_WIDTH{1'b0}};
+    assign m_axi_awvalid = s_axi_awvalid;
+    assign s_axi_awready = m_axi_awready;
+
+end
+
+// W channel
+
+if (W_REG_TYPE > 1) begin
+// skid buffer, no bubble cycles
+
+// datapath registers
+reg                   s_axi_wready_reg = 1'b0;
+
+reg [DATA_WIDTH-1:0]  m_axi_wdata_reg  = {DATA_WIDTH{1'b0}};
+reg [STRB_WIDTH-1:0]  m_axi_wstrb_reg  = {STRB_WIDTH{1'b0}};
+reg                   m_axi_wlast_reg  = 1'b0;
+reg [WUSER_WIDTH-1:0] m_axi_wuser_reg  = {WUSER_WIDTH{1'b0}};
+reg                   m_axi_wvalid_reg = 1'b0, m_axi_wvalid_next;
+
+reg [DATA_WIDTH-1:0]  temp_m_axi_wdata_reg  = {DATA_WIDTH{1'b0}};
+reg [STRB_WIDTH-1:0]  temp_m_axi_wstrb_reg  = {STRB_WIDTH{1'b0}};
+reg                   temp_m_axi_wlast_reg  = 1'b0;
+reg [WUSER_WIDTH-1:0] temp_m_axi_wuser_reg  = {WUSER_WIDTH{1'b0}};
+reg                   temp_m_axi_wvalid_reg = 1'b0, temp_m_axi_wvalid_next;
+
+// datapath control
+reg store_axi_w_input_to_output;
+reg store_axi_w_input_to_temp;
+reg store_axi_w_temp_to_output;
+
+assign s_axi_wready = s_axi_wready_reg;
+
+assign m_axi_wdata  = m_axi_wdata_reg;
+assign m_axi_wstrb  = m_axi_wstrb_reg;
+assign m_axi_wlast  = m_axi_wlast_reg;
+assign m_axi_wuser  = WUSER_ENABLE ? m_axi_wuser_reg : {WUSER_WIDTH{1'b0}};
+assign m_axi_wvalid = m_axi_wvalid_reg;
+
+// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
+wire s_axi_wready_early = m_axi_wready | (~temp_m_axi_wvalid_reg & (~m_axi_wvalid_reg | ~s_axi_wvalid));
+
+always @* begin
+    // transfer sink ready state to source
+    m_axi_wvalid_next = m_axi_wvalid_reg;
+    temp_m_axi_wvalid_next = temp_m_axi_wvalid_reg;
+
+    store_axi_w_input_to_output = 1'b0;
+    store_axi_w_input_to_temp = 1'b0;
+    store_axi_w_temp_to_output = 1'b0;
+
+    if (s_axi_wready_reg) begin
+        // input is ready
+        if (m_axi_wready | ~m_axi_wvalid_reg) begin
+            // output is ready or currently not valid, transfer data to output
+            m_axi_wvalid_next = s_axi_wvalid;
+            store_axi_w_input_to_output = 1'b1;
+        end else begin
+            // output is not ready, store input in temp
+            temp_m_axi_wvalid_next = s_axi_wvalid;
+            store_axi_w_input_to_temp = 1'b1;
+        end
+    end else if (m_axi_wready) begin
+        // input is not ready, but output is ready
+        m_axi_wvalid_next = temp_m_axi_wvalid_reg;
+        temp_m_axi_wvalid_next = 1'b0;
+        store_axi_w_temp_to_output = 1'b1;
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        s_axi_wready_reg <= 1'b0;
+        m_axi_wvalid_reg <= 1'b0;
+        temp_m_axi_wvalid_reg <= 1'b0;
+    end else begin
+        s_axi_wready_reg <= s_axi_wready_early;
+        m_axi_wvalid_reg <= m_axi_wvalid_next;
+        temp_m_axi_wvalid_reg <= temp_m_axi_wvalid_next;
+    end
+
+    // datapath
+    if (store_axi_w_input_to_output) begin
+        m_axi_wdata_reg <= s_axi_wdata;
+        m_axi_wstrb_reg <= s_axi_wstrb;
+        m_axi_wlast_reg <= s_axi_wlast;
+        m_axi_wuser_reg <= s_axi_wuser;
+    end else if (store_axi_w_temp_to_output) begin
+        m_axi_wdata_reg <= temp_m_axi_wdata_reg;
+        m_axi_wstrb_reg <= temp_m_axi_wstrb_reg;
+        m_axi_wlast_reg <= temp_m_axi_wlast_reg;
+        m_axi_wuser_reg <= temp_m_axi_wuser_reg;
+    end
+
+    if (store_axi_w_input_to_temp) begin
+        temp_m_axi_wdata_reg <= s_axi_wdata;
+        temp_m_axi_wstrb_reg <= s_axi_wstrb;
+        temp_m_axi_wlast_reg <= s_axi_wlast;
+        temp_m_axi_wuser_reg <= s_axi_wuser;
+    end
+end
+
+end else if (W_REG_TYPE == 1) begin
+// simple register, inserts bubble cycles
+
+// datapath registers
+reg                   s_axi_wready_reg = 1'b0;
+
+reg [DATA_WIDTH-1:0]  m_axi_wdata_reg  = {DATA_WIDTH{1'b0}};
+reg [STRB_WIDTH-1:0]  m_axi_wstrb_reg  = {STRB_WIDTH{1'b0}};
+reg                   m_axi_wlast_reg  = 1'b0;
+reg [WUSER_WIDTH-1:0] m_axi_wuser_reg  = {WUSER_WIDTH{1'b0}};
+reg                   m_axi_wvalid_reg = 1'b0, m_axi_wvalid_next;
+
+// datapath control
+reg store_axi_w_input_to_output;
+
+assign s_axi_wready = s_axi_wready_reg;
+
+assign m_axi_wdata  = m_axi_wdata_reg;
+assign m_axi_wstrb  = m_axi_wstrb_reg;
+assign m_axi_wlast  = m_axi_wlast_reg;
+assign m_axi_wuser  = WUSER_ENABLE ? m_axi_wuser_reg : {WUSER_WIDTH{1'b0}};
+assign m_axi_wvalid = m_axi_wvalid_reg;
+
+// enable ready input next cycle if output buffer will be empty
+wire s_axi_wready_ewly = !m_axi_wvalid_next;
+
+always @* begin
+    // transfer sink ready state to source
+    m_axi_wvalid_next = m_axi_wvalid_reg;
+
+    store_axi_w_input_to_output = 1'b0;
+
+    if (s_axi_wready_reg) begin
+        m_axi_wvalid_next = s_axi_wvalid;
+        store_axi_w_input_to_output = 1'b1;
+    end else if (m_axi_wready) begin
+        m_axi_wvalid_next = 1'b0;
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        s_axi_wready_reg <= 1'b0;
+        m_axi_wvalid_reg <= 1'b0;
+    end else begin
+        s_axi_wready_reg <= s_axi_wready_ewly;
+        m_axi_wvalid_reg <= m_axi_wvalid_next;
+    end
+
+    // datapath
+    if (store_axi_w_input_to_output) begin
+        m_axi_wdata_reg <= s_axi_wdata;
+        m_axi_wstrb_reg <= s_axi_wstrb;
+        m_axi_wlast_reg <= s_axi_wlast;
+        m_axi_wuser_reg <= s_axi_wuser;
+    end
+end
+
+end else begin
+
+    // bypass W channel
+    assign m_axi_wdata = s_axi_wdata;
+    assign m_axi_wstrb = s_axi_wstrb;
+    assign m_axi_wlast = s_axi_wlast;
+    assign m_axi_wuser = WUSER_ENABLE ? s_axi_wuser : {WUSER_WIDTH{1'b0}};
+    assign m_axi_wvalid = s_axi_wvalid;
+    assign s_axi_wready = m_axi_wready;
+
+end
+
+// B channel
+
+if (B_REG_TYPE > 1) begin
+// skid buffer, no bubble cycles
+
+// datapath registers
+reg                   m_axi_bready_reg = 1'b0;
+
+reg [ID_WIDTH-1:0]    s_axi_bid_reg    = {ID_WIDTH{1'b0}};
+reg [1:0]             s_axi_bresp_reg  = 2'b0;
+reg [BUSER_WIDTH-1:0] s_axi_buser_reg  = {BUSER_WIDTH{1'b0}};
+reg                   s_axi_bvalid_reg = 1'b0, s_axi_bvalid_next;
+
+reg [ID_WIDTH-1:0]    temp_s_axi_bid_reg    = {ID_WIDTH{1'b0}};
+reg [1:0]             temp_s_axi_bresp_reg  = 2'b0;
+reg [BUSER_WIDTH-1:0] temp_s_axi_buser_reg  = {BUSER_WIDTH{1'b0}};
+reg                   temp_s_axi_bvalid_reg = 1'b0, temp_s_axi_bvalid_next;
+
+// datapath control
+reg store_axi_b_input_to_output;
+reg store_axi_b_input_to_temp;
+reg store_axi_b_temp_to_output;
+
+assign m_axi_bready = m_axi_bready_reg;
+
+assign s_axi_bid    = s_axi_bid_reg;
+assign s_axi_bresp  = s_axi_bresp_reg;
+assign s_axi_buser  = BUSER_ENABLE ? s_axi_buser_reg : {BUSER_WIDTH{1'b0}};
+assign s_axi_bvalid = s_axi_bvalid_reg;
+
+// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
+wire m_axi_bready_early = s_axi_bready | (~temp_s_axi_bvalid_reg & (~s_axi_bvalid_reg | ~m_axi_bvalid));
+
+always @* begin
+    // transfer sink ready state to source
+    s_axi_bvalid_next = s_axi_bvalid_reg;
+    temp_s_axi_bvalid_next = temp_s_axi_bvalid_reg;
+
+    store_axi_b_input_to_output = 1'b0;
+    store_axi_b_input_to_temp = 1'b0;
+    store_axi_b_temp_to_output = 1'b0;
+
+    if (m_axi_bready_reg) begin
+        // input is ready
+        if (s_axi_bready | ~s_axi_bvalid_reg) begin
+            // output is ready or currently not valid, transfer data to output
+            s_axi_bvalid_next = m_axi_bvalid;
+            store_axi_b_input_to_output = 1'b1;
+        end else begin
+            // output is not ready, store input in temp
+            temp_s_axi_bvalid_next = m_axi_bvalid;
+            store_axi_b_input_to_temp = 1'b1;
+        end
+    end else if (s_axi_bready) begin
+        // input is not ready, but output is ready
+        s_axi_bvalid_next = temp_s_axi_bvalid_reg;
+        temp_s_axi_bvalid_next = 1'b0;
+        store_axi_b_temp_to_output = 1'b1;
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        m_axi_bready_reg <= 1'b0;
+        s_axi_bvalid_reg <= 1'b0;
+        temp_s_axi_bvalid_reg <= 1'b0;
+    end else begin
+        m_axi_bready_reg <= m_axi_bready_early;
+        s_axi_bvalid_reg <= s_axi_bvalid_next;
+        temp_s_axi_bvalid_reg <= temp_s_axi_bvalid_next;
+    end
+
+    // datapath
+    if (store_axi_b_input_to_output) begin
+        s_axi_bid_reg   <= m_axi_bid;
+        s_axi_bresp_reg <= m_axi_bresp;
+        s_axi_buser_reg <= m_axi_buser;
+    end else if (store_axi_b_temp_to_output) begin
+        s_axi_bid_reg   <= temp_s_axi_bid_reg;
+        s_axi_bresp_reg <= temp_s_axi_bresp_reg;
+        s_axi_buser_reg <= temp_s_axi_buser_reg;
+    end
+
+    if (store_axi_b_input_to_temp) begin
+        temp_s_axi_bid_reg   <= m_axi_bid;
+        temp_s_axi_bresp_reg <= m_axi_bresp;
+        temp_s_axi_buser_reg <= m_axi_buser;
+    end
+end
+
+end else if (B_REG_TYPE == 1) begin
+// simple register, inserts bubble cycles
+
+// datapath registers
+reg                   m_axi_bready_reg = 1'b0;
+
+reg [ID_WIDTH-1:0]    s_axi_bid_reg    = {ID_WIDTH{1'b0}};
+reg [1:0]             s_axi_bresp_reg  = 2'b0;
+reg [BUSER_WIDTH-1:0] s_axi_buser_reg  = {BUSER_WIDTH{1'b0}};
+reg                   s_axi_bvalid_reg = 1'b0, s_axi_bvalid_next;
+
+// datapath control
+reg store_axi_b_input_to_output;
+
+assign m_axi_bready = m_axi_bready_reg;
+
+assign s_axi_bid    = s_axi_bid_reg;
+assign s_axi_bresp  = s_axi_bresp_reg;
+assign s_axi_buser  = BUSER_ENABLE ? s_axi_buser_reg : {BUSER_WIDTH{1'b0}};
+assign s_axi_bvalid = s_axi_bvalid_reg;
+
+// enable ready input next cycle if output buffer will be empty
+wire m_axi_bready_early = !s_axi_bvalid_next;
+
+always @* begin
+    // transfer sink ready state to source
+    s_axi_bvalid_next = s_axi_bvalid_reg;
+
+    store_axi_b_input_to_output = 1'b0;
+
+    if (m_axi_bready_reg) begin
+        s_axi_bvalid_next = m_axi_bvalid;
+        store_axi_b_input_to_output = 1'b1;
+    end else if (s_axi_bready) begin
+        s_axi_bvalid_next = 1'b0;
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        m_axi_bready_reg <= 1'b0;
+        s_axi_bvalid_reg <= 1'b0;
+    end else begin
+        m_axi_bready_reg <= m_axi_bready_early;
+        s_axi_bvalid_reg <= s_axi_bvalid_next;
+    end
+
+    // datapath
+    if (store_axi_b_input_to_output) begin
+        s_axi_bid_reg   <= m_axi_bid;
+        s_axi_bresp_reg <= m_axi_bresp;
+        s_axi_buser_reg <= m_axi_buser;
+    end
+end
+
+end else begin
+
+    // bypass B channel
+    assign s_axi_bid = m_axi_bid;
+    assign s_axi_bresp = m_axi_bresp;
+    assign s_axi_buser = BUSER_ENABLE ? m_axi_buser : {BUSER_WIDTH{1'b0}};
+    assign s_axi_bvalid = m_axi_bvalid;
+    assign m_axi_bready = s_axi_bready;
+
+end
+
+endgenerate
+
+endmodule
+
+`resetall
diff --git a/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/detect_burst.v b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/detect_burst.v
new file mode 100644
index 00000000..5a3b2191
--- /dev/null
+++ b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/detect_burst.v
@@ -0,0 +1,159 @@
+`default_nettype none
+
+// Detect burst from address stream.
+module detect_burst #(
+  parameter AddrWidth         = 64,
+  parameter DataWidthBytesLog = 6,
+  parameter WaitTimeWidth     = 4,
+  parameter BurstLenWidth     = 8
+) (
+  input wire clk,
+  input wire rst,
+
+  input wire [WaitTimeWidth-1:0] max_wait_time,
+  input wire [BurstLenWidth-1:0] max_burst_len,  // 0 disables detection
+
+  input  wire [AddrWidth-1:0] addr_dout,
+  input  wire                 addr_empty_n,
+  output reg                  addr_read,
+
+  output wire [BurstLenWidth+AddrWidth-1:0] addr_din,
+  input  wire                               addr_full_n,
+  output wire                               addr_write,
+
+  output wire [BurstLenWidth-1:0] burst_len_0_din,
+  input  wire                     burst_len_0_full_n,
+  output wire                     burst_len_0_write,
+
+  output wire [BurstLenWidth-1:0] burst_len_1_din,
+  input  wire                     burst_len_1_full_n,
+  output wire                     burst_len_1_write
+);
+  // parameter
+  localparam NextAddrWidth = AddrWidth - DataWidthBytesLog;
+  // AXI burst must not cross a 4KB boundary
+  localparam BurstBoundaryLenWidth = $clog2(4096);
+
+  // state
+  reg [AddrWidth-1:0]     base_addr;
+  reg                     base_valid;
+  reg [BurstLenWidth-1:0] burst_len;
+  reg [WaitTimeWidth-1:0] wait_time;
+  reg [NextAddrWidth-1:0] next_addr;
+
+  // logic
+  reg                     write_enable;
+  reg [AddrWidth-1:0]     base_addr_next;
+  reg                     base_valid_next;
+  reg [BurstLenWidth-1:0] burst_len_next;
+  reg [WaitTimeWidth-1:0] wait_time_next;
+
+  wire [NextAddrWidth-1:0] next_addr_next =
+      base_addr_next[AddrWidth-1:DataWidthBytesLog] +
+      {{(NextAddrWidth-BurstLenWidth){1'b0}}, burst_len_next} +
+      {{(NextAddrWidth-1){1'b0}}, 1'b1};
+
+  assign addr_write = write_enable;
+  assign burst_len_0_write = write_enable;
+  assign burst_len_1_write = write_enable;
+  assign addr_din = {burst_len, base_addr};
+  assign burst_len_0_din = burst_len;
+  assign burst_len_1_din = burst_len;
+
+  // register the input for timing closure
+  reg addr_empty_n_q;
+  reg [AddrWidth-1:0] addr_dout_q;
+  always @(posedge clk) begin
+    if (addr_full_n && burst_len_0_full_n && burst_len_1_full_n) begin
+      addr_empty_n_q <= addr_empty_n;
+      addr_dout_q <= addr_dout;
+    end
+  end
+  wire [AddrWidth-1:0] curr_addr = addr_dout_q;
+
+  always @* begin
+    // defaults
+    addr_read = 1'b0;
+    if (!addr_full_n || !burst_len_0_full_n || !burst_len_1_full_n) begin
+      addr_read = 1'b0;
+    end else if (addr_empty_n) begin
+      // read new item if non-empty
+      addr_read = 1'b1;
+    end else if (base_valid) begin
+      addr_read = 1'b0;
+    end
+  end
+
+  always @* begin
+    // defaults
+    write_enable = 1'b0;
+    base_addr_next = base_addr;
+    base_valid_next = base_valid;
+    wait_time_next = wait_time;
+    burst_len_next = burst_len;
+    if (!addr_full_n || !burst_len_0_full_n || !burst_len_1_full_n) begin
+      // output FIFO full, do nothing
+    end else if (addr_empty_n_q) begin
+      wait_time_next = 0;
+      if (!base_valid) begin
+        base_addr_next = curr_addr;
+        base_valid_next = 1'b1;
+
+        write_enable = 1'b0;
+        burst_len_next = burst_len;
+      end else begin
+        if (next_addr == curr_addr[AddrWidth-1:DataWidthBytesLog] &&
+            curr_addr[BurstBoundaryLenWidth-1:0] != {BurstBoundaryLenWidth{1'b0}} &&
+            burst_len < max_burst_len) begin
+          burst_len_next = burst_len + 1;
+
+          write_enable = 1'b0;
+          base_addr_next = base_addr;
+          base_valid_next = base_valid;
+        end else begin
+          // no more burst detected
+          write_enable = 1'b1;
+          burst_len_next = 0;
+          base_addr_next = curr_addr;
+
+          base_valid_next = base_valid;
+        end
+      end
+    end else if (base_valid) begin
+      if (wait_time < max_wait_time) begin
+        wait_time_next = wait_time + 1;
+
+        write_enable = 1'b0;
+        base_addr_next = base_addr;
+        base_valid_next = base_valid;
+        burst_len_next = burst_len;
+      end else begin
+        write_enable = 1'b1;
+        wait_time_next = 0;
+        base_valid_next = 1'b0;
+        burst_len_next = 0;
+
+        base_addr_next = base_addr;
+      end
+    end
+  end
+
+  always @(posedge clk) begin
+    if (rst) begin
+      base_addr <= {AddrWidth{1'b0}};
+      base_valid <= 1'd0;
+      burst_len <= {BurstLenWidth{1'b0}};
+      wait_time <= {WaitTimeWidth{1'b0}};
+      next_addr <= {{(NextAddrWidth-1){1'b0}}, 1'b1};
+    end else begin
+      base_addr <= base_addr_next;
+      base_valid <= base_valid_next;
+      burst_len <= burst_len_next;
+      wait_time <= wait_time_next;
+      next_addr <= next_addr_next;
+    end
+  end
+
+endmodule  // detect_burst
+
+`default_nettype wire
diff --git a/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/fifo.v b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/fifo.v
new file mode 100644
index 00000000..d2559d97
--- /dev/null
+++ b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/fifo.v
@@ -0,0 +1,107 @@
+`default_nettype none
+
+// first-word fall-through (FWFT) FIFO
+module fifo #(
+  parameter DATA_WIDTH = 32,
+  parameter ADDR_WIDTH = 5,
+  parameter DEPTH      = 32
+) (
+  input wire clk,
+  input wire reset,
+
+  // write
+  output wire                  if_full_n,
+  input  wire                  if_write_ce,
+  input  wire                  if_write,
+  input  wire [DATA_WIDTH-1:0] if_din,
+
+  // read
+  output wire                  if_empty_n,
+  input  wire                  if_read_ce,
+  input  wire                  if_read,
+  output wire [DATA_WIDTH-1:0] if_dout
+);
+
+generate
+  if (DEPTH == 1) begin : d1
+    fifo_fwd #(
+      .DATA_WIDTH(DATA_WIDTH)
+    ) unit (
+      .clk  (clk),
+      .reset(reset),
+
+      .if_full_n  (if_full_n),
+      .if_write_ce(if_write_ce),
+      .if_write   (if_write),
+      .if_din     (if_din),
+
+      .if_empty_n(if_empty_n),
+      .if_read_ce(if_read_ce),
+      .if_read   (if_read),
+      .if_dout   (if_dout)
+    );
+  end else if (DATA_WIDTH >= 36 && DEPTH >= 4096) begin : uram
+    fifo_bram #(
+      .MEM_STYLE ("ultra"),
+      .DATA_WIDTH(DATA_WIDTH),
+      .ADDR_WIDTH(ADDR_WIDTH),
+      .DEPTH     (DEPTH)
+    ) unit (
+      .clk  (clk),
+      .reset(reset),
+
+      .if_full_n  (if_full_n),
+      .if_write_ce(if_write_ce),
+      .if_write   (if_write),
+      .if_din     (if_din),
+
+      .if_empty_n(if_empty_n),
+      .if_read_ce(if_read_ce),
+      .if_read   (if_read),
+      .if_dout   (if_dout)
+    );
+  end else if (DEPTH >=128) begin : bram
+    fifo_bram #(
+      .MEM_STYLE ("block"),
+      .DATA_WIDTH(DATA_WIDTH),
+      .ADDR_WIDTH(ADDR_WIDTH),
+      .DEPTH     (DEPTH)
+    ) unit (
+      .clk  (clk),
+      .reset(reset),
+
+      .if_full_n  (if_full_n),
+      .if_write_ce(if_write_ce),
+      .if_write   (if_write),
+      .if_din     (if_din),
+
+      .if_empty_n(if_empty_n),
+      .if_read_ce(if_read_ce),
+      .if_read   (if_read),
+      .if_dout   (if_dout)
+    );
+  end else begin : srl
+    fifo_srl #(
+      .DATA_WIDTH(DATA_WIDTH),
+      .ADDR_WIDTH(ADDR_WIDTH),
+      .DEPTH     (DEPTH)
+    ) unit (
+      .clk  (clk),
+      .reset(reset),
+
+      .if_full_n  (if_full_n),
+      .if_write_ce(if_write_ce),
+      .if_write   (if_write),
+      .if_din     (if_din),
+
+      .if_empty_n(if_empty_n),
+      .if_read_ce(if_read_ce),
+      .if_read   (if_read),
+      .if_dout   (if_dout)
+    );
+  end
+endgenerate
+
+endmodule  // fifo
+
+`default_nettype wire
diff --git a/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/fifo_bram.v b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/fifo_bram.v
new file mode 100644
index 00000000..8b5aea64
--- /dev/null
+++ b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/fifo_bram.v
@@ -0,0 +1,151 @@
+`default_nettype none
+
+// first-word fall-through (FWFT) FIFO using block RAM
+// based on HLS generated code
+module fifo_bram #(
+  parameter MEM_STYLE  = "auto",
+  parameter DATA_WIDTH = 32,
+  parameter ADDR_WIDTH = 5,
+  parameter DEPTH      = 32
+) (
+  input wire clk,
+  input wire reset,
+
+  // write
+  output wire                  if_full_n,
+  input  wire                  if_write_ce,
+  input  wire                  if_write,
+  input  wire [DATA_WIDTH-1:0] if_din,
+
+  // read
+  output wire                  if_empty_n,
+  input  wire                  if_read_ce,
+  input  wire                  if_read,
+  output wire [DATA_WIDTH-1:0] if_dout
+);
+
+(* ram_style = MEM_STYLE *)
+reg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];
+reg  [DATA_WIDTH-1:0] q_buf;
+reg  [ADDR_WIDTH-1:0] waddr;
+reg  [ADDR_WIDTH-1:0] raddr;
+wire [ADDR_WIDTH-1:0] wnext;
+wire [ADDR_WIDTH-1:0] rnext;
+wire                  push;
+wire                  pop;
+reg  [ADDR_WIDTH-1:0] used;
+reg                   full_n;
+reg                   empty_n;
+reg  [DATA_WIDTH-1:0] q_tmp;
+reg                   show_ahead;
+reg  [DATA_WIDTH-1:0] dout_buf;
+reg                   dout_valid;
+
+localparam DepthM1 = DEPTH[ADDR_WIDTH-1:0] - 1'd1;
+
+assign if_full_n  = full_n;
+assign if_empty_n = dout_valid;
+assign if_dout    = dout_buf;
+assign push       = full_n & if_write_ce & if_write;
+assign pop        = empty_n & if_read_ce & (~dout_valid | if_read);
+assign wnext      = !push              ? waddr              :
+                    (waddr == DepthM1) ? {ADDR_WIDTH{1'b0}} : waddr + 1'd1;
+assign rnext      = !pop               ? raddr              :
+                    (raddr == DepthM1) ? {ADDR_WIDTH{1'b0}} : raddr + 1'd1;
+
+// waddr
+always @(posedge clk) begin
+  if (reset)
+    waddr <= {ADDR_WIDTH{1'b0}};
+  else
+    waddr <= wnext;
+end
+
+// raddr
+always @(posedge clk) begin
+  if (reset)
+    raddr <= {ADDR_WIDTH{1'b0}};
+  else
+    raddr <= rnext;
+end
+
+// used
+always @(posedge clk) begin
+  if (reset)
+    used <= {ADDR_WIDTH{1'b0}};
+  else if (push && !pop)
+    used <= used + 1'b1;
+  else if (!push && pop)
+    used <= used - 1'b1;
+end
+
+// full_n
+always @(posedge clk) begin
+  if (reset)
+    full_n <= 1'b1;
+  else if (push && !pop)
+    full_n <= (used != DepthM1);
+  else if (!push && pop)
+    full_n <= 1'b1;
+end
+
+// empty_n
+always @(posedge clk) begin
+  if (reset)
+    empty_n <= 1'b0;
+  else if (push && !pop)
+    empty_n <= 1'b1;
+  else if (!push && pop)
+    empty_n <= (used != {{(ADDR_WIDTH-1){1'b0}},1'b1});
+end
+
+// mem
+always @(posedge clk) begin
+  if (push)
+    mem[waddr] <= if_din;
+end
+
+// q_buf
+always @(posedge clk) begin
+  q_buf <= mem[rnext];
+end
+
+// q_tmp
+always @(posedge clk) begin
+  if (reset)
+    q_tmp <= {DATA_WIDTH{1'b0}};
+  else if (push)
+    q_tmp <= if_din;
+end
+
+// show_ahead
+always @(posedge clk) begin
+  if (reset)
+    show_ahead <= 1'b0;
+  else if (push && used == {{(ADDR_WIDTH-1){1'b0}},pop})
+    show_ahead <= 1'b1;
+  else
+    show_ahead <= 1'b0;
+end
+
+// dout_buf
+always @(posedge clk) begin
+  if (reset)
+    dout_buf <= {DATA_WIDTH{1'b0}};
+  else if (pop)
+    dout_buf <= show_ahead? q_tmp : q_buf;
+end
+
+// dout_valid
+always @(posedge clk) begin
+  if (reset)
+    dout_valid <= 1'b0;
+  else if (pop)
+    dout_valid <= 1'b1;
+  else if (if_read_ce & if_read)
+    dout_valid <= 1'b0;
+end
+
+endmodule  // fifo_bram
+
+`default_nettype wire
diff --git a/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/fifo_fwd.v b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/fifo_fwd.v
new file mode 100644
index 00000000..870695ea
--- /dev/null
+++ b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/fifo_fwd.v
@@ -0,0 +1,58 @@
+`default_nettype none
+
+// first-word fall-through (FWFT) FIFO with latency=0 and depth=1
+module fifo_fwd #(
+  parameter MEM_STYLE  = "",  // ignored
+  parameter DATA_WIDTH = 32,
+  parameter ADDR_WIDTH = 0,   // ignored
+  parameter DEPTH      = 1    // ignored
+) (
+  input wire clk,
+  input wire reset,
+
+  // write
+  output wire                  if_full_n,
+  input  wire                  if_write_ce,
+  input  wire                  if_write,
+  input  wire [DATA_WIDTH-1:0] if_din,
+
+  // read
+  output wire                  if_empty_n,
+  input  wire                  if_read_ce,
+  input  wire                  if_read,
+  output wire [DATA_WIDTH-1:0] if_dout
+);
+  reg [DATA_WIDTH-1:0] mem;
+  reg                  is_mem_valid;
+
+  // If mem is valid, the FIFO is not empty and is full; if read, mem becomes
+  // invalid. If mem is not valid, the FIFO is not empty if and only if written
+  // and is not full; if written but not read, mem becomes valid.
+
+  assign if_empty_n = is_mem_valid || (if_write && if_write_ce);
+  assign if_full_n  = !is_mem_valid;
+  assign if_dout    = is_mem_valid ? mem : if_din;
+
+  always @(posedge clk) begin
+    if (reset) begin
+      is_mem_valid <= 1'b0;
+    end else begin
+      if (is_mem_valid) begin
+        if (if_read && if_read_ce) begin
+          is_mem_valid <= 1'b0;
+        end
+      end else begin
+        if (if_write && if_write_ce && !(if_read && if_read_ce)) begin
+          is_mem_valid <= 1'b1;
+        end
+      end
+
+      if (if_write && if_write_ce) begin
+        mem <= if_din;
+      end
+    end
+  end
+
+endmodule  // fifo_fwd
+
+`default_nettype wire
diff --git a/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/fifo_srl.v b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/fifo_srl.v
new file mode 100644
index 00000000..8ed7a247
--- /dev/null
+++ b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/fifo_srl.v
@@ -0,0 +1,84 @@
+`default_nettype none
+
+// first-word fall-through (FWFT) FIFO using shift register LUT
+// based on HLS generated code
+module fifo_srl #(
+  parameter MEM_STYLE  = "shiftreg",
+  parameter DATA_WIDTH = 32,
+  parameter ADDR_WIDTH = 5,
+  parameter DEPTH      = 32
+) (
+  input wire clk,
+  input wire reset,
+
+  // write
+  output wire                  if_full_n,
+  input  wire                  if_write_ce,
+  input  wire                  if_write,
+  input  wire [DATA_WIDTH-1:0] if_din,
+
+  // read
+  output wire                  if_empty_n,
+  input  wire                  if_read_ce,
+  input  wire                  if_read,
+  output wire [DATA_WIDTH-1:0] if_dout
+);
+  parameter REAL_DEPTH = DEPTH < 4 ? 4 : DEPTH;
+  parameter REAL_ADDR_WIDTH = $clog2(REAL_DEPTH)+1;
+
+  wire [REAL_ADDR_WIDTH - 1:0] shift_reg_addr;
+  wire [DATA_WIDTH - 1:0] shift_reg_data;
+  wire [DATA_WIDTH - 1:0] shift_reg_q;
+  wire                    shift_reg_ce;
+  reg  [REAL_ADDR_WIDTH:0]     out_ptr;
+  reg                     internal_empty_n;
+  reg                     internal_full_n;
+
+  (* shreg_extract = "yes" *) reg [DATA_WIDTH-1:0] mem [0:REAL_DEPTH-1];
+
+  assign if_empty_n = internal_empty_n;
+  assign if_full_n = internal_full_n;
+  assign shift_reg_data = if_din;
+  assign if_dout = shift_reg_q;
+
+  assign shift_reg_addr = out_ptr[REAL_ADDR_WIDTH] == 1'b0 ? out_ptr[REAL_ADDR_WIDTH-1:0] : {REAL_ADDR_WIDTH{1'b0}};
+  assign shift_reg_ce = (if_write & if_write_ce) & internal_full_n;
+
+  assign shift_reg_q = mem[shift_reg_addr];
+
+  always @(posedge clk) begin
+    if (reset) begin
+      out_ptr <= ~{REAL_ADDR_WIDTH+1{1'b0}};
+      internal_empty_n <= 1'b0;
+      internal_full_n <= 1'b1;
+    end else begin
+      if (((if_read && if_read_ce) && internal_empty_n) &&
+          (!(if_write && if_write_ce) || !internal_full_n)) begin
+        out_ptr <= out_ptr - 1'b1;
+        if (out_ptr == {(REAL_ADDR_WIDTH+1){1'b0}})
+          internal_empty_n <= 1'b0;
+        internal_full_n <= 1'b1;
+      end
+      else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
+        ((if_write & if_write_ce) == 1 & internal_full_n == 1))
+      begin
+        out_ptr <= out_ptr + 1'b1;
+        internal_empty_n <= 1'b1;
+        if (out_ptr == REAL_DEPTH - {{(REAL_ADDR_WIDTH-1){1'b0}}, 2'd2})
+          internal_full_n <= 1'b0;
+      end
+    end
+  end
+
+  integer i;
+  always @(posedge clk) begin
+    if (shift_reg_ce) begin
+      for (i = 0; i < REAL_DEPTH - 1; i = i + 1)
+        mem[i + 1] <= mem[i];
+      mem[0] <= shift_reg_data;
+    end
+  end
+
+endmodule  // fifo_srl
+
+`default_nettype wire
diff --git a/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/generate_last.v b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/generate_last.v
new file mode 100644
index 00000000..7c9a8ac6
--- /dev/null
+++ b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/generate_last.v
@@ -0,0 +1,72 @@
+`default_nettype none
+
+module generate_last #(
+  parameter BurstLenWidth = 8
+) (
+  input wire clk,
+  input wire rst,
+
+  input  wire [BurstLenWidth-1:0] burst_len_dout,
+  input  wire                     burst_len_empty_n,
+  output reg                      burst_len_read,
+
+  output reg  last_din,
+  input  wire last_full_n,
+  output reg  last_write
+);
+
+  // state
+  reg                     busy;
+  reg [BurstLenWidth-1:0] count;
+
+  // logic
+  reg                     busy_next;
+  reg [BurstLenWidth-1:0] count_next;
+
+  always @* begin
+    busy_next = busy;
+    count_next = count;
+    burst_len_read = 1'b0;
+    last_write = 1'b0;
+    last_din = 1'bx;
+
+    if (last_full_n) begin
+      if (busy == 1'b0) begin
+        if (burst_len_empty_n) begin
+          // read from burst_len
+          burst_len_read = 1'b1;
+          count_next = burst_len_dout;
+
+          // write to last
+          last_write = 1'b1;
+          last_din = ~|count_next;
+
+          // change busy
+          if (|count_next) busy_next = 1'b1;
+        end
+      end else begin
+        count_next = count - 1'b1;
+
+        // write to last
+        last_write = 1'b1;
+        last_din = ~|count_next;
+
+        // change busy
+        if (~|count_next) busy_next = 1'b0;
+      end
+    end
+  end
+
+  always @(posedge clk) begin
+    if (rst) begin
+      busy <= 1'b0;
+      count <= {BurstLenWidth{1'b0}};
+    end else begin
+      busy <= busy_next;
+      count <= count_next;
+    end
+  end
+
+endmodule  // generate_last
+
+`default_nettype wire
diff --git a/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/priority_encoder.v b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/priority_encoder.v
new file mode 100644
index 00000000..cf82512b
--- /dev/null
+++ b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/priority_encoder.v
@@ -0,0 +1,92 @@
+/*
+
+Copyright (c) 2014-2021 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * Priority encoder module
+ */
+module priority_encoder #
+(
+    parameter WIDTH = 4,
+    // LSB priority selection
+    parameter LSB_HIGH_PRIORITY = 0
+)
+(
+    input  wire [WIDTH-1:0]         input_unencoded,
+    output wire                     output_valid,
+    output wire [$clog2(WIDTH)-1:0] output_encoded,
+    output wire [WIDTH-1:0]         output_unencoded
+);
+
+parameter LEVELS = WIDTH > 2 ? $clog2(WIDTH) : 1;
+parameter W = 2**LEVELS;
+
+// pad input to even power of two
+wire [W-1:0] input_padded = {{W-WIDTH{1'b0}}, input_unencoded};
+
+wire [W/2-1:0] stage_valid[LEVELS-1:0];
+wire [W/2-1:0] stage_enc[LEVELS-1:0];
+
+generate
+    genvar l, n;
+
+    // process input bits; generate valid bit and encoded bit for each pair
+    for (n = 0; n < W/2; n = n + 1) begin : loop_in
+        assign stage_valid[0][n] = |input_padded[n*2+1:n*2];
+        if (LSB_HIGH_PRIORITY) begin
+            // bit 0 is highest priority
+            assign stage_enc[0][n] = !input_padded[n*2+0];
+        end else begin
+            // bit 0 is lowest priority
+            assign stage_enc[0][n] = input_padded[n*2+1];
+        end
+    end
+
+    // compress down to single valid bit and encoded bus
+    for (l = 1; l < LEVELS; l = l + 1) begin : loop_levels
+        for (n = 0; n < W/(2*2**l); n = n + 1) begin : loop_compress
+            assign stage_valid[l][n] = |stage_valid[l-1][n*2+1:n*2];
+            if (LSB_HIGH_PRIORITY) begin
+                // bit 0 is highest priority
+                assign stage_enc[l][(n+1)*(l+1)-1:n*(l+1)] = stage_valid[l-1][n*2+0] ? {1'b0, stage_enc[l-1][(n*2+1)*l-1:(n*2+0)*l]} : {1'b1, stage_enc[l-1][(n*2+2)*l-1:(n*2+1)*l]};
+            end else begin
+                // bit 0 is lowest priority
+                assign stage_enc[l][(n+1)*(l+1)-1:n*(l+1)] = stage_valid[l-1][n*2+1] ? {1'b1, stage_enc[l-1][(n*2+2)*l-1:(n*2+1)*l]} : {1'b0, stage_enc[l-1][(n*2+1)*l-1:(n*2+0)*l]};
+            end
+        end
+    end
+endgenerate
+
+assign output_valid = stage_valid[LEVELS-1];
+assign output_encoded = stage_enc[LEVELS-1];
+assign output_unencoded = 1 << output_encoded;
+
+endmodule
+
+`resetall
diff --git a/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/relay_station.v b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/relay_station.v
new file mode 100644
index 00000000..522d8524
--- /dev/null
+++ b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/relay_station.v
@@ -0,0 +1,522 @@
+`default_nettype none
+
+// first-word fall-through (FWFT) FIFO that is friendly for floorplanning
+module relay_station #(
+    parameter DATA_WIDTH = 32,
+    parameter ADDR_WIDTH = 5,
+    parameter DEPTH      = 2,
+    parameter LEVEL      = 2,
+    parameter CONNECT    = 1   // add api to disconnect the relay station
+) (
+  input wire clk,
+  input wire reset,
+
+  // write
+  output wire                  if_full_n,
+  input  wire                  if_write_ce,
+  input  wire                  if_write,
+  input  wire [DATA_WIDTH-1:0] if_din,
+
+  // read
+  output wire                  if_empty_n,
+  input  wire                  if_read_ce,
+  input  wire                  if_read,
+  output wire [DATA_WIDTH-1:0] if_dout
+);
+
+  wire                  full_n  [LEVEL:0];
+  wire                  empty_n [LEVEL:0];
+  wire [DATA_WIDTH-1:0] data    [LEVEL:0];
+
+  // both full_n and write are registered, thus one level of relay_station cause
+  // two additional latency for the almost full fifo
+  parameter GRACE_PERIOD = LEVEL * 2;
+  parameter REAL_DEPTH = GRACE_PERIOD + DEPTH + 4;
+  parameter REAL_ADDR_WIDTH  = $clog2(REAL_DEPTH);
+
+  genvar i;
+  generate
+  if (CONNECT > 0) begin
+    if (LEVEL > 0) begin
+
+      for (i = 0; i < LEVEL; i = i + 1) begin : inst
+        if (i < LEVEL - 1) begin
+          fifo_reg #(
+            .DATA_WIDTH(DATA_WIDTH)
+          ) unit (
+            .clk(clk),
+            .reset(reset),
+
+            // connect to fifo[i+1]
+            .if_empty_n(empty_n[i+1]),
+            .if_read_ce(if_read_ce),
+            .if_read   (full_n[i+1]),
+            .if_dout   (data[i+1]),
+
+            // connect to fifo[i-1]
+            .if_full_n  (full_n[i]),
+            .if_write_ce(if_write_ce),
+            .if_write   (empty_n[i]),
+            .if_din     (data[i])
+          );
+
+        end else begin
+          (* keep = "true" *) fifo_almost_full #(
+            .DATA_WIDTH(DATA_WIDTH),
+            .ADDR_WIDTH(REAL_ADDR_WIDTH),
+            .DEPTH(REAL_DEPTH),
+            .GRACE_PERIOD(GRACE_PERIOD)
+          ) unit (
+            .clk(clk),
+            .reset(reset),
+
+            // connect to fifo[i+1]
+            .if_empty_n(empty_n[i+1]),
+            .if_read_ce(if_read_ce),
+            .if_read   (full_n[i+1]),
+            .if_dout   (data[i+1]),
+
+            // connect to fifo[i-1]
+            .if_full_n  (full_n[i]),
+            .if_write_ce(if_write_ce),
+            .if_write   (empty_n[i]),
+            .if_din     (data[i])
+          );
+        end
+      end
+
+      // write
+      assign if_full_n  = full_n[0];  // output
+      assign empty_n[0] = if_write & full_n[0];   // input
+      assign data[0]    = if_din;     // input
+
+      // read
+      assign if_empty_n    = empty_n[LEVEL];  // output
+      assign full_n[LEVEL] = if_read;         // input
+      assign if_dout       = data[LEVEL];     // output
+
+    end
+
+    // LEVEL == 0
+    else begin
+      assign if_full_n  = if_read;  // output
+      assign if_empty_n    = if_write;  // output
+      assign if_dout       = if_din;     // output
+    end
+  end
+
+  // disconnect the relay station
+  else begin
+    assign if_full_n  = 0;  // output
+    assign if_empty_n = 0;  // output
+    // leave the dout port dangling to facilitate pruning
+    // assign if_dout    = 0;     // output
+  end
+  endgenerate
+
+endmodule   // relay_station
+
+/////////////////////////////////////////////////////////////
+
+module fifo_reg #(
+  parameter DATA_WIDTH = 32
+) (
+  input wire clk,
+  input wire reset,
+
+  // write
+  (* keep = "true" *)
+  output reg                   if_full_n,
+  input  wire                  if_write_ce,
+  input  wire                  if_write,
+  input  wire [DATA_WIDTH-1:0] if_din,
+
+  // read
+  (* keep = "true" *)
+  output reg                   if_empty_n,
+  input  wire                  if_read_ce,
+  input  wire                  if_read,
+  (* keep = "true" *)
+  output reg  [DATA_WIDTH-1:0] if_dout
+);
+
+  always @ (posedge clk) begin
+    if_dout <= if_din;
+    if_empty_n <= if_write;
+    if_full_n <= if_read;
+  end
+
+endmodule
+
+/////////////////////////////////////////////////////////////////
+
+// first-word fall-through (FWFT) FIFO
+module fifo_almost_full #(
+  parameter DATA_WIDTH = 32,
+  parameter ADDR_WIDTH = 5,
+  parameter DEPTH      = 32,
+  parameter GRACE_PERIOD = 2
+) (
+  input wire clk,
+  input wire reset,
+
+  // write
+  output wire                  if_full_n,
+  input  wire                  if_write_ce,
+  input  wire                  if_write,
+  input  wire [DATA_WIDTH-1:0] if_din,
+
+  // read
+  output wire                  if_empty_n,
+  input  wire                  if_read_ce,
+  input  wire                  if_read,
+  output wire [DATA_WIDTH-1:0] if_dout
+);
+
+generate
+  if (DATA_WIDTH >= 36 && DEPTH >= 4096) begin : uram
+    fifo_bram_almost_full #(
+      .MEM_STYLE   ("ultra"),
+      .DATA_WIDTH  (DATA_WIDTH),
+      .ADDR_WIDTH  (ADDR_WIDTH),
+      .DEPTH       (DEPTH),
+      .GRACE_PERIOD(GRACE_PERIOD)
+    ) unit (
+      .clk  (clk),
+      .reset(reset),
+
+      .if_full_n  (if_full_n),
+      .if_write_ce(if_write_ce),
+      .if_write   (if_write),
+      .if_din     (if_din),
+
+      .if_empty_n(if_empty_n),
+      .if_read_ce(if_read_ce),
+      .if_read   (if_read),
+      .if_dout   (if_dout)
+    );
+  end else if (DEPTH >= 128) begin : bram
+    fifo_bram_almost_full #(
+      .MEM_STYLE ("block"),
+      .DATA_WIDTH(DATA_WIDTH),
+      .ADDR_WIDTH(ADDR_WIDTH),
+      .DEPTH     (DEPTH),
+      .GRACE_PERIOD(GRACE_PERIOD) /*********/
+    ) unit (
+      .clk  (clk),
+      .reset(reset),
+
+      .if_full_n  (if_full_n),
+      .if_write_ce(if_write_ce),
+      .if_write   (if_write),
+      .if_din     (if_din),
+
+      .if_empty_n(if_empty_n),
+      .if_read_ce(if_read_ce),
+      .if_read   (if_read),
+      .if_dout   (if_dout)
+    );
+  end else begin : srl
+    fifo_srl_almost_full #(
+      .DATA_WIDTH(DATA_WIDTH),
+      .ADDR_WIDTH(ADDR_WIDTH),
+      .DEPTH     (DEPTH),
+      .GRACE_PERIOD(GRACE_PERIOD) /*********/
+    ) unit (
+      .clk  (clk),
+      .reset(reset),
+
+      .if_full_n  (if_full_n),
+      .if_write_ce(if_write_ce),
+      .if_write   (if_write),
+      .if_din     (if_din),
+
+      .if_empty_n(if_empty_n),
+      .if_read_ce(if_read_ce),
+      .if_read   (if_read),
+      .if_dout   (if_dout)
+    );
+  end
+endgenerate
+
+endmodule  // fifo
+
+/////////////////////////////////////////////////////////////////
+
+module fifo_srl_almost_full #(
+  parameter MEM_STYLE    = "shiftreg",
+  parameter DATA_WIDTH   = 32,
+  parameter ADDR_WIDTH   = 4,
+  parameter DEPTH        = 16,
+  parameter GRACE_PERIOD = 2
+) (
+  input wire clk,
+  input wire reset,
+
+  // write
+  output wire                  if_full_n,
+  input  wire                  if_write_ce,
+  input  wire                  if_write,
+  input  wire [DATA_WIDTH-1:0] if_din,
+
+  // read
+  output wire                  if_empty_n,
+  input  wire                  if_read_ce,
+  input  wire                  if_read,
+  output wire [DATA_WIDTH-1:0] if_dout
+);
+
+parameter REAL_DEPTH = DEPTH < 4 ? 4 : DEPTH;
+parameter REAL_ADDR_WIDTH = $clog2(REAL_DEPTH)+1;
+
+wire[REAL_ADDR_WIDTH - 1:0] shiftReg_addr ;
+wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
+wire                     shiftReg_ce;
+reg[REAL_ADDR_WIDTH:0] mOutPtr = ~{(REAL_ADDR_WIDTH+1){1'b0}};
+reg internal_empty_n = 0, internal_full_n = 1;
+
+assign if_empty_n = internal_empty_n;
+
+/*******************************************/
+// assign if_full_n = internal_full_n;
+reg almost_full_q;
+wire almost_full = mOutPtr >= REAL_DEPTH - 1 - GRACE_PERIOD - 1 && mOutPtr != ~{REAL_ADDR_WIDTH+1{1'b0}};
+always @ (posedge clk) almost_full_q <= almost_full;
+assign if_full_n = ~almost_full_q;
+/*******************************************/
+
+assign shiftReg_data = if_din;
+assign if_dout = shiftReg_q;
+
+always @ (posedge clk) begin
+    if (reset == 1'b1)
+    begin
+        mOutPtr <= ~{REAL_ADDR_WIDTH+1{1'b0}};
+        internal_empty_n <= 1'b0;
+        internal_full_n <= 1'b1;
+    end
+    else begin
+        if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
+            ((if_write & if_write_ce) == 0 | internal_full_n == 0))
+        begin
+            mOutPtr <= mOutPtr - 5'd1;
+            if (mOutPtr == 0)
+                internal_empty_n <= 1'b0;
+            internal_full_n <= 1'b1;
+        end
+        else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
+            ((if_write & if_write_ce) == 1 & internal_full_n == 1))
+        begin
+            mOutPtr <= mOutPtr + 5'd1;
+            internal_empty_n <= 1'b1;
+            if (mOutPtr == REAL_DEPTH - 5'd2)
+                internal_full_n <= 1'b0;
+        end
+    end
+end
+
+assign shiftReg_addr = mOutPtr[REAL_ADDR_WIDTH] == 1'b0 ? mOutPtr[REAL_ADDR_WIDTH-1:0]:{REAL_ADDR_WIDTH{1'b0}};
+assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
+
+fifo_srl_almost_full_internal
+#(
+    .DATA_WIDTH(DATA_WIDTH),
+    .ADDR_WIDTH(REAL_ADDR_WIDTH),
+    .DEPTH(REAL_DEPTH))
+U_fifo_w32_d16_A_ram (
+    .clk(clk),
+    .data(shiftReg_data),
+    .ce(shiftReg_ce),
+    .a(shiftReg_addr),
+    .q(shiftReg_q));
+
+endmodule
+
+module fifo_srl_almost_full_internal #(
+  parameter DATA_WIDTH = 32'd32,
+  parameter ADDR_WIDTH = 32'd4,
+  parameter DEPTH      = 5'd16
+) (
+  input  wire                  clk,
+  input  wire [DATA_WIDTH-1:0] data,
+  input  wire                  ce,
+  input  wire [ADDR_WIDTH-1:0] a,
+  output wire [DATA_WIDTH-1:0] q
+);
+
+(* shreg_extract = "yes" *) reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
+integer i;
+
+always @ (posedge clk)
+    begin
+        if (ce)
+        begin
+            for (i=0;i<DEPTH-1;i=i+1)
+                SRL_SIG[i+1] <= SRL_SIG[i];
+            SRL_SIG[0] <= data;
+        end
+    end
+
+assign q = SRL_SIG[a];
+
+endmodule
+
+///////////////////////////////////////////////////////////
+
+// first-word fall-through (FWFT) FIFO using block RAM
+// based on HLS generated code
+module fifo_bram_almost_full #(
+  parameter MEM_STYLE  = "auto",
+  parameter DATA_WIDTH = 32,
+  parameter ADDR_WIDTH = 5,
+  parameter DEPTH      = 32,
+  parameter GRACE_PERIOD = 2
+) (
+  input wire clk,
+  input wire reset,
+
+  // write
+  output wire                  if_full_n,
+  input  wire                  if_write_ce,
+  input  wire                  if_write,
+  input  wire [DATA_WIDTH-1:0] if_din,
+
+  // read
+  output wire                  if_empty_n,
+  input  wire                  if_read_ce,
+  input  wire                  if_read,
+  output wire [DATA_WIDTH-1:0] if_dout
+);
+
+(* ram_style = MEM_STYLE *)
+reg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];
+reg  [DATA_WIDTH-1:0] q_buf;
+reg  [ADDR_WIDTH-1:0] waddr;
+reg  [ADDR_WIDTH-1:0] raddr;
+wire [ADDR_WIDTH-1:0] wnext;
+wire [ADDR_WIDTH-1:0] rnext;
+wire                  push;
+wire                  pop;
+reg  [ADDR_WIDTH-1:0] used;
+reg                   full_n;
+reg                   empty_n;
+reg  [DATA_WIDTH-1:0] q_tmp;
+reg                   show_ahead;
+reg  [DATA_WIDTH-1:0] dout_buf;
+reg                   dout_valid;
+
+localparam DepthM1 = DEPTH[ADDR_WIDTH-1:0] - 1'd1;
+
+/**************************************/
+wire almost_full = (used >= DEPTH - 1 - GRACE_PERIOD);
+//assign if_full_n  = full_n;
+assign if_full_n  = ~almost_full;
+/**************************************/
+
+assign if_empty_n = dout_valid;
+assign if_dout    = dout_buf;
+assign push       = full_n & if_write_ce & if_write;
+assign pop        = empty_n & if_read_ce & (~dout_valid | if_read);
+assign wnext      = !push              ? waddr              :
+                    (waddr == DepthM1) ? {ADDR_WIDTH{1'b0}} : waddr + 1'd1;
+assign rnext      = !pop               ? raddr              :
+                    (raddr == DepthM1) ? {ADDR_WIDTH{1'b0}} : raddr + 1'd1;
+
+
+
+// waddr
+always @(posedge clk) begin
+  if (reset)
+    waddr <= {ADDR_WIDTH{1'b0}};
+  else
+    waddr <= wnext;
+end
+
+// raddr
+always @(posedge clk) begin
+  if (reset)
+    raddr <= {ADDR_WIDTH{1'b0}};
+  else
+    raddr <= rnext;
+end
+
+// used
+always @(posedge clk) begin
+  if (reset)
+    used <= {ADDR_WIDTH{1'b0}};
+  else if (push && !pop)
+    used <= used + 1'b1;
+  else if (!push && pop)
+    used <= used - 1'b1;
+end
+
+// full_n
+always @(posedge clk) begin
+  if (reset)
+    full_n <= 1'b1;
+  else if (push && !pop)
+    full_n <= (used != DepthM1);
+  else if (!push && pop)
+    full_n <= 1'b1;
+end
+
+// empty_n
+always @(posedge clk) begin
+  if (reset)
+    empty_n <= 1'b0;
+  else if (push && !pop)
+    empty_n <= 1'b1;
+  else if (!push && pop)
+    empty_n <= (used != {{(ADDR_WIDTH-1){1'b0}},1'b1});
+end
+
+// mem
+always @(posedge clk) begin
+  if (push)
+    mem[waddr] <= if_din;
+end
+
+// q_buf
+always @(posedge clk) begin
+  q_buf <= mem[rnext];
+end
+
+// q_tmp
+always @(posedge clk) begin
+  if (reset)
+    q_tmp <= {DATA_WIDTH{1'b0}};
+  else if (push)
+    q_tmp <= if_din;
+end
+
+// show_ahead
+always @(posedge clk) begin
+  if (reset)
+    show_ahead <= 1'b0;
+  else if (push && used == {{(ADDR_WIDTH-1){1'b0}},pop})
+    show_ahead <= 1'b1;
+  else
+    show_ahead <= 1'b0;
+end
+
+// dout_buf
+always @(posedge clk) begin
+  if (reset)
+    dout_buf <= {DATA_WIDTH{1'b0}};
+  else if (pop)
+    dout_buf <= show_ahead? q_tmp : q_buf;
+end
+
+// dout_valid
+always @(posedge clk) begin
+  if (reset)
+    dout_valid <= 1'b0;
+  else if (pop)
+    dout_valid <= 1'b1;
+  else if (if_read_ce & if_read)
+    dout_valid <= 1'b0;
+end
+
+endmodule  // fifo_bram
+
+`default_nettype wire
diff --git a/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/vadd_bw.v b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/vadd_bw.v
new file mode 100644
index 00000000..c998c846
--- /dev/null
+++ b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/vadd_bw.v
@@ -0,0 +1,14140 @@
+`timescale 1 ns / 1 ps
+
+(* CORE_GENERATION_INFO = "vadd_bw_vadd_bw,hls_ip_2022_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xcu50-fsvh2104-2-e,HLS_INPUT_CLOCK=3.330000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=1.000000,HLS_SYN_LAT=0,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=2066,HLS_SYN_LUT=3752,HLS_VERSION=2022_2}" *)
+
+
+module vadd_bw
+(
+  s_axi_control_AWVALID,
+  s_axi_control_AWREADY,
+  s_axi_control_AWADDR,
+  s_axi_control_WVALID,
+  s_axi_control_WREADY,
+  s_axi_control_WDATA,
+  s_axi_control_WSTRB,
+  s_axi_control_ARVALID,
+  s_axi_control_ARREADY,
+  s_axi_control_ARADDR,
+  s_axi_control_RVALID,
+  s_axi_control_RREADY,
+  s_axi_control_RDATA,
+  s_axi_control_RRESP,
+  s_axi_control_BVALID,
+  s_axi_control_BREADY,
+  s_axi_control_BRESP,
+  ap_clk,
+  ap_rst_n,
+  interrupt,
+  m_axi_rmem0_ARADDR,
+  m_axi_rmem0_ARBURST,
+  m_axi_rmem0_ARCACHE,
+  m_axi_rmem0_ARID,
+  m_axi_rmem0_ARLEN,
+  m_axi_rmem0_ARLOCK,
+  m_axi_rmem0_ARPROT,
+  m_axi_rmem0_ARQOS,
+  m_axi_rmem0_ARREADY,
+  m_axi_rmem0_ARSIZE,
+  m_axi_rmem0_ARVALID,
+  m_axi_rmem0_AWADDR,
+  m_axi_rmem0_AWBURST,
+  m_axi_rmem0_AWCACHE,
+  m_axi_rmem0_AWID,
+  m_axi_rmem0_AWLEN,
+  m_axi_rmem0_AWLOCK,
+  m_axi_rmem0_AWPROT,
+  m_axi_rmem0_AWQOS,
+  m_axi_rmem0_AWREADY,
+  m_axi_rmem0_AWSIZE,
+  m_axi_rmem0_AWVALID,
+  m_axi_rmem0_BID,
+  m_axi_rmem0_BREADY,
+  m_axi_rmem0_BRESP,
+  m_axi_rmem0_BVALID,
+  m_axi_rmem0_RDATA,
+  m_axi_rmem0_RID,
+  m_axi_rmem0_RLAST,
+  m_axi_rmem0_RREADY,
+  m_axi_rmem0_RRESP,
+  m_axi_rmem0_RVALID,
+  m_axi_rmem0_WDATA,
+  m_axi_rmem0_WLAST,
+  m_axi_rmem0_WREADY,
+  m_axi_rmem0_WSTRB,
+  m_axi_rmem0_WVALID,
+  m_axi_rmem1_ARADDR,
+  m_axi_rmem1_ARBURST,
+  m_axi_rmem1_ARCACHE,
+  m_axi_rmem1_ARID,
+  m_axi_rmem1_ARLEN,
+  m_axi_rmem1_ARLOCK,
+  m_axi_rmem1_ARPROT,
+  m_axi_rmem1_ARQOS,
+  m_axi_rmem1_ARREADY,
+  m_axi_rmem1_ARSIZE,
+  m_axi_rmem1_ARVALID,
+  m_axi_rmem1_AWADDR,
+  m_axi_rmem1_AWBURST,
+  m_axi_rmem1_AWCACHE,
+  m_axi_rmem1_AWID,
+  m_axi_rmem1_AWLEN,
+  m_axi_rmem1_AWLOCK,
+  m_axi_rmem1_AWPROT,
+  m_axi_rmem1_AWQOS,
+  m_axi_rmem1_AWREADY,
+  m_axi_rmem1_AWSIZE,
+  m_axi_rmem1_AWVALID,
+  m_axi_rmem1_BID,
+  m_axi_rmem1_BREADY,
+  m_axi_rmem1_BRESP,
+  m_axi_rmem1_BVALID,
+  m_axi_rmem1_RDATA,
+  m_axi_rmem1_RID,
+  m_axi_rmem1_RLAST,
+  m_axi_rmem1_RREADY,
+  m_axi_rmem1_RRESP,
+  m_axi_rmem1_RVALID,
+  m_axi_rmem1_WDATA,
+  m_axi_rmem1_WLAST,
+  m_axi_rmem1_WREADY,
+  m_axi_rmem1_WSTRB,
+  m_axi_rmem1_WVALID,
+  m_axi_rmem2_ARADDR,
+  m_axi_rmem2_ARBURST,
+  m_axi_rmem2_ARCACHE,
+  m_axi_rmem2_ARID,
+  m_axi_rmem2_ARLEN,
+  m_axi_rmem2_ARLOCK,
+  m_axi_rmem2_ARPROT,
+  m_axi_rmem2_ARQOS,
+  m_axi_rmem2_ARREADY,
+  m_axi_rmem2_ARSIZE,
+  m_axi_rmem2_ARVALID,
+  m_axi_rmem2_AWADDR,
+  m_axi_rmem2_AWBURST,
+  m_axi_rmem2_AWCACHE,
+  m_axi_rmem2_AWID,
+  m_axi_rmem2_AWLEN,
+  m_axi_rmem2_AWLOCK,
+  m_axi_rmem2_AWPROT,
+  m_axi_rmem2_AWQOS,
+  m_axi_rmem2_AWREADY,
+  m_axi_rmem2_AWSIZE,
+  m_axi_rmem2_AWVALID,
+  m_axi_rmem2_BID,
+  m_axi_rmem2_BREADY,
+  m_axi_rmem2_BRESP,
+  m_axi_rmem2_BVALID,
+  m_axi_rmem2_RDATA,
+  m_axi_rmem2_RID,
+  m_axi_rmem2_RLAST,
+  m_axi_rmem2_RREADY,
+  m_axi_rmem2_RRESP,
+  m_axi_rmem2_RVALID,
+  m_axi_rmem2_WDATA,
+  m_axi_rmem2_WLAST,
+  m_axi_rmem2_WREADY,
+  m_axi_rmem2_WSTRB,
+  m_axi_rmem2_WVALID,
+  m_axi_rmem3_ARADDR,
+  m_axi_rmem3_ARBURST,
+  m_axi_rmem3_ARCACHE,
+  m_axi_rmem3_ARID,
+  m_axi_rmem3_ARLEN,
+  m_axi_rmem3_ARLOCK,
+  m_axi_rmem3_ARPROT,
+  m_axi_rmem3_ARQOS,
+  m_axi_rmem3_ARREADY,
+  m_axi_rmem3_ARSIZE,
+  m_axi_rmem3_ARVALID,
+  m_axi_rmem3_AWADDR,
+  m_axi_rmem3_AWBURST,
+  m_axi_rmem3_AWCACHE,
+  m_axi_rmem3_AWID,
+  m_axi_rmem3_AWLEN,
+  m_axi_rmem3_AWLOCK,
+  m_axi_rmem3_AWPROT,
+  m_axi_rmem3_AWQOS,
+  m_axi_rmem3_AWREADY,
+  m_axi_rmem3_AWSIZE,
+  m_axi_rmem3_AWVALID,
+  m_axi_rmem3_BID,
+  m_axi_rmem3_BREADY,
+  m_axi_rmem3_BRESP,
+  m_axi_rmem3_BVALID,
+  m_axi_rmem3_RDATA,
+  m_axi_rmem3_RID,
+  m_axi_rmem3_RLAST,
+  m_axi_rmem3_RREADY,
+  m_axi_rmem3_RRESP,
+  m_axi_rmem3_RVALID,
+  m_axi_rmem3_WDATA,
+  m_axi_rmem3_WLAST,
+  m_axi_rmem3_WREADY,
+  m_axi_rmem3_WSTRB,
+  m_axi_rmem3_WVALID,
+  m_axi_rmem4_ARADDR,
+  m_axi_rmem4_ARBURST,
+  m_axi_rmem4_ARCACHE,
+  m_axi_rmem4_ARID,
+  m_axi_rmem4_ARLEN,
+  m_axi_rmem4_ARLOCK,
+  m_axi_rmem4_ARPROT,
+  m_axi_rmem4_ARQOS,
+  m_axi_rmem4_ARREADY,
+  m_axi_rmem4_ARSIZE,
+  m_axi_rmem4_ARVALID,
+  m_axi_rmem4_AWADDR,
+  m_axi_rmem4_AWBURST,
+  m_axi_rmem4_AWCACHE,
+  m_axi_rmem4_AWID,
+  m_axi_rmem4_AWLEN,
+  m_axi_rmem4_AWLOCK,
+  m_axi_rmem4_AWPROT,
+  m_axi_rmem4_AWQOS,
+  m_axi_rmem4_AWREADY,
+  m_axi_rmem4_AWSIZE,
+  m_axi_rmem4_AWVALID,
+  m_axi_rmem4_BID,
+  m_axi_rmem4_BREADY,
+  m_axi_rmem4_BRESP,
+  m_axi_rmem4_BVALID,
+  m_axi_rmem4_RDATA,
+  m_axi_rmem4_RID,
+  m_axi_rmem4_RLAST,
+  m_axi_rmem4_RREADY,
+  m_axi_rmem4_RRESP,
+  m_axi_rmem4_RVALID,
+  m_axi_rmem4_WDATA,
+  m_axi_rmem4_WLAST,
+  m_axi_rmem4_WREADY,
+  m_axi_rmem4_WSTRB,
+  m_axi_rmem4_WVALID,
+  m_axi_rmem5_ARADDR,
+  m_axi_rmem5_ARBURST,
+  m_axi_rmem5_ARCACHE,
+  m_axi_rmem5_ARID,
+  m_axi_rmem5_ARLEN,
+  m_axi_rmem5_ARLOCK,
+  m_axi_rmem5_ARPROT,
+  m_axi_rmem5_ARQOS,
+  m_axi_rmem5_ARREADY,
+  m_axi_rmem5_ARSIZE,
+  m_axi_rmem5_ARVALID,
+  m_axi_rmem5_AWADDR,
+  m_axi_rmem5_AWBURST,
+  m_axi_rmem5_AWCACHE,
+  m_axi_rmem5_AWID,
+  m_axi_rmem5_AWLEN,
+  m_axi_rmem5_AWLOCK,
+  m_axi_rmem5_AWPROT,
+  m_axi_rmem5_AWQOS,
+  m_axi_rmem5_AWREADY,
+  m_axi_rmem5_AWSIZE,
+  m_axi_rmem5_AWVALID,
+  m_axi_rmem5_BID,
+  m_axi_rmem5_BREADY,
+  m_axi_rmem5_BRESP,
+  m_axi_rmem5_BVALID,
+  m_axi_rmem5_RDATA,
+  m_axi_rmem5_RID,
+  m_axi_rmem5_RLAST,
+  m_axi_rmem5_RREADY,
+  m_axi_rmem5_RRESP,
+  m_axi_rmem5_RVALID,
+  m_axi_rmem5_WDATA,
+  m_axi_rmem5_WLAST,
+  m_axi_rmem5_WREADY,
+  m_axi_rmem5_WSTRB,
+  m_axi_rmem5_WVALID,
+  m_axi_rmem6_ARADDR,
+  m_axi_rmem6_ARBURST,
+  m_axi_rmem6_ARCACHE,
+  m_axi_rmem6_ARID,
+  m_axi_rmem6_ARLEN,
+  m_axi_rmem6_ARLOCK,
+  m_axi_rmem6_ARPROT,
+  m_axi_rmem6_ARQOS,
+  m_axi_rmem6_ARREADY,
+  m_axi_rmem6_ARSIZE,
+  m_axi_rmem6_ARVALID,
+  m_axi_rmem6_AWADDR,
+  m_axi_rmem6_AWBURST,
+  m_axi_rmem6_AWCACHE,
+  m_axi_rmem6_AWID,
+  m_axi_rmem6_AWLEN,
+  m_axi_rmem6_AWLOCK,
+  m_axi_rmem6_AWPROT,
+  m_axi_rmem6_AWQOS,
+  m_axi_rmem6_AWREADY,
+  m_axi_rmem6_AWSIZE,
+  m_axi_rmem6_AWVALID,
+  m_axi_rmem6_BID,
+  m_axi_rmem6_BREADY,
+  m_axi_rmem6_BRESP,
+  m_axi_rmem6_BVALID,
+  m_axi_rmem6_RDATA,
+  m_axi_rmem6_RID,
+  m_axi_rmem6_RLAST,
+  m_axi_rmem6_RREADY,
+  m_axi_rmem6_RRESP,
+  m_axi_rmem6_RVALID,
+  m_axi_rmem6_WDATA,
+  m_axi_rmem6_WLAST,
+  m_axi_rmem6_WREADY,
+  m_axi_rmem6_WSTRB,
+  m_axi_rmem6_WVALID,
+  m_axi_rmem7_ARADDR,
+  m_axi_rmem7_ARBURST,
+  m_axi_rmem7_ARCACHE,
+  m_axi_rmem7_ARID,
+  m_axi_rmem7_ARLEN,
+  m_axi_rmem7_ARLOCK,
+  m_axi_rmem7_ARPROT,
+  m_axi_rmem7_ARQOS,
+  m_axi_rmem7_ARREADY,
+  m_axi_rmem7_ARSIZE,
+  m_axi_rmem7_ARVALID,
+  m_axi_rmem7_AWADDR,
+  m_axi_rmem7_AWBURST,
+  m_axi_rmem7_AWCACHE,
+  m_axi_rmem7_AWID,
+  m_axi_rmem7_AWLEN,
+  m_axi_rmem7_AWLOCK,
+  m_axi_rmem7_AWPROT,
+  m_axi_rmem7_AWQOS,
+  m_axi_rmem7_AWREADY,
+  m_axi_rmem7_AWSIZE,
+  m_axi_rmem7_AWVALID,
+  m_axi_rmem7_BID,
+  m_axi_rmem7_BREADY,
+  m_axi_rmem7_BRESP,
+  m_axi_rmem7_BVALID,
+  m_axi_rmem7_RDATA,
+  m_axi_rmem7_RID,
+  m_axi_rmem7_RLAST,
+  m_axi_rmem7_RREADY,
+  m_axi_rmem7_RRESP,
+  m_axi_rmem7_RVALID,
+  m_axi_rmem7_WDATA,
+  m_axi_rmem7_WLAST,
+  m_axi_rmem7_WREADY,
+  m_axi_rmem7_WSTRB,
+  m_axi_rmem7_WVALID,
+  m_axi_rmem8_ARADDR,
+  m_axi_rmem8_ARBURST,
+  m_axi_rmem8_ARCACHE,
+  m_axi_rmem8_ARID,
+  m_axi_rmem8_ARLEN,
+  m_axi_rmem8_ARLOCK,
+  m_axi_rmem8_ARPROT,
+  m_axi_rmem8_ARQOS,
+  m_axi_rmem8_ARREADY,
+  m_axi_rmem8_ARSIZE,
+  m_axi_rmem8_ARVALID,
+  m_axi_rmem8_AWADDR,
+  m_axi_rmem8_AWBURST,
+  m_axi_rmem8_AWCACHE,
+  m_axi_rmem8_AWID,
+  m_axi_rmem8_AWLEN,
+  m_axi_rmem8_AWLOCK,
+  m_axi_rmem8_AWPROT,
+  m_axi_rmem8_AWQOS,
+  m_axi_rmem8_AWREADY,
+  m_axi_rmem8_AWSIZE,
+  m_axi_rmem8_AWVALID,
+  m_axi_rmem8_BID,
+  m_axi_rmem8_BREADY,
+  m_axi_rmem8_BRESP,
+  m_axi_rmem8_BVALID,
+  m_axi_rmem8_RDATA,
+  m_axi_rmem8_RID,
+  m_axi_rmem8_RLAST,
+  m_axi_rmem8_RREADY,
+  m_axi_rmem8_RRESP,
+  m_axi_rmem8_RVALID,
+  m_axi_rmem8_WDATA,
+  m_axi_rmem8_WLAST,
+  m_axi_rmem8_WREADY,
+  m_axi_rmem8_WSTRB,
+  m_axi_rmem8_WVALID,
+  m_axi_rmem9_ARADDR,
+  m_axi_rmem9_ARBURST,
+  m_axi_rmem9_ARCACHE,
+  m_axi_rmem9_ARID,
+  m_axi_rmem9_ARLEN,
+  m_axi_rmem9_ARLOCK,
+  m_axi_rmem9_ARPROT,
+  m_axi_rmem9_ARQOS,
+  m_axi_rmem9_ARREADY,
+  m_axi_rmem9_ARSIZE,
+  m_axi_rmem9_ARVALID,
+  m_axi_rmem9_AWADDR,
+  m_axi_rmem9_AWBURST,
+  m_axi_rmem9_AWCACHE,
+  m_axi_rmem9_AWID,
+  m_axi_rmem9_AWLEN,
+  m_axi_rmem9_AWLOCK,
+  m_axi_rmem9_AWPROT,
+  m_axi_rmem9_AWQOS,
+  m_axi_rmem9_AWREADY,
+  m_axi_rmem9_AWSIZE,
+  m_axi_rmem9_AWVALID,
+  m_axi_rmem9_BID,
+  m_axi_rmem9_BREADY,
+  m_axi_rmem9_BRESP,
+  m_axi_rmem9_BVALID,
+  m_axi_rmem9_RDATA,
+  m_axi_rmem9_RID,
+  m_axi_rmem9_RLAST,
+  m_axi_rmem9_RREADY,
+  m_axi_rmem9_RRESP,
+  m_axi_rmem9_RVALID,
+  m_axi_rmem9_WDATA,
+  m_axi_rmem9_WLAST,
+  m_axi_rmem9_WREADY,
+  m_axi_rmem9_WSTRB,
+  m_axi_rmem9_WVALID,
+  m_axi_rmem10_ARADDR,
+  m_axi_rmem10_ARBURST,
+  m_axi_rmem10_ARCACHE,
+  m_axi_rmem10_ARID,
+  m_axi_rmem10_ARLEN,
+  m_axi_rmem10_ARLOCK,
+  m_axi_rmem10_ARPROT,
+  m_axi_rmem10_ARQOS,
+  m_axi_rmem10_ARREADY,
+  m_axi_rmem10_ARSIZE,
+  m_axi_rmem10_ARVALID,
+  m_axi_rmem10_AWADDR,
+  m_axi_rmem10_AWBURST,
+  m_axi_rmem10_AWCACHE,
+  m_axi_rmem10_AWID,
+  m_axi_rmem10_AWLEN,
+  m_axi_rmem10_AWLOCK,
+  m_axi_rmem10_AWPROT,
+  m_axi_rmem10_AWQOS,
+  m_axi_rmem10_AWREADY,
+  m_axi_rmem10_AWSIZE,
+  m_axi_rmem10_AWVALID,
+  m_axi_rmem10_BID,
+  m_axi_rmem10_BREADY,
+  m_axi_rmem10_BRESP,
+  m_axi_rmem10_BVALID,
+  m_axi_rmem10_RDATA,
+  m_axi_rmem10_RID,
+  m_axi_rmem10_RLAST,
+  m_axi_rmem10_RREADY,
+  m_axi_rmem10_RRESP,
+  m_axi_rmem10_RVALID,
+  m_axi_rmem10_WDATA,
+  m_axi_rmem10_WLAST,
+  m_axi_rmem10_WREADY,
+  m_axi_rmem10_WSTRB,
+  m_axi_rmem10_WVALID,
+  m_axi_rmem11_ARADDR,
+  m_axi_rmem11_ARBURST,
+  m_axi_rmem11_ARCACHE,
+  m_axi_rmem11_ARID,
+  m_axi_rmem11_ARLEN,
+  m_axi_rmem11_ARLOCK,
+  m_axi_rmem11_ARPROT,
+  m_axi_rmem11_ARQOS,
+  m_axi_rmem11_ARREADY,
+  m_axi_rmem11_ARSIZE,
+  m_axi_rmem11_ARVALID,
+  m_axi_rmem11_AWADDR,
+  m_axi_rmem11_AWBURST,
+  m_axi_rmem11_AWCACHE,
+  m_axi_rmem11_AWID,
+  m_axi_rmem11_AWLEN,
+  m_axi_rmem11_AWLOCK,
+  m_axi_rmem11_AWPROT,
+  m_axi_rmem11_AWQOS,
+  m_axi_rmem11_AWREADY,
+  m_axi_rmem11_AWSIZE,
+  m_axi_rmem11_AWVALID,
+  m_axi_rmem11_BID,
+  m_axi_rmem11_BREADY,
+  m_axi_rmem11_BRESP,
+  m_axi_rmem11_BVALID,
+  m_axi_rmem11_RDATA,
+  m_axi_rmem11_RID,
+  m_axi_rmem11_RLAST,
+  m_axi_rmem11_RREADY,
+  m_axi_rmem11_RRESP,
+  m_axi_rmem11_RVALID,
+  m_axi_rmem11_WDATA,
+  m_axi_rmem11_WLAST,
+  m_axi_rmem11_WREADY,
+  m_axi_rmem11_WSTRB,
+  m_axi_rmem11_WVALID,
+  m_axi_rmem12_ARADDR,
+  m_axi_rmem12_ARBURST,
+  m_axi_rmem12_ARCACHE,
+  m_axi_rmem12_ARID,
+  m_axi_rmem12_ARLEN,
+  m_axi_rmem12_ARLOCK,
+  m_axi_rmem12_ARPROT,
+  m_axi_rmem12_ARQOS,
+  m_axi_rmem12_ARREADY,
+  m_axi_rmem12_ARSIZE,
+  m_axi_rmem12_ARVALID,
+  m_axi_rmem12_AWADDR,
+  m_axi_rmem12_AWBURST,
+  m_axi_rmem12_AWCACHE,
+  m_axi_rmem12_AWID,
+  m_axi_rmem12_AWLEN,
+  m_axi_rmem12_AWLOCK,
+  m_axi_rmem12_AWPROT,
+  m_axi_rmem12_AWQOS,
+  m_axi_rmem12_AWREADY,
+  m_axi_rmem12_AWSIZE,
+  m_axi_rmem12_AWVALID,
+  m_axi_rmem12_BID,
+  m_axi_rmem12_BREADY,
+  m_axi_rmem12_BRESP,
+  m_axi_rmem12_BVALID,
+  m_axi_rmem12_RDATA,
+  m_axi_rmem12_RID,
+  m_axi_rmem12_RLAST,
+  m_axi_rmem12_RREADY,
+  m_axi_rmem12_RRESP,
+  m_axi_rmem12_RVALID,
+  m_axi_rmem12_WDATA,
+  m_axi_rmem12_WLAST,
+  m_axi_rmem12_WREADY,
+  m_axi_rmem12_WSTRB,
+  m_axi_rmem12_WVALID,
+  m_axi_rmem13_ARADDR,
+  m_axi_rmem13_ARBURST,
+  m_axi_rmem13_ARCACHE,
+  m_axi_rmem13_ARID,
+  m_axi_rmem13_ARLEN,
+  m_axi_rmem13_ARLOCK,
+  m_axi_rmem13_ARPROT,
+  m_axi_rmem13_ARQOS,
+  m_axi_rmem13_ARREADY,
+  m_axi_rmem13_ARSIZE,
+  m_axi_rmem13_ARVALID,
+  m_axi_rmem13_AWADDR,
+  m_axi_rmem13_AWBURST,
+  m_axi_rmem13_AWCACHE,
+  m_axi_rmem13_AWID,
+  m_axi_rmem13_AWLEN,
+  m_axi_rmem13_AWLOCK,
+  m_axi_rmem13_AWPROT,
+  m_axi_rmem13_AWQOS,
+  m_axi_rmem13_AWREADY,
+  m_axi_rmem13_AWSIZE,
+  m_axi_rmem13_AWVALID,
+  m_axi_rmem13_BID,
+  m_axi_rmem13_BREADY,
+  m_axi_rmem13_BRESP,
+  m_axi_rmem13_BVALID,
+  m_axi_rmem13_RDATA,
+  m_axi_rmem13_RID,
+  m_axi_rmem13_RLAST,
+  m_axi_rmem13_RREADY,
+  m_axi_rmem13_RRESP,
+  m_axi_rmem13_RVALID,
+  m_axi_rmem13_WDATA,
+  m_axi_rmem13_WLAST,
+  m_axi_rmem13_WREADY,
+  m_axi_rmem13_WSTRB,
+  m_axi_rmem13_WVALID,
+  m_axi_rmem14_ARADDR,
+  m_axi_rmem14_ARBURST,
+  m_axi_rmem14_ARCACHE,
+  m_axi_rmem14_ARID,
+  m_axi_rmem14_ARLEN,
+  m_axi_rmem14_ARLOCK,
+  m_axi_rmem14_ARPROT,
+  m_axi_rmem14_ARQOS,
+  m_axi_rmem14_ARREADY,
+  m_axi_rmem14_ARSIZE,
+  m_axi_rmem14_ARVALID,
+  m_axi_rmem14_AWADDR,
+  m_axi_rmem14_AWBURST,
+  m_axi_rmem14_AWCACHE,
+  m_axi_rmem14_AWID,
+  m_axi_rmem14_AWLEN,
+  m_axi_rmem14_AWLOCK,
+  m_axi_rmem14_AWPROT,
+  m_axi_rmem14_AWQOS,
+  m_axi_rmem14_AWREADY,
+  m_axi_rmem14_AWSIZE,
+  m_axi_rmem14_AWVALID,
+  m_axi_rmem14_BID,
+  m_axi_rmem14_BREADY,
+  m_axi_rmem14_BRESP,
+  m_axi_rmem14_BVALID,
+  m_axi_rmem14_RDATA,
+  m_axi_rmem14_RID,
+  m_axi_rmem14_RLAST,
+  m_axi_rmem14_RREADY,
+  m_axi_rmem14_RRESP,
+  m_axi_rmem14_RVALID,
+  m_axi_rmem14_WDATA,
+  m_axi_rmem14_WLAST,
+  m_axi_rmem14_WREADY,
+  m_axi_rmem14_WSTRB,
+  m_axi_rmem14_WVALID,
+  m_axi_rmem15_ARADDR,
+  m_axi_rmem15_ARBURST,
+  m_axi_rmem15_ARCACHE,
+  m_axi_rmem15_ARID,
+  m_axi_rmem15_ARLEN,
+  m_axi_rmem15_ARLOCK,
+  m_axi_rmem15_ARPROT,
+  m_axi_rmem15_ARQOS,
+  m_axi_rmem15_ARREADY,
+  m_axi_rmem15_ARSIZE,
+  m_axi_rmem15_ARVALID,
+  m_axi_rmem15_AWADDR,
+  m_axi_rmem15_AWBURST,
+  m_axi_rmem15_AWCACHE,
+  m_axi_rmem15_AWID,
+  m_axi_rmem15_AWLEN,
+  m_axi_rmem15_AWLOCK,
+  m_axi_rmem15_AWPROT,
+  m_axi_rmem15_AWQOS,
+  m_axi_rmem15_AWREADY,
+  m_axi_rmem15_AWSIZE,
+  m_axi_rmem15_AWVALID,
+  m_axi_rmem15_BID,
+  m_axi_rmem15_BREADY,
+  m_axi_rmem15_BRESP,
+  m_axi_rmem15_BVALID,
+  m_axi_rmem15_RDATA,
+  m_axi_rmem15_RID,
+  m_axi_rmem15_RLAST,
+  m_axi_rmem15_RREADY,
+  m_axi_rmem15_RRESP,
+  m_axi_rmem15_RVALID,
+  m_axi_rmem15_WDATA,
+  m_axi_rmem15_WLAST,
+  m_axi_rmem15_WREADY,
+  m_axi_rmem15_WSTRB,
+  m_axi_rmem15_WVALID,
+  m_axi_rmem16_ARADDR,
+  m_axi_rmem16_ARBURST,
+  m_axi_rmem16_ARCACHE,
+  m_axi_rmem16_ARID,
+  m_axi_rmem16_ARLEN,
+  m_axi_rmem16_ARLOCK,
+  m_axi_rmem16_ARPROT,
+  m_axi_rmem16_ARQOS,
+  m_axi_rmem16_ARREADY,
+  m_axi_rmem16_ARSIZE,
+  m_axi_rmem16_ARVALID,
+  m_axi_rmem16_AWADDR,
+  m_axi_rmem16_AWBURST,
+  m_axi_rmem16_AWCACHE,
+  m_axi_rmem16_AWID,
+  m_axi_rmem16_AWLEN,
+  m_axi_rmem16_AWLOCK,
+  m_axi_rmem16_AWPROT,
+  m_axi_rmem16_AWQOS,
+  m_axi_rmem16_AWREADY,
+  m_axi_rmem16_AWSIZE,
+  m_axi_rmem16_AWVALID,
+  m_axi_rmem16_BID,
+  m_axi_rmem16_BREADY,
+  m_axi_rmem16_BRESP,
+  m_axi_rmem16_BVALID,
+  m_axi_rmem16_RDATA,
+  m_axi_rmem16_RID,
+  m_axi_rmem16_RLAST,
+  m_axi_rmem16_RREADY,
+  m_axi_rmem16_RRESP,
+  m_axi_rmem16_RVALID,
+  m_axi_rmem16_WDATA,
+  m_axi_rmem16_WLAST,
+  m_axi_rmem16_WREADY,
+  m_axi_rmem16_WSTRB,
+  m_axi_rmem16_WVALID,
+  m_axi_rmem17_ARADDR,
+  m_axi_rmem17_ARBURST,
+  m_axi_rmem17_ARCACHE,
+  m_axi_rmem17_ARID,
+  m_axi_rmem17_ARLEN,
+  m_axi_rmem17_ARLOCK,
+  m_axi_rmem17_ARPROT,
+  m_axi_rmem17_ARQOS,
+  m_axi_rmem17_ARREADY,
+  m_axi_rmem17_ARSIZE,
+  m_axi_rmem17_ARVALID,
+  m_axi_rmem17_AWADDR,
+  m_axi_rmem17_AWBURST,
+  m_axi_rmem17_AWCACHE,
+  m_axi_rmem17_AWID,
+  m_axi_rmem17_AWLEN,
+  m_axi_rmem17_AWLOCK,
+  m_axi_rmem17_AWPROT,
+  m_axi_rmem17_AWQOS,
+  m_axi_rmem17_AWREADY,
+  m_axi_rmem17_AWSIZE,
+  m_axi_rmem17_AWVALID,
+  m_axi_rmem17_BID,
+  m_axi_rmem17_BREADY,
+  m_axi_rmem17_BRESP,
+  m_axi_rmem17_BVALID,
+  m_axi_rmem17_RDATA,
+  m_axi_rmem17_RID,
+  m_axi_rmem17_RLAST,
+  m_axi_rmem17_RREADY,
+  m_axi_rmem17_RRESP,
+  m_axi_rmem17_RVALID,
+  m_axi_rmem17_WDATA,
+  m_axi_rmem17_WLAST,
+  m_axi_rmem17_WREADY,
+  m_axi_rmem17_WSTRB,
+  m_axi_rmem17_WVALID,
+  m_axi_rmem18_ARADDR,
+  m_axi_rmem18_ARBURST,
+  m_axi_rmem18_ARCACHE,
+  m_axi_rmem18_ARID,
+  m_axi_rmem18_ARLEN,
+  m_axi_rmem18_ARLOCK,
+  m_axi_rmem18_ARPROT,
+  m_axi_rmem18_ARQOS,
+  m_axi_rmem18_ARREADY,
+  m_axi_rmem18_ARSIZE,
+  m_axi_rmem18_ARVALID,
+  m_axi_rmem18_AWADDR,
+  m_axi_rmem18_AWBURST,
+  m_axi_rmem18_AWCACHE,
+  m_axi_rmem18_AWID,
+  m_axi_rmem18_AWLEN,
+  m_axi_rmem18_AWLOCK,
+  m_axi_rmem18_AWPROT,
+  m_axi_rmem18_AWQOS,
+  m_axi_rmem18_AWREADY,
+  m_axi_rmem18_AWSIZE,
+  m_axi_rmem18_AWVALID,
+  m_axi_rmem18_BID,
+  m_axi_rmem18_BREADY,
+  m_axi_rmem18_BRESP,
+  m_axi_rmem18_BVALID,
+  m_axi_rmem18_RDATA,
+  m_axi_rmem18_RID,
+  m_axi_rmem18_RLAST,
+  m_axi_rmem18_RREADY,
+  m_axi_rmem18_RRESP,
+  m_axi_rmem18_RVALID,
+  m_axi_rmem18_WDATA,
+  m_axi_rmem18_WLAST,
+  m_axi_rmem18_WREADY,
+  m_axi_rmem18_WSTRB,
+  m_axi_rmem18_WVALID,
+  m_axi_rmem19_ARADDR,
+  m_axi_rmem19_ARBURST,
+  m_axi_rmem19_ARCACHE,
+  m_axi_rmem19_ARID,
+  m_axi_rmem19_ARLEN,
+  m_axi_rmem19_ARLOCK,
+  m_axi_rmem19_ARPROT,
+  m_axi_rmem19_ARQOS,
+  m_axi_rmem19_ARREADY,
+  m_axi_rmem19_ARSIZE,
+  m_axi_rmem19_ARVALID,
+  m_axi_rmem19_AWADDR,
+  m_axi_rmem19_AWBURST,
+  m_axi_rmem19_AWCACHE,
+  m_axi_rmem19_AWID,
+  m_axi_rmem19_AWLEN,
+  m_axi_rmem19_AWLOCK,
+  m_axi_rmem19_AWPROT,
+  m_axi_rmem19_AWQOS,
+  m_axi_rmem19_AWREADY,
+  m_axi_rmem19_AWSIZE,
+  m_axi_rmem19_AWVALID,
+  m_axi_rmem19_BID,
+  m_axi_rmem19_BREADY,
+  m_axi_rmem19_BRESP,
+  m_axi_rmem19_BVALID,
+  m_axi_rmem19_RDATA,
+  m_axi_rmem19_RID,
+  m_axi_rmem19_RLAST,
+  m_axi_rmem19_RREADY,
+  m_axi_rmem19_RRESP,
+  m_axi_rmem19_RVALID,
+  m_axi_rmem19_WDATA,
+  m_axi_rmem19_WLAST,
+  m_axi_rmem19_WREADY,
+  m_axi_rmem19_WSTRB,
+  m_axi_rmem19_WVALID,
+  m_axi_rmem20_ARADDR,
+  m_axi_rmem20_ARBURST,
+  m_axi_rmem20_ARCACHE,
+  m_axi_rmem20_ARID,
+  m_axi_rmem20_ARLEN,
+  m_axi_rmem20_ARLOCK,
+  m_axi_rmem20_ARPROT,
+  m_axi_rmem20_ARQOS,
+  m_axi_rmem20_ARREADY,
+  m_axi_rmem20_ARSIZE,
+  m_axi_rmem20_ARVALID,
+  m_axi_rmem20_AWADDR,
+  m_axi_rmem20_AWBURST,
+  m_axi_rmem20_AWCACHE,
+  m_axi_rmem20_AWID,
+  m_axi_rmem20_AWLEN,
+  m_axi_rmem20_AWLOCK,
+  m_axi_rmem20_AWPROT,
+  m_axi_rmem20_AWQOS,
+  m_axi_rmem20_AWREADY,
+  m_axi_rmem20_AWSIZE,
+  m_axi_rmem20_AWVALID,
+  m_axi_rmem20_BID,
+  m_axi_rmem20_BREADY,
+  m_axi_rmem20_BRESP,
+  m_axi_rmem20_BVALID,
+  m_axi_rmem20_RDATA,
+  m_axi_rmem20_RID,
+  m_axi_rmem20_RLAST,
+  m_axi_rmem20_RREADY,
+  m_axi_rmem20_RRESP,
+  m_axi_rmem20_RVALID,
+  m_axi_rmem20_WDATA,
+  m_axi_rmem20_WLAST,
+  m_axi_rmem20_WREADY,
+  m_axi_rmem20_WSTRB,
+  m_axi_rmem20_WVALID,
+  m_axi_rmem21_ARADDR,
+  m_axi_rmem21_ARBURST,
+  m_axi_rmem21_ARCACHE,
+  m_axi_rmem21_ARID,
+  m_axi_rmem21_ARLEN,
+  m_axi_rmem21_ARLOCK,
+  m_axi_rmem21_ARPROT,
+  m_axi_rmem21_ARQOS,
+  m_axi_rmem21_ARREADY,
+  m_axi_rmem21_ARSIZE,
+  m_axi_rmem21_ARVALID,
+  m_axi_rmem21_AWADDR,
+  m_axi_rmem21_AWBURST,
+  m_axi_rmem21_AWCACHE,
+  m_axi_rmem21_AWID,
+  m_axi_rmem21_AWLEN,
+  m_axi_rmem21_AWLOCK,
+  m_axi_rmem21_AWPROT,
+  m_axi_rmem21_AWQOS,
+  m_axi_rmem21_AWREADY,
+  m_axi_rmem21_AWSIZE,
+  m_axi_rmem21_AWVALID,
+  m_axi_rmem21_BID,
+  m_axi_rmem21_BREADY,
+  m_axi_rmem21_BRESP,
+  m_axi_rmem21_BVALID,
+  m_axi_rmem21_RDATA,
+  m_axi_rmem21_RID,
+  m_axi_rmem21_RLAST,
+  m_axi_rmem21_RREADY,
+  m_axi_rmem21_RRESP,
+  m_axi_rmem21_RVALID,
+  m_axi_rmem21_WDATA,
+  m_axi_rmem21_WLAST,
+  m_axi_rmem21_WREADY,
+  m_axi_rmem21_WSTRB,
+  m_axi_rmem21_WVALID,
+  m_axi_rmem22_ARADDR,
+  m_axi_rmem22_ARBURST,
+  m_axi_rmem22_ARCACHE,
+  m_axi_rmem22_ARID,
+  m_axi_rmem22_ARLEN,
+  m_axi_rmem22_ARLOCK,
+  m_axi_rmem22_ARPROT,
+  m_axi_rmem22_ARQOS,
+  m_axi_rmem22_ARREADY,
+  m_axi_rmem22_ARSIZE,
+  m_axi_rmem22_ARVALID,
+  m_axi_rmem22_AWADDR,
+  m_axi_rmem22_AWBURST,
+  m_axi_rmem22_AWCACHE,
+  m_axi_rmem22_AWID,
+  m_axi_rmem22_AWLEN,
+  m_axi_rmem22_AWLOCK,
+  m_axi_rmem22_AWPROT,
+  m_axi_rmem22_AWQOS,
+  m_axi_rmem22_AWREADY,
+  m_axi_rmem22_AWSIZE,
+  m_axi_rmem22_AWVALID,
+  m_axi_rmem22_BID,
+  m_axi_rmem22_BREADY,
+  m_axi_rmem22_BRESP,
+  m_axi_rmem22_BVALID,
+  m_axi_rmem22_RDATA,
+  m_axi_rmem22_RID,
+  m_axi_rmem22_RLAST,
+  m_axi_rmem22_RREADY,
+  m_axi_rmem22_RRESP,
+  m_axi_rmem22_RVALID,
+  m_axi_rmem22_WDATA,
+  m_axi_rmem22_WLAST,
+  m_axi_rmem22_WREADY,
+  m_axi_rmem22_WSTRB,
+  m_axi_rmem22_WVALID,
+  m_axi_rmem23_ARADDR,
+  m_axi_rmem23_ARBURST,
+  m_axi_rmem23_ARCACHE,
+  m_axi_rmem23_ARID,
+  m_axi_rmem23_ARLEN,
+  m_axi_rmem23_ARLOCK,
+  m_axi_rmem23_ARPROT,
+  m_axi_rmem23_ARQOS,
+  m_axi_rmem23_ARREADY,
+  m_axi_rmem23_ARSIZE,
+  m_axi_rmem23_ARVALID,
+  m_axi_rmem23_AWADDR,
+  m_axi_rmem23_AWBURST,
+  m_axi_rmem23_AWCACHE,
+  m_axi_rmem23_AWID,
+  m_axi_rmem23_AWLEN,
+  m_axi_rmem23_AWLOCK,
+  m_axi_rmem23_AWPROT,
+  m_axi_rmem23_AWQOS,
+  m_axi_rmem23_AWREADY,
+  m_axi_rmem23_AWSIZE,
+  m_axi_rmem23_AWVALID,
+  m_axi_rmem23_BID,
+  m_axi_rmem23_BREADY,
+  m_axi_rmem23_BRESP,
+  m_axi_rmem23_BVALID,
+  m_axi_rmem23_RDATA,
+  m_axi_rmem23_RID,
+  m_axi_rmem23_RLAST,
+  m_axi_rmem23_RREADY,
+  m_axi_rmem23_RRESP,
+  m_axi_rmem23_RVALID,
+  m_axi_rmem23_WDATA,
+  m_axi_rmem23_WLAST,
+  m_axi_rmem23_WREADY,
+  m_axi_rmem23_WSTRB,
+  m_axi_rmem23_WVALID,
+  m_axi_rmem24_ARADDR,
+  m_axi_rmem24_ARBURST,
+  m_axi_rmem24_ARCACHE,
+  m_axi_rmem24_ARID,
+  m_axi_rmem24_ARLEN,
+  m_axi_rmem24_ARLOCK,
+  m_axi_rmem24_ARPROT,
+  m_axi_rmem24_ARQOS,
+  m_axi_rmem24_ARREADY,
+  m_axi_rmem24_ARSIZE,
+  m_axi_rmem24_ARVALID,
+  m_axi_rmem24_AWADDR,
+  m_axi_rmem24_AWBURST,
+  m_axi_rmem24_AWCACHE,
+  m_axi_rmem24_AWID,
+  m_axi_rmem24_AWLEN,
+  m_axi_rmem24_AWLOCK,
+  m_axi_rmem24_AWPROT,
+  m_axi_rmem24_AWQOS,
+  m_axi_rmem24_AWREADY,
+  m_axi_rmem24_AWSIZE,
+  m_axi_rmem24_AWVALID,
+  m_axi_rmem24_BID,
+  m_axi_rmem24_BREADY,
+  m_axi_rmem24_BRESP,
+  m_axi_rmem24_BVALID,
+  m_axi_rmem24_RDATA,
+  m_axi_rmem24_RID,
+  m_axi_rmem24_RLAST,
+  m_axi_rmem24_RREADY,
+  m_axi_rmem24_RRESP,
+  m_axi_rmem24_RVALID,
+  m_axi_rmem24_WDATA,
+  m_axi_rmem24_WLAST,
+  m_axi_rmem24_WREADY,
+  m_axi_rmem24_WSTRB,
+  m_axi_rmem24_WVALID,
+  m_axi_rmem25_ARADDR,
+  m_axi_rmem25_ARBURST,
+  m_axi_rmem25_ARCACHE,
+  m_axi_rmem25_ARID,
+  m_axi_rmem25_ARLEN,
+  m_axi_rmem25_ARLOCK,
+  m_axi_rmem25_ARPROT,
+  m_axi_rmem25_ARQOS,
+  m_axi_rmem25_ARREADY,
+  m_axi_rmem25_ARSIZE,
+  m_axi_rmem25_ARVALID,
+  m_axi_rmem25_AWADDR,
+  m_axi_rmem25_AWBURST,
+  m_axi_rmem25_AWCACHE,
+  m_axi_rmem25_AWID,
+  m_axi_rmem25_AWLEN,
+  m_axi_rmem25_AWLOCK,
+  m_axi_rmem25_AWPROT,
+  m_axi_rmem25_AWQOS,
+  m_axi_rmem25_AWREADY,
+  m_axi_rmem25_AWSIZE,
+  m_axi_rmem25_AWVALID,
+  m_axi_rmem25_BID,
+  m_axi_rmem25_BREADY,
+  m_axi_rmem25_BRESP,
+  m_axi_rmem25_BVALID,
+  m_axi_rmem25_RDATA,
+  m_axi_rmem25_RID,
+  m_axi_rmem25_RLAST,
+  m_axi_rmem25_RREADY,
+  m_axi_rmem25_RRESP,
+  m_axi_rmem25_RVALID,
+  m_axi_rmem25_WDATA,
+  m_axi_rmem25_WLAST,
+  m_axi_rmem25_WREADY,
+  m_axi_rmem25_WSTRB,
+  m_axi_rmem25_WVALID,
+  m_axi_rmem26_ARADDR,
+  m_axi_rmem26_ARBURST,
+  m_axi_rmem26_ARCACHE,
+  m_axi_rmem26_ARID,
+  m_axi_rmem26_ARLEN,
+  m_axi_rmem26_ARLOCK,
+  m_axi_rmem26_ARPROT,
+  m_axi_rmem26_ARQOS,
+  m_axi_rmem26_ARREADY,
+  m_axi_rmem26_ARSIZE,
+  m_axi_rmem26_ARVALID,
+  m_axi_rmem26_AWADDR,
+  m_axi_rmem26_AWBURST,
+  m_axi_rmem26_AWCACHE,
+  m_axi_rmem26_AWID,
+  m_axi_rmem26_AWLEN,
+  m_axi_rmem26_AWLOCK,
+  m_axi_rmem26_AWPROT,
+  m_axi_rmem26_AWQOS,
+  m_axi_rmem26_AWREADY,
+  m_axi_rmem26_AWSIZE,
+  m_axi_rmem26_AWVALID,
+  m_axi_rmem26_BID,
+  m_axi_rmem26_BREADY,
+  m_axi_rmem26_BRESP,
+  m_axi_rmem26_BVALID,
+  m_axi_rmem26_RDATA,
+  m_axi_rmem26_RID,
+  m_axi_rmem26_RLAST,
+  m_axi_rmem26_RREADY,
+  m_axi_rmem26_RRESP,
+  m_axi_rmem26_RVALID,
+  m_axi_rmem26_WDATA,
+  m_axi_rmem26_WLAST,
+  m_axi_rmem26_WREADY,
+  m_axi_rmem26_WSTRB,
+  m_axi_rmem26_WVALID,
+  m_axi_rmem27_ARADDR,
+  m_axi_rmem27_ARBURST,
+  m_axi_rmem27_ARCACHE,
+  m_axi_rmem27_ARID,
+  m_axi_rmem27_ARLEN,
+  m_axi_rmem27_ARLOCK,
+  m_axi_rmem27_ARPROT,
+  m_axi_rmem27_ARQOS,
+  m_axi_rmem27_ARREADY,
+  m_axi_rmem27_ARSIZE,
+  m_axi_rmem27_ARVALID,
+  m_axi_rmem27_AWADDR,
+  m_axi_rmem27_AWBURST,
+  m_axi_rmem27_AWCACHE,
+  m_axi_rmem27_AWID,
+  m_axi_rmem27_AWLEN,
+  m_axi_rmem27_AWLOCK,
+  m_axi_rmem27_AWPROT,
+  m_axi_rmem27_AWQOS,
+  m_axi_rmem27_AWREADY,
+  m_axi_rmem27_AWSIZE,
+  m_axi_rmem27_AWVALID,
+  m_axi_rmem27_BID,
+  m_axi_rmem27_BREADY,
+  m_axi_rmem27_BRESP,
+  m_axi_rmem27_BVALID,
+  m_axi_rmem27_RDATA,
+  m_axi_rmem27_RID,
+  m_axi_rmem27_RLAST,
+  m_axi_rmem27_RREADY,
+  m_axi_rmem27_RRESP,
+  m_axi_rmem27_RVALID,
+  m_axi_rmem27_WDATA,
+  m_axi_rmem27_WLAST,
+  m_axi_rmem27_WREADY,
+  m_axi_rmem27_WSTRB,
+  m_axi_rmem27_WVALID
+);
+
+  parameter C_S_AXI_CONTROL_DATA_WIDTH = 32;
+  parameter C_S_AXI_CONTROL_ADDR_WIDTH = 9;
+  parameter C_S_AXI_DATA_WIDTH = 32;
+  parameter C_S_AXI_CONTROL_WSTRB_WIDTH = 32 / 8;
+  parameter C_S_AXI_WSTRB_WIDTH = 32 / 8;
+  (* RS_HS = "s_axi_control_AW.valid" *)input s_axi_control_AWVALID;
+  (* RS_HS = "s_axi_control_AW.ready" *)output s_axi_control_AWREADY;
+  (* RS_HS = "s_axi_control_AW.data" *)input [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR;
+  (* RS_HS = "s_axi_control_W.valid" *)input s_axi_control_WVALID;
+  (* RS_HS = "s_axi_control_W.ready" *)output s_axi_control_WREADY;
+  (* RS_HS = "s_axi_control_W.data" *)input [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA;
+  (* RS_HS = "s_axi_control_W.data" *)input [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB;
+  (* RS_HS = "s_axi_control_AR.valid" *)input s_axi_control_ARVALID;
+  (* RS_HS = "s_axi_control_AR.ready" *)output s_axi_control_ARREADY;
+  (* RS_HS = "s_axi_control_AR.data" *)input [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_ARADDR;
+  (* RS_HS = "s_axi_control_R.valid" *)output s_axi_control_RVALID;
+  (* RS_HS = "s_axi_control_R.ready" *)input s_axi_control_RREADY;
+  (* RS_HS = "s_axi_control_R.data" *)output [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_RDATA;
+  (* RS_HS = "s_axi_control_R.data" *)output [1:0] s_axi_control_RRESP;
+  (* RS_HS = "s_axi_control_B.valid" *)output s_axi_control_BVALID;
+  (* RS_HS = "s_axi_control_B.ready" *)input s_axi_control_BREADY;
+  (* RS_HS = "s_axi_control_B.data" *)output [1:0] s_axi_control_BRESP;
+  (* RS_CLK *)input ap_clk;
+  (* RS_RST = "ff" *)input ap_rst_n;
+  (* RS_FF = "interrupt" *)output interrupt;
+  (* RS_HS = "m_axi_rmem0_AR.data" *)output [63:0] m_axi_rmem0_ARADDR;
+  (* RS_HS = "m_axi_rmem0_AR.data" *)output [1:0] m_axi_rmem0_ARBURST;
+  (* RS_HS = "m_axi_rmem0_AR.data" *)output [3:0] m_axi_rmem0_ARCACHE;
+  (* RS_HS = "m_axi_rmem0_AR.data" *)output [1:0] m_axi_rmem0_ARID;
+  (* RS_HS = "m_axi_rmem0_AR.data" *)output [7:0] m_axi_rmem0_ARLEN;
+  (* RS_HS = "m_axi_rmem0_AR.data" *)output m_axi_rmem0_ARLOCK;
+  (* RS_HS = "m_axi_rmem0_AR.data" *)output [2:0] m_axi_rmem0_ARPROT;
+  (* RS_HS = "m_axi_rmem0_AR.data" *)output [3:0] m_axi_rmem0_ARQOS;
+  (* RS_HS = "m_axi_rmem0_AR.ready" *)input m_axi_rmem0_ARREADY;
+  (* RS_HS = "m_axi_rmem0_AR.data" *)output [2:0] m_axi_rmem0_ARSIZE;
+  (* RS_HS = "m_axi_rmem0_AR.valid" *)output m_axi_rmem0_ARVALID;
+  (* RS_HS = "m_axi_rmem0_AW.data" *)output [63:0] m_axi_rmem0_AWADDR;
+  (* RS_HS = "m_axi_rmem0_AW.data" *)output [1:0] m_axi_rmem0_AWBURST;
+  (* RS_HS = "m_axi_rmem0_AW.data" *)output [3:0] m_axi_rmem0_AWCACHE;
+  (* RS_HS = "m_axi_rmem0_AW.data" *)output [1:0] m_axi_rmem0_AWID;
+  (* RS_HS = "m_axi_rmem0_AW.data" *)output [7:0] m_axi_rmem0_AWLEN;
+  (* RS_HS = "m_axi_rmem0_AW.data" *)output m_axi_rmem0_AWLOCK;
+  (* RS_HS = "m_axi_rmem0_AW.data" *)output [2:0] m_axi_rmem0_AWPROT;
+  (* RS_HS = "m_axi_rmem0_AW.data" *)output [3:0] m_axi_rmem0_AWQOS;
+  (* RS_HS = "m_axi_rmem0_AW.ready" *)input m_axi_rmem0_AWREADY;
+  (* RS_HS = "m_axi_rmem0_AW.data" *)output [2:0] m_axi_rmem0_AWSIZE;
+  (* RS_HS = "m_axi_rmem0_AW.valid" *)output m_axi_rmem0_AWVALID;
+  (* RS_HS = "m_axi_rmem0_B.data" *)input [1:0] m_axi_rmem0_BID;
+  (* RS_HS = "m_axi_rmem0_B.ready" *)output m_axi_rmem0_BREADY;
+  (* RS_HS = "m_axi_rmem0_B.data" *)input [1:0] m_axi_rmem0_BRESP;
+  (* RS_HS = "m_axi_rmem0_B.valid" *)input m_axi_rmem0_BVALID;
+  (* RS_HS = "m_axi_rmem0_R.data" *)input [511:0] m_axi_rmem0_RDATA;
+  (* RS_HS = "m_axi_rmem0_R.data" *)input [1:0] m_axi_rmem0_RID;
+  (* RS_HS = "m_axi_rmem0_R.data" *)input m_axi_rmem0_RLAST;
+  (* RS_HS = "m_axi_rmem0_R.ready" *)output m_axi_rmem0_RREADY;
+  (* RS_HS = "m_axi_rmem0_R.data" *)input [1:0] m_axi_rmem0_RRESP;
+  (* RS_HS = "m_axi_rmem0_R.valid" *)input m_axi_rmem0_RVALID;
+  (* RS_HS = "m_axi_rmem0_W.data" *)output [511:0] m_axi_rmem0_WDATA;
+  (* RS_HS = "m_axi_rmem0_W.data" *)output m_axi_rmem0_WLAST;
+  (* RS_HS = "m_axi_rmem0_W.ready" *)input m_axi_rmem0_WREADY;
+  (* RS_HS = "m_axi_rmem0_W.data" *)output [63:0] m_axi_rmem0_WSTRB;
+  (* RS_HS = "m_axi_rmem0_W.valid" *)output m_axi_rmem0_WVALID;
+  (* RS_HS = "m_axi_rmem1_AR.data" *)output [63:0] m_axi_rmem1_ARADDR;
+  (* RS_HS = "m_axi_rmem1_AR.data" *)output [1:0] m_axi_rmem1_ARBURST;
+  (* RS_HS = "m_axi_rmem1_AR.data" *)output [3:0] m_axi_rmem1_ARCACHE;
+  (* RS_HS = "m_axi_rmem1_AR.data" *)output [1:0] m_axi_rmem1_ARID;
+  (* RS_HS = "m_axi_rmem1_AR.data" *)output [7:0] m_axi_rmem1_ARLEN;
+  (* RS_HS = "m_axi_rmem1_AR.data" *)output m_axi_rmem1_ARLOCK;
+  (* RS_HS = "m_axi_rmem1_AR.data" *)output [2:0] m_axi_rmem1_ARPROT;
+  (* RS_HS = "m_axi_rmem1_AR.data" *)output [3:0] m_axi_rmem1_ARQOS;
+  (* RS_HS = "m_axi_rmem1_AR.ready" *)input m_axi_rmem1_ARREADY;
+  (* RS_HS = "m_axi_rmem1_AR.data" *)output [2:0] m_axi_rmem1_ARSIZE;
+  (* RS_HS = "m_axi_rmem1_AR.valid" *)output m_axi_rmem1_ARVALID;
+  (* RS_HS = "m_axi_rmem1_AW.data" *)output [63:0] m_axi_rmem1_AWADDR;
+  (* RS_HS = "m_axi_rmem1_AW.data" *)output [1:0] m_axi_rmem1_AWBURST;
+  (* RS_HS = "m_axi_rmem1_AW.data" *)output [3:0] m_axi_rmem1_AWCACHE;
+  (* RS_HS = "m_axi_rmem1_AW.data" *)output [1:0] m_axi_rmem1_AWID;
+  (* RS_HS = "m_axi_rmem1_AW.data" *)output [7:0] m_axi_rmem1_AWLEN;
+  (* RS_HS = "m_axi_rmem1_AW.data" *)output m_axi_rmem1_AWLOCK;
+  (* RS_HS = "m_axi_rmem1_AW.data" *)output [2:0] m_axi_rmem1_AWPROT;
+  (* RS_HS = "m_axi_rmem1_AW.data" *)output [3:0] m_axi_rmem1_AWQOS;
+  (* RS_HS = "m_axi_rmem1_AW.ready" *)input m_axi_rmem1_AWREADY;
+  (* RS_HS = "m_axi_rmem1_AW.data" *)output [2:0] m_axi_rmem1_AWSIZE;
+  (* RS_HS = "m_axi_rmem1_AW.valid" *)output m_axi_rmem1_AWVALID;
+  (* RS_HS = "m_axi_rmem1_B.data" *)input [1:0] m_axi_rmem1_BID;
+  (* RS_HS = "m_axi_rmem1_B.ready" *)output m_axi_rmem1_BREADY;
+  (* RS_HS = "m_axi_rmem1_B.data" *)input [1:0] m_axi_rmem1_BRESP;
+  (* RS_HS = "m_axi_rmem1_B.valid" *)input m_axi_rmem1_BVALID;
+  (* RS_HS = "m_axi_rmem1_R.data" *)input [511:0] m_axi_rmem1_RDATA;
+  (* RS_HS = "m_axi_rmem1_R.data" *)input [1:0] m_axi_rmem1_RID;
+  (* RS_HS = "m_axi_rmem1_R.data" *)input m_axi_rmem1_RLAST;
+  (* RS_HS = "m_axi_rmem1_R.ready" *)output m_axi_rmem1_RREADY;
+  (* RS_HS = "m_axi_rmem1_R.data" *)input [1:0] m_axi_rmem1_RRESP;
+  (* RS_HS = "m_axi_rmem1_R.valid" *)input m_axi_rmem1_RVALID;
+  (* RS_HS = "m_axi_rmem1_W.data" *)output [511:0] m_axi_rmem1_WDATA;
+  (* RS_HS = "m_axi_rmem1_W.data" *)output m_axi_rmem1_WLAST;
+  (* RS_HS = "m_axi_rmem1_W.ready" *)input m_axi_rmem1_WREADY;
+  (* RS_HS = "m_axi_rmem1_W.data" *)output [63:0] m_axi_rmem1_WSTRB;
+  (* RS_HS = "m_axi_rmem1_W.valid" *)output m_axi_rmem1_WVALID;
+  (* RS_HS = "m_axi_rmem2_AR.data" *)output [63:0] m_axi_rmem2_ARADDR;
+  (* RS_HS = "m_axi_rmem2_AR.data" *)output [1:0] m_axi_rmem2_ARBURST;
+  (* RS_HS = "m_axi_rmem2_AR.data" *)output [3:0] m_axi_rmem2_ARCACHE;
+  (* RS_HS = "m_axi_rmem2_AR.data" *)output [1:0] m_axi_rmem2_ARID;
+  (* RS_HS = "m_axi_rmem2_AR.data" *)output [7:0] m_axi_rmem2_ARLEN;
+  (* RS_HS = "m_axi_rmem2_AR.data" *)output m_axi_rmem2_ARLOCK;
+  (* RS_HS = "m_axi_rmem2_AR.data" *)output [2:0] m_axi_rmem2_ARPROT;
+  (* RS_HS = "m_axi_rmem2_AR.data" *)output [3:0] m_axi_rmem2_ARQOS;
+  (* RS_HS = "m_axi_rmem2_AR.ready" *)input m_axi_rmem2_ARREADY;
+  (* RS_HS = "m_axi_rmem2_AR.data" *)output [2:0] m_axi_rmem2_ARSIZE;
+  (* RS_HS = "m_axi_rmem2_AR.valid" *)output m_axi_rmem2_ARVALID;
+  (* RS_HS = "m_axi_rmem2_AW.data" *)output [63:0] m_axi_rmem2_AWADDR;
+  (* RS_HS = "m_axi_rmem2_AW.data" *)output [1:0] m_axi_rmem2_AWBURST;
+  (* RS_HS = "m_axi_rmem2_AW.data" *)output [3:0] m_axi_rmem2_AWCACHE;
+  (* RS_HS = "m_axi_rmem2_AW.data" *)output [1:0] m_axi_rmem2_AWID;
+  (* RS_HS = "m_axi_rmem2_AW.data" *)output [7:0] m_axi_rmem2_AWLEN;
+  (* RS_HS = "m_axi_rmem2_AW.data" *)output m_axi_rmem2_AWLOCK;
+  (* RS_HS = "m_axi_rmem2_AW.data" *)output [2:0] m_axi_rmem2_AWPROT;
+  (* RS_HS = "m_axi_rmem2_AW.data" *)output [3:0] m_axi_rmem2_AWQOS;
+  (* RS_HS = "m_axi_rmem2_AW.ready" *)input m_axi_rmem2_AWREADY;
+  (* RS_HS = "m_axi_rmem2_AW.data" *)output [2:0] m_axi_rmem2_AWSIZE;
+  (* RS_HS = "m_axi_rmem2_AW.valid" *)output m_axi_rmem2_AWVALID;
+  (* RS_HS = "m_axi_rmem2_B.data" *)input [1:0] m_axi_rmem2_BID;
+  (* RS_HS = "m_axi_rmem2_B.ready" *)output m_axi_rmem2_BREADY;
+  (* RS_HS = "m_axi_rmem2_B.data" *)input [1:0] m_axi_rmem2_BRESP;
+  (* RS_HS = "m_axi_rmem2_B.valid" *)input m_axi_rmem2_BVALID;
+  (* RS_HS = "m_axi_rmem2_R.data" *)input [511:0] m_axi_rmem2_RDATA;
+  (* RS_HS = "m_axi_rmem2_R.data" *)input [1:0] m_axi_rmem2_RID;
+  (* RS_HS = "m_axi_rmem2_R.data" *)input m_axi_rmem2_RLAST;
+  (* RS_HS = "m_axi_rmem2_R.ready" *)output m_axi_rmem2_RREADY;
+  (* RS_HS = "m_axi_rmem2_R.data" *)input [1:0] m_axi_rmem2_RRESP;
+  (* RS_HS = "m_axi_rmem2_R.valid" *)input m_axi_rmem2_RVALID;
+  (* RS_HS = "m_axi_rmem2_W.data" *)output [511:0] m_axi_rmem2_WDATA;
+  (* RS_HS = "m_axi_rmem2_W.data" *)output m_axi_rmem2_WLAST;
+  (* RS_HS = "m_axi_rmem2_W.ready" *)input m_axi_rmem2_WREADY;
+  (* RS_HS = "m_axi_rmem2_W.data" *)output [63:0] m_axi_rmem2_WSTRB;
+  (* RS_HS = "m_axi_rmem2_W.valid" *)output m_axi_rmem2_WVALID;
+  (* RS_HS = "m_axi_rmem3_AR.data" *)output [63:0] m_axi_rmem3_ARADDR;
+  (* RS_HS = "m_axi_rmem3_AR.data" *)output [1:0] m_axi_rmem3_ARBURST;
+  (* RS_HS = "m_axi_rmem3_AR.data" *)output [3:0] m_axi_rmem3_ARCACHE;
+  (* RS_HS = "m_axi_rmem3_AR.data" *)output [1:0] m_axi_rmem3_ARID;
+  (* RS_HS = "m_axi_rmem3_AR.data" *)output [7:0] m_axi_rmem3_ARLEN;
+  (* RS_HS = "m_axi_rmem3_AR.data" *)output m_axi_rmem3_ARLOCK;
+  (* RS_HS = "m_axi_rmem3_AR.data" *)output [2:0] m_axi_rmem3_ARPROT;
+  (* RS_HS = "m_axi_rmem3_AR.data" *)output [3:0] m_axi_rmem3_ARQOS;
+  (* RS_HS = "m_axi_rmem3_AR.ready" *)input m_axi_rmem3_ARREADY;
+  (* RS_HS = "m_axi_rmem3_AR.data" *)output [2:0] m_axi_rmem3_ARSIZE;
+  (* RS_HS = "m_axi_rmem3_AR.valid" *)output m_axi_rmem3_ARVALID;
+  (* RS_HS = "m_axi_rmem3_AW.data" *)output [63:0] m_axi_rmem3_AWADDR;
+  (* RS_HS = "m_axi_rmem3_AW.data" *)output [1:0] m_axi_rmem3_AWBURST;
+  (* RS_HS = "m_axi_rmem3_AW.data" *)output [3:0] m_axi_rmem3_AWCACHE;
+  (* RS_HS = "m_axi_rmem3_AW.data" *)output [1:0] m_axi_rmem3_AWID;
+  (* RS_HS = "m_axi_rmem3_AW.data" *)output [7:0] m_axi_rmem3_AWLEN;
+  (* RS_HS = "m_axi_rmem3_AW.data" *)output m_axi_rmem3_AWLOCK;
+  (* RS_HS = "m_axi_rmem3_AW.data" *)output [2:0] m_axi_rmem3_AWPROT;
+  (* RS_HS = "m_axi_rmem3_AW.data" *)output [3:0] m_axi_rmem3_AWQOS;
+  (* RS_HS = "m_axi_rmem3_AW.ready" *)input m_axi_rmem3_AWREADY;
+  (* RS_HS = "m_axi_rmem3_AW.data" *)output [2:0] m_axi_rmem3_AWSIZE;
+  (* RS_HS = "m_axi_rmem3_AW.valid" *)output m_axi_rmem3_AWVALID;
+  (* RS_HS = "m_axi_rmem3_B.data" *)input [1:0] m_axi_rmem3_BID;
+  (* RS_HS = "m_axi_rmem3_B.ready" *)output m_axi_rmem3_BREADY;
+  (* RS_HS = "m_axi_rmem3_B.data" *)input [1:0] m_axi_rmem3_BRESP;
+  (* RS_HS = "m_axi_rmem3_B.valid" *)input m_axi_rmem3_BVALID;
+  (* RS_HS = "m_axi_rmem3_R.data" *)input [511:0] m_axi_rmem3_RDATA;
+  (* RS_HS = "m_axi_rmem3_R.data" *)input [1:0] m_axi_rmem3_RID;
+  (* RS_HS = "m_axi_rmem3_R.data" *)input m_axi_rmem3_RLAST;
+  (* RS_HS = "m_axi_rmem3_R.ready" *)output m_axi_rmem3_RREADY;
+  (* RS_HS = "m_axi_rmem3_R.data" *)input [1:0] m_axi_rmem3_RRESP;
+  (* RS_HS = "m_axi_rmem3_R.valid" *)input m_axi_rmem3_RVALID;
+  (* RS_HS = "m_axi_rmem3_W.data" *)output [511:0] m_axi_rmem3_WDATA;
+  (* RS_HS = "m_axi_rmem3_W.data" *)output m_axi_rmem3_WLAST;
+  (* RS_HS = "m_axi_rmem3_W.ready" *)input m_axi_rmem3_WREADY;
+  (* RS_HS = "m_axi_rmem3_W.data" *)output [63:0] m_axi_rmem3_WSTRB;
+  (* RS_HS = "m_axi_rmem3_W.valid" *)output m_axi_rmem3_WVALID;
+  (* RS_HS = "m_axi_rmem4_AR.data" *)output [63:0] m_axi_rmem4_ARADDR;
+  (* RS_HS = "m_axi_rmem4_AR.data" *)output [1:0] m_axi_rmem4_ARBURST;
+  (* RS_HS = "m_axi_rmem4_AR.data" *)output [3:0] m_axi_rmem4_ARCACHE;
+  (* RS_HS = "m_axi_rmem4_AR.data" *)output [1:0] m_axi_rmem4_ARID;
+  (* RS_HS = "m_axi_rmem4_AR.data" *)output [7:0] m_axi_rmem4_ARLEN;
+  (* RS_HS = "m_axi_rmem4_AR.data" *)output m_axi_rmem4_ARLOCK;
+  (* RS_HS = "m_axi_rmem4_AR.data" *)output [2:0] m_axi_rmem4_ARPROT;
+  (* RS_HS = "m_axi_rmem4_AR.data" *)output [3:0] m_axi_rmem4_ARQOS;
+  (* RS_HS = "m_axi_rmem4_AR.ready" *)input m_axi_rmem4_ARREADY;
+  (* RS_HS = "m_axi_rmem4_AR.data" *)output [2:0] m_axi_rmem4_ARSIZE;
+  (* RS_HS = "m_axi_rmem4_AR.valid" *)output m_axi_rmem4_ARVALID;
+  (* RS_HS = "m_axi_rmem4_AW.data" *)output [63:0] m_axi_rmem4_AWADDR;
+  (* RS_HS = "m_axi_rmem4_AW.data" *)output [1:0] m_axi_rmem4_AWBURST;
+  (* RS_HS = "m_axi_rmem4_AW.data" *)output [3:0] m_axi_rmem4_AWCACHE;
+  (* RS_HS = "m_axi_rmem4_AW.data" *)output [1:0] m_axi_rmem4_AWID;
+  (* RS_HS = "m_axi_rmem4_AW.data" *)output [7:0] m_axi_rmem4_AWLEN;
+  (* RS_HS = "m_axi_rmem4_AW.data" *)output m_axi_rmem4_AWLOCK;
+  (* RS_HS = "m_axi_rmem4_AW.data" *)output [2:0] m_axi_rmem4_AWPROT;
+  (* RS_HS = "m_axi_rmem4_AW.data" *)output [3:0] m_axi_rmem4_AWQOS;
+  (* RS_HS = "m_axi_rmem4_AW.ready" *)input m_axi_rmem4_AWREADY;
+  (* RS_HS = "m_axi_rmem4_AW.data" *)output [2:0] m_axi_rmem4_AWSIZE;
+  (* RS_HS = "m_axi_rmem4_AW.valid" *)output m_axi_rmem4_AWVALID;
+  (* RS_HS = "m_axi_rmem4_B.data" *)input [1:0] m_axi_rmem4_BID;
+  (* RS_HS = "m_axi_rmem4_B.ready" *)output m_axi_rmem4_BREADY;
+  (* RS_HS = "m_axi_rmem4_B.data" *)input [1:0] m_axi_rmem4_BRESP;
+  (* RS_HS = "m_axi_rmem4_B.valid" *)input m_axi_rmem4_BVALID;
+  (* RS_HS = "m_axi_rmem4_R.data" *)input [511:0] m_axi_rmem4_RDATA;
+  (* RS_HS = "m_axi_rmem4_R.data" *)input [1:0] m_axi_rmem4_RID;
+  (* RS_HS = "m_axi_rmem4_R.data" *)input m_axi_rmem4_RLAST;
+  (* RS_HS = "m_axi_rmem4_R.ready" *)output m_axi_rmem4_RREADY;
+  (* RS_HS = "m_axi_rmem4_R.data" *)input [1:0] m_axi_rmem4_RRESP;
+  (* RS_HS = "m_axi_rmem4_R.valid" *)input m_axi_rmem4_RVALID;
+  (* RS_HS = "m_axi_rmem4_W.data" *)output [511:0] m_axi_rmem4_WDATA;
+  (* RS_HS = "m_axi_rmem4_W.data" *)output m_axi_rmem4_WLAST;
+  (* RS_HS = "m_axi_rmem4_W.ready" *)input m_axi_rmem4_WREADY;
+  (* RS_HS = "m_axi_rmem4_W.data" *)output [63:0] m_axi_rmem4_WSTRB;
+  (* RS_HS = "m_axi_rmem4_W.valid" *)output m_axi_rmem4_WVALID;
+  (* RS_HS = "m_axi_rmem5_AR.data" *)output [63:0] m_axi_rmem5_ARADDR;
+  (* RS_HS = "m_axi_rmem5_AR.data" *)output [1:0] m_axi_rmem5_ARBURST;
+  (* RS_HS = "m_axi_rmem5_AR.data" *)output [3:0] m_axi_rmem5_ARCACHE;
+  (* RS_HS = "m_axi_rmem5_AR.data" *)output [1:0] m_axi_rmem5_ARID;
+  (* RS_HS = "m_axi_rmem5_AR.data" *)output [7:0] m_axi_rmem5_ARLEN;
+  (* RS_HS = "m_axi_rmem5_AR.data" *)output m_axi_rmem5_ARLOCK;
+  (* RS_HS = "m_axi_rmem5_AR.data" *)output [2:0] m_axi_rmem5_ARPROT;
+  (* RS_HS = "m_axi_rmem5_AR.data" *)output [3:0] m_axi_rmem5_ARQOS;
+  (* RS_HS = "m_axi_rmem5_AR.ready" *)input m_axi_rmem5_ARREADY;
+  (* RS_HS = "m_axi_rmem5_AR.data" *)output [2:0] m_axi_rmem5_ARSIZE;
+  (* RS_HS = "m_axi_rmem5_AR.valid" *)output m_axi_rmem5_ARVALID;
+  (* RS_HS = "m_axi_rmem5_AW.data" *)output [63:0] m_axi_rmem5_AWADDR;
+  (* RS_HS = "m_axi_rmem5_AW.data" *)output [1:0] m_axi_rmem5_AWBURST;
+  (* RS_HS = "m_axi_rmem5_AW.data" *)output [3:0] m_axi_rmem5_AWCACHE;
+  (* RS_HS = "m_axi_rmem5_AW.data" *)output [1:0] m_axi_rmem5_AWID;
+  (* RS_HS = "m_axi_rmem5_AW.data" *)output [7:0] m_axi_rmem5_AWLEN;
+  (* RS_HS = "m_axi_rmem5_AW.data" *)output m_axi_rmem5_AWLOCK;
+  (* RS_HS = "m_axi_rmem5_AW.data" *)output [2:0] m_axi_rmem5_AWPROT;
+  (* RS_HS = "m_axi_rmem5_AW.data" *)output [3:0] m_axi_rmem5_AWQOS;
+  (* RS_HS = "m_axi_rmem5_AW.ready" *)input m_axi_rmem5_AWREADY;
+  (* RS_HS = "m_axi_rmem5_AW.data" *)output [2:0] m_axi_rmem5_AWSIZE;
+  (* RS_HS = "m_axi_rmem5_AW.valid" *)output m_axi_rmem5_AWVALID;
+  (* RS_HS = "m_axi_rmem5_B.data" *)input [1:0] m_axi_rmem5_BID;
+  (* RS_HS = "m_axi_rmem5_B.ready" *)output m_axi_rmem5_BREADY;
+  (* RS_HS = "m_axi_rmem5_B.data" *)input [1:0] m_axi_rmem5_BRESP;
+  (* RS_HS = "m_axi_rmem5_B.valid" *)input m_axi_rmem5_BVALID;
+  (* RS_HS = "m_axi_rmem5_R.data" *)input [511:0] m_axi_rmem5_RDATA;
+  (* RS_HS = "m_axi_rmem5_R.data" *)input [1:0] m_axi_rmem5_RID;
+  (* RS_HS = "m_axi_rmem5_R.data" *)input m_axi_rmem5_RLAST;
+  (* RS_HS = "m_axi_rmem5_R.ready" *)output m_axi_rmem5_RREADY;
+  (* RS_HS = "m_axi_rmem5_R.data" *)input [1:0] m_axi_rmem5_RRESP;
+  (* RS_HS = "m_axi_rmem5_R.valid" *)input m_axi_rmem5_RVALID;
+  (* RS_HS = "m_axi_rmem5_W.data" *)output [511:0] m_axi_rmem5_WDATA;
+  (* RS_HS = "m_axi_rmem5_W.data" *)output m_axi_rmem5_WLAST;
+  (* RS_HS = "m_axi_rmem5_W.ready" *)input m_axi_rmem5_WREADY;
+  (* RS_HS = "m_axi_rmem5_W.data" *)output [63:0] m_axi_rmem5_WSTRB;
+  (* RS_HS = "m_axi_rmem5_W.valid" *)output m_axi_rmem5_WVALID;
+  (* RS_HS = "m_axi_rmem6_AR.data" *)output [63:0] m_axi_rmem6_ARADDR;
+  (* RS_HS = "m_axi_rmem6_AR.data" *)output [1:0] m_axi_rmem6_ARBURST;
+  (* RS_HS = "m_axi_rmem6_AR.data" *)output [3:0] m_axi_rmem6_ARCACHE;
+  (* RS_HS = "m_axi_rmem6_AR.data" *)output [1:0] m_axi_rmem6_ARID;
+  (* RS_HS = "m_axi_rmem6_AR.data" *)output [7:0] m_axi_rmem6_ARLEN;
+  (* RS_HS = "m_axi_rmem6_AR.data" *)output m_axi_rmem6_ARLOCK;
+  (* RS_HS = "m_axi_rmem6_AR.data" *)output [2:0] m_axi_rmem6_ARPROT;
+  (* RS_HS = "m_axi_rmem6_AR.data" *)output [3:0] m_axi_rmem6_ARQOS;
+  (* RS_HS = "m_axi_rmem6_AR.ready" *)input m_axi_rmem6_ARREADY;
+  (* RS_HS = "m_axi_rmem6_AR.data" *)output [2:0] m_axi_rmem6_ARSIZE;
+  (* RS_HS = "m_axi_rmem6_AR.valid" *)output m_axi_rmem6_ARVALID;
+  (* RS_HS = "m_axi_rmem6_AW.data" *)output [63:0] m_axi_rmem6_AWADDR;
+  (* RS_HS = "m_axi_rmem6_AW.data" *)output [1:0] m_axi_rmem6_AWBURST;
+  (* RS_HS = "m_axi_rmem6_AW.data" *)output [3:0] m_axi_rmem6_AWCACHE;
+  (* RS_HS = "m_axi_rmem6_AW.data" *)output [1:0] m_axi_rmem6_AWID;
+  (* RS_HS = "m_axi_rmem6_AW.data" *)output [7:0] m_axi_rmem6_AWLEN;
+  (* RS_HS = "m_axi_rmem6_AW.data" *)output m_axi_rmem6_AWLOCK;
+  (* RS_HS = "m_axi_rmem6_AW.data" *)output [2:0] m_axi_rmem6_AWPROT;
+  (* RS_HS = "m_axi_rmem6_AW.data" *)output [3:0] m_axi_rmem6_AWQOS;
+  (* RS_HS = "m_axi_rmem6_AW.ready" *)input m_axi_rmem6_AWREADY;
+  (* RS_HS = "m_axi_rmem6_AW.data" *)output [2:0] m_axi_rmem6_AWSIZE;
+  (* RS_HS = "m_axi_rmem6_AW.valid" *)output m_axi_rmem6_AWVALID;
+  (* RS_HS = "m_axi_rmem6_B.data" *)input [1:0] m_axi_rmem6_BID;
+  (* RS_HS = "m_axi_rmem6_B.ready" *)output m_axi_rmem6_BREADY;
+  (* RS_HS = "m_axi_rmem6_B.data" *)input [1:0] m_axi_rmem6_BRESP;
+  (* RS_HS = "m_axi_rmem6_B.valid" *)input m_axi_rmem6_BVALID;
+  (* RS_HS = "m_axi_rmem6_R.data" *)input [511:0] m_axi_rmem6_RDATA;
+  (* RS_HS = "m_axi_rmem6_R.data" *)input [1:0] m_axi_rmem6_RID;
+  (* RS_HS = "m_axi_rmem6_R.data" *)input m_axi_rmem6_RLAST;
+  (* RS_HS = "m_axi_rmem6_R.ready" *)output m_axi_rmem6_RREADY;
+  (* RS_HS = "m_axi_rmem6_R.data" *)input [1:0] m_axi_rmem6_RRESP;
+  (* RS_HS = "m_axi_rmem6_R.valid" *)input m_axi_rmem6_RVALID;
+  (* RS_HS = "m_axi_rmem6_W.data" *)output [511:0] m_axi_rmem6_WDATA;
+  (* RS_HS = "m_axi_rmem6_W.data" *)output m_axi_rmem6_WLAST;
+  (* RS_HS = "m_axi_rmem6_W.ready" *)input m_axi_rmem6_WREADY;
+  (* RS_HS = "m_axi_rmem6_W.data" *)output [63:0] m_axi_rmem6_WSTRB;
+  (* RS_HS = "m_axi_rmem6_W.valid" *)output m_axi_rmem6_WVALID;
+  (* RS_HS = "m_axi_rmem7_AR.data" *)output [63:0] m_axi_rmem7_ARADDR;
+  (* RS_HS = "m_axi_rmem7_AR.data" *)output [1:0] m_axi_rmem7_ARBURST;
+  (* RS_HS = "m_axi_rmem7_AR.data" *)output [3:0] m_axi_rmem7_ARCACHE;
+  (* RS_HS = "m_axi_rmem7_AR.data" *)output [1:0] m_axi_rmem7_ARID;
+  (* RS_HS = "m_axi_rmem7_AR.data" *)output [7:0] m_axi_rmem7_ARLEN;
+  (* RS_HS = "m_axi_rmem7_AR.data" *)output m_axi_rmem7_ARLOCK;
+  (* RS_HS = "m_axi_rmem7_AR.data" *)output [2:0] m_axi_rmem7_ARPROT;
+  (* RS_HS = "m_axi_rmem7_AR.data" *)output [3:0] m_axi_rmem7_ARQOS;
+  (* RS_HS = "m_axi_rmem7_AR.ready" *)input m_axi_rmem7_ARREADY;
+  (* RS_HS = "m_axi_rmem7_AR.data" *)output [2:0] m_axi_rmem7_ARSIZE;
+  (* RS_HS = "m_axi_rmem7_AR.valid" *)output m_axi_rmem7_ARVALID;
+  (* RS_HS = "m_axi_rmem7_AW.data" *)output [63:0] m_axi_rmem7_AWADDR;
+  (* RS_HS = "m_axi_rmem7_AW.data" *)output [1:0] m_axi_rmem7_AWBURST;
+  (* RS_HS = "m_axi_rmem7_AW.data" *)output [3:0] m_axi_rmem7_AWCACHE;
+  (* RS_HS = "m_axi_rmem7_AW.data" *)output [1:0] m_axi_rmem7_AWID;
+  (* RS_HS = "m_axi_rmem7_AW.data" *)output [7:0] m_axi_rmem7_AWLEN;
+  (* RS_HS = "m_axi_rmem7_AW.data" *)output m_axi_rmem7_AWLOCK;
+  (* RS_HS = "m_axi_rmem7_AW.data" *)output [2:0] m_axi_rmem7_AWPROT;
+  (* RS_HS = "m_axi_rmem7_AW.data" *)output [3:0] m_axi_rmem7_AWQOS;
+  (* RS_HS = "m_axi_rmem7_AW.ready" *)input m_axi_rmem7_AWREADY;
+  (* RS_HS = "m_axi_rmem7_AW.data" *)output [2:0] m_axi_rmem7_AWSIZE;
+  (* RS_HS = "m_axi_rmem7_AW.valid" *)output m_axi_rmem7_AWVALID;
+  (* RS_HS = "m_axi_rmem7_B.data" *)input [1:0] m_axi_rmem7_BID;
+  (* RS_HS = "m_axi_rmem7_B.ready" *)output m_axi_rmem7_BREADY;
+  (* RS_HS = "m_axi_rmem7_B.data" *)input [1:0] m_axi_rmem7_BRESP;
+  (* RS_HS = "m_axi_rmem7_B.valid" *)input m_axi_rmem7_BVALID;
+  (* RS_HS = "m_axi_rmem7_R.data" *)input [511:0] m_axi_rmem7_RDATA;
+  (* RS_HS = "m_axi_rmem7_R.data" *)input [1:0] m_axi_rmem7_RID;
+  (* RS_HS = "m_axi_rmem7_R.data" *)input m_axi_rmem7_RLAST;
+  (* RS_HS = "m_axi_rmem7_R.ready" *)output m_axi_rmem7_RREADY;
+  (* RS_HS = "m_axi_rmem7_R.data" *)input [1:0] m_axi_rmem7_RRESP;
+  (* RS_HS = "m_axi_rmem7_R.valid" *)input m_axi_rmem7_RVALID;
+  (* RS_HS = "m_axi_rmem7_W.data" *)output [511:0] m_axi_rmem7_WDATA;
+  (* RS_HS = "m_axi_rmem7_W.data" *)output m_axi_rmem7_WLAST;
+  (* RS_HS = "m_axi_rmem7_W.ready" *)input m_axi_rmem7_WREADY;
+  (* RS_HS = "m_axi_rmem7_W.data" *)output [63:0] m_axi_rmem7_WSTRB;
+  (* RS_HS = "m_axi_rmem7_W.valid" *)output m_axi_rmem7_WVALID;
+  (* RS_HS = "m_axi_rmem8_AR.data" *)output [63:0] m_axi_rmem8_ARADDR;
+  (* RS_HS = "m_axi_rmem8_AR.data" *)output [1:0] m_axi_rmem8_ARBURST;
+  (* RS_HS = "m_axi_rmem8_AR.data" *)output [3:0] m_axi_rmem8_ARCACHE;
+  (* RS_HS = "m_axi_rmem8_AR.data" *)output [1:0] m_axi_rmem8_ARID;
+  (* RS_HS = "m_axi_rmem8_AR.data" *)output [7:0] m_axi_rmem8_ARLEN;
+  (* RS_HS = "m_axi_rmem8_AR.data" *)output m_axi_rmem8_ARLOCK;
+  (* RS_HS = "m_axi_rmem8_AR.data" *)output [2:0] m_axi_rmem8_ARPROT;
+  (* RS_HS = "m_axi_rmem8_AR.data" *)output [3:0] m_axi_rmem8_ARQOS;
+  (* RS_HS = "m_axi_rmem8_AR.ready" *)input m_axi_rmem8_ARREADY;
+  (* RS_HS = "m_axi_rmem8_AR.data" *)output [2:0] m_axi_rmem8_ARSIZE;
+  (* RS_HS = "m_axi_rmem8_AR.valid" *)output m_axi_rmem8_ARVALID;
+  (* RS_HS = "m_axi_rmem8_AW.data" *)output [63:0] m_axi_rmem8_AWADDR;
+  (* RS_HS = "m_axi_rmem8_AW.data" *)output [1:0] m_axi_rmem8_AWBURST;
+  (* RS_HS = "m_axi_rmem8_AW.data" *)output [3:0] m_axi_rmem8_AWCACHE;
+  (* RS_HS = "m_axi_rmem8_AW.data" *)output [1:0] m_axi_rmem8_AWID;
+  (* RS_HS = "m_axi_rmem8_AW.data" *)output [7:0] m_axi_rmem8_AWLEN;
+  (* RS_HS = "m_axi_rmem8_AW.data" *)output m_axi_rmem8_AWLOCK;
+  (* RS_HS = "m_axi_rmem8_AW.data" *)output [2:0] m_axi_rmem8_AWPROT;
+  (* RS_HS = "m_axi_rmem8_AW.data" *)output [3:0] m_axi_rmem8_AWQOS;
+  (* RS_HS = "m_axi_rmem8_AW.ready" *)input m_axi_rmem8_AWREADY;
+  (* RS_HS = "m_axi_rmem8_AW.data" *)output [2:0] m_axi_rmem8_AWSIZE;
+  (* RS_HS = "m_axi_rmem8_AW.valid" *)output m_axi_rmem8_AWVALID;
+  (* RS_HS = "m_axi_rmem8_B.data" *)input [1:0] m_axi_rmem8_BID;
+  (* RS_HS = "m_axi_rmem8_B.ready" *)output m_axi_rmem8_BREADY;
+  (* RS_HS = "m_axi_rmem8_B.data" *)input [1:0] m_axi_rmem8_BRESP;
+  (* RS_HS = "m_axi_rmem8_B.valid" *)input m_axi_rmem8_BVALID;
+  (* RS_HS = "m_axi_rmem8_R.data" *)input [511:0] m_axi_rmem8_RDATA;
+  (* RS_HS = "m_axi_rmem8_R.data" *)input [1:0] m_axi_rmem8_RID;
+  (* RS_HS = "m_axi_rmem8_R.data" *)input m_axi_rmem8_RLAST;
+  (* RS_HS = "m_axi_rmem8_R.ready" *)output m_axi_rmem8_RREADY;
+  (* RS_HS = "m_axi_rmem8_R.data" *)input [1:0] m_axi_rmem8_RRESP;
+  (* RS_HS = "m_axi_rmem8_R.valid" *)input m_axi_rmem8_RVALID;
+  (* RS_HS = "m_axi_rmem8_W.data" *)output [511:0] m_axi_rmem8_WDATA;
+  (* RS_HS = "m_axi_rmem8_W.data" *)output m_axi_rmem8_WLAST;
+  (* RS_HS = "m_axi_rmem8_W.ready" *)input m_axi_rmem8_WREADY;
+  (* RS_HS = "m_axi_rmem8_W.data" *)output [63:0] m_axi_rmem8_WSTRB;
+  (* RS_HS = "m_axi_rmem8_W.valid" *)output m_axi_rmem8_WVALID;
+  (* RS_HS = "m_axi_rmem9_AR.data" *)output [63:0] m_axi_rmem9_ARADDR;
+  (* RS_HS = "m_axi_rmem9_AR.data" *)output [1:0] m_axi_rmem9_ARBURST;
+  (* RS_HS = "m_axi_rmem9_AR.data" *)output [3:0] m_axi_rmem9_ARCACHE;
+  (* RS_HS = "m_axi_rmem9_AR.data" *)output [1:0] m_axi_rmem9_ARID;
+  (* RS_HS = "m_axi_rmem9_AR.data" *)output [7:0] m_axi_rmem9_ARLEN;
+  (* RS_HS = "m_axi_rmem9_AR.data" *)output m_axi_rmem9_ARLOCK;
+  (* RS_HS = "m_axi_rmem9_AR.data" *)output [2:0] m_axi_rmem9_ARPROT;
+  (* RS_HS = "m_axi_rmem9_AR.data" *)output [3:0] m_axi_rmem9_ARQOS;
+  (* RS_HS = "m_axi_rmem9_AR.ready" *)input m_axi_rmem9_ARREADY;
+  (* RS_HS = "m_axi_rmem9_AR.data" *)output [2:0] m_axi_rmem9_ARSIZE;
+  (* RS_HS = "m_axi_rmem9_AR.valid" *)output m_axi_rmem9_ARVALID;
+  (* RS_HS = "m_axi_rmem9_AW.data" *)output [63:0] m_axi_rmem9_AWADDR;
+  (* RS_HS = "m_axi_rmem9_AW.data" *)output [1:0] m_axi_rmem9_AWBURST;
+  (* RS_HS = "m_axi_rmem9_AW.data" *)output [3:0] m_axi_rmem9_AWCACHE;
+  (* RS_HS = "m_axi_rmem9_AW.data" *)output [1:0] m_axi_rmem9_AWID;
+  (* RS_HS = "m_axi_rmem9_AW.data" *)output [7:0] m_axi_rmem9_AWLEN;
+  (* RS_HS = "m_axi_rmem9_AW.data" *)output m_axi_rmem9_AWLOCK;
+  (* RS_HS = "m_axi_rmem9_AW.data" *)output [2:0] m_axi_rmem9_AWPROT;
+  (* RS_HS = "m_axi_rmem9_AW.data" *)output [3:0] m_axi_rmem9_AWQOS;
+  (* RS_HS = "m_axi_rmem9_AW.ready" *)input m_axi_rmem9_AWREADY;
+  (* RS_HS = "m_axi_rmem9_AW.data" *)output [2:0] m_axi_rmem9_AWSIZE;
+  (* RS_HS = "m_axi_rmem9_AW.valid" *)output m_axi_rmem9_AWVALID;
+  (* RS_HS = "m_axi_rmem9_B.data" *)input [1:0] m_axi_rmem9_BID;
+  (* RS_HS = "m_axi_rmem9_B.ready" *)output m_axi_rmem9_BREADY;
+  (* RS_HS = "m_axi_rmem9_B.data" *)input [1:0] m_axi_rmem9_BRESP;
+  (* RS_HS = "m_axi_rmem9_B.valid" *)input m_axi_rmem9_BVALID;
+  (* RS_HS = "m_axi_rmem9_R.data" *)input [511:0] m_axi_rmem9_RDATA;
+  (* RS_HS = "m_axi_rmem9_R.data" *)input [1:0] m_axi_rmem9_RID;
+  (* RS_HS = "m_axi_rmem9_R.data" *)input m_axi_rmem9_RLAST;
+  (* RS_HS = "m_axi_rmem9_R.ready" *)output m_axi_rmem9_RREADY;
+  (* RS_HS = "m_axi_rmem9_R.data" *)input [1:0] m_axi_rmem9_RRESP;
+  (* RS_HS = "m_axi_rmem9_R.valid" *)input m_axi_rmem9_RVALID;
+  (* RS_HS = "m_axi_rmem9_W.data" *)output [511:0] m_axi_rmem9_WDATA;
+  (* RS_HS = "m_axi_rmem9_W.data" *)output m_axi_rmem9_WLAST;
+  (* RS_HS = "m_axi_rmem9_W.ready" *)input m_axi_rmem9_WREADY;
+  (* RS_HS = "m_axi_rmem9_W.data" *)output [63:0] m_axi_rmem9_WSTRB;
+  (* RS_HS = "m_axi_rmem9_W.valid" *)output m_axi_rmem9_WVALID;
+  (* RS_HS = "m_axi_rmem10_AR.data" *)output [63:0] m_axi_rmem10_ARADDR;
+  (* RS_HS = "m_axi_rmem10_AR.data" *)output [1:0] m_axi_rmem10_ARBURST;
+  (* RS_HS = "m_axi_rmem10_AR.data" *)output [3:0] m_axi_rmem10_ARCACHE;
+  (* RS_HS = "m_axi_rmem10_AR.data" *)output [1:0] m_axi_rmem10_ARID;
+  (* RS_HS = "m_axi_rmem10_AR.data" *)output [7:0] m_axi_rmem10_ARLEN;
+  (* RS_HS = "m_axi_rmem10_AR.data" *)output m_axi_rmem10_ARLOCK;
+  (* RS_HS = "m_axi_rmem10_AR.data" *)output [2:0] m_axi_rmem10_ARPROT;
+  (* RS_HS = "m_axi_rmem10_AR.data" *)output [3:0] m_axi_rmem10_ARQOS;
+  (* RS_HS = "m_axi_rmem10_AR.ready" *)input m_axi_rmem10_ARREADY;
+  (* RS_HS = "m_axi_rmem10_AR.data" *)output [2:0] m_axi_rmem10_ARSIZE;
+  (* RS_HS = "m_axi_rmem10_AR.valid" *)output m_axi_rmem10_ARVALID;
+  (* RS_HS = "m_axi_rmem10_AW.data" *)output [63:0] m_axi_rmem10_AWADDR;
+  (* RS_HS = "m_axi_rmem10_AW.data" *)output [1:0] m_axi_rmem10_AWBURST;
+  (* RS_HS = "m_axi_rmem10_AW.data" *)output [3:0] m_axi_rmem10_AWCACHE;
+  (* RS_HS = "m_axi_rmem10_AW.data" *)output [1:0] m_axi_rmem10_AWID;
+  (* RS_HS = "m_axi_rmem10_AW.data" *)output [7:0] m_axi_rmem10_AWLEN;
+  (* RS_HS = "m_axi_rmem10_AW.data" *)output m_axi_rmem10_AWLOCK;
+  (* RS_HS = "m_axi_rmem10_AW.data" *)output [2:0] m_axi_rmem10_AWPROT;
+  (* RS_HS = "m_axi_rmem10_AW.data" *)output [3:0] m_axi_rmem10_AWQOS;
+  (* RS_HS = "m_axi_rmem10_AW.ready" *)input m_axi_rmem10_AWREADY;
+  (* RS_HS = "m_axi_rmem10_AW.data" *)output [2:0] m_axi_rmem10_AWSIZE;
+  (* RS_HS = "m_axi_rmem10_AW.valid" *)output m_axi_rmem10_AWVALID;
+  (* RS_HS = "m_axi_rmem10_B.data" *)input [1:0] m_axi_rmem10_BID;
+  (* RS_HS = "m_axi_rmem10_B.ready" *)output m_axi_rmem10_BREADY;
+  (* RS_HS = "m_axi_rmem10_B.data" *)input [1:0] m_axi_rmem10_BRESP;
+  (* RS_HS = "m_axi_rmem10_B.valid" *)input m_axi_rmem10_BVALID;
+  (* RS_HS = "m_axi_rmem10_R.data" *)input [511:0] m_axi_rmem10_RDATA;
+  (* RS_HS = "m_axi_rmem10_R.data" *)input [1:0] m_axi_rmem10_RID;
+  (* RS_HS = "m_axi_rmem10_R.data" *)input m_axi_rmem10_RLAST;
+  (* RS_HS = "m_axi_rmem10_R.ready" *)output m_axi_rmem10_RREADY;
+  (* RS_HS = "m_axi_rmem10_R.data" *)input [1:0] m_axi_rmem10_RRESP;
+  (* RS_HS = "m_axi_rmem10_R.valid" *)input m_axi_rmem10_RVALID;
+  (* RS_HS = "m_axi_rmem10_W.data" *)output [511:0] m_axi_rmem10_WDATA;
+  (* RS_HS = "m_axi_rmem10_W.data" *)output m_axi_rmem10_WLAST;
+  (* RS_HS = "m_axi_rmem10_W.ready" *)input m_axi_rmem10_WREADY;
+  (* RS_HS = "m_axi_rmem10_W.data" *)output [63:0] m_axi_rmem10_WSTRB;
+  (* RS_HS = "m_axi_rmem10_W.valid" *)output m_axi_rmem10_WVALID;
+  (* RS_HS = "m_axi_rmem11_AR.data" *)output [63:0] m_axi_rmem11_ARADDR;
+  (* RS_HS = "m_axi_rmem11_AR.data" *)output [1:0] m_axi_rmem11_ARBURST;
+  (* RS_HS = "m_axi_rmem11_AR.data" *)output [3:0] m_axi_rmem11_ARCACHE;
+  (* RS_HS = "m_axi_rmem11_AR.data" *)output [1:0] m_axi_rmem11_ARID;
+  (* RS_HS = "m_axi_rmem11_AR.data" *)output [7:0] m_axi_rmem11_ARLEN;
+  (* RS_HS = "m_axi_rmem11_AR.data" *)output m_axi_rmem11_ARLOCK;
+  (* RS_HS = "m_axi_rmem11_AR.data" *)output [2:0] m_axi_rmem11_ARPROT;
+  (* RS_HS = "m_axi_rmem11_AR.data" *)output [3:0] m_axi_rmem11_ARQOS;
+  (* RS_HS = "m_axi_rmem11_AR.ready" *)input m_axi_rmem11_ARREADY;
+  (* RS_HS = "m_axi_rmem11_AR.data" *)output [2:0] m_axi_rmem11_ARSIZE;
+  (* RS_HS = "m_axi_rmem11_AR.valid" *)output m_axi_rmem11_ARVALID;
+  (* RS_HS = "m_axi_rmem11_AW.data" *)output [63:0] m_axi_rmem11_AWADDR;
+  (* RS_HS = "m_axi_rmem11_AW.data" *)output [1:0] m_axi_rmem11_AWBURST;
+  (* RS_HS = "m_axi_rmem11_AW.data" *)output [3:0] m_axi_rmem11_AWCACHE;
+  (* RS_HS = "m_axi_rmem11_AW.data" *)output [1:0] m_axi_rmem11_AWID;
+  (* RS_HS = "m_axi_rmem11_AW.data" *)output [7:0] m_axi_rmem11_AWLEN;
+  (* RS_HS = "m_axi_rmem11_AW.data" *)output m_axi_rmem11_AWLOCK;
+  (* RS_HS = "m_axi_rmem11_AW.data" *)output [2:0] m_axi_rmem11_AWPROT;
+  (* RS_HS = "m_axi_rmem11_AW.data" *)output [3:0] m_axi_rmem11_AWQOS;
+  (* RS_HS = "m_axi_rmem11_AW.ready" *)input m_axi_rmem11_AWREADY;
+  (* RS_HS = "m_axi_rmem11_AW.data" *)output [2:0] m_axi_rmem11_AWSIZE;
+  (* RS_HS = "m_axi_rmem11_AW.valid" *)output m_axi_rmem11_AWVALID;
+  (* RS_HS = "m_axi_rmem11_B.data" *)input [1:0] m_axi_rmem11_BID;
+  (* RS_HS = "m_axi_rmem11_B.ready" *)output m_axi_rmem11_BREADY;
+  (* RS_HS = "m_axi_rmem11_B.data" *)input [1:0] m_axi_rmem11_BRESP;
+  (* RS_HS = "m_axi_rmem11_B.valid" *)input m_axi_rmem11_BVALID;
+  (* RS_HS = "m_axi_rmem11_R.data" *)input [511:0] m_axi_rmem11_RDATA;
+  (* RS_HS = "m_axi_rmem11_R.data" *)input [1:0] m_axi_rmem11_RID;
+  (* RS_HS = "m_axi_rmem11_R.data" *)input m_axi_rmem11_RLAST;
+  (* RS_HS = "m_axi_rmem11_R.ready" *)output m_axi_rmem11_RREADY;
+  (* RS_HS = "m_axi_rmem11_R.data" *)input [1:0] m_axi_rmem11_RRESP;
+  (* RS_HS = "m_axi_rmem11_R.valid" *)input m_axi_rmem11_RVALID;
+  (* RS_HS = "m_axi_rmem11_W.data" *)output [511:0] m_axi_rmem11_WDATA;
+  (* RS_HS = "m_axi_rmem11_W.data" *)output m_axi_rmem11_WLAST;
+  (* RS_HS = "m_axi_rmem11_W.ready" *)input m_axi_rmem11_WREADY;
+  (* RS_HS = "m_axi_rmem11_W.data" *)output [63:0] m_axi_rmem11_WSTRB;
+  (* RS_HS = "m_axi_rmem11_W.valid" *)output m_axi_rmem11_WVALID;
+  (* RS_HS = "m_axi_rmem12_AR.data" *)output [63:0] m_axi_rmem12_ARADDR;
+  (* RS_HS = "m_axi_rmem12_AR.data" *)output [1:0] m_axi_rmem12_ARBURST;
+  (* RS_HS = "m_axi_rmem12_AR.data" *)output [3:0] m_axi_rmem12_ARCACHE;
+  (* RS_HS = "m_axi_rmem12_AR.data" *)output [1:0] m_axi_rmem12_ARID;
+  (* RS_HS = "m_axi_rmem12_AR.data" *)output [7:0] m_axi_rmem12_ARLEN;
+  (* RS_HS = "m_axi_rmem12_AR.data" *)output m_axi_rmem12_ARLOCK;
+  (* RS_HS = "m_axi_rmem12_AR.data" *)output [2:0] m_axi_rmem12_ARPROT;
+  (* RS_HS = "m_axi_rmem12_AR.data" *)output [3:0] m_axi_rmem12_ARQOS;
+  (* RS_HS = "m_axi_rmem12_AR.ready" *)input m_axi_rmem12_ARREADY;
+  (* RS_HS = "m_axi_rmem12_AR.data" *)output [2:0] m_axi_rmem12_ARSIZE;
+  (* RS_HS = "m_axi_rmem12_AR.valid" *)output m_axi_rmem12_ARVALID;
+  (* RS_HS = "m_axi_rmem12_AW.data" *)output [63:0] m_axi_rmem12_AWADDR;
+  (* RS_HS = "m_axi_rmem12_AW.data" *)output [1:0] m_axi_rmem12_AWBURST;
+  (* RS_HS = "m_axi_rmem12_AW.data" *)output [3:0] m_axi_rmem12_AWCACHE;
+  (* RS_HS = "m_axi_rmem12_AW.data" *)output [1:0] m_axi_rmem12_AWID;
+  (* RS_HS = "m_axi_rmem12_AW.data" *)output [7:0] m_axi_rmem12_AWLEN;
+  (* RS_HS = "m_axi_rmem12_AW.data" *)output m_axi_rmem12_AWLOCK;
+  (* RS_HS = "m_axi_rmem12_AW.data" *)output [2:0] m_axi_rmem12_AWPROT;
+  (* RS_HS = "m_axi_rmem12_AW.data" *)output [3:0] m_axi_rmem12_AWQOS;
+  (* RS_HS = "m_axi_rmem12_AW.ready" *)input m_axi_rmem12_AWREADY;
+  (* RS_HS = "m_axi_rmem12_AW.data" *)output [2:0] m_axi_rmem12_AWSIZE;
+  (* RS_HS = "m_axi_rmem12_AW.valid" *)output m_axi_rmem12_AWVALID;
+  (* RS_HS = "m_axi_rmem12_B.data" *)input [1:0] m_axi_rmem12_BID;
+  (* RS_HS = "m_axi_rmem12_B.ready" *)output m_axi_rmem12_BREADY;
+  (* RS_HS = "m_axi_rmem12_B.data" *)input [1:0] m_axi_rmem12_BRESP;
+  (* RS_HS = "m_axi_rmem12_B.valid" *)input m_axi_rmem12_BVALID;
+  (* RS_HS = "m_axi_rmem12_R.data" *)input [511:0] m_axi_rmem12_RDATA;
+  (* RS_HS = "m_axi_rmem12_R.data" *)input [1:0] m_axi_rmem12_RID;
+  (* RS_HS = "m_axi_rmem12_R.data" *)input m_axi_rmem12_RLAST;
+  (* RS_HS = "m_axi_rmem12_R.ready" *)output m_axi_rmem12_RREADY;
+  (* RS_HS = "m_axi_rmem12_R.data" *)input [1:0] m_axi_rmem12_RRESP;
+  (* RS_HS = "m_axi_rmem12_R.valid" *)input m_axi_rmem12_RVALID;
+  (* RS_HS = "m_axi_rmem12_W.data" *)output [511:0] m_axi_rmem12_WDATA;
+  (* RS_HS = "m_axi_rmem12_W.data" *)output m_axi_rmem12_WLAST;
+  (* RS_HS = "m_axi_rmem12_W.ready" *)input m_axi_rmem12_WREADY;
+  (* RS_HS = "m_axi_rmem12_W.data" *)output [63:0] m_axi_rmem12_WSTRB;
+  (* RS_HS = "m_axi_rmem12_W.valid" *)output m_axi_rmem12_WVALID;
+  (* RS_HS = "m_axi_rmem13_AR.data" *)output [63:0] m_axi_rmem13_ARADDR;
+  (* RS_HS = "m_axi_rmem13_AR.data" *)output [1:0] m_axi_rmem13_ARBURST;
+  (* RS_HS = "m_axi_rmem13_AR.data" *)output [3:0] m_axi_rmem13_ARCACHE;
+  (* RS_HS = "m_axi_rmem13_AR.data" *)output [1:0] m_axi_rmem13_ARID;
+  (* RS_HS = "m_axi_rmem13_AR.data" *)output [7:0] m_axi_rmem13_ARLEN;
+  (* RS_HS = "m_axi_rmem13_AR.data" *)output m_axi_rmem13_ARLOCK;
+  (* RS_HS = "m_axi_rmem13_AR.data" *)output [2:0] m_axi_rmem13_ARPROT;
+  (* RS_HS = "m_axi_rmem13_AR.data" *)output [3:0] m_axi_rmem13_ARQOS;
+  (* RS_HS = "m_axi_rmem13_AR.ready" *)input m_axi_rmem13_ARREADY;
+  (* RS_HS = "m_axi_rmem13_AR.data" *)output [2:0] m_axi_rmem13_ARSIZE;
+  (* RS_HS = "m_axi_rmem13_AR.valid" *)output m_axi_rmem13_ARVALID;
+  (* RS_HS = "m_axi_rmem13_AW.data" *)output [63:0] m_axi_rmem13_AWADDR;
+  (* RS_HS = "m_axi_rmem13_AW.data" *)output [1:0] m_axi_rmem13_AWBURST;
+  (* RS_HS = "m_axi_rmem13_AW.data" *)output [3:0] m_axi_rmem13_AWCACHE;
+  (* RS_HS = "m_axi_rmem13_AW.data" *)output [1:0] m_axi_rmem13_AWID;
+  (* RS_HS = "m_axi_rmem13_AW.data" *)output [7:0] m_axi_rmem13_AWLEN;
+  (* RS_HS = "m_axi_rmem13_AW.data" *)output m_axi_rmem13_AWLOCK;
+  (* RS_HS = "m_axi_rmem13_AW.data" *)output [2:0] m_axi_rmem13_AWPROT;
+  (* RS_HS = "m_axi_rmem13_AW.data" *)output [3:0] m_axi_rmem13_AWQOS;
+  (* RS_HS = "m_axi_rmem13_AW.ready" *)input m_axi_rmem13_AWREADY;
+  (* RS_HS = "m_axi_rmem13_AW.data" *)output [2:0] m_axi_rmem13_AWSIZE;
+  (* RS_HS = "m_axi_rmem13_AW.valid" *)output m_axi_rmem13_AWVALID;
+  (* RS_HS = "m_axi_rmem13_B.data" *)input [1:0] m_axi_rmem13_BID;
+  (* RS_HS = "m_axi_rmem13_B.ready" *)output m_axi_rmem13_BREADY;
+  (* RS_HS = "m_axi_rmem13_B.data" *)input [1:0] m_axi_rmem13_BRESP;
+  (* RS_HS = "m_axi_rmem13_B.valid" *)input m_axi_rmem13_BVALID;
+  (* RS_HS = "m_axi_rmem13_R.data" *)input [511:0] m_axi_rmem13_RDATA;
+  (* RS_HS = "m_axi_rmem13_R.data" *)input [1:0] m_axi_rmem13_RID;
+  (* RS_HS = "m_axi_rmem13_R.data" *)input m_axi_rmem13_RLAST;
+  (* RS_HS = "m_axi_rmem13_R.ready" *)output m_axi_rmem13_RREADY;
+  (* RS_HS = "m_axi_rmem13_R.data" *)input [1:0] m_axi_rmem13_RRESP;
+  (* RS_HS = "m_axi_rmem13_R.valid" *)input m_axi_rmem13_RVALID;
+  (* RS_HS = "m_axi_rmem13_W.data" *)output [511:0] m_axi_rmem13_WDATA;
+  (* RS_HS = "m_axi_rmem13_W.data" *)output m_axi_rmem13_WLAST;
+  (* RS_HS = "m_axi_rmem13_W.ready" *)input m_axi_rmem13_WREADY;
+  (* RS_HS = "m_axi_rmem13_W.data" *)output [63:0] m_axi_rmem13_WSTRB;
+  (* RS_HS = "m_axi_rmem13_W.valid" *)output m_axi_rmem13_WVALID;
+  (* RS_HS = "m_axi_rmem14_AR.data" *)output [63:0] m_axi_rmem14_ARADDR;
+  (* RS_HS = "m_axi_rmem14_AR.data" *)output [1:0] m_axi_rmem14_ARBURST;
+  (* RS_HS = "m_axi_rmem14_AR.data" *)output [3:0] m_axi_rmem14_ARCACHE;
+  (* RS_HS = "m_axi_rmem14_AR.data" *)output [1:0] m_axi_rmem14_ARID;
+  (* RS_HS = "m_axi_rmem14_AR.data" *)output [7:0] m_axi_rmem14_ARLEN;
+  (* RS_HS = "m_axi_rmem14_AR.data" *)output m_axi_rmem14_ARLOCK;
+  (* RS_HS = "m_axi_rmem14_AR.data" *)output [2:0] m_axi_rmem14_ARPROT;
+  (* RS_HS = "m_axi_rmem14_AR.data" *)output [3:0] m_axi_rmem14_ARQOS;
+  (* RS_HS = "m_axi_rmem14_AR.ready" *)input m_axi_rmem14_ARREADY;
+  (* RS_HS = "m_axi_rmem14_AR.data" *)output [2:0] m_axi_rmem14_ARSIZE;
+  (* RS_HS = "m_axi_rmem14_AR.valid" *)output m_axi_rmem14_ARVALID;
+  (* RS_HS = "m_axi_rmem14_AW.data" *)output [63:0] m_axi_rmem14_AWADDR;
+  (* RS_HS = "m_axi_rmem14_AW.data" *)output [1:0] m_axi_rmem14_AWBURST;
+  (* RS_HS = "m_axi_rmem14_AW.data" *)output [3:0] m_axi_rmem14_AWCACHE;
+  (* RS_HS = "m_axi_rmem14_AW.data" *)output [1:0] m_axi_rmem14_AWID;
+  (* RS_HS = "m_axi_rmem14_AW.data" *)output [7:0] m_axi_rmem14_AWLEN;
+  (* RS_HS = "m_axi_rmem14_AW.data" *)output m_axi_rmem14_AWLOCK;
+  (* RS_HS = "m_axi_rmem14_AW.data" *)output [2:0] m_axi_rmem14_AWPROT;
+  (* RS_HS = "m_axi_rmem14_AW.data" *)output [3:0] m_axi_rmem14_AWQOS;
+  (* RS_HS = "m_axi_rmem14_AW.ready" *)input m_axi_rmem14_AWREADY;
+  (* RS_HS = "m_axi_rmem14_AW.data" *)output [2:0] m_axi_rmem14_AWSIZE;
+  (* RS_HS = "m_axi_rmem14_AW.valid" *)output m_axi_rmem14_AWVALID;
+  (* RS_HS = "m_axi_rmem14_B.data" *)input [1:0] m_axi_rmem14_BID;
+  (* RS_HS = "m_axi_rmem14_B.ready" *)output m_axi_rmem14_BREADY;
+  (* RS_HS = "m_axi_rmem14_B.data" *)input [1:0] m_axi_rmem14_BRESP;
+  (* RS_HS = "m_axi_rmem14_B.valid" *)input m_axi_rmem14_BVALID;
+  (* RS_HS = "m_axi_rmem14_R.data" *)input [511:0] m_axi_rmem14_RDATA;
+  (* RS_HS = "m_axi_rmem14_R.data" *)input [1:0] m_axi_rmem14_RID;
+  (* RS_HS = "m_axi_rmem14_R.data" *)input m_axi_rmem14_RLAST;
+  (* RS_HS = "m_axi_rmem14_R.ready" *)output m_axi_rmem14_RREADY;
+  (* RS_HS = "m_axi_rmem14_R.data" *)input [1:0] m_axi_rmem14_RRESP;
+  (* RS_HS = "m_axi_rmem14_R.valid" *)input m_axi_rmem14_RVALID;
+  (* RS_HS = "m_axi_rmem14_W.data" *)output [511:0] m_axi_rmem14_WDATA;
+  (* RS_HS = "m_axi_rmem14_W.data" *)output m_axi_rmem14_WLAST;
+  (* RS_HS = "m_axi_rmem14_W.ready" *)input m_axi_rmem14_WREADY;
+  (* RS_HS = "m_axi_rmem14_W.data" *)output [63:0] m_axi_rmem14_WSTRB;
+  (* RS_HS = "m_axi_rmem14_W.valid" *)output m_axi_rmem14_WVALID;
+  (* RS_HS = "m_axi_rmem15_AR.data" *)output [63:0] m_axi_rmem15_ARADDR;
+  (* RS_HS = "m_axi_rmem15_AR.data" *)output [1:0] m_axi_rmem15_ARBURST;
+  (* RS_HS = "m_axi_rmem15_AR.data" *)output [3:0] m_axi_rmem15_ARCACHE;
+  (* RS_HS = "m_axi_rmem15_AR.data" *)output [1:0] m_axi_rmem15_ARID;
+  (* RS_HS = "m_axi_rmem15_AR.data" *)output [7:0] m_axi_rmem15_ARLEN;
+  (* RS_HS = "m_axi_rmem15_AR.data" *)output m_axi_rmem15_ARLOCK;
+  (* RS_HS = "m_axi_rmem15_AR.data" *)output [2:0] m_axi_rmem15_ARPROT;
+  (* RS_HS = "m_axi_rmem15_AR.data" *)output [3:0] m_axi_rmem15_ARQOS;
+  (* RS_HS = "m_axi_rmem15_AR.ready" *)input m_axi_rmem15_ARREADY;
+  (* RS_HS = "m_axi_rmem15_AR.data" *)output [2:0] m_axi_rmem15_ARSIZE;
+  (* RS_HS = "m_axi_rmem15_AR.valid" *)output m_axi_rmem15_ARVALID;
+  (* RS_HS = "m_axi_rmem15_AW.data" *)output [63:0] m_axi_rmem15_AWADDR;
+  (* RS_HS = "m_axi_rmem15_AW.data" *)output [1:0] m_axi_rmem15_AWBURST;
+  (* RS_HS = "m_axi_rmem15_AW.data" *)output [3:0] m_axi_rmem15_AWCACHE;
+  (* RS_HS = "m_axi_rmem15_AW.data" *)output [1:0] m_axi_rmem15_AWID;
+  (* RS_HS = "m_axi_rmem15_AW.data" *)output [7:0] m_axi_rmem15_AWLEN;
+  (* RS_HS = "m_axi_rmem15_AW.data" *)output m_axi_rmem15_AWLOCK;
+  (* RS_HS = "m_axi_rmem15_AW.data" *)output [2:0] m_axi_rmem15_AWPROT;
+  (* RS_HS = "m_axi_rmem15_AW.data" *)output [3:0] m_axi_rmem15_AWQOS;
+  (* RS_HS = "m_axi_rmem15_AW.ready" *)input m_axi_rmem15_AWREADY;
+  (* RS_HS = "m_axi_rmem15_AW.data" *)output [2:0] m_axi_rmem15_AWSIZE;
+  (* RS_HS = "m_axi_rmem15_AW.valid" *)output m_axi_rmem15_AWVALID;
+  (* RS_HS = "m_axi_rmem15_B.data" *)input [1:0] m_axi_rmem15_BID;
+  (* RS_HS = "m_axi_rmem15_B.ready" *)output m_axi_rmem15_BREADY;
+  (* RS_HS = "m_axi_rmem15_B.data" *)input [1:0] m_axi_rmem15_BRESP;
+  (* RS_HS = "m_axi_rmem15_B.valid" *)input m_axi_rmem15_BVALID;
+  (* RS_HS = "m_axi_rmem15_R.data" *)input [511:0] m_axi_rmem15_RDATA;
+  (* RS_HS = "m_axi_rmem15_R.data" *)input [1:0] m_axi_rmem15_RID;
+  (* RS_HS = "m_axi_rmem15_R.data" *)input m_axi_rmem15_RLAST;
+  (* RS_HS = "m_axi_rmem15_R.ready" *)output m_axi_rmem15_RREADY;
+  (* RS_HS = "m_axi_rmem15_R.data" *)input [1:0] m_axi_rmem15_RRESP;
+  (* RS_HS = "m_axi_rmem15_R.valid" *)input m_axi_rmem15_RVALID;
+  (* RS_HS = "m_axi_rmem15_W.data" *)output [511:0] m_axi_rmem15_WDATA;
+  (* RS_HS = "m_axi_rmem15_W.data" *)output m_axi_rmem15_WLAST;
+  (* RS_HS = "m_axi_rmem15_W.ready" *)input m_axi_rmem15_WREADY;
+  (* RS_HS = "m_axi_rmem15_W.data" *)output [63:0] m_axi_rmem15_WSTRB;
+  (* RS_HS = "m_axi_rmem15_W.valid" *)output m_axi_rmem15_WVALID;
+  (* RS_HS = "m_axi_rmem16_AR.data" *)output [63:0] m_axi_rmem16_ARADDR;
+  (* RS_HS = "m_axi_rmem16_AR.data" *)output [1:0] m_axi_rmem16_ARBURST;
+  (* RS_HS = "m_axi_rmem16_AR.data" *)output [3:0] m_axi_rmem16_ARCACHE;
+  (* RS_HS = "m_axi_rmem16_AR.data" *)output [1:0] m_axi_rmem16_ARID;
+  (* RS_HS = "m_axi_rmem16_AR.data" *)output [7:0] m_axi_rmem16_ARLEN;
+  (* RS_HS = "m_axi_rmem16_AR.data" *)output m_axi_rmem16_ARLOCK;
+  (* RS_HS = "m_axi_rmem16_AR.data" *)output [2:0] m_axi_rmem16_ARPROT;
+  (* RS_HS = "m_axi_rmem16_AR.data" *)output [3:0] m_axi_rmem16_ARQOS;
+  (* RS_HS = "m_axi_rmem16_AR.ready" *)input m_axi_rmem16_ARREADY;
+  (* RS_HS = "m_axi_rmem16_AR.data" *)output [2:0] m_axi_rmem16_ARSIZE;
+  (* RS_HS = "m_axi_rmem16_AR.valid" *)output m_axi_rmem16_ARVALID;
+  (* RS_HS = "m_axi_rmem16_AW.data" *)output [63:0] m_axi_rmem16_AWADDR;
+  (* RS_HS = "m_axi_rmem16_AW.data" *)output [1:0] m_axi_rmem16_AWBURST;
+  (* RS_HS = "m_axi_rmem16_AW.data" *)output [3:0] m_axi_rmem16_AWCACHE;
+  (* RS_HS = "m_axi_rmem16_AW.data" *)output [1:0] m_axi_rmem16_AWID;
+  (* RS_HS = "m_axi_rmem16_AW.data" *)output [7:0] m_axi_rmem16_AWLEN;
+  (* RS_HS = "m_axi_rmem16_AW.data" *)output m_axi_rmem16_AWLOCK;
+  (* RS_HS = "m_axi_rmem16_AW.data" *)output [2:0] m_axi_rmem16_AWPROT;
+  (* RS_HS = "m_axi_rmem16_AW.data" *)output [3:0] m_axi_rmem16_AWQOS;
+  (* RS_HS = "m_axi_rmem16_AW.ready" *)input m_axi_rmem16_AWREADY;
+  (* RS_HS = "m_axi_rmem16_AW.data" *)output [2:0] m_axi_rmem16_AWSIZE;
+  (* RS_HS = "m_axi_rmem16_AW.valid" *)output m_axi_rmem16_AWVALID;
+  (* RS_HS = "m_axi_rmem16_B.data" *)input [1:0] m_axi_rmem16_BID;
+  (* RS_HS = "m_axi_rmem16_B.ready" *)output m_axi_rmem16_BREADY;
+  (* RS_HS = "m_axi_rmem16_B.data" *)input [1:0] m_axi_rmem16_BRESP;
+  (* RS_HS = "m_axi_rmem16_B.valid" *)input m_axi_rmem16_BVALID;
+  (* RS_HS = "m_axi_rmem16_R.data" *)input [511:0] m_axi_rmem16_RDATA;
+  (* RS_HS = "m_axi_rmem16_R.data" *)input [1:0] m_axi_rmem16_RID;
+  (* RS_HS = "m_axi_rmem16_R.data" *)input m_axi_rmem16_RLAST;
+  (* RS_HS = "m_axi_rmem16_R.ready" *)output m_axi_rmem16_RREADY;
+  (* RS_HS = "m_axi_rmem16_R.data" *)input [1:0] m_axi_rmem16_RRESP;
+  (* RS_HS = "m_axi_rmem16_R.valid" *)input m_axi_rmem16_RVALID;
+  (* RS_HS = "m_axi_rmem16_W.data" *)output [511:0] m_axi_rmem16_WDATA;
+  (* RS_HS = "m_axi_rmem16_W.data" *)output m_axi_rmem16_WLAST;
+  (* RS_HS = "m_axi_rmem16_W.ready" *)input m_axi_rmem16_WREADY;
+  (* RS_HS = "m_axi_rmem16_W.data" *)output [63:0] m_axi_rmem16_WSTRB;
+  (* RS_HS = "m_axi_rmem16_W.valid" *)output m_axi_rmem16_WVALID;
+  (* RS_HS = "m_axi_rmem17_AR.data" *)output [63:0] m_axi_rmem17_ARADDR;
+  (* RS_HS = "m_axi_rmem17_AR.data" *)output [1:0] m_axi_rmem17_ARBURST;
+  (* RS_HS = "m_axi_rmem17_AR.data" *)output [3:0] m_axi_rmem17_ARCACHE;
+  (* RS_HS = "m_axi_rmem17_AR.data" *)output [1:0] m_axi_rmem17_ARID;
+  (* RS_HS = "m_axi_rmem17_AR.data" *)output [7:0] m_axi_rmem17_ARLEN;
+  (* RS_HS = "m_axi_rmem17_AR.data" *)output m_axi_rmem17_ARLOCK;
+  (* RS_HS = "m_axi_rmem17_AR.data" *)output [2:0] m_axi_rmem17_ARPROT;
+  (* RS_HS = "m_axi_rmem17_AR.data" *)output [3:0] m_axi_rmem17_ARQOS;
+  (* RS_HS = "m_axi_rmem17_AR.ready" *)input m_axi_rmem17_ARREADY;
+  (* RS_HS = "m_axi_rmem17_AR.data" *)output [2:0] m_axi_rmem17_ARSIZE;
+  (* RS_HS = "m_axi_rmem17_AR.valid" *)output m_axi_rmem17_ARVALID;
+  (* RS_HS = "m_axi_rmem17_AW.data" *)output [63:0] m_axi_rmem17_AWADDR;
+  (* RS_HS = "m_axi_rmem17_AW.data" *)output [1:0] m_axi_rmem17_AWBURST;
+  (* RS_HS = "m_axi_rmem17_AW.data" *)output [3:0] m_axi_rmem17_AWCACHE;
+  (* RS_HS = "m_axi_rmem17_AW.data" *)output [1:0] m_axi_rmem17_AWID;
+  (* RS_HS = "m_axi_rmem17_AW.data" *)output [7:0] m_axi_rmem17_AWLEN;
+  (* RS_HS = "m_axi_rmem17_AW.data" *)output m_axi_rmem17_AWLOCK;
+  (* RS_HS = "m_axi_rmem17_AW.data" *)output [2:0] m_axi_rmem17_AWPROT;
+  (* RS_HS = "m_axi_rmem17_AW.data" *)output [3:0] m_axi_rmem17_AWQOS;
+  (* RS_HS = "m_axi_rmem17_AW.ready" *)input m_axi_rmem17_AWREADY;
+  (* RS_HS = "m_axi_rmem17_AW.data" *)output [2:0] m_axi_rmem17_AWSIZE;
+  (* RS_HS = "m_axi_rmem17_AW.valid" *)output m_axi_rmem17_AWVALID;
+  (* RS_HS = "m_axi_rmem17_B.data" *)input [1:0] m_axi_rmem17_BID;
+  (* RS_HS = "m_axi_rmem17_B.ready" *)output m_axi_rmem17_BREADY;
+  (* RS_HS = "m_axi_rmem17_B.data" *)input [1:0] m_axi_rmem17_BRESP;
+  (* RS_HS = "m_axi_rmem17_B.valid" *)input m_axi_rmem17_BVALID;
+  (* RS_HS = "m_axi_rmem17_R.data" *)input [511:0] m_axi_rmem17_RDATA;
+  (* RS_HS = "m_axi_rmem17_R.data" *)input [1:0] m_axi_rmem17_RID;
+  (* RS_HS = "m_axi_rmem17_R.data" *)input m_axi_rmem17_RLAST;
+  (* RS_HS = "m_axi_rmem17_R.ready" *)output m_axi_rmem17_RREADY;
+  (* RS_HS = "m_axi_rmem17_R.data" *)input [1:0] m_axi_rmem17_RRESP;
+  (* RS_HS = "m_axi_rmem17_R.valid" *)input m_axi_rmem17_RVALID;
+  (* RS_HS = "m_axi_rmem17_W.data" *)output [511:0] m_axi_rmem17_WDATA;
+  (* RS_HS = "m_axi_rmem17_W.data" *)output m_axi_rmem17_WLAST;
+  (* RS_HS = "m_axi_rmem17_W.ready" *)input m_axi_rmem17_WREADY;
+  (* RS_HS = "m_axi_rmem17_W.data" *)output [63:0] m_axi_rmem17_WSTRB;
+  (* RS_HS = "m_axi_rmem17_W.valid" *)output m_axi_rmem17_WVALID;
+  (* RS_HS = "m_axi_rmem18_AR.data" *)output [63:0] m_axi_rmem18_ARADDR;
+  (* RS_HS = "m_axi_rmem18_AR.data" *)output [1:0] m_axi_rmem18_ARBURST;
+  (* RS_HS = "m_axi_rmem18_AR.data" *)output [3:0] m_axi_rmem18_ARCACHE;
+  (* RS_HS = "m_axi_rmem18_AR.data" *)output [1:0] m_axi_rmem18_ARID;
+  (* RS_HS = "m_axi_rmem18_AR.data" *)output [7:0] m_axi_rmem18_ARLEN;
+  (* RS_HS = "m_axi_rmem18_AR.data" *)output m_axi_rmem18_ARLOCK;
+  (* RS_HS = "m_axi_rmem18_AR.data" *)output [2:0] m_axi_rmem18_ARPROT;
+  (* RS_HS = "m_axi_rmem18_AR.data" *)output [3:0] m_axi_rmem18_ARQOS;
+  (* RS_HS = "m_axi_rmem18_AR.ready" *)input m_axi_rmem18_ARREADY;
+  (* RS_HS = "m_axi_rmem18_AR.data" *)output [2:0] m_axi_rmem18_ARSIZE;
+  (* RS_HS = "m_axi_rmem18_AR.valid" *)output m_axi_rmem18_ARVALID;
+  (* RS_HS = "m_axi_rmem18_AW.data" *)output [63:0] m_axi_rmem18_AWADDR;
+  (* RS_HS = "m_axi_rmem18_AW.data" *)output [1:0] m_axi_rmem18_AWBURST;
+  (* RS_HS = "m_axi_rmem18_AW.data" *)output [3:0] m_axi_rmem18_AWCACHE;
+  (* RS_HS = "m_axi_rmem18_AW.data" *)output [1:0] m_axi_rmem18_AWID;
+  (* RS_HS = "m_axi_rmem18_AW.data" *)output [7:0] m_axi_rmem18_AWLEN;
+  (* RS_HS = "m_axi_rmem18_AW.data" *)output m_axi_rmem18_AWLOCK;
+  (* RS_HS = "m_axi_rmem18_AW.data" *)output [2:0] m_axi_rmem18_AWPROT;
+  (* RS_HS = "m_axi_rmem18_AW.data" *)output [3:0] m_axi_rmem18_AWQOS;
+  (* RS_HS = "m_axi_rmem18_AW.ready" *)input m_axi_rmem18_AWREADY;
+  (* RS_HS = "m_axi_rmem18_AW.data" *)output [2:0] m_axi_rmem18_AWSIZE;
+  (* RS_HS = "m_axi_rmem18_AW.valid" *)output m_axi_rmem18_AWVALID;
+  (* RS_HS = "m_axi_rmem18_B.data" *)input [1:0] m_axi_rmem18_BID;
+  (* RS_HS = "m_axi_rmem18_B.ready" *)output m_axi_rmem18_BREADY;
+  (* RS_HS = "m_axi_rmem18_B.data" *)input [1:0] m_axi_rmem18_BRESP;
+  (* RS_HS = "m_axi_rmem18_B.valid" *)input m_axi_rmem18_BVALID;
+  (* RS_HS = "m_axi_rmem18_R.data" *)input [511:0] m_axi_rmem18_RDATA;
+  (* RS_HS = "m_axi_rmem18_R.data" *)input [1:0] m_axi_rmem18_RID;
+  (* RS_HS = "m_axi_rmem18_R.data" *)input m_axi_rmem18_RLAST;
+  (* RS_HS = "m_axi_rmem18_R.ready" *)output m_axi_rmem18_RREADY;
+  (* RS_HS = "m_axi_rmem18_R.data" *)input [1:0] m_axi_rmem18_RRESP;
+  (* RS_HS = "m_axi_rmem18_R.valid" *)input m_axi_rmem18_RVALID;
+  (* RS_HS = "m_axi_rmem18_W.data" *)output [511:0] m_axi_rmem18_WDATA;
+  (* RS_HS = "m_axi_rmem18_W.data" *)output m_axi_rmem18_WLAST;
+  (* RS_HS = "m_axi_rmem18_W.ready" *)input m_axi_rmem18_WREADY;
+  (* RS_HS = "m_axi_rmem18_W.data" *)output [63:0] m_axi_rmem18_WSTRB;
+  (* RS_HS = "m_axi_rmem18_W.valid" *)output m_axi_rmem18_WVALID;
+  (* RS_HS = "m_axi_rmem19_AR.data" *)output [63:0] m_axi_rmem19_ARADDR;
+  (* RS_HS = "m_axi_rmem19_AR.data" *)output [1:0] m_axi_rmem19_ARBURST;
+  (* RS_HS = "m_axi_rmem19_AR.data" *)output [3:0] m_axi_rmem19_ARCACHE;
+  (* RS_HS = "m_axi_rmem19_AR.data" *)output [1:0] m_axi_rmem19_ARID;
+  (* RS_HS = "m_axi_rmem19_AR.data" *)output [7:0] m_axi_rmem19_ARLEN;
+  (* RS_HS = "m_axi_rmem19_AR.data" *)output m_axi_rmem19_ARLOCK;
+  (* RS_HS = "m_axi_rmem19_AR.data" *)output [2:0] m_axi_rmem19_ARPROT;
+  (* RS_HS = "m_axi_rmem19_AR.data" *)output [3:0] m_axi_rmem19_ARQOS;
+  (* RS_HS = "m_axi_rmem19_AR.ready" *)input m_axi_rmem19_ARREADY;
+  (* RS_HS = "m_axi_rmem19_AR.data" *)output [2:0] m_axi_rmem19_ARSIZE;
+  (* RS_HS = "m_axi_rmem19_AR.valid" *)output m_axi_rmem19_ARVALID;
+  (* RS_HS = "m_axi_rmem19_AW.data" *)output [63:0] m_axi_rmem19_AWADDR;
+  (* RS_HS = "m_axi_rmem19_AW.data" *)output [1:0] m_axi_rmem19_AWBURST;
+  (* RS_HS = "m_axi_rmem19_AW.data" *)output [3:0] m_axi_rmem19_AWCACHE;
+  (* RS_HS = "m_axi_rmem19_AW.data" *)output [1:0] m_axi_rmem19_AWID;
+  (* RS_HS = "m_axi_rmem19_AW.data" *)output [7:0] m_axi_rmem19_AWLEN;
+  (* RS_HS = "m_axi_rmem19_AW.data" *)output m_axi_rmem19_AWLOCK;
+  (* RS_HS = "m_axi_rmem19_AW.data" *)output [2:0] m_axi_rmem19_AWPROT;
+  (* RS_HS = "m_axi_rmem19_AW.data" *)output [3:0] m_axi_rmem19_AWQOS;
+  (* RS_HS = "m_axi_rmem19_AW.ready" *)input m_axi_rmem19_AWREADY;
+  (* RS_HS = "m_axi_rmem19_AW.data" *)output [2:0] m_axi_rmem19_AWSIZE;
+  (* RS_HS = "m_axi_rmem19_AW.valid" *)output m_axi_rmem19_AWVALID;
+  (* RS_HS = "m_axi_rmem19_B.data" *)input [1:0] m_axi_rmem19_BID;
+  (* RS_HS = "m_axi_rmem19_B.ready" *)output m_axi_rmem19_BREADY;
+  (* RS_HS = "m_axi_rmem19_B.data" *)input [1:0] m_axi_rmem19_BRESP;
+  (* RS_HS = "m_axi_rmem19_B.valid" *)input m_axi_rmem19_BVALID;
+  (* RS_HS = "m_axi_rmem19_R.data" *)input [511:0] m_axi_rmem19_RDATA;
+  (* RS_HS = "m_axi_rmem19_R.data" *)input [1:0] m_axi_rmem19_RID;
+  (* RS_HS = "m_axi_rmem19_R.data" *)input m_axi_rmem19_RLAST;
+  (* RS_HS = "m_axi_rmem19_R.ready" *)output m_axi_rmem19_RREADY;
+  (* RS_HS = "m_axi_rmem19_R.data" *)input [1:0] m_axi_rmem19_RRESP;
+  (* RS_HS = "m_axi_rmem19_R.valid" *)input m_axi_rmem19_RVALID;
+  (* RS_HS = "m_axi_rmem19_W.data" *)output [511:0] m_axi_rmem19_WDATA;
+  (* RS_HS = "m_axi_rmem19_W.data" *)output m_axi_rmem19_WLAST;
+  (* RS_HS = "m_axi_rmem19_W.ready" *)input m_axi_rmem19_WREADY;
+  (* RS_HS = "m_axi_rmem19_W.data" *)output [63:0] m_axi_rmem19_WSTRB;
+  (* RS_HS = "m_axi_rmem19_W.valid" *)output m_axi_rmem19_WVALID;
+  (* RS_HS = "m_axi_rmem20_AR.data" *)output [63:0] m_axi_rmem20_ARADDR;
+  (* RS_HS = "m_axi_rmem20_AR.data" *)output [1:0] m_axi_rmem20_ARBURST;
+  (* RS_HS = "m_axi_rmem20_AR.data" *)output [3:0] m_axi_rmem20_ARCACHE;
+  (* RS_HS = "m_axi_rmem20_AR.data" *)output [1:0] m_axi_rmem20_ARID;
+  (* RS_HS = "m_axi_rmem20_AR.data" *)output [7:0] m_axi_rmem20_ARLEN;
+  (* RS_HS = "m_axi_rmem20_AR.data" *)output m_axi_rmem20_ARLOCK;
+  (* RS_HS = "m_axi_rmem20_AR.data" *)output [2:0] m_axi_rmem20_ARPROT;
+  (* RS_HS = "m_axi_rmem20_AR.data" *)output [3:0] m_axi_rmem20_ARQOS;
+  (* RS_HS = "m_axi_rmem20_AR.ready" *)input m_axi_rmem20_ARREADY;
+  (* RS_HS = "m_axi_rmem20_AR.data" *)output [2:0] m_axi_rmem20_ARSIZE;
+  (* RS_HS = "m_axi_rmem20_AR.valid" *)output m_axi_rmem20_ARVALID;
+  (* RS_HS = "m_axi_rmem20_AW.data" *)output [63:0] m_axi_rmem20_AWADDR;
+  (* RS_HS = "m_axi_rmem20_AW.data" *)output [1:0] m_axi_rmem20_AWBURST;
+  (* RS_HS = "m_axi_rmem20_AW.data" *)output [3:0] m_axi_rmem20_AWCACHE;
+  (* RS_HS = "m_axi_rmem20_AW.data" *)output [1:0] m_axi_rmem20_AWID;
+  (* RS_HS = "m_axi_rmem20_AW.data" *)output [7:0] m_axi_rmem20_AWLEN;
+  (* RS_HS = "m_axi_rmem20_AW.data" *)output m_axi_rmem20_AWLOCK;
+  (* RS_HS = "m_axi_rmem20_AW.data" *)output [2:0] m_axi_rmem20_AWPROT;
+  (* RS_HS = "m_axi_rmem20_AW.data" *)output [3:0] m_axi_rmem20_AWQOS;
+  (* RS_HS = "m_axi_rmem20_AW.ready" *)input m_axi_rmem20_AWREADY;
+  (* RS_HS = "m_axi_rmem20_AW.data" *)output [2:0] m_axi_rmem20_AWSIZE;
+  (* RS_HS = "m_axi_rmem20_AW.valid" *)output m_axi_rmem20_AWVALID;
+  (* RS_HS = "m_axi_rmem20_B.data" *)input [1:0] m_axi_rmem20_BID;
+  (* RS_HS = "m_axi_rmem20_B.ready" *)output m_axi_rmem20_BREADY;
+  (* RS_HS = "m_axi_rmem20_B.data" *)input [1:0] m_axi_rmem20_BRESP;
+  (* RS_HS = "m_axi_rmem20_B.valid" *)input m_axi_rmem20_BVALID;
+  (* RS_HS = "m_axi_rmem20_R.data" *)input [511:0] m_axi_rmem20_RDATA;
+  (* RS_HS = "m_axi_rmem20_R.data" *)input [1:0] m_axi_rmem20_RID;
+  (* RS_HS = "m_axi_rmem20_R.data" *)input m_axi_rmem20_RLAST;
+  (* RS_HS = "m_axi_rmem20_R.ready" *)output m_axi_rmem20_RREADY;
+  (* RS_HS = "m_axi_rmem20_R.data" *)input [1:0] m_axi_rmem20_RRESP;
+  (* RS_HS = "m_axi_rmem20_R.valid" *)input m_axi_rmem20_RVALID;
+  (* RS_HS = "m_axi_rmem20_W.data" *)output [511:0] m_axi_rmem20_WDATA;
+  (* RS_HS = "m_axi_rmem20_W.data" *)output m_axi_rmem20_WLAST;
+  (* RS_HS = "m_axi_rmem20_W.ready" *)input m_axi_rmem20_WREADY;
+  (* RS_HS = "m_axi_rmem20_W.data" *)output [63:0] m_axi_rmem20_WSTRB;
+  (* RS_HS = "m_axi_rmem20_W.valid" *)output m_axi_rmem20_WVALID;
+  (* RS_HS = "m_axi_rmem21_AR.data" *)output [63:0] m_axi_rmem21_ARADDR;
+  (* RS_HS = "m_axi_rmem21_AR.data" *)output [1:0] m_axi_rmem21_ARBURST;
+  (* RS_HS = "m_axi_rmem21_AR.data" *)output [3:0] m_axi_rmem21_ARCACHE;
+  (* RS_HS = "m_axi_rmem21_AR.data" *)output [1:0] m_axi_rmem21_ARID;
+  (* RS_HS = "m_axi_rmem21_AR.data" *)output [7:0] m_axi_rmem21_ARLEN;
+  (* RS_HS = "m_axi_rmem21_AR.data" *)output m_axi_rmem21_ARLOCK;
+  (* RS_HS = "m_axi_rmem21_AR.data" *)output [2:0] m_axi_rmem21_ARPROT;
+  (* RS_HS = "m_axi_rmem21_AR.data" *)output [3:0] m_axi_rmem21_ARQOS;
+  (* RS_HS = "m_axi_rmem21_AR.ready" *)input m_axi_rmem21_ARREADY;
+  (* RS_HS = "m_axi_rmem21_AR.data" *)output [2:0] m_axi_rmem21_ARSIZE;
+  (* RS_HS = "m_axi_rmem21_AR.valid" *)output m_axi_rmem21_ARVALID;
+  (* RS_HS = "m_axi_rmem21_AW.data" *)output [63:0] m_axi_rmem21_AWADDR;
+  (* RS_HS = "m_axi_rmem21_AW.data" *)output [1:0] m_axi_rmem21_AWBURST;
+  (* RS_HS = "m_axi_rmem21_AW.data" *)output [3:0] m_axi_rmem21_AWCACHE;
+  (* RS_HS = "m_axi_rmem21_AW.data" *)output [1:0] m_axi_rmem21_AWID;
+  (* RS_HS = "m_axi_rmem21_AW.data" *)output [7:0] m_axi_rmem21_AWLEN;
+  (* RS_HS = "m_axi_rmem21_AW.data" *)output m_axi_rmem21_AWLOCK;
+  (* RS_HS = "m_axi_rmem21_AW.data" *)output [2:0] m_axi_rmem21_AWPROT;
+  (* RS_HS = "m_axi_rmem21_AW.data" *)output [3:0] m_axi_rmem21_AWQOS;
+  (* RS_HS = "m_axi_rmem21_AW.ready" *)input m_axi_rmem21_AWREADY;
+  (* RS_HS = "m_axi_rmem21_AW.data" *)output [2:0] m_axi_rmem21_AWSIZE;
+  (* RS_HS = "m_axi_rmem21_AW.valid" *)output m_axi_rmem21_AWVALID;
+  (* RS_HS = "m_axi_rmem21_B.data" *)input [1:0] m_axi_rmem21_BID;
+  (* RS_HS = "m_axi_rmem21_B.ready" *)output m_axi_rmem21_BREADY;
+  (* RS_HS = "m_axi_rmem21_B.data" *)input [1:0] m_axi_rmem21_BRESP;
+  (* RS_HS = "m_axi_rmem21_B.valid" *)input m_axi_rmem21_BVALID;
+  (* RS_HS = "m_axi_rmem21_R.data" *)input [511:0] m_axi_rmem21_RDATA;
+  (* RS_HS = "m_axi_rmem21_R.data" *)input [1:0] m_axi_rmem21_RID;
+  (* RS_HS = "m_axi_rmem21_R.data" *)input m_axi_rmem21_RLAST;
+  (* RS_HS = "m_axi_rmem21_R.ready" *)output m_axi_rmem21_RREADY;
+  (* RS_HS = "m_axi_rmem21_R.data" *)input [1:0] m_axi_rmem21_RRESP;
+  (* RS_HS = "m_axi_rmem21_R.valid" *)input m_axi_rmem21_RVALID;
+  (* RS_HS = "m_axi_rmem21_W.data" *)output [511:0] m_axi_rmem21_WDATA;
+  (* RS_HS = "m_axi_rmem21_W.data" *)output m_axi_rmem21_WLAST;
+  (* RS_HS = "m_axi_rmem21_W.ready" *)input m_axi_rmem21_WREADY;
+  (* RS_HS = "m_axi_rmem21_W.data" *)output [63:0] m_axi_rmem21_WSTRB;
+  (* RS_HS = "m_axi_rmem21_W.valid" *)output m_axi_rmem21_WVALID;
+  (* RS_HS = "m_axi_rmem22_AR.data" *)output [63:0] m_axi_rmem22_ARADDR;
+  (* RS_HS = "m_axi_rmem22_AR.data" *)output [1:0] m_axi_rmem22_ARBURST;
+  (* RS_HS = "m_axi_rmem22_AR.data" *)output [3:0] m_axi_rmem22_ARCACHE;
+  (* RS_HS = "m_axi_rmem22_AR.data" *)output [1:0] m_axi_rmem22_ARID;
+  (* RS_HS = "m_axi_rmem22_AR.data" *)output [7:0] m_axi_rmem22_ARLEN;
+  (* RS_HS = "m_axi_rmem22_AR.data" *)output m_axi_rmem22_ARLOCK;
+  (* RS_HS = "m_axi_rmem22_AR.data" *)output [2:0] m_axi_rmem22_ARPROT;
+  (* RS_HS = "m_axi_rmem22_AR.data" *)output [3:0] m_axi_rmem22_ARQOS;
+  (* RS_HS = "m_axi_rmem22_AR.ready" *)input m_axi_rmem22_ARREADY;
+  (* RS_HS = "m_axi_rmem22_AR.data" *)output [2:0] m_axi_rmem22_ARSIZE;
+  (* RS_HS = "m_axi_rmem22_AR.valid" *)output m_axi_rmem22_ARVALID;
+  (* RS_HS = "m_axi_rmem22_AW.data" *)output [63:0] m_axi_rmem22_AWADDR;
+  (* RS_HS = "m_axi_rmem22_AW.data" *)output [1:0] m_axi_rmem22_AWBURST;
+  (* RS_HS = "m_axi_rmem22_AW.data" *)output [3:0] m_axi_rmem22_AWCACHE;
+  (* RS_HS = "m_axi_rmem22_AW.data" *)output [1:0] m_axi_rmem22_AWID;
+  (* RS_HS = "m_axi_rmem22_AW.data" *)output [7:0] m_axi_rmem22_AWLEN;
+  (* RS_HS = "m_axi_rmem22_AW.data" *)output m_axi_rmem22_AWLOCK;
+  (* RS_HS = "m_axi_rmem22_AW.data" *)output [2:0] m_axi_rmem22_AWPROT;
+  (* RS_HS = "m_axi_rmem22_AW.data" *)output [3:0] m_axi_rmem22_AWQOS;
+  (* RS_HS = "m_axi_rmem22_AW.ready" *)input m_axi_rmem22_AWREADY;
+  (* RS_HS = "m_axi_rmem22_AW.data" *)output [2:0] m_axi_rmem22_AWSIZE;
+  (* RS_HS = "m_axi_rmem22_AW.valid" *)output m_axi_rmem22_AWVALID;
+  (* RS_HS = "m_axi_rmem22_B.data" *)input [1:0] m_axi_rmem22_BID;
+  (* RS_HS = "m_axi_rmem22_B.ready" *)output m_axi_rmem22_BREADY;
+  (* RS_HS = "m_axi_rmem22_B.data" *)input [1:0] m_axi_rmem22_BRESP;
+  (* RS_HS = "m_axi_rmem22_B.valid" *)input m_axi_rmem22_BVALID;
+  (* RS_HS = "m_axi_rmem22_R.data" *)input [511:0] m_axi_rmem22_RDATA;
+  (* RS_HS = "m_axi_rmem22_R.data" *)input [1:0] m_axi_rmem22_RID;
+  (* RS_HS = "m_axi_rmem22_R.data" *)input m_axi_rmem22_RLAST;
+  (* RS_HS = "m_axi_rmem22_R.ready" *)output m_axi_rmem22_RREADY;
+  (* RS_HS = "m_axi_rmem22_R.data" *)input [1:0] m_axi_rmem22_RRESP;
+  (* RS_HS = "m_axi_rmem22_R.valid" *)input m_axi_rmem22_RVALID;
+  (* RS_HS = "m_axi_rmem22_W.data" *)output [511:0] m_axi_rmem22_WDATA;
+  (* RS_HS = "m_axi_rmem22_W.data" *)output m_axi_rmem22_WLAST;
+  (* RS_HS = "m_axi_rmem22_W.ready" *)input m_axi_rmem22_WREADY;
+  (* RS_HS = "m_axi_rmem22_W.data" *)output [63:0] m_axi_rmem22_WSTRB;
+  (* RS_HS = "m_axi_rmem22_W.valid" *)output m_axi_rmem22_WVALID;
+  (* RS_HS = "m_axi_rmem23_AR.data" *)output [63:0] m_axi_rmem23_ARADDR;
+  (* RS_HS = "m_axi_rmem23_AR.data" *)output [1:0] m_axi_rmem23_ARBURST;
+  (* RS_HS = "m_axi_rmem23_AR.data" *)output [3:0] m_axi_rmem23_ARCACHE;
+  (* RS_HS = "m_axi_rmem23_AR.data" *)output [1:0] m_axi_rmem23_ARID;
+  (* RS_HS = "m_axi_rmem23_AR.data" *)output [7:0] m_axi_rmem23_ARLEN;
+  (* RS_HS = "m_axi_rmem23_AR.data" *)output m_axi_rmem23_ARLOCK;
+  (* RS_HS = "m_axi_rmem23_AR.data" *)output [2:0] m_axi_rmem23_ARPROT;
+  (* RS_HS = "m_axi_rmem23_AR.data" *)output [3:0] m_axi_rmem23_ARQOS;
+  (* RS_HS = "m_axi_rmem23_AR.ready" *)input m_axi_rmem23_ARREADY;
+  (* RS_HS = "m_axi_rmem23_AR.data" *)output [2:0] m_axi_rmem23_ARSIZE;
+  (* RS_HS = "m_axi_rmem23_AR.valid" *)output m_axi_rmem23_ARVALID;
+  (* RS_HS = "m_axi_rmem23_AW.data" *)output [63:0] m_axi_rmem23_AWADDR;
+  (* RS_HS = "m_axi_rmem23_AW.data" *)output [1:0] m_axi_rmem23_AWBURST;
+  (* RS_HS = "m_axi_rmem23_AW.data" *)output [3:0] m_axi_rmem23_AWCACHE;
+  (* RS_HS = "m_axi_rmem23_AW.data" *)output [1:0] m_axi_rmem23_AWID;
+  (* RS_HS = "m_axi_rmem23_AW.data" *)output [7:0] m_axi_rmem23_AWLEN;
+  (* RS_HS = "m_axi_rmem23_AW.data" *)output m_axi_rmem23_AWLOCK;
+  (* RS_HS = "m_axi_rmem23_AW.data" *)output [2:0] m_axi_rmem23_AWPROT;
+  (* RS_HS = "m_axi_rmem23_AW.data" *)output [3:0] m_axi_rmem23_AWQOS;
+  (* RS_HS = "m_axi_rmem23_AW.ready" *)input m_axi_rmem23_AWREADY;
+  (* RS_HS = "m_axi_rmem23_AW.data" *)output [2:0] m_axi_rmem23_AWSIZE;
+  (* RS_HS = "m_axi_rmem23_AW.valid" *)output m_axi_rmem23_AWVALID;
+  (* RS_HS = "m_axi_rmem23_B.data" *)input [1:0] m_axi_rmem23_BID;
+  (* RS_HS = "m_axi_rmem23_B.ready" *)output m_axi_rmem23_BREADY;
+  (* RS_HS = "m_axi_rmem23_B.data" *)input [1:0] m_axi_rmem23_BRESP;
+  (* RS_HS = "m_axi_rmem23_B.valid" *)input m_axi_rmem23_BVALID;
+  (* RS_HS = "m_axi_rmem23_R.data" *)input [511:0] m_axi_rmem23_RDATA;
+  (* RS_HS = "m_axi_rmem23_R.data" *)input [1:0] m_axi_rmem23_RID;
+  (* RS_HS = "m_axi_rmem23_R.data" *)input m_axi_rmem23_RLAST;
+  (* RS_HS = "m_axi_rmem23_R.ready" *)output m_axi_rmem23_RREADY;
+  (* RS_HS = "m_axi_rmem23_R.data" *)input [1:0] m_axi_rmem23_RRESP;
+  (* RS_HS = "m_axi_rmem23_R.valid" *)input m_axi_rmem23_RVALID;
+  (* RS_HS = "m_axi_rmem23_W.data" *)output [511:0] m_axi_rmem23_WDATA;
+  (* RS_HS = "m_axi_rmem23_W.data" *)output m_axi_rmem23_WLAST;
+  (* RS_HS = "m_axi_rmem23_W.ready" *)input m_axi_rmem23_WREADY;
+  (* RS_HS = "m_axi_rmem23_W.data" *)output [63:0] m_axi_rmem23_WSTRB;
+  (* RS_HS = "m_axi_rmem23_W.valid" *)output m_axi_rmem23_WVALID;
+  (* RS_HS = "m_axi_rmem24_AR.data" *)output [63:0] m_axi_rmem24_ARADDR;
+  (* RS_HS = "m_axi_rmem24_AR.data" *)output [1:0] m_axi_rmem24_ARBURST;
+  (* RS_HS = "m_axi_rmem24_AR.data" *)output [3:0] m_axi_rmem24_ARCACHE;
+  (* RS_HS = "m_axi_rmem24_AR.data" *)output [1:0] m_axi_rmem24_ARID;
+  (* RS_HS = "m_axi_rmem24_AR.data" *)output [7:0] m_axi_rmem24_ARLEN;
+  (* RS_HS = "m_axi_rmem24_AR.data" *)output m_axi_rmem24_ARLOCK;
+  (* RS_HS = "m_axi_rmem24_AR.data" *)output [2:0] m_axi_rmem24_ARPROT;
+  (* RS_HS = "m_axi_rmem24_AR.data" *)output [3:0] m_axi_rmem24_ARQOS;
+  (* RS_HS = "m_axi_rmem24_AR.ready" *)input m_axi_rmem24_ARREADY;
+  (* RS_HS = "m_axi_rmem24_AR.data" *)output [2:0] m_axi_rmem24_ARSIZE;
+  (* RS_HS = "m_axi_rmem24_AR.valid" *)output m_axi_rmem24_ARVALID;
+  (* RS_HS = "m_axi_rmem24_AW.data" *)output [63:0] m_axi_rmem24_AWADDR;
+  (* RS_HS = "m_axi_rmem24_AW.data" *)output [1:0] m_axi_rmem24_AWBURST;
+  (* RS_HS = "m_axi_rmem24_AW.data" *)output [3:0] m_axi_rmem24_AWCACHE;
+  (* RS_HS = "m_axi_rmem24_AW.data" *)output [1:0] m_axi_rmem24_AWID;
+  (* RS_HS = "m_axi_rmem24_AW.data" *)output [7:0] m_axi_rmem24_AWLEN;
+  (* RS_HS = "m_axi_rmem24_AW.data" *)output m_axi_rmem24_AWLOCK;
+  (* RS_HS = "m_axi_rmem24_AW.data" *)output [2:0] m_axi_rmem24_AWPROT;
+  (* RS_HS = "m_axi_rmem24_AW.data" *)output [3:0] m_axi_rmem24_AWQOS;
+  (* RS_HS = "m_axi_rmem24_AW.ready" *)input m_axi_rmem24_AWREADY;
+  (* RS_HS = "m_axi_rmem24_AW.data" *)output [2:0] m_axi_rmem24_AWSIZE;
+  (* RS_HS = "m_axi_rmem24_AW.valid" *)output m_axi_rmem24_AWVALID;
+  (* RS_HS = "m_axi_rmem24_B.data" *)input [1:0] m_axi_rmem24_BID;
+  (* RS_HS = "m_axi_rmem24_B.ready" *)output m_axi_rmem24_BREADY;
+  (* RS_HS = "m_axi_rmem24_B.data" *)input [1:0] m_axi_rmem24_BRESP;
+  (* RS_HS = "m_axi_rmem24_B.valid" *)input m_axi_rmem24_BVALID;
+  (* RS_HS = "m_axi_rmem24_R.data" *)input [511:0] m_axi_rmem24_RDATA;
+  (* RS_HS = "m_axi_rmem24_R.data" *)input [1:0] m_axi_rmem24_RID;
+  (* RS_HS = "m_axi_rmem24_R.data" *)input m_axi_rmem24_RLAST;
+  (* RS_HS = "m_axi_rmem24_R.ready" *)output m_axi_rmem24_RREADY;
+  (* RS_HS = "m_axi_rmem24_R.data" *)input [1:0] m_axi_rmem24_RRESP;
+  (* RS_HS = "m_axi_rmem24_R.valid" *)input m_axi_rmem24_RVALID;
+  (* RS_HS = "m_axi_rmem24_W.data" *)output [511:0] m_axi_rmem24_WDATA;
+  (* RS_HS = "m_axi_rmem24_W.data" *)output m_axi_rmem24_WLAST;
+  (* RS_HS = "m_axi_rmem24_W.ready" *)input m_axi_rmem24_WREADY;
+  (* RS_HS = "m_axi_rmem24_W.data" *)output [63:0] m_axi_rmem24_WSTRB;
+  (* RS_HS = "m_axi_rmem24_W.valid" *)output m_axi_rmem24_WVALID;
+  (* RS_HS = "m_axi_rmem25_AR.data" *)output [63:0] m_axi_rmem25_ARADDR;
+  (* RS_HS = "m_axi_rmem25_AR.data" *)output [1:0] m_axi_rmem25_ARBURST;
+  (* RS_HS = "m_axi_rmem25_AR.data" *)output [3:0] m_axi_rmem25_ARCACHE;
+  (* RS_HS = "m_axi_rmem25_AR.data" *)output [1:0] m_axi_rmem25_ARID;
+  (* RS_HS = "m_axi_rmem25_AR.data" *)output [7:0] m_axi_rmem25_ARLEN;
+  (* RS_HS = "m_axi_rmem25_AR.data" *)output m_axi_rmem25_ARLOCK;
+  (* RS_HS = "m_axi_rmem25_AR.data" *)output [2:0] m_axi_rmem25_ARPROT;
+  (* RS_HS = "m_axi_rmem25_AR.data" *)output [3:0] m_axi_rmem25_ARQOS;
+  (* RS_HS = "m_axi_rmem25_AR.ready" *)input m_axi_rmem25_ARREADY;
+  (* RS_HS = "m_axi_rmem25_AR.data" *)output [2:0] m_axi_rmem25_ARSIZE;
+  (* RS_HS = "m_axi_rmem25_AR.valid" *)output m_axi_rmem25_ARVALID;
+  (* RS_HS = "m_axi_rmem25_AW.data" *)output [63:0] m_axi_rmem25_AWADDR;
+  (* RS_HS = "m_axi_rmem25_AW.data" *)output [1:0] m_axi_rmem25_AWBURST;
+  (* RS_HS = "m_axi_rmem25_AW.data" *)output [3:0] m_axi_rmem25_AWCACHE;
+  (* RS_HS = "m_axi_rmem25_AW.data" *)output [1:0] m_axi_rmem25_AWID;
+  (* RS_HS = "m_axi_rmem25_AW.data" *)output [7:0] m_axi_rmem25_AWLEN;
+  (* RS_HS = "m_axi_rmem25_AW.data" *)output m_axi_rmem25_AWLOCK;
+  (* RS_HS = "m_axi_rmem25_AW.data" *)output [2:0] m_axi_rmem25_AWPROT;
+  (* RS_HS = "m_axi_rmem25_AW.data" *)output [3:0] m_axi_rmem25_AWQOS;
+  (* RS_HS = "m_axi_rmem25_AW.ready" *)input m_axi_rmem25_AWREADY;
+  (* RS_HS = "m_axi_rmem25_AW.data" *)output [2:0] m_axi_rmem25_AWSIZE;
+  (* RS_HS = "m_axi_rmem25_AW.valid" *)output m_axi_rmem25_AWVALID;
+  (* RS_HS = "m_axi_rmem25_B.data" *)input [1:0] m_axi_rmem25_BID;
+  (* RS_HS = "m_axi_rmem25_B.ready" *)output m_axi_rmem25_BREADY;
+  (* RS_HS = "m_axi_rmem25_B.data" *)input [1:0] m_axi_rmem25_BRESP;
+  (* RS_HS = "m_axi_rmem25_B.valid" *)input m_axi_rmem25_BVALID;
+  (* RS_HS = "m_axi_rmem25_R.data" *)input [511:0] m_axi_rmem25_RDATA;
+  (* RS_HS = "m_axi_rmem25_R.data" *)input [1:0] m_axi_rmem25_RID;
+  (* RS_HS = "m_axi_rmem25_R.data" *)input m_axi_rmem25_RLAST;
+  (* RS_HS = "m_axi_rmem25_R.ready" *)output m_axi_rmem25_RREADY;
+  (* RS_HS = "m_axi_rmem25_R.data" *)input [1:0] m_axi_rmem25_RRESP;
+  (* RS_HS = "m_axi_rmem25_R.valid" *)input m_axi_rmem25_RVALID;
+  (* RS_HS = "m_axi_rmem25_W.data" *)output [511:0] m_axi_rmem25_WDATA;
+  (* RS_HS = "m_axi_rmem25_W.data" *)output m_axi_rmem25_WLAST;
+  (* RS_HS = "m_axi_rmem25_W.ready" *)input m_axi_rmem25_WREADY;
+  (* RS_HS = "m_axi_rmem25_W.data" *)output [63:0] m_axi_rmem25_WSTRB;
+  (* RS_HS = "m_axi_rmem25_W.valid" *)output m_axi_rmem25_WVALID;
+  (* RS_HS = "m_axi_rmem26_AR.data" *)output [63:0] m_axi_rmem26_ARADDR;
+  (* RS_HS = "m_axi_rmem26_AR.data" *)output [1:0] m_axi_rmem26_ARBURST;
+  (* RS_HS = "m_axi_rmem26_AR.data" *)output [3:0] m_axi_rmem26_ARCACHE;
+  (* RS_HS = "m_axi_rmem26_AR.data" *)output [1:0] m_axi_rmem26_ARID;
+  (* RS_HS = "m_axi_rmem26_AR.data" *)output [7:0] m_axi_rmem26_ARLEN;
+  (* RS_HS = "m_axi_rmem26_AR.data" *)output m_axi_rmem26_ARLOCK;
+  (* RS_HS = "m_axi_rmem26_AR.data" *)output [2:0] m_axi_rmem26_ARPROT;
+  (* RS_HS = "m_axi_rmem26_AR.data" *)output [3:0] m_axi_rmem26_ARQOS;
+  (* RS_HS = "m_axi_rmem26_AR.ready" *)input m_axi_rmem26_ARREADY;
+  (* RS_HS = "m_axi_rmem26_AR.data" *)output [2:0] m_axi_rmem26_ARSIZE;
+  (* RS_HS = "m_axi_rmem26_AR.valid" *)output m_axi_rmem26_ARVALID;
+  (* RS_HS = "m_axi_rmem26_AW.data" *)output [63:0] m_axi_rmem26_AWADDR;
+  (* RS_HS = "m_axi_rmem26_AW.data" *)output [1:0] m_axi_rmem26_AWBURST;
+  (* RS_HS = "m_axi_rmem26_AW.data" *)output [3:0] m_axi_rmem26_AWCACHE;
+  (* RS_HS = "m_axi_rmem26_AW.data" *)output [1:0] m_axi_rmem26_AWID;
+  (* RS_HS = "m_axi_rmem26_AW.data" *)output [7:0] m_axi_rmem26_AWLEN;
+  (* RS_HS = "m_axi_rmem26_AW.data" *)output m_axi_rmem26_AWLOCK;
+  (* RS_HS = "m_axi_rmem26_AW.data" *)output [2:0] m_axi_rmem26_AWPROT;
+  (* RS_HS = "m_axi_rmem26_AW.data" *)output [3:0] m_axi_rmem26_AWQOS;
+  (* RS_HS = "m_axi_rmem26_AW.ready" *)input m_axi_rmem26_AWREADY;
+  (* RS_HS = "m_axi_rmem26_AW.data" *)output [2:0] m_axi_rmem26_AWSIZE;
+  (* RS_HS = "m_axi_rmem26_AW.valid" *)output m_axi_rmem26_AWVALID;
+  (* RS_HS = "m_axi_rmem26_B.data" *)input [1:0] m_axi_rmem26_BID;
+  (* RS_HS = "m_axi_rmem26_B.ready" *)output m_axi_rmem26_BREADY;
+  (* RS_HS = "m_axi_rmem26_B.data" *)input [1:0] m_axi_rmem26_BRESP;
+  (* RS_HS = "m_axi_rmem26_B.valid" *)input m_axi_rmem26_BVALID;
+  (* RS_HS = "m_axi_rmem26_R.data" *)input [511:0] m_axi_rmem26_RDATA;
+  (* RS_HS = "m_axi_rmem26_R.data" *)input [1:0] m_axi_rmem26_RID;
+  (* RS_HS = "m_axi_rmem26_R.data" *)input m_axi_rmem26_RLAST;
+  (* RS_HS = "m_axi_rmem26_R.ready" *)output m_axi_rmem26_RREADY;
+  (* RS_HS = "m_axi_rmem26_R.data" *)input [1:0] m_axi_rmem26_RRESP;
+  (* RS_HS = "m_axi_rmem26_R.valid" *)input m_axi_rmem26_RVALID;
+  (* RS_HS = "m_axi_rmem26_W.data" *)output [511:0] m_axi_rmem26_WDATA;
+  (* RS_HS = "m_axi_rmem26_W.data" *)output m_axi_rmem26_WLAST;
+  (* RS_HS = "m_axi_rmem26_W.ready" *)input m_axi_rmem26_WREADY;
+  (* RS_HS = "m_axi_rmem26_W.data" *)output [63:0] m_axi_rmem26_WSTRB;
+  (* RS_HS = "m_axi_rmem26_W.valid" *)output m_axi_rmem26_WVALID;
+  (* RS_HS = "m_axi_rmem27_AR.data" *)output [63:0] m_axi_rmem27_ARADDR;
+  (* RS_HS = "m_axi_rmem27_AR.data" *)output [1:0] m_axi_rmem27_ARBURST;
+  (* RS_HS = "m_axi_rmem27_AR.data" *)output [3:0] m_axi_rmem27_ARCACHE;
+  (* RS_HS = "m_axi_rmem27_AR.data" *)output [1:0] m_axi_rmem27_ARID;
+  (* RS_HS = "m_axi_rmem27_AR.data" *)output [7:0] m_axi_rmem27_ARLEN;
+  (* RS_HS = "m_axi_rmem27_AR.data" *)output m_axi_rmem27_ARLOCK;
+  (* RS_HS = "m_axi_rmem27_AR.data" *)output [2:0] m_axi_rmem27_ARPROT;
+  (* RS_HS = "m_axi_rmem27_AR.data" *)output [3:0] m_axi_rmem27_ARQOS;
+  (* RS_HS = "m_axi_rmem27_AR.ready" *)input m_axi_rmem27_ARREADY;
+  (* RS_HS = "m_axi_rmem27_AR.data" *)output [2:0] m_axi_rmem27_ARSIZE;
+  (* RS_HS = "m_axi_rmem27_AR.valid" *)output m_axi_rmem27_ARVALID;
+  (* RS_HS = "m_axi_rmem27_AW.data" *)output [63:0] m_axi_rmem27_AWADDR;
+  (* RS_HS = "m_axi_rmem27_AW.data" *)output [1:0] m_axi_rmem27_AWBURST;
+  (* RS_HS = "m_axi_rmem27_AW.data" *)output [3:0] m_axi_rmem27_AWCACHE;
+  (* RS_HS = "m_axi_rmem27_AW.data" *)output [1:0] m_axi_rmem27_AWID;
+  (* RS_HS = "m_axi_rmem27_AW.data" *)output [7:0] m_axi_rmem27_AWLEN;
+  (* RS_HS = "m_axi_rmem27_AW.data" *)output m_axi_rmem27_AWLOCK;
+  (* RS_HS = "m_axi_rmem27_AW.data" *)output [2:0] m_axi_rmem27_AWPROT;
+  (* RS_HS = "m_axi_rmem27_AW.data" *)output [3:0] m_axi_rmem27_AWQOS;
+  (* RS_HS = "m_axi_rmem27_AW.ready" *)input m_axi_rmem27_AWREADY;
+  (* RS_HS = "m_axi_rmem27_AW.data" *)output [2:0] m_axi_rmem27_AWSIZE;
+  (* RS_HS = "m_axi_rmem27_AW.valid" *)output m_axi_rmem27_AWVALID;
+  (* RS_HS = "m_axi_rmem27_B.data" *)input [1:0] m_axi_rmem27_BID;
+  (* RS_HS = "m_axi_rmem27_B.ready" *)output m_axi_rmem27_BREADY;
+  (* RS_HS = "m_axi_rmem27_B.data" *)input [1:0] m_axi_rmem27_BRESP;
+  (* RS_HS = "m_axi_rmem27_B.valid" *)input m_axi_rmem27_BVALID;
+  (* RS_HS = "m_axi_rmem27_R.data" *)input [511:0] m_axi_rmem27_RDATA;
+  (* RS_HS = "m_axi_rmem27_R.data" *)input [1:0] m_axi_rmem27_RID;
+  (* RS_HS = "m_axi_rmem27_R.data" *)input m_axi_rmem27_RLAST;
+  (* RS_HS = "m_axi_rmem27_R.ready" *)output m_axi_rmem27_RREADY;
+  (* RS_HS = "m_axi_rmem27_R.data" *)input [1:0] m_axi_rmem27_RRESP;
+  (* RS_HS = "m_axi_rmem27_R.valid" *)input m_axi_rmem27_RVALID;
+  (* RS_HS = "m_axi_rmem27_W.data" *)output [511:0] m_axi_rmem27_WDATA;
+  (* RS_HS = "m_axi_rmem27_W.data" *)output m_axi_rmem27_WLAST;
+  (* RS_HS = "m_axi_rmem27_W.ready" *)input m_axi_rmem27_WREADY;
+  (* RS_HS = "m_axi_rmem27_W.data" *)output [63:0] m_axi_rmem27_WSTRB;
+  (* RS_HS = "m_axi_rmem27_W.valid" *)output m_axi_rmem27_WVALID;
+  wire ap_start;
+  wire [63:0] rmem0;
+  wire [63:0] rmem1;
+  wire [63:0] rmem2;
+  wire [63:0] rmem3;
+  wire [63:0] rmem4;
+  wire [63:0] rmem5;
+  wire [63:0] rmem6;
+  wire [63:0] rmem7;
+  wire [63:0] rmem8;
+  wire [63:0] rmem9;
+  wire [63:0] rmem10;
+  wire [63:0] rmem11;
+  wire [63:0] rmem12;
+  wire [63:0] rmem13;
+  wire [63:0] rmem14;
+  wire [63:0] rmem15;
+  wire [63:0] rmem16;
+  wire [63:0] rmem17;
+  wire [63:0] rmem18;
+  wire [63:0] rmem19;
+  wire [63:0] rmem20;
+  wire [63:0] rmem21;
+  wire [63:0] rmem22;
+  wire [63:0] rmem23;
+  wire [63:0] rmem24;
+  wire [63:0] rmem25;
+  wire [63:0] rmem26;
+  wire [63:0] rmem27;
+  wire [63:0] n;
+  wire [512:0] qr0_vadd_bw__dout;
+  wire qr0_vadd_bw__empty_n;
+  wire qr0_vadd_bw__read;
+  wire [512:0] qr0_vadd_bw__din;
+  wire qr0_vadd_bw__full_n;
+  wire qr0_vadd_bw__write;
+  wire [512:0] qr10_vadd_bw__dout;
+  wire qr10_vadd_bw__empty_n;
+  wire qr10_vadd_bw__read;
+  wire [512:0] qr10_vadd_bw__din;
+  wire qr10_vadd_bw__full_n;
+  wire qr10_vadd_bw__write;
+  wire [512:0] qr11_vadd_bw__dout;
+  wire qr11_vadd_bw__empty_n;
+  wire qr11_vadd_bw__read;
+  wire [512:0] qr11_vadd_bw__din;
+  wire qr11_vadd_bw__full_n;
+  wire qr11_vadd_bw__write;
+  wire [512:0] qr12_vadd_bw__dout;
+  wire qr12_vadd_bw__empty_n;
+  wire qr12_vadd_bw__read;
+  wire [512:0] qr12_vadd_bw__din;
+  wire qr12_vadd_bw__full_n;
+  wire qr12_vadd_bw__write;
+  wire [512:0] qr13_vadd_bw__dout;
+  wire qr13_vadd_bw__empty_n;
+  wire qr13_vadd_bw__read;
+  wire [512:0] qr13_vadd_bw__din;
+  wire qr13_vadd_bw__full_n;
+  wire qr13_vadd_bw__write;
+  wire [512:0] qr14_vadd_bw__dout;
+  wire qr14_vadd_bw__empty_n;
+  wire qr14_vadd_bw__read;
+  wire [512:0] qr14_vadd_bw__din;
+  wire qr14_vadd_bw__full_n;
+  wire qr14_vadd_bw__write;
+  wire [512:0] qr15_vadd_bw__dout;
+  wire qr15_vadd_bw__empty_n;
+  wire qr15_vadd_bw__read;
+  wire [512:0] qr15_vadd_bw__din;
+  wire qr15_vadd_bw__full_n;
+  wire qr15_vadd_bw__write;
+  wire [512:0] qr16_vadd_bw__dout;
+  wire qr16_vadd_bw__empty_n;
+  wire qr16_vadd_bw__read;
+  wire [512:0] qr16_vadd_bw__din;
+  wire qr16_vadd_bw__full_n;
+  wire qr16_vadd_bw__write;
+  wire [512:0] qr17_vadd_bw__dout;
+  wire qr17_vadd_bw__empty_n;
+  wire qr17_vadd_bw__read;
+  wire [512:0] qr17_vadd_bw__din;
+  wire qr17_vadd_bw__full_n;
+  wire qr17_vadd_bw__write;
+  wire [512:0] qr18_vadd_bw__dout;
+  wire qr18_vadd_bw__empty_n;
+  wire qr18_vadd_bw__read;
+  wire [512:0] qr18_vadd_bw__din;
+  wire qr18_vadd_bw__full_n;
+  wire qr18_vadd_bw__write;
+  wire [512:0] qr19_vadd_bw__dout;
+  wire qr19_vadd_bw__empty_n;
+  wire qr19_vadd_bw__read;
+  wire [512:0] qr19_vadd_bw__din;
+  wire qr19_vadd_bw__full_n;
+  wire qr19_vadd_bw__write;
+  wire [512:0] qr1_vadd_bw__dout;
+  wire qr1_vadd_bw__empty_n;
+  wire qr1_vadd_bw__read;
+  wire [512:0] qr1_vadd_bw__din;
+  wire qr1_vadd_bw__full_n;
+  wire qr1_vadd_bw__write;
+  wire [512:0] qr20_vadd_bw__dout;
+  wire qr20_vadd_bw__empty_n;
+  wire qr20_vadd_bw__read;
+  wire [512:0] qr20_vadd_bw__din;
+  wire qr20_vadd_bw__full_n;
+  wire qr20_vadd_bw__write;
+  wire [512:0] qr21_vadd_bw__dout;
+  wire qr21_vadd_bw__empty_n;
+  wire qr21_vadd_bw__read;
+  wire [512:0] qr21_vadd_bw__din;
+  wire qr21_vadd_bw__full_n;
+  wire qr21_vadd_bw__write;
+  wire [512:0] qr22_vadd_bw__dout;
+  wire qr22_vadd_bw__empty_n;
+  wire qr22_vadd_bw__read;
+  wire [512:0] qr22_vadd_bw__din;
+  wire qr22_vadd_bw__full_n;
+  wire qr22_vadd_bw__write;
+  wire [512:0] qr23_vadd_bw__dout;
+  wire qr23_vadd_bw__empty_n;
+  wire qr23_vadd_bw__read;
+  wire [512:0] qr23_vadd_bw__din;
+  wire qr23_vadd_bw__full_n;
+  wire qr23_vadd_bw__write;
+  wire [512:0] qr24_vadd_bw__dout;
+  wire qr24_vadd_bw__empty_n;
+  wire qr24_vadd_bw__read;
+  wire [512:0] qr24_vadd_bw__din;
+  wire qr24_vadd_bw__full_n;
+  wire qr24_vadd_bw__write;
+  wire [512:0] qr25_vadd_bw__dout;
+  wire qr25_vadd_bw__empty_n;
+  wire qr25_vadd_bw__read;
+  wire [512:0] qr25_vadd_bw__din;
+  wire qr25_vadd_bw__full_n;
+  wire qr25_vadd_bw__write;
+  wire [512:0] qr26_vadd_bw__dout;
+  wire qr26_vadd_bw__empty_n;
+  wire qr26_vadd_bw__read;
+  wire [512:0] qr26_vadd_bw__din;
+  wire qr26_vadd_bw__full_n;
+  wire qr26_vadd_bw__write;
+  wire [512:0] qr27_vadd_bw__dout;
+  wire qr27_vadd_bw__empty_n;
+  wire qr27_vadd_bw__read;
+  wire [512:0] qr27_vadd_bw__din;
+  wire qr27_vadd_bw__full_n;
+  wire qr27_vadd_bw__write;
+  wire [512:0] qr2_vadd_bw__dout;
+  wire qr2_vadd_bw__empty_n;
+  wire qr2_vadd_bw__read;
+  wire [512:0] qr2_vadd_bw__din;
+  wire qr2_vadd_bw__full_n;
+  wire qr2_vadd_bw__write;
+  wire [512:0] qr3_vadd_bw__dout;
+  wire qr3_vadd_bw__empty_n;
+  wire qr3_vadd_bw__read;
+  wire [512:0] qr3_vadd_bw__din;
+  wire qr3_vadd_bw__full_n;
+  wire qr3_vadd_bw__write;
+  wire [512:0] qr4_vadd_bw__dout;
+  wire qr4_vadd_bw__empty_n;
+  wire qr4_vadd_bw__read;
+  wire [512:0] qr4_vadd_bw__din;
+  wire qr4_vadd_bw__full_n;
+  wire qr4_vadd_bw__write;
+  wire [512:0] qr5_vadd_bw__dout;
+  wire qr5_vadd_bw__empty_n;
+  wire qr5_vadd_bw__read;
+  wire [512:0] qr5_vadd_bw__din;
+  wire qr5_vadd_bw__full_n;
+  wire qr5_vadd_bw__write;
+  wire [512:0] qr6_vadd_bw__dout;
+  wire qr6_vadd_bw__empty_n;
+  wire qr6_vadd_bw__read;
+  wire [512:0] qr6_vadd_bw__din;
+  wire qr6_vadd_bw__full_n;
+  wire qr6_vadd_bw__write;
+  wire [512:0] qr7_vadd_bw__dout;
+  wire qr7_vadd_bw__empty_n;
+  wire qr7_vadd_bw__read;
+  wire [512:0] qr7_vadd_bw__din;
+  wire qr7_vadd_bw__full_n;
+  wire qr7_vadd_bw__write;
+  wire [512:0] qr8_vadd_bw__dout;
+  wire qr8_vadd_bw__empty_n;
+  wire qr8_vadd_bw__read;
+  wire [512:0] qr8_vadd_bw__din;
+  wire qr8_vadd_bw__full_n;
+  wire qr8_vadd_bw__write;
+  wire [512:0] qr9_vadd_bw__dout;
+  wire qr9_vadd_bw__empty_n;
+  wire qr9_vadd_bw__read;
+  wire [512:0] qr9_vadd_bw__din;
+  wire qr9_vadd_bw__full_n;
+  wire qr9_vadd_bw__write;
+  wire [512:0] qw0_vadd_bw__dout;
+  wire qw0_vadd_bw__empty_n;
+  wire qw0_vadd_bw__read;
+  wire [512:0] qw0_vadd_bw__din;
+  wire qw0_vadd_bw__full_n;
+  wire qw0_vadd_bw__write;
+  wire [512:0] qw10_vadd_bw__dout;
+  wire qw10_vadd_bw__empty_n;
+  wire qw10_vadd_bw__read;
+  wire [512:0] qw10_vadd_bw__din;
+  wire qw10_vadd_bw__full_n;
+  wire qw10_vadd_bw__write;
+  wire [512:0] qw11_vadd_bw__dout;
+  wire qw11_vadd_bw__empty_n;
+  wire qw11_vadd_bw__read;
+  wire [512:0] qw11_vadd_bw__din;
+  wire qw11_vadd_bw__full_n;
+  wire qw11_vadd_bw__write;
+  wire [512:0] qw12_vadd_bw__dout;
+  wire qw12_vadd_bw__empty_n;
+  wire qw12_vadd_bw__read;
+  wire [512:0] qw12_vadd_bw__din;
+  wire qw12_vadd_bw__full_n;
+  wire qw12_vadd_bw__write;
+  wire [512:0] qw13_vadd_bw__dout;
+  wire qw13_vadd_bw__empty_n;
+  wire qw13_vadd_bw__read;
+  wire [512:0] qw13_vadd_bw__din;
+  wire qw13_vadd_bw__full_n;
+  wire qw13_vadd_bw__write;
+  wire [512:0] qw14_vadd_bw__dout;
+  wire qw14_vadd_bw__empty_n;
+  wire qw14_vadd_bw__read;
+  wire [512:0] qw14_vadd_bw__din;
+  wire qw14_vadd_bw__full_n;
+  wire qw14_vadd_bw__write;
+  wire [512:0] qw15_vadd_bw__dout;
+  wire qw15_vadd_bw__empty_n;
+  wire qw15_vadd_bw__read;
+  wire [512:0] qw15_vadd_bw__din;
+  wire qw15_vadd_bw__full_n;
+  wire qw15_vadd_bw__write;
+  wire [512:0] qw16_vadd_bw__dout;
+  wire qw16_vadd_bw__empty_n;
+  wire qw16_vadd_bw__read;
+  wire [512:0] qw16_vadd_bw__din;
+  wire qw16_vadd_bw__full_n;
+  wire qw16_vadd_bw__write;
+  wire [512:0] qw17_vadd_bw__dout;
+  wire qw17_vadd_bw__empty_n;
+  wire qw17_vadd_bw__read;
+  wire [512:0] qw17_vadd_bw__din;
+  wire qw17_vadd_bw__full_n;
+  wire qw17_vadd_bw__write;
+  wire [512:0] qw18_vadd_bw__dout;
+  wire qw18_vadd_bw__empty_n;
+  wire qw18_vadd_bw__read;
+  wire [512:0] qw18_vadd_bw__din;
+  wire qw18_vadd_bw__full_n;
+  wire qw18_vadd_bw__write;
+  wire [512:0] qw19_vadd_bw__dout;
+  wire qw19_vadd_bw__empty_n;
+  wire qw19_vadd_bw__read;
+  wire [512:0] qw19_vadd_bw__din;
+  wire qw19_vadd_bw__full_n;
+  wire qw19_vadd_bw__write;
+  wire [512:0] qw1_vadd_bw__dout;
+  wire qw1_vadd_bw__empty_n;
+  wire qw1_vadd_bw__read;
+  wire [512:0] qw1_vadd_bw__din;
+  wire qw1_vadd_bw__full_n;
+  wire qw1_vadd_bw__write;
+  wire [512:0] qw20_vadd_bw__dout;
+  wire qw20_vadd_bw__empty_n;
+  wire qw20_vadd_bw__read;
+  wire [512:0] qw20_vadd_bw__din;
+  wire qw20_vadd_bw__full_n;
+  wire qw20_vadd_bw__write;
+  wire [512:0] qw21_vadd_bw__dout;
+  wire qw21_vadd_bw__empty_n;
+  wire qw21_vadd_bw__read;
+  wire [512:0] qw21_vadd_bw__din;
+  wire qw21_vadd_bw__full_n;
+  wire qw21_vadd_bw__write;
+  wire [512:0] qw22_vadd_bw__dout;
+  wire qw22_vadd_bw__empty_n;
+  wire qw22_vadd_bw__read;
+  wire [512:0] qw22_vadd_bw__din;
+  wire qw22_vadd_bw__full_n;
+  wire qw22_vadd_bw__write;
+  wire [512:0] qw23_vadd_bw__dout;
+  wire qw23_vadd_bw__empty_n;
+  wire qw23_vadd_bw__read;
+  wire [512:0] qw23_vadd_bw__din;
+  wire qw23_vadd_bw__full_n;
+  wire qw23_vadd_bw__write;
+  wire [512:0] qw24_vadd_bw__dout;
+  wire qw24_vadd_bw__empty_n;
+  wire qw24_vadd_bw__read;
+  wire [512:0] qw24_vadd_bw__din;
+  wire qw24_vadd_bw__full_n;
+  wire qw24_vadd_bw__write;
+  wire [512:0] qw25_vadd_bw__dout;
+  wire qw25_vadd_bw__empty_n;
+  wire qw25_vadd_bw__read;
+  wire [512:0] qw25_vadd_bw__din;
+  wire qw25_vadd_bw__full_n;
+  wire qw25_vadd_bw__write;
+  wire [512:0] qw26_vadd_bw__dout;
+  wire qw26_vadd_bw__empty_n;
+  wire qw26_vadd_bw__read;
+  wire [512:0] qw26_vadd_bw__din;
+  wire qw26_vadd_bw__full_n;
+  wire qw26_vadd_bw__write;
+  wire [512:0] qw27_vadd_bw__dout;
+  wire qw27_vadd_bw__empty_n;
+  wire qw27_vadd_bw__read;
+  wire [512:0] qw27_vadd_bw__din;
+  wire qw27_vadd_bw__full_n;
+  wire qw27_vadd_bw__write;
+  wire [512:0] qw2_vadd_bw__dout;
+  wire qw2_vadd_bw__empty_n;
+  wire qw2_vadd_bw__read;
+  wire [512:0] qw2_vadd_bw__din;
+  wire qw2_vadd_bw__full_n;
+  wire qw2_vadd_bw__write;
+  wire [512:0] qw3_vadd_bw__dout;
+  wire qw3_vadd_bw__empty_n;
+  wire qw3_vadd_bw__read;
+  wire [512:0] qw3_vadd_bw__din;
+  wire qw3_vadd_bw__full_n;
+  wire qw3_vadd_bw__write;
+  wire [512:0] qw4_vadd_bw__dout;
+  wire qw4_vadd_bw__empty_n;
+  wire qw4_vadd_bw__read;
+  wire [512:0] qw4_vadd_bw__din;
+  wire qw4_vadd_bw__full_n;
+  wire qw4_vadd_bw__write;
+  wire [512:0] qw5_vadd_bw__dout;
+  wire qw5_vadd_bw__empty_n;
+  wire qw5_vadd_bw__read;
+  wire [512:0] qw5_vadd_bw__din;
+  wire qw5_vadd_bw__full_n;
+  wire qw5_vadd_bw__write;
+  wire [512:0] qw6_vadd_bw__dout;
+  wire qw6_vadd_bw__empty_n;
+  wire qw6_vadd_bw__read;
+  wire [512:0] qw6_vadd_bw__din;
+  wire qw6_vadd_bw__full_n;
+  wire qw6_vadd_bw__write;
+  wire [512:0] qw7_vadd_bw__dout;
+  wire qw7_vadd_bw__empty_n;
+  wire qw7_vadd_bw__read;
+  wire [512:0] qw7_vadd_bw__din;
+  wire qw7_vadd_bw__full_n;
+  wire qw7_vadd_bw__write;
+  wire [512:0] qw8_vadd_bw__dout;
+  wire qw8_vadd_bw__empty_n;
+  wire qw8_vadd_bw__read;
+  wire [512:0] qw8_vadd_bw__din;
+  wire qw8_vadd_bw__full_n;
+  wire qw8_vadd_bw__write;
+  wire [512:0] qw9_vadd_bw__dout;
+  wire qw9_vadd_bw__empty_n;
+  wire qw9_vadd_bw__read;
+  wire [512:0] qw9_vadd_bw__din;
+  wire qw9_vadd_bw__full_n;
+  wire qw9_vadd_bw__write;
+  wire [63:0] m_axi_rmem0___Mmap2Stream_0___mmap_ARADDR;
+  wire [1:0] m_axi_rmem0___Mmap2Stream_0___mmap_ARBURST;
+  wire [3:0] m_axi_rmem0___Mmap2Stream_0___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem0___Mmap2Stream_0___mmap_ARID;
+  wire [7:0] m_axi_rmem0___Mmap2Stream_0___mmap_ARLEN;
+  wire m_axi_rmem0___Mmap2Stream_0___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem0___Mmap2Stream_0___mmap_ARPROT;
+  wire [3:0] m_axi_rmem0___Mmap2Stream_0___mmap_ARQOS;
+  wire m_axi_rmem0___Mmap2Stream_0___mmap_ARREADY;
+  wire [2:0] m_axi_rmem0___Mmap2Stream_0___mmap_ARSIZE;
+  wire m_axi_rmem0___Mmap2Stream_0___mmap_ARVALID;
+  wire [63:0] m_axi_rmem0___Mmap2Stream_0___mmap_AWADDR;
+  wire [1:0] m_axi_rmem0___Mmap2Stream_0___mmap_AWBURST;
+  wire [3:0] m_axi_rmem0___Mmap2Stream_0___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem0___Mmap2Stream_0___mmap_AWID;
+  wire [7:0] m_axi_rmem0___Mmap2Stream_0___mmap_AWLEN;
+  wire m_axi_rmem0___Mmap2Stream_0___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem0___Mmap2Stream_0___mmap_AWPROT;
+  wire [3:0] m_axi_rmem0___Mmap2Stream_0___mmap_AWQOS;
+  wire m_axi_rmem0___Mmap2Stream_0___mmap_AWREADY;
+  wire [2:0] m_axi_rmem0___Mmap2Stream_0___mmap_AWSIZE;
+  wire m_axi_rmem0___Mmap2Stream_0___mmap_AWVALID;
+  wire [0:0] m_axi_rmem0___Mmap2Stream_0___mmap_BID;
+  wire m_axi_rmem0___Mmap2Stream_0___mmap_BREADY;
+  wire [1:0] m_axi_rmem0___Mmap2Stream_0___mmap_BRESP;
+  wire m_axi_rmem0___Mmap2Stream_0___mmap_BVALID;
+  wire [511:0] m_axi_rmem0___Mmap2Stream_0___mmap_RDATA;
+  wire [0:0] m_axi_rmem0___Mmap2Stream_0___mmap_RID;
+  wire m_axi_rmem0___Mmap2Stream_0___mmap_RLAST;
+  wire m_axi_rmem0___Mmap2Stream_0___mmap_RREADY;
+  wire [1:0] m_axi_rmem0___Mmap2Stream_0___mmap_RRESP;
+  wire m_axi_rmem0___Mmap2Stream_0___mmap_RVALID;
+  wire [511:0] m_axi_rmem0___Mmap2Stream_0___mmap_WDATA;
+  wire m_axi_rmem0___Mmap2Stream_0___mmap_WLAST;
+  wire m_axi_rmem0___Mmap2Stream_0___mmap_WREADY;
+  wire [63:0] m_axi_rmem0___Mmap2Stream_0___mmap_WSTRB;
+  wire m_axi_rmem0___Mmap2Stream_0___mmap_WVALID;
+  wire [63:0] m_axi_rmem0___Stream2Mmap_0___mmap_ARADDR;
+  wire [1:0] m_axi_rmem0___Stream2Mmap_0___mmap_ARBURST;
+  wire [3:0] m_axi_rmem0___Stream2Mmap_0___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem0___Stream2Mmap_0___mmap_ARID;
+  wire [7:0] m_axi_rmem0___Stream2Mmap_0___mmap_ARLEN;
+  wire m_axi_rmem0___Stream2Mmap_0___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem0___Stream2Mmap_0___mmap_ARPROT;
+  wire [3:0] m_axi_rmem0___Stream2Mmap_0___mmap_ARQOS;
+  wire m_axi_rmem0___Stream2Mmap_0___mmap_ARREADY;
+  wire [2:0] m_axi_rmem0___Stream2Mmap_0___mmap_ARSIZE;
+  wire m_axi_rmem0___Stream2Mmap_0___mmap_ARVALID;
+  wire [63:0] m_axi_rmem0___Stream2Mmap_0___mmap_AWADDR;
+  wire [1:0] m_axi_rmem0___Stream2Mmap_0___mmap_AWBURST;
+  wire [3:0] m_axi_rmem0___Stream2Mmap_0___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem0___Stream2Mmap_0___mmap_AWID;
+  wire [7:0] m_axi_rmem0___Stream2Mmap_0___mmap_AWLEN;
+  wire m_axi_rmem0___Stream2Mmap_0___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem0___Stream2Mmap_0___mmap_AWPROT;
+  wire [3:0] m_axi_rmem0___Stream2Mmap_0___mmap_AWQOS;
+  wire m_axi_rmem0___Stream2Mmap_0___mmap_AWREADY;
+  wire [2:0] m_axi_rmem0___Stream2Mmap_0___mmap_AWSIZE;
+  wire m_axi_rmem0___Stream2Mmap_0___mmap_AWVALID;
+  wire [0:0] m_axi_rmem0___Stream2Mmap_0___mmap_BID;
+  wire m_axi_rmem0___Stream2Mmap_0___mmap_BREADY;
+  wire [1:0] m_axi_rmem0___Stream2Mmap_0___mmap_BRESP;
+  wire m_axi_rmem0___Stream2Mmap_0___mmap_BVALID;
+  wire [511:0] m_axi_rmem0___Stream2Mmap_0___mmap_RDATA;
+  wire [0:0] m_axi_rmem0___Stream2Mmap_0___mmap_RID;
+  wire m_axi_rmem0___Stream2Mmap_0___mmap_RLAST;
+  wire m_axi_rmem0___Stream2Mmap_0___mmap_RREADY;
+  wire [1:0] m_axi_rmem0___Stream2Mmap_0___mmap_RRESP;
+  wire m_axi_rmem0___Stream2Mmap_0___mmap_RVALID;
+  wire [511:0] m_axi_rmem0___Stream2Mmap_0___mmap_WDATA;
+  wire m_axi_rmem0___Stream2Mmap_0___mmap_WLAST;
+  wire m_axi_rmem0___Stream2Mmap_0___mmap_WREADY;
+  wire [63:0] m_axi_rmem0___Stream2Mmap_0___mmap_WSTRB;
+  wire m_axi_rmem0___Stream2Mmap_0___mmap_WVALID;
+  wire [63:0] m_axi_rmem1___Mmap2Stream_1___mmap_ARADDR;
+  wire [1:0] m_axi_rmem1___Mmap2Stream_1___mmap_ARBURST;
+  wire [3:0] m_axi_rmem1___Mmap2Stream_1___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem1___Mmap2Stream_1___mmap_ARID;
+  wire [7:0] m_axi_rmem1___Mmap2Stream_1___mmap_ARLEN;
+  wire m_axi_rmem1___Mmap2Stream_1___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem1___Mmap2Stream_1___mmap_ARPROT;
+  wire [3:0] m_axi_rmem1___Mmap2Stream_1___mmap_ARQOS;
+  wire m_axi_rmem1___Mmap2Stream_1___mmap_ARREADY;
+  wire [2:0] m_axi_rmem1___Mmap2Stream_1___mmap_ARSIZE;
+  wire m_axi_rmem1___Mmap2Stream_1___mmap_ARVALID;
+  wire [63:0] m_axi_rmem1___Mmap2Stream_1___mmap_AWADDR;
+  wire [1:0] m_axi_rmem1___Mmap2Stream_1___mmap_AWBURST;
+  wire [3:0] m_axi_rmem1___Mmap2Stream_1___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem1___Mmap2Stream_1___mmap_AWID;
+  wire [7:0] m_axi_rmem1___Mmap2Stream_1___mmap_AWLEN;
+  wire m_axi_rmem1___Mmap2Stream_1___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem1___Mmap2Stream_1___mmap_AWPROT;
+  wire [3:0] m_axi_rmem1___Mmap2Stream_1___mmap_AWQOS;
+  wire m_axi_rmem1___Mmap2Stream_1___mmap_AWREADY;
+  wire [2:0] m_axi_rmem1___Mmap2Stream_1___mmap_AWSIZE;
+  wire m_axi_rmem1___Mmap2Stream_1___mmap_AWVALID;
+  wire [0:0] m_axi_rmem1___Mmap2Stream_1___mmap_BID;
+  wire m_axi_rmem1___Mmap2Stream_1___mmap_BREADY;
+  wire [1:0] m_axi_rmem1___Mmap2Stream_1___mmap_BRESP;
+  wire m_axi_rmem1___Mmap2Stream_1___mmap_BVALID;
+  wire [511:0] m_axi_rmem1___Mmap2Stream_1___mmap_RDATA;
+  wire [0:0] m_axi_rmem1___Mmap2Stream_1___mmap_RID;
+  wire m_axi_rmem1___Mmap2Stream_1___mmap_RLAST;
+  wire m_axi_rmem1___Mmap2Stream_1___mmap_RREADY;
+  wire [1:0] m_axi_rmem1___Mmap2Stream_1___mmap_RRESP;
+  wire m_axi_rmem1___Mmap2Stream_1___mmap_RVALID;
+  wire [511:0] m_axi_rmem1___Mmap2Stream_1___mmap_WDATA;
+  wire m_axi_rmem1___Mmap2Stream_1___mmap_WLAST;
+  wire m_axi_rmem1___Mmap2Stream_1___mmap_WREADY;
+  wire [63:0] m_axi_rmem1___Mmap2Stream_1___mmap_WSTRB;
+  wire m_axi_rmem1___Mmap2Stream_1___mmap_WVALID;
+  wire [63:0] m_axi_rmem1___Stream2Mmap_1___mmap_ARADDR;
+  wire [1:0] m_axi_rmem1___Stream2Mmap_1___mmap_ARBURST;
+  wire [3:0] m_axi_rmem1___Stream2Mmap_1___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem1___Stream2Mmap_1___mmap_ARID;
+  wire [7:0] m_axi_rmem1___Stream2Mmap_1___mmap_ARLEN;
+  wire m_axi_rmem1___Stream2Mmap_1___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem1___Stream2Mmap_1___mmap_ARPROT;
+  wire [3:0] m_axi_rmem1___Stream2Mmap_1___mmap_ARQOS;
+  wire m_axi_rmem1___Stream2Mmap_1___mmap_ARREADY;
+  wire [2:0] m_axi_rmem1___Stream2Mmap_1___mmap_ARSIZE;
+  wire m_axi_rmem1___Stream2Mmap_1___mmap_ARVALID;
+  wire [63:0] m_axi_rmem1___Stream2Mmap_1___mmap_AWADDR;
+  wire [1:0] m_axi_rmem1___Stream2Mmap_1___mmap_AWBURST;
+  wire [3:0] m_axi_rmem1___Stream2Mmap_1___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem1___Stream2Mmap_1___mmap_AWID;
+  wire [7:0] m_axi_rmem1___Stream2Mmap_1___mmap_AWLEN;
+  wire m_axi_rmem1___Stream2Mmap_1___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem1___Stream2Mmap_1___mmap_AWPROT;
+  wire [3:0] m_axi_rmem1___Stream2Mmap_1___mmap_AWQOS;
+  wire m_axi_rmem1___Stream2Mmap_1___mmap_AWREADY;
+  wire [2:0] m_axi_rmem1___Stream2Mmap_1___mmap_AWSIZE;
+  wire m_axi_rmem1___Stream2Mmap_1___mmap_AWVALID;
+  wire [0:0] m_axi_rmem1___Stream2Mmap_1___mmap_BID;
+  wire m_axi_rmem1___Stream2Mmap_1___mmap_BREADY;
+  wire [1:0] m_axi_rmem1___Stream2Mmap_1___mmap_BRESP;
+  wire m_axi_rmem1___Stream2Mmap_1___mmap_BVALID;
+  wire [511:0] m_axi_rmem1___Stream2Mmap_1___mmap_RDATA;
+  wire [0:0] m_axi_rmem1___Stream2Mmap_1___mmap_RID;
+  wire m_axi_rmem1___Stream2Mmap_1___mmap_RLAST;
+  wire m_axi_rmem1___Stream2Mmap_1___mmap_RREADY;
+  wire [1:0] m_axi_rmem1___Stream2Mmap_1___mmap_RRESP;
+  wire m_axi_rmem1___Stream2Mmap_1___mmap_RVALID;
+  wire [511:0] m_axi_rmem1___Stream2Mmap_1___mmap_WDATA;
+  wire m_axi_rmem1___Stream2Mmap_1___mmap_WLAST;
+  wire m_axi_rmem1___Stream2Mmap_1___mmap_WREADY;
+  wire [63:0] m_axi_rmem1___Stream2Mmap_1___mmap_WSTRB;
+  wire m_axi_rmem1___Stream2Mmap_1___mmap_WVALID;
+  wire [63:0] m_axi_rmem2___Mmap2Stream_2___mmap_ARADDR;
+  wire [1:0] m_axi_rmem2___Mmap2Stream_2___mmap_ARBURST;
+  wire [3:0] m_axi_rmem2___Mmap2Stream_2___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem2___Mmap2Stream_2___mmap_ARID;
+  wire [7:0] m_axi_rmem2___Mmap2Stream_2___mmap_ARLEN;
+  wire m_axi_rmem2___Mmap2Stream_2___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem2___Mmap2Stream_2___mmap_ARPROT;
+  wire [3:0] m_axi_rmem2___Mmap2Stream_2___mmap_ARQOS;
+  wire m_axi_rmem2___Mmap2Stream_2___mmap_ARREADY;
+  wire [2:0] m_axi_rmem2___Mmap2Stream_2___mmap_ARSIZE;
+  wire m_axi_rmem2___Mmap2Stream_2___mmap_ARVALID;
+  wire [63:0] m_axi_rmem2___Mmap2Stream_2___mmap_AWADDR;
+  wire [1:0] m_axi_rmem2___Mmap2Stream_2___mmap_AWBURST;
+  wire [3:0] m_axi_rmem2___Mmap2Stream_2___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem2___Mmap2Stream_2___mmap_AWID;
+  wire [7:0] m_axi_rmem2___Mmap2Stream_2___mmap_AWLEN;
+  wire m_axi_rmem2___Mmap2Stream_2___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem2___Mmap2Stream_2___mmap_AWPROT;
+  wire [3:0] m_axi_rmem2___Mmap2Stream_2___mmap_AWQOS;
+  wire m_axi_rmem2___Mmap2Stream_2___mmap_AWREADY;
+  wire [2:0] m_axi_rmem2___Mmap2Stream_2___mmap_AWSIZE;
+  wire m_axi_rmem2___Mmap2Stream_2___mmap_AWVALID;
+  wire [0:0] m_axi_rmem2___Mmap2Stream_2___mmap_BID;
+  wire m_axi_rmem2___Mmap2Stream_2___mmap_BREADY;
+  wire [1:0] m_axi_rmem2___Mmap2Stream_2___mmap_BRESP;
+  wire m_axi_rmem2___Mmap2Stream_2___mmap_BVALID;
+  wire [511:0] m_axi_rmem2___Mmap2Stream_2___mmap_RDATA;
+  wire [0:0] m_axi_rmem2___Mmap2Stream_2___mmap_RID;
+  wire m_axi_rmem2___Mmap2Stream_2___mmap_RLAST;
+  wire m_axi_rmem2___Mmap2Stream_2___mmap_RREADY;
+  wire [1:0] m_axi_rmem2___Mmap2Stream_2___mmap_RRESP;
+  wire m_axi_rmem2___Mmap2Stream_2___mmap_RVALID;
+  wire [511:0] m_axi_rmem2___Mmap2Stream_2___mmap_WDATA;
+  wire m_axi_rmem2___Mmap2Stream_2___mmap_WLAST;
+  wire m_axi_rmem2___Mmap2Stream_2___mmap_WREADY;
+  wire [63:0] m_axi_rmem2___Mmap2Stream_2___mmap_WSTRB;
+  wire m_axi_rmem2___Mmap2Stream_2___mmap_WVALID;
+  wire [63:0] m_axi_rmem2___Stream2Mmap_2___mmap_ARADDR;
+  wire [1:0] m_axi_rmem2___Stream2Mmap_2___mmap_ARBURST;
+  wire [3:0] m_axi_rmem2___Stream2Mmap_2___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem2___Stream2Mmap_2___mmap_ARID;
+  wire [7:0] m_axi_rmem2___Stream2Mmap_2___mmap_ARLEN;
+  wire m_axi_rmem2___Stream2Mmap_2___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem2___Stream2Mmap_2___mmap_ARPROT;
+  wire [3:0] m_axi_rmem2___Stream2Mmap_2___mmap_ARQOS;
+  wire m_axi_rmem2___Stream2Mmap_2___mmap_ARREADY;
+  wire [2:0] m_axi_rmem2___Stream2Mmap_2___mmap_ARSIZE;
+  wire m_axi_rmem2___Stream2Mmap_2___mmap_ARVALID;
+  wire [63:0] m_axi_rmem2___Stream2Mmap_2___mmap_AWADDR;
+  wire [1:0] m_axi_rmem2___Stream2Mmap_2___mmap_AWBURST;
+  wire [3:0] m_axi_rmem2___Stream2Mmap_2___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem2___Stream2Mmap_2___mmap_AWID;
+  wire [7:0] m_axi_rmem2___Stream2Mmap_2___mmap_AWLEN;
+  wire m_axi_rmem2___Stream2Mmap_2___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem2___Stream2Mmap_2___mmap_AWPROT;
+  wire [3:0] m_axi_rmem2___Stream2Mmap_2___mmap_AWQOS;
+  wire m_axi_rmem2___Stream2Mmap_2___mmap_AWREADY;
+  wire [2:0] m_axi_rmem2___Stream2Mmap_2___mmap_AWSIZE;
+  wire m_axi_rmem2___Stream2Mmap_2___mmap_AWVALID;
+  wire [0:0] m_axi_rmem2___Stream2Mmap_2___mmap_BID;
+  wire m_axi_rmem2___Stream2Mmap_2___mmap_BREADY;
+  wire [1:0] m_axi_rmem2___Stream2Mmap_2___mmap_BRESP;
+  wire m_axi_rmem2___Stream2Mmap_2___mmap_BVALID;
+  wire [511:0] m_axi_rmem2___Stream2Mmap_2___mmap_RDATA;
+  wire [0:0] m_axi_rmem2___Stream2Mmap_2___mmap_RID;
+  wire m_axi_rmem2___Stream2Mmap_2___mmap_RLAST;
+  wire m_axi_rmem2___Stream2Mmap_2___mmap_RREADY;
+  wire [1:0] m_axi_rmem2___Stream2Mmap_2___mmap_RRESP;
+  wire m_axi_rmem2___Stream2Mmap_2___mmap_RVALID;
+  wire [511:0] m_axi_rmem2___Stream2Mmap_2___mmap_WDATA;
+  wire m_axi_rmem2___Stream2Mmap_2___mmap_WLAST;
+  wire m_axi_rmem2___Stream2Mmap_2___mmap_WREADY;
+  wire [63:0] m_axi_rmem2___Stream2Mmap_2___mmap_WSTRB;
+  wire m_axi_rmem2___Stream2Mmap_2___mmap_WVALID;
+  wire [63:0] m_axi_rmem3___Mmap2Stream_3___mmap_ARADDR;
+  wire [1:0] m_axi_rmem3___Mmap2Stream_3___mmap_ARBURST;
+  wire [3:0] m_axi_rmem3___Mmap2Stream_3___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem3___Mmap2Stream_3___mmap_ARID;
+  wire [7:0] m_axi_rmem3___Mmap2Stream_3___mmap_ARLEN;
+  wire m_axi_rmem3___Mmap2Stream_3___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem3___Mmap2Stream_3___mmap_ARPROT;
+  wire [3:0] m_axi_rmem3___Mmap2Stream_3___mmap_ARQOS;
+  wire m_axi_rmem3___Mmap2Stream_3___mmap_ARREADY;
+  wire [2:0] m_axi_rmem3___Mmap2Stream_3___mmap_ARSIZE;
+  wire m_axi_rmem3___Mmap2Stream_3___mmap_ARVALID;
+  wire [63:0] m_axi_rmem3___Mmap2Stream_3___mmap_AWADDR;
+  wire [1:0] m_axi_rmem3___Mmap2Stream_3___mmap_AWBURST;
+  wire [3:0] m_axi_rmem3___Mmap2Stream_3___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem3___Mmap2Stream_3___mmap_AWID;
+  wire [7:0] m_axi_rmem3___Mmap2Stream_3___mmap_AWLEN;
+  wire m_axi_rmem3___Mmap2Stream_3___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem3___Mmap2Stream_3___mmap_AWPROT;
+  wire [3:0] m_axi_rmem3___Mmap2Stream_3___mmap_AWQOS;
+  wire m_axi_rmem3___Mmap2Stream_3___mmap_AWREADY;
+  wire [2:0] m_axi_rmem3___Mmap2Stream_3___mmap_AWSIZE;
+  wire m_axi_rmem3___Mmap2Stream_3___mmap_AWVALID;
+  wire [0:0] m_axi_rmem3___Mmap2Stream_3___mmap_BID;
+  wire m_axi_rmem3___Mmap2Stream_3___mmap_BREADY;
+  wire [1:0] m_axi_rmem3___Mmap2Stream_3___mmap_BRESP;
+  wire m_axi_rmem3___Mmap2Stream_3___mmap_BVALID;
+  wire [511:0] m_axi_rmem3___Mmap2Stream_3___mmap_RDATA;
+  wire [0:0] m_axi_rmem3___Mmap2Stream_3___mmap_RID;
+  wire m_axi_rmem3___Mmap2Stream_3___mmap_RLAST;
+  wire m_axi_rmem3___Mmap2Stream_3___mmap_RREADY;
+  wire [1:0] m_axi_rmem3___Mmap2Stream_3___mmap_RRESP;
+  wire m_axi_rmem3___Mmap2Stream_3___mmap_RVALID;
+  wire [511:0] m_axi_rmem3___Mmap2Stream_3___mmap_WDATA;
+  wire m_axi_rmem3___Mmap2Stream_3___mmap_WLAST;
+  wire m_axi_rmem3___Mmap2Stream_3___mmap_WREADY;
+  wire [63:0] m_axi_rmem3___Mmap2Stream_3___mmap_WSTRB;
+  wire m_axi_rmem3___Mmap2Stream_3___mmap_WVALID;
+  wire [63:0] m_axi_rmem3___Stream2Mmap_3___mmap_ARADDR;
+  wire [1:0] m_axi_rmem3___Stream2Mmap_3___mmap_ARBURST;
+  wire [3:0] m_axi_rmem3___Stream2Mmap_3___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem3___Stream2Mmap_3___mmap_ARID;
+  wire [7:0] m_axi_rmem3___Stream2Mmap_3___mmap_ARLEN;
+  wire m_axi_rmem3___Stream2Mmap_3___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem3___Stream2Mmap_3___mmap_ARPROT;
+  wire [3:0] m_axi_rmem3___Stream2Mmap_3___mmap_ARQOS;
+  wire m_axi_rmem3___Stream2Mmap_3___mmap_ARREADY;
+  wire [2:0] m_axi_rmem3___Stream2Mmap_3___mmap_ARSIZE;
+  wire m_axi_rmem3___Stream2Mmap_3___mmap_ARVALID;
+  wire [63:0] m_axi_rmem3___Stream2Mmap_3___mmap_AWADDR;
+  wire [1:0] m_axi_rmem3___Stream2Mmap_3___mmap_AWBURST;
+  wire [3:0] m_axi_rmem3___Stream2Mmap_3___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem3___Stream2Mmap_3___mmap_AWID;
+  wire [7:0] m_axi_rmem3___Stream2Mmap_3___mmap_AWLEN;
+  wire m_axi_rmem3___Stream2Mmap_3___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem3___Stream2Mmap_3___mmap_AWPROT;
+  wire [3:0] m_axi_rmem3___Stream2Mmap_3___mmap_AWQOS;
+  wire m_axi_rmem3___Stream2Mmap_3___mmap_AWREADY;
+  wire [2:0] m_axi_rmem3___Stream2Mmap_3___mmap_AWSIZE;
+  wire m_axi_rmem3___Stream2Mmap_3___mmap_AWVALID;
+  wire [0:0] m_axi_rmem3___Stream2Mmap_3___mmap_BID;
+  wire m_axi_rmem3___Stream2Mmap_3___mmap_BREADY;
+  wire [1:0] m_axi_rmem3___Stream2Mmap_3___mmap_BRESP;
+  wire m_axi_rmem3___Stream2Mmap_3___mmap_BVALID;
+  wire [511:0] m_axi_rmem3___Stream2Mmap_3___mmap_RDATA;
+  wire [0:0] m_axi_rmem3___Stream2Mmap_3___mmap_RID;
+  wire m_axi_rmem3___Stream2Mmap_3___mmap_RLAST;
+  wire m_axi_rmem3___Stream2Mmap_3___mmap_RREADY;
+  wire [1:0] m_axi_rmem3___Stream2Mmap_3___mmap_RRESP;
+  wire m_axi_rmem3___Stream2Mmap_3___mmap_RVALID;
+  wire [511:0] m_axi_rmem3___Stream2Mmap_3___mmap_WDATA;
+  wire m_axi_rmem3___Stream2Mmap_3___mmap_WLAST;
+  wire m_axi_rmem3___Stream2Mmap_3___mmap_WREADY;
+  wire [63:0] m_axi_rmem3___Stream2Mmap_3___mmap_WSTRB;
+  wire m_axi_rmem3___Stream2Mmap_3___mmap_WVALID;
+  wire [63:0] m_axi_rmem4___Mmap2Stream_4___mmap_ARADDR;
+  wire [1:0] m_axi_rmem4___Mmap2Stream_4___mmap_ARBURST;
+  wire [3:0] m_axi_rmem4___Mmap2Stream_4___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem4___Mmap2Stream_4___mmap_ARID;
+  wire [7:0] m_axi_rmem4___Mmap2Stream_4___mmap_ARLEN;
+  wire m_axi_rmem4___Mmap2Stream_4___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem4___Mmap2Stream_4___mmap_ARPROT;
+  wire [3:0] m_axi_rmem4___Mmap2Stream_4___mmap_ARQOS;
+  wire m_axi_rmem4___Mmap2Stream_4___mmap_ARREADY;
+  wire [2:0] m_axi_rmem4___Mmap2Stream_4___mmap_ARSIZE;
+  wire m_axi_rmem4___Mmap2Stream_4___mmap_ARVALID;
+  wire [63:0] m_axi_rmem4___Mmap2Stream_4___mmap_AWADDR;
+  wire [1:0] m_axi_rmem4___Mmap2Stream_4___mmap_AWBURST;
+  wire [3:0] m_axi_rmem4___Mmap2Stream_4___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem4___Mmap2Stream_4___mmap_AWID;
+  wire [7:0] m_axi_rmem4___Mmap2Stream_4___mmap_AWLEN;
+  wire m_axi_rmem4___Mmap2Stream_4___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem4___Mmap2Stream_4___mmap_AWPROT;
+  wire [3:0] m_axi_rmem4___Mmap2Stream_4___mmap_AWQOS;
+  wire m_axi_rmem4___Mmap2Stream_4___mmap_AWREADY;
+  wire [2:0] m_axi_rmem4___Mmap2Stream_4___mmap_AWSIZE;
+  wire m_axi_rmem4___Mmap2Stream_4___mmap_AWVALID;
+  wire [0:0] m_axi_rmem4___Mmap2Stream_4___mmap_BID;
+  wire m_axi_rmem4___Mmap2Stream_4___mmap_BREADY;
+  wire [1:0] m_axi_rmem4___Mmap2Stream_4___mmap_BRESP;
+  wire m_axi_rmem4___Mmap2Stream_4___mmap_BVALID;
+  wire [511:0] m_axi_rmem4___Mmap2Stream_4___mmap_RDATA;
+  wire [0:0] m_axi_rmem4___Mmap2Stream_4___mmap_RID;
+  wire m_axi_rmem4___Mmap2Stream_4___mmap_RLAST;
+  wire m_axi_rmem4___Mmap2Stream_4___mmap_RREADY;
+  wire [1:0] m_axi_rmem4___Mmap2Stream_4___mmap_RRESP;
+  wire m_axi_rmem4___Mmap2Stream_4___mmap_RVALID;
+  wire [511:0] m_axi_rmem4___Mmap2Stream_4___mmap_WDATA;
+  wire m_axi_rmem4___Mmap2Stream_4___mmap_WLAST;
+  wire m_axi_rmem4___Mmap2Stream_4___mmap_WREADY;
+  wire [63:0] m_axi_rmem4___Mmap2Stream_4___mmap_WSTRB;
+  wire m_axi_rmem4___Mmap2Stream_4___mmap_WVALID;
+  wire [63:0] m_axi_rmem4___Stream2Mmap_4___mmap_ARADDR;
+  wire [1:0] m_axi_rmem4___Stream2Mmap_4___mmap_ARBURST;
+  wire [3:0] m_axi_rmem4___Stream2Mmap_4___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem4___Stream2Mmap_4___mmap_ARID;
+  wire [7:0] m_axi_rmem4___Stream2Mmap_4___mmap_ARLEN;
+  wire m_axi_rmem4___Stream2Mmap_4___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem4___Stream2Mmap_4___mmap_ARPROT;
+  wire [3:0] m_axi_rmem4___Stream2Mmap_4___mmap_ARQOS;
+  wire m_axi_rmem4___Stream2Mmap_4___mmap_ARREADY;
+  wire [2:0] m_axi_rmem4___Stream2Mmap_4___mmap_ARSIZE;
+  wire m_axi_rmem4___Stream2Mmap_4___mmap_ARVALID;
+  wire [63:0] m_axi_rmem4___Stream2Mmap_4___mmap_AWADDR;
+  wire [1:0] m_axi_rmem4___Stream2Mmap_4___mmap_AWBURST;
+  wire [3:0] m_axi_rmem4___Stream2Mmap_4___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem4___Stream2Mmap_4___mmap_AWID;
+  wire [7:0] m_axi_rmem4___Stream2Mmap_4___mmap_AWLEN;
+  wire m_axi_rmem4___Stream2Mmap_4___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem4___Stream2Mmap_4___mmap_AWPROT;
+  wire [3:0] m_axi_rmem4___Stream2Mmap_4___mmap_AWQOS;
+  wire m_axi_rmem4___Stream2Mmap_4___mmap_AWREADY;
+  wire [2:0] m_axi_rmem4___Stream2Mmap_4___mmap_AWSIZE;
+  wire m_axi_rmem4___Stream2Mmap_4___mmap_AWVALID;
+  wire [0:0] m_axi_rmem4___Stream2Mmap_4___mmap_BID;
+  wire m_axi_rmem4___Stream2Mmap_4___mmap_BREADY;
+  wire [1:0] m_axi_rmem4___Stream2Mmap_4___mmap_BRESP;
+  wire m_axi_rmem4___Stream2Mmap_4___mmap_BVALID;
+  wire [511:0] m_axi_rmem4___Stream2Mmap_4___mmap_RDATA;
+  wire [0:0] m_axi_rmem4___Stream2Mmap_4___mmap_RID;
+  wire m_axi_rmem4___Stream2Mmap_4___mmap_RLAST;
+  wire m_axi_rmem4___Stream2Mmap_4___mmap_RREADY;
+  wire [1:0] m_axi_rmem4___Stream2Mmap_4___mmap_RRESP;
+  wire m_axi_rmem4___Stream2Mmap_4___mmap_RVALID;
+  wire [511:0] m_axi_rmem4___Stream2Mmap_4___mmap_WDATA;
+  wire m_axi_rmem4___Stream2Mmap_4___mmap_WLAST;
+  wire m_axi_rmem4___Stream2Mmap_4___mmap_WREADY;
+  wire [63:0] m_axi_rmem4___Stream2Mmap_4___mmap_WSTRB;
+  wire m_axi_rmem4___Stream2Mmap_4___mmap_WVALID;
+  wire [63:0] m_axi_rmem5___Mmap2Stream_5___mmap_ARADDR;
+  wire [1:0] m_axi_rmem5___Mmap2Stream_5___mmap_ARBURST;
+  wire [3:0] m_axi_rmem5___Mmap2Stream_5___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem5___Mmap2Stream_5___mmap_ARID;
+  wire [7:0] m_axi_rmem5___Mmap2Stream_5___mmap_ARLEN;
+  wire m_axi_rmem5___Mmap2Stream_5___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem5___Mmap2Stream_5___mmap_ARPROT;
+  wire [3:0] m_axi_rmem5___Mmap2Stream_5___mmap_ARQOS;
+  wire m_axi_rmem5___Mmap2Stream_5___mmap_ARREADY;
+  wire [2:0] m_axi_rmem5___Mmap2Stream_5___mmap_ARSIZE;
+  wire m_axi_rmem5___Mmap2Stream_5___mmap_ARVALID;
+  wire [63:0] m_axi_rmem5___Mmap2Stream_5___mmap_AWADDR;
+  wire [1:0] m_axi_rmem5___Mmap2Stream_5___mmap_AWBURST;
+  wire [3:0] m_axi_rmem5___Mmap2Stream_5___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem5___Mmap2Stream_5___mmap_AWID;
+  wire [7:0] m_axi_rmem5___Mmap2Stream_5___mmap_AWLEN;
+  wire m_axi_rmem5___Mmap2Stream_5___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem5___Mmap2Stream_5___mmap_AWPROT;
+  wire [3:0] m_axi_rmem5___Mmap2Stream_5___mmap_AWQOS;
+  wire m_axi_rmem5___Mmap2Stream_5___mmap_AWREADY;
+  wire [2:0] m_axi_rmem5___Mmap2Stream_5___mmap_AWSIZE;
+  wire m_axi_rmem5___Mmap2Stream_5___mmap_AWVALID;
+  wire [0:0] m_axi_rmem5___Mmap2Stream_5___mmap_BID;
+  wire m_axi_rmem5___Mmap2Stream_5___mmap_BREADY;
+  wire [1:0] m_axi_rmem5___Mmap2Stream_5___mmap_BRESP;
+  wire m_axi_rmem5___Mmap2Stream_5___mmap_BVALID;
+  wire [511:0] m_axi_rmem5___Mmap2Stream_5___mmap_RDATA;
+  wire [0:0] m_axi_rmem5___Mmap2Stream_5___mmap_RID;
+  wire m_axi_rmem5___Mmap2Stream_5___mmap_RLAST;
+  wire m_axi_rmem5___Mmap2Stream_5___mmap_RREADY;
+  wire [1:0] m_axi_rmem5___Mmap2Stream_5___mmap_RRESP;
+  wire m_axi_rmem5___Mmap2Stream_5___mmap_RVALID;
+  wire [511:0] m_axi_rmem5___Mmap2Stream_5___mmap_WDATA;
+  wire m_axi_rmem5___Mmap2Stream_5___mmap_WLAST;
+  wire m_axi_rmem5___Mmap2Stream_5___mmap_WREADY;
+  wire [63:0] m_axi_rmem5___Mmap2Stream_5___mmap_WSTRB;
+  wire m_axi_rmem5___Mmap2Stream_5___mmap_WVALID;
+  wire [63:0] m_axi_rmem5___Stream2Mmap_5___mmap_ARADDR;
+  wire [1:0] m_axi_rmem5___Stream2Mmap_5___mmap_ARBURST;
+  wire [3:0] m_axi_rmem5___Stream2Mmap_5___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem5___Stream2Mmap_5___mmap_ARID;
+  wire [7:0] m_axi_rmem5___Stream2Mmap_5___mmap_ARLEN;
+  wire m_axi_rmem5___Stream2Mmap_5___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem5___Stream2Mmap_5___mmap_ARPROT;
+  wire [3:0] m_axi_rmem5___Stream2Mmap_5___mmap_ARQOS;
+  wire m_axi_rmem5___Stream2Mmap_5___mmap_ARREADY;
+  wire [2:0] m_axi_rmem5___Stream2Mmap_5___mmap_ARSIZE;
+  wire m_axi_rmem5___Stream2Mmap_5___mmap_ARVALID;
+  wire [63:0] m_axi_rmem5___Stream2Mmap_5___mmap_AWADDR;
+  wire [1:0] m_axi_rmem5___Stream2Mmap_5___mmap_AWBURST;
+  wire [3:0] m_axi_rmem5___Stream2Mmap_5___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem5___Stream2Mmap_5___mmap_AWID;
+  wire [7:0] m_axi_rmem5___Stream2Mmap_5___mmap_AWLEN;
+  wire m_axi_rmem5___Stream2Mmap_5___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem5___Stream2Mmap_5___mmap_AWPROT;
+  wire [3:0] m_axi_rmem5___Stream2Mmap_5___mmap_AWQOS;
+  wire m_axi_rmem5___Stream2Mmap_5___mmap_AWREADY;
+  wire [2:0] m_axi_rmem5___Stream2Mmap_5___mmap_AWSIZE;
+  wire m_axi_rmem5___Stream2Mmap_5___mmap_AWVALID;
+  wire [0:0] m_axi_rmem5___Stream2Mmap_5___mmap_BID;
+  wire m_axi_rmem5___Stream2Mmap_5___mmap_BREADY;
+  wire [1:0] m_axi_rmem5___Stream2Mmap_5___mmap_BRESP;
+  wire m_axi_rmem5___Stream2Mmap_5___mmap_BVALID;
+  wire [511:0] m_axi_rmem5___Stream2Mmap_5___mmap_RDATA;
+  wire [0:0] m_axi_rmem5___Stream2Mmap_5___mmap_RID;
+  wire m_axi_rmem5___Stream2Mmap_5___mmap_RLAST;
+  wire m_axi_rmem5___Stream2Mmap_5___mmap_RREADY;
+  wire [1:0] m_axi_rmem5___Stream2Mmap_5___mmap_RRESP;
+  wire m_axi_rmem5___Stream2Mmap_5___mmap_RVALID;
+  wire [511:0] m_axi_rmem5___Stream2Mmap_5___mmap_WDATA;
+  wire m_axi_rmem5___Stream2Mmap_5___mmap_WLAST;
+  wire m_axi_rmem5___Stream2Mmap_5___mmap_WREADY;
+  wire [63:0] m_axi_rmem5___Stream2Mmap_5___mmap_WSTRB;
+  wire m_axi_rmem5___Stream2Mmap_5___mmap_WVALID;
+  wire [63:0] m_axi_rmem6___Mmap2Stream_6___mmap_ARADDR;
+  wire [1:0] m_axi_rmem6___Mmap2Stream_6___mmap_ARBURST;
+  wire [3:0] m_axi_rmem6___Mmap2Stream_6___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem6___Mmap2Stream_6___mmap_ARID;
+  wire [7:0] m_axi_rmem6___Mmap2Stream_6___mmap_ARLEN;
+  wire m_axi_rmem6___Mmap2Stream_6___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem6___Mmap2Stream_6___mmap_ARPROT;
+  wire [3:0] m_axi_rmem6___Mmap2Stream_6___mmap_ARQOS;
+  wire m_axi_rmem6___Mmap2Stream_6___mmap_ARREADY;
+  wire [2:0] m_axi_rmem6___Mmap2Stream_6___mmap_ARSIZE;
+  wire m_axi_rmem6___Mmap2Stream_6___mmap_ARVALID;
+  wire [63:0] m_axi_rmem6___Mmap2Stream_6___mmap_AWADDR;
+  wire [1:0] m_axi_rmem6___Mmap2Stream_6___mmap_AWBURST;
+  wire [3:0] m_axi_rmem6___Mmap2Stream_6___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem6___Mmap2Stream_6___mmap_AWID;
+  wire [7:0] m_axi_rmem6___Mmap2Stream_6___mmap_AWLEN;
+  wire m_axi_rmem6___Mmap2Stream_6___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem6___Mmap2Stream_6___mmap_AWPROT;
+  wire [3:0] m_axi_rmem6___Mmap2Stream_6___mmap_AWQOS;
+  wire m_axi_rmem6___Mmap2Stream_6___mmap_AWREADY;
+  wire [2:0] m_axi_rmem6___Mmap2Stream_6___mmap_AWSIZE;
+  wire m_axi_rmem6___Mmap2Stream_6___mmap_AWVALID;
+  wire [0:0] m_axi_rmem6___Mmap2Stream_6___mmap_BID;
+  wire m_axi_rmem6___Mmap2Stream_6___mmap_BREADY;
+  wire [1:0] m_axi_rmem6___Mmap2Stream_6___mmap_BRESP;
+  wire m_axi_rmem6___Mmap2Stream_6___mmap_BVALID;
+  wire [511:0] m_axi_rmem6___Mmap2Stream_6___mmap_RDATA;
+  wire [0:0] m_axi_rmem6___Mmap2Stream_6___mmap_RID;
+  wire m_axi_rmem6___Mmap2Stream_6___mmap_RLAST;
+  wire m_axi_rmem6___Mmap2Stream_6___mmap_RREADY;
+  wire [1:0] m_axi_rmem6___Mmap2Stream_6___mmap_RRESP;
+  wire m_axi_rmem6___Mmap2Stream_6___mmap_RVALID;
+  wire [511:0] m_axi_rmem6___Mmap2Stream_6___mmap_WDATA;
+  wire m_axi_rmem6___Mmap2Stream_6___mmap_WLAST;
+  wire m_axi_rmem6___Mmap2Stream_6___mmap_WREADY;
+  wire [63:0] m_axi_rmem6___Mmap2Stream_6___mmap_WSTRB;
+  wire m_axi_rmem6___Mmap2Stream_6___mmap_WVALID;
+  wire [63:0] m_axi_rmem6___Stream2Mmap_6___mmap_ARADDR;
+  wire [1:0] m_axi_rmem6___Stream2Mmap_6___mmap_ARBURST;
+  wire [3:0] m_axi_rmem6___Stream2Mmap_6___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem6___Stream2Mmap_6___mmap_ARID;
+  wire [7:0] m_axi_rmem6___Stream2Mmap_6___mmap_ARLEN;
+  wire m_axi_rmem6___Stream2Mmap_6___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem6___Stream2Mmap_6___mmap_ARPROT;
+  wire [3:0] m_axi_rmem6___Stream2Mmap_6___mmap_ARQOS;
+  wire m_axi_rmem6___Stream2Mmap_6___mmap_ARREADY;
+  wire [2:0] m_axi_rmem6___Stream2Mmap_6___mmap_ARSIZE;
+  wire m_axi_rmem6___Stream2Mmap_6___mmap_ARVALID;
+  wire [63:0] m_axi_rmem6___Stream2Mmap_6___mmap_AWADDR;
+  wire [1:0] m_axi_rmem6___Stream2Mmap_6___mmap_AWBURST;
+  wire [3:0] m_axi_rmem6___Stream2Mmap_6___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem6___Stream2Mmap_6___mmap_AWID;
+  wire [7:0] m_axi_rmem6___Stream2Mmap_6___mmap_AWLEN;
+  wire m_axi_rmem6___Stream2Mmap_6___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem6___Stream2Mmap_6___mmap_AWPROT;
+  wire [3:0] m_axi_rmem6___Stream2Mmap_6___mmap_AWQOS;
+  wire m_axi_rmem6___Stream2Mmap_6___mmap_AWREADY;
+  wire [2:0] m_axi_rmem6___Stream2Mmap_6___mmap_AWSIZE;
+  wire m_axi_rmem6___Stream2Mmap_6___mmap_AWVALID;
+  wire [0:0] m_axi_rmem6___Stream2Mmap_6___mmap_BID;
+  wire m_axi_rmem6___Stream2Mmap_6___mmap_BREADY;
+  wire [1:0] m_axi_rmem6___Stream2Mmap_6___mmap_BRESP;
+  wire m_axi_rmem6___Stream2Mmap_6___mmap_BVALID;
+  wire [511:0] m_axi_rmem6___Stream2Mmap_6___mmap_RDATA;
+  wire [0:0] m_axi_rmem6___Stream2Mmap_6___mmap_RID;
+  wire m_axi_rmem6___Stream2Mmap_6___mmap_RLAST;
+  wire m_axi_rmem6___Stream2Mmap_6___mmap_RREADY;
+  wire [1:0] m_axi_rmem6___Stream2Mmap_6___mmap_RRESP;
+  wire m_axi_rmem6___Stream2Mmap_6___mmap_RVALID;
+  wire [511:0] m_axi_rmem6___Stream2Mmap_6___mmap_WDATA;
+  wire m_axi_rmem6___Stream2Mmap_6___mmap_WLAST;
+  wire m_axi_rmem6___Stream2Mmap_6___mmap_WREADY;
+  wire [63:0] m_axi_rmem6___Stream2Mmap_6___mmap_WSTRB;
+  wire m_axi_rmem6___Stream2Mmap_6___mmap_WVALID;
+  wire [63:0] m_axi_rmem7___Mmap2Stream_7___mmap_ARADDR;
+  wire [1:0] m_axi_rmem7___Mmap2Stream_7___mmap_ARBURST;
+  wire [3:0] m_axi_rmem7___Mmap2Stream_7___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem7___Mmap2Stream_7___mmap_ARID;
+  wire [7:0] m_axi_rmem7___Mmap2Stream_7___mmap_ARLEN;
+  wire m_axi_rmem7___Mmap2Stream_7___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem7___Mmap2Stream_7___mmap_ARPROT;
+  wire [3:0] m_axi_rmem7___Mmap2Stream_7___mmap_ARQOS;
+  wire m_axi_rmem7___Mmap2Stream_7___mmap_ARREADY;
+  wire [2:0] m_axi_rmem7___Mmap2Stream_7___mmap_ARSIZE;
+  wire m_axi_rmem7___Mmap2Stream_7___mmap_ARVALID;
+  wire [63:0] m_axi_rmem7___Mmap2Stream_7___mmap_AWADDR;
+  wire [1:0] m_axi_rmem7___Mmap2Stream_7___mmap_AWBURST;
+  wire [3:0] m_axi_rmem7___Mmap2Stream_7___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem7___Mmap2Stream_7___mmap_AWID;
+  wire [7:0] m_axi_rmem7___Mmap2Stream_7___mmap_AWLEN;
+  wire m_axi_rmem7___Mmap2Stream_7___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem7___Mmap2Stream_7___mmap_AWPROT;
+  wire [3:0] m_axi_rmem7___Mmap2Stream_7___mmap_AWQOS;
+  wire m_axi_rmem7___Mmap2Stream_7___mmap_AWREADY;
+  wire [2:0] m_axi_rmem7___Mmap2Stream_7___mmap_AWSIZE;
+  wire m_axi_rmem7___Mmap2Stream_7___mmap_AWVALID;
+  wire [0:0] m_axi_rmem7___Mmap2Stream_7___mmap_BID;
+  wire m_axi_rmem7___Mmap2Stream_7___mmap_BREADY;
+  wire [1:0] m_axi_rmem7___Mmap2Stream_7___mmap_BRESP;
+  wire m_axi_rmem7___Mmap2Stream_7___mmap_BVALID;
+  wire [511:0] m_axi_rmem7___Mmap2Stream_7___mmap_RDATA;
+  wire [0:0] m_axi_rmem7___Mmap2Stream_7___mmap_RID;
+  wire m_axi_rmem7___Mmap2Stream_7___mmap_RLAST;
+  wire m_axi_rmem7___Mmap2Stream_7___mmap_RREADY;
+  wire [1:0] m_axi_rmem7___Mmap2Stream_7___mmap_RRESP;
+  wire m_axi_rmem7___Mmap2Stream_7___mmap_RVALID;
+  wire [511:0] m_axi_rmem7___Mmap2Stream_7___mmap_WDATA;
+  wire m_axi_rmem7___Mmap2Stream_7___mmap_WLAST;
+  wire m_axi_rmem7___Mmap2Stream_7___mmap_WREADY;
+  wire [63:0] m_axi_rmem7___Mmap2Stream_7___mmap_WSTRB;
+  wire m_axi_rmem7___Mmap2Stream_7___mmap_WVALID;
+  wire [63:0] m_axi_rmem7___Stream2Mmap_7___mmap_ARADDR;
+  wire [1:0] m_axi_rmem7___Stream2Mmap_7___mmap_ARBURST;
+  wire [3:0] m_axi_rmem7___Stream2Mmap_7___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem7___Stream2Mmap_7___mmap_ARID;
+  wire [7:0] m_axi_rmem7___Stream2Mmap_7___mmap_ARLEN;
+  wire m_axi_rmem7___Stream2Mmap_7___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem7___Stream2Mmap_7___mmap_ARPROT;
+  wire [3:0] m_axi_rmem7___Stream2Mmap_7___mmap_ARQOS;
+  wire m_axi_rmem7___Stream2Mmap_7___mmap_ARREADY;
+  wire [2:0] m_axi_rmem7___Stream2Mmap_7___mmap_ARSIZE;
+  wire m_axi_rmem7___Stream2Mmap_7___mmap_ARVALID;
+  wire [63:0] m_axi_rmem7___Stream2Mmap_7___mmap_AWADDR;
+  wire [1:0] m_axi_rmem7___Stream2Mmap_7___mmap_AWBURST;
+  wire [3:0] m_axi_rmem7___Stream2Mmap_7___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem7___Stream2Mmap_7___mmap_AWID;
+  wire [7:0] m_axi_rmem7___Stream2Mmap_7___mmap_AWLEN;
+  wire m_axi_rmem7___Stream2Mmap_7___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem7___Stream2Mmap_7___mmap_AWPROT;
+  wire [3:0] m_axi_rmem7___Stream2Mmap_7___mmap_AWQOS;
+  wire m_axi_rmem7___Stream2Mmap_7___mmap_AWREADY;
+  wire [2:0] m_axi_rmem7___Stream2Mmap_7___mmap_AWSIZE;
+  wire m_axi_rmem7___Stream2Mmap_7___mmap_AWVALID;
+  wire [0:0] m_axi_rmem7___Stream2Mmap_7___mmap_BID;
+  wire m_axi_rmem7___Stream2Mmap_7___mmap_BREADY;
+  wire [1:0] m_axi_rmem7___Stream2Mmap_7___mmap_BRESP;
+  wire m_axi_rmem7___Stream2Mmap_7___mmap_BVALID;
+  wire [511:0] m_axi_rmem7___Stream2Mmap_7___mmap_RDATA;
+  wire [0:0] m_axi_rmem7___Stream2Mmap_7___mmap_RID;
+  wire m_axi_rmem7___Stream2Mmap_7___mmap_RLAST;
+  wire m_axi_rmem7___Stream2Mmap_7___mmap_RREADY;
+  wire [1:0] m_axi_rmem7___Stream2Mmap_7___mmap_RRESP;
+  wire m_axi_rmem7___Stream2Mmap_7___mmap_RVALID;
+  wire [511:0] m_axi_rmem7___Stream2Mmap_7___mmap_WDATA;
+  wire m_axi_rmem7___Stream2Mmap_7___mmap_WLAST;
+  wire m_axi_rmem7___Stream2Mmap_7___mmap_WREADY;
+  wire [63:0] m_axi_rmem7___Stream2Mmap_7___mmap_WSTRB;
+  wire m_axi_rmem7___Stream2Mmap_7___mmap_WVALID;
+  wire [63:0] m_axi_rmem8___Mmap2Stream_8___mmap_ARADDR;
+  wire [1:0] m_axi_rmem8___Mmap2Stream_8___mmap_ARBURST;
+  wire [3:0] m_axi_rmem8___Mmap2Stream_8___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem8___Mmap2Stream_8___mmap_ARID;
+  wire [7:0] m_axi_rmem8___Mmap2Stream_8___mmap_ARLEN;
+  wire m_axi_rmem8___Mmap2Stream_8___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem8___Mmap2Stream_8___mmap_ARPROT;
+  wire [3:0] m_axi_rmem8___Mmap2Stream_8___mmap_ARQOS;
+  wire m_axi_rmem8___Mmap2Stream_8___mmap_ARREADY;
+  wire [2:0] m_axi_rmem8___Mmap2Stream_8___mmap_ARSIZE;
+  wire m_axi_rmem8___Mmap2Stream_8___mmap_ARVALID;
+  wire [63:0] m_axi_rmem8___Mmap2Stream_8___mmap_AWADDR;
+  wire [1:0] m_axi_rmem8___Mmap2Stream_8___mmap_AWBURST;
+  wire [3:0] m_axi_rmem8___Mmap2Stream_8___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem8___Mmap2Stream_8___mmap_AWID;
+  wire [7:0] m_axi_rmem8___Mmap2Stream_8___mmap_AWLEN;
+  wire m_axi_rmem8___Mmap2Stream_8___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem8___Mmap2Stream_8___mmap_AWPROT;
+  wire [3:0] m_axi_rmem8___Mmap2Stream_8___mmap_AWQOS;
+  wire m_axi_rmem8___Mmap2Stream_8___mmap_AWREADY;
+  wire [2:0] m_axi_rmem8___Mmap2Stream_8___mmap_AWSIZE;
+  wire m_axi_rmem8___Mmap2Stream_8___mmap_AWVALID;
+  wire [0:0] m_axi_rmem8___Mmap2Stream_8___mmap_BID;
+  wire m_axi_rmem8___Mmap2Stream_8___mmap_BREADY;
+  wire [1:0] m_axi_rmem8___Mmap2Stream_8___mmap_BRESP;
+  wire m_axi_rmem8___Mmap2Stream_8___mmap_BVALID;
+  wire [511:0] m_axi_rmem8___Mmap2Stream_8___mmap_RDATA;
+  wire [0:0] m_axi_rmem8___Mmap2Stream_8___mmap_RID;
+  wire m_axi_rmem8___Mmap2Stream_8___mmap_RLAST;
+  wire m_axi_rmem8___Mmap2Stream_8___mmap_RREADY;
+  wire [1:0] m_axi_rmem8___Mmap2Stream_8___mmap_RRESP;
+  wire m_axi_rmem8___Mmap2Stream_8___mmap_RVALID;
+  wire [511:0] m_axi_rmem8___Mmap2Stream_8___mmap_WDATA;
+  wire m_axi_rmem8___Mmap2Stream_8___mmap_WLAST;
+  wire m_axi_rmem8___Mmap2Stream_8___mmap_WREADY;
+  wire [63:0] m_axi_rmem8___Mmap2Stream_8___mmap_WSTRB;
+  wire m_axi_rmem8___Mmap2Stream_8___mmap_WVALID;
+  wire [63:0] m_axi_rmem8___Stream2Mmap_8___mmap_ARADDR;
+  wire [1:0] m_axi_rmem8___Stream2Mmap_8___mmap_ARBURST;
+  wire [3:0] m_axi_rmem8___Stream2Mmap_8___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem8___Stream2Mmap_8___mmap_ARID;
+  wire [7:0] m_axi_rmem8___Stream2Mmap_8___mmap_ARLEN;
+  wire m_axi_rmem8___Stream2Mmap_8___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem8___Stream2Mmap_8___mmap_ARPROT;
+  wire [3:0] m_axi_rmem8___Stream2Mmap_8___mmap_ARQOS;
+  wire m_axi_rmem8___Stream2Mmap_8___mmap_ARREADY;
+  wire [2:0] m_axi_rmem8___Stream2Mmap_8___mmap_ARSIZE;
+  wire m_axi_rmem8___Stream2Mmap_8___mmap_ARVALID;
+  wire [63:0] m_axi_rmem8___Stream2Mmap_8___mmap_AWADDR;
+  wire [1:0] m_axi_rmem8___Stream2Mmap_8___mmap_AWBURST;
+  wire [3:0] m_axi_rmem8___Stream2Mmap_8___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem8___Stream2Mmap_8___mmap_AWID;
+  wire [7:0] m_axi_rmem8___Stream2Mmap_8___mmap_AWLEN;
+  wire m_axi_rmem8___Stream2Mmap_8___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem8___Stream2Mmap_8___mmap_AWPROT;
+  wire [3:0] m_axi_rmem8___Stream2Mmap_8___mmap_AWQOS;
+  wire m_axi_rmem8___Stream2Mmap_8___mmap_AWREADY;
+  wire [2:0] m_axi_rmem8___Stream2Mmap_8___mmap_AWSIZE;
+  wire m_axi_rmem8___Stream2Mmap_8___mmap_AWVALID;
+  wire [0:0] m_axi_rmem8___Stream2Mmap_8___mmap_BID;
+  wire m_axi_rmem8___Stream2Mmap_8___mmap_BREADY;
+  wire [1:0] m_axi_rmem8___Stream2Mmap_8___mmap_BRESP;
+  wire m_axi_rmem8___Stream2Mmap_8___mmap_BVALID;
+  wire [511:0] m_axi_rmem8___Stream2Mmap_8___mmap_RDATA;
+  wire [0:0] m_axi_rmem8___Stream2Mmap_8___mmap_RID;
+  wire m_axi_rmem8___Stream2Mmap_8___mmap_RLAST;
+  wire m_axi_rmem8___Stream2Mmap_8___mmap_RREADY;
+  wire [1:0] m_axi_rmem8___Stream2Mmap_8___mmap_RRESP;
+  wire m_axi_rmem8___Stream2Mmap_8___mmap_RVALID;
+  wire [511:0] m_axi_rmem8___Stream2Mmap_8___mmap_WDATA;
+  wire m_axi_rmem8___Stream2Mmap_8___mmap_WLAST;
+  wire m_axi_rmem8___Stream2Mmap_8___mmap_WREADY;
+  wire [63:0] m_axi_rmem8___Stream2Mmap_8___mmap_WSTRB;
+  wire m_axi_rmem8___Stream2Mmap_8___mmap_WVALID;
+  wire [63:0] m_axi_rmem9___Mmap2Stream_9___mmap_ARADDR;
+  wire [1:0] m_axi_rmem9___Mmap2Stream_9___mmap_ARBURST;
+  wire [3:0] m_axi_rmem9___Mmap2Stream_9___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem9___Mmap2Stream_9___mmap_ARID;
+  wire [7:0] m_axi_rmem9___Mmap2Stream_9___mmap_ARLEN;
+  wire m_axi_rmem9___Mmap2Stream_9___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem9___Mmap2Stream_9___mmap_ARPROT;
+  wire [3:0] m_axi_rmem9___Mmap2Stream_9___mmap_ARQOS;
+  wire m_axi_rmem9___Mmap2Stream_9___mmap_ARREADY;
+  wire [2:0] m_axi_rmem9___Mmap2Stream_9___mmap_ARSIZE;
+  wire m_axi_rmem9___Mmap2Stream_9___mmap_ARVALID;
+  wire [63:0] m_axi_rmem9___Mmap2Stream_9___mmap_AWADDR;
+  wire [1:0] m_axi_rmem9___Mmap2Stream_9___mmap_AWBURST;
+  wire [3:0] m_axi_rmem9___Mmap2Stream_9___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem9___Mmap2Stream_9___mmap_AWID;
+  wire [7:0] m_axi_rmem9___Mmap2Stream_9___mmap_AWLEN;
+  wire m_axi_rmem9___Mmap2Stream_9___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem9___Mmap2Stream_9___mmap_AWPROT;
+  wire [3:0] m_axi_rmem9___Mmap2Stream_9___mmap_AWQOS;
+  wire m_axi_rmem9___Mmap2Stream_9___mmap_AWREADY;
+  wire [2:0] m_axi_rmem9___Mmap2Stream_9___mmap_AWSIZE;
+  wire m_axi_rmem9___Mmap2Stream_9___mmap_AWVALID;
+  wire [0:0] m_axi_rmem9___Mmap2Stream_9___mmap_BID;
+  wire m_axi_rmem9___Mmap2Stream_9___mmap_BREADY;
+  wire [1:0] m_axi_rmem9___Mmap2Stream_9___mmap_BRESP;
+  wire m_axi_rmem9___Mmap2Stream_9___mmap_BVALID;
+  wire [511:0] m_axi_rmem9___Mmap2Stream_9___mmap_RDATA;
+  wire [0:0] m_axi_rmem9___Mmap2Stream_9___mmap_RID;
+  wire m_axi_rmem9___Mmap2Stream_9___mmap_RLAST;
+  wire m_axi_rmem9___Mmap2Stream_9___mmap_RREADY;
+  wire [1:0] m_axi_rmem9___Mmap2Stream_9___mmap_RRESP;
+  wire m_axi_rmem9___Mmap2Stream_9___mmap_RVALID;
+  wire [511:0] m_axi_rmem9___Mmap2Stream_9___mmap_WDATA;
+  wire m_axi_rmem9___Mmap2Stream_9___mmap_WLAST;
+  wire m_axi_rmem9___Mmap2Stream_9___mmap_WREADY;
+  wire [63:0] m_axi_rmem9___Mmap2Stream_9___mmap_WSTRB;
+  wire m_axi_rmem9___Mmap2Stream_9___mmap_WVALID;
+  wire [63:0] m_axi_rmem9___Stream2Mmap_9___mmap_ARADDR;
+  wire [1:0] m_axi_rmem9___Stream2Mmap_9___mmap_ARBURST;
+  wire [3:0] m_axi_rmem9___Stream2Mmap_9___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem9___Stream2Mmap_9___mmap_ARID;
+  wire [7:0] m_axi_rmem9___Stream2Mmap_9___mmap_ARLEN;
+  wire m_axi_rmem9___Stream2Mmap_9___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem9___Stream2Mmap_9___mmap_ARPROT;
+  wire [3:0] m_axi_rmem9___Stream2Mmap_9___mmap_ARQOS;
+  wire m_axi_rmem9___Stream2Mmap_9___mmap_ARREADY;
+  wire [2:0] m_axi_rmem9___Stream2Mmap_9___mmap_ARSIZE;
+  wire m_axi_rmem9___Stream2Mmap_9___mmap_ARVALID;
+  wire [63:0] m_axi_rmem9___Stream2Mmap_9___mmap_AWADDR;
+  wire [1:0] m_axi_rmem9___Stream2Mmap_9___mmap_AWBURST;
+  wire [3:0] m_axi_rmem9___Stream2Mmap_9___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem9___Stream2Mmap_9___mmap_AWID;
+  wire [7:0] m_axi_rmem9___Stream2Mmap_9___mmap_AWLEN;
+  wire m_axi_rmem9___Stream2Mmap_9___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem9___Stream2Mmap_9___mmap_AWPROT;
+  wire [3:0] m_axi_rmem9___Stream2Mmap_9___mmap_AWQOS;
+  wire m_axi_rmem9___Stream2Mmap_9___mmap_AWREADY;
+  wire [2:0] m_axi_rmem9___Stream2Mmap_9___mmap_AWSIZE;
+  wire m_axi_rmem9___Stream2Mmap_9___mmap_AWVALID;
+  wire [0:0] m_axi_rmem9___Stream2Mmap_9___mmap_BID;
+  wire m_axi_rmem9___Stream2Mmap_9___mmap_BREADY;
+  wire [1:0] m_axi_rmem9___Stream2Mmap_9___mmap_BRESP;
+  wire m_axi_rmem9___Stream2Mmap_9___mmap_BVALID;
+  wire [511:0] m_axi_rmem9___Stream2Mmap_9___mmap_RDATA;
+  wire [0:0] m_axi_rmem9___Stream2Mmap_9___mmap_RID;
+  wire m_axi_rmem9___Stream2Mmap_9___mmap_RLAST;
+  wire m_axi_rmem9___Stream2Mmap_9___mmap_RREADY;
+  wire [1:0] m_axi_rmem9___Stream2Mmap_9___mmap_RRESP;
+  wire m_axi_rmem9___Stream2Mmap_9___mmap_RVALID;
+  wire [511:0] m_axi_rmem9___Stream2Mmap_9___mmap_WDATA;
+  wire m_axi_rmem9___Stream2Mmap_9___mmap_WLAST;
+  wire m_axi_rmem9___Stream2Mmap_9___mmap_WREADY;
+  wire [63:0] m_axi_rmem9___Stream2Mmap_9___mmap_WSTRB;
+  wire m_axi_rmem9___Stream2Mmap_9___mmap_WVALID;
+  wire [63:0] m_axi_rmem10___Mmap2Stream_10___mmap_ARADDR;
+  wire [1:0] m_axi_rmem10___Mmap2Stream_10___mmap_ARBURST;
+  wire [3:0] m_axi_rmem10___Mmap2Stream_10___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem10___Mmap2Stream_10___mmap_ARID;
+  wire [7:0] m_axi_rmem10___Mmap2Stream_10___mmap_ARLEN;
+  wire m_axi_rmem10___Mmap2Stream_10___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem10___Mmap2Stream_10___mmap_ARPROT;
+  wire [3:0] m_axi_rmem10___Mmap2Stream_10___mmap_ARQOS;
+  wire m_axi_rmem10___Mmap2Stream_10___mmap_ARREADY;
+  wire [2:0] m_axi_rmem10___Mmap2Stream_10___mmap_ARSIZE;
+  wire m_axi_rmem10___Mmap2Stream_10___mmap_ARVALID;
+  wire [63:0] m_axi_rmem10___Mmap2Stream_10___mmap_AWADDR;
+  wire [1:0] m_axi_rmem10___Mmap2Stream_10___mmap_AWBURST;
+  wire [3:0] m_axi_rmem10___Mmap2Stream_10___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem10___Mmap2Stream_10___mmap_AWID;
+  wire [7:0] m_axi_rmem10___Mmap2Stream_10___mmap_AWLEN;
+  wire m_axi_rmem10___Mmap2Stream_10___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem10___Mmap2Stream_10___mmap_AWPROT;
+  wire [3:0] m_axi_rmem10___Mmap2Stream_10___mmap_AWQOS;
+  wire m_axi_rmem10___Mmap2Stream_10___mmap_AWREADY;
+  wire [2:0] m_axi_rmem10___Mmap2Stream_10___mmap_AWSIZE;
+  wire m_axi_rmem10___Mmap2Stream_10___mmap_AWVALID;
+  wire [0:0] m_axi_rmem10___Mmap2Stream_10___mmap_BID;
+  wire m_axi_rmem10___Mmap2Stream_10___mmap_BREADY;
+  wire [1:0] m_axi_rmem10___Mmap2Stream_10___mmap_BRESP;
+  wire m_axi_rmem10___Mmap2Stream_10___mmap_BVALID;
+  wire [511:0] m_axi_rmem10___Mmap2Stream_10___mmap_RDATA;
+  wire [0:0] m_axi_rmem10___Mmap2Stream_10___mmap_RID;
+  wire m_axi_rmem10___Mmap2Stream_10___mmap_RLAST;
+  wire m_axi_rmem10___Mmap2Stream_10___mmap_RREADY;
+  wire [1:0] m_axi_rmem10___Mmap2Stream_10___mmap_RRESP;
+  wire m_axi_rmem10___Mmap2Stream_10___mmap_RVALID;
+  wire [511:0] m_axi_rmem10___Mmap2Stream_10___mmap_WDATA;
+  wire m_axi_rmem10___Mmap2Stream_10___mmap_WLAST;
+  wire m_axi_rmem10___Mmap2Stream_10___mmap_WREADY;
+  wire [63:0] m_axi_rmem10___Mmap2Stream_10___mmap_WSTRB;
+  wire m_axi_rmem10___Mmap2Stream_10___mmap_WVALID;
+  wire [63:0] m_axi_rmem10___Stream2Mmap_10___mmap_ARADDR;
+  wire [1:0] m_axi_rmem10___Stream2Mmap_10___mmap_ARBURST;
+  wire [3:0] m_axi_rmem10___Stream2Mmap_10___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem10___Stream2Mmap_10___mmap_ARID;
+  wire [7:0] m_axi_rmem10___Stream2Mmap_10___mmap_ARLEN;
+  wire m_axi_rmem10___Stream2Mmap_10___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem10___Stream2Mmap_10___mmap_ARPROT;
+  wire [3:0] m_axi_rmem10___Stream2Mmap_10___mmap_ARQOS;
+  wire m_axi_rmem10___Stream2Mmap_10___mmap_ARREADY;
+  wire [2:0] m_axi_rmem10___Stream2Mmap_10___mmap_ARSIZE;
+  wire m_axi_rmem10___Stream2Mmap_10___mmap_ARVALID;
+  wire [63:0] m_axi_rmem10___Stream2Mmap_10___mmap_AWADDR;
+  wire [1:0] m_axi_rmem10___Stream2Mmap_10___mmap_AWBURST;
+  wire [3:0] m_axi_rmem10___Stream2Mmap_10___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem10___Stream2Mmap_10___mmap_AWID;
+  wire [7:0] m_axi_rmem10___Stream2Mmap_10___mmap_AWLEN;
+  wire m_axi_rmem10___Stream2Mmap_10___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem10___Stream2Mmap_10___mmap_AWPROT;
+  wire [3:0] m_axi_rmem10___Stream2Mmap_10___mmap_AWQOS;
+  wire m_axi_rmem10___Stream2Mmap_10___mmap_AWREADY;
+  wire [2:0] m_axi_rmem10___Stream2Mmap_10___mmap_AWSIZE;
+  wire m_axi_rmem10___Stream2Mmap_10___mmap_AWVALID;
+  wire [0:0] m_axi_rmem10___Stream2Mmap_10___mmap_BID;
+  wire m_axi_rmem10___Stream2Mmap_10___mmap_BREADY;
+  wire [1:0] m_axi_rmem10___Stream2Mmap_10___mmap_BRESP;
+  wire m_axi_rmem10___Stream2Mmap_10___mmap_BVALID;
+  wire [511:0] m_axi_rmem10___Stream2Mmap_10___mmap_RDATA;
+  wire [0:0] m_axi_rmem10___Stream2Mmap_10___mmap_RID;
+  wire m_axi_rmem10___Stream2Mmap_10___mmap_RLAST;
+  wire m_axi_rmem10___Stream2Mmap_10___mmap_RREADY;
+  wire [1:0] m_axi_rmem10___Stream2Mmap_10___mmap_RRESP;
+  wire m_axi_rmem10___Stream2Mmap_10___mmap_RVALID;
+  wire [511:0] m_axi_rmem10___Stream2Mmap_10___mmap_WDATA;
+  wire m_axi_rmem10___Stream2Mmap_10___mmap_WLAST;
+  wire m_axi_rmem10___Stream2Mmap_10___mmap_WREADY;
+  wire [63:0] m_axi_rmem10___Stream2Mmap_10___mmap_WSTRB;
+  wire m_axi_rmem10___Stream2Mmap_10___mmap_WVALID;
+  wire [63:0] m_axi_rmem11___Mmap2Stream_11___mmap_ARADDR;
+  wire [1:0] m_axi_rmem11___Mmap2Stream_11___mmap_ARBURST;
+  wire [3:0] m_axi_rmem11___Mmap2Stream_11___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem11___Mmap2Stream_11___mmap_ARID;
+  wire [7:0] m_axi_rmem11___Mmap2Stream_11___mmap_ARLEN;
+  wire m_axi_rmem11___Mmap2Stream_11___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem11___Mmap2Stream_11___mmap_ARPROT;
+  wire [3:0] m_axi_rmem11___Mmap2Stream_11___mmap_ARQOS;
+  wire m_axi_rmem11___Mmap2Stream_11___mmap_ARREADY;
+  wire [2:0] m_axi_rmem11___Mmap2Stream_11___mmap_ARSIZE;
+  wire m_axi_rmem11___Mmap2Stream_11___mmap_ARVALID;
+  wire [63:0] m_axi_rmem11___Mmap2Stream_11___mmap_AWADDR;
+  wire [1:0] m_axi_rmem11___Mmap2Stream_11___mmap_AWBURST;
+  wire [3:0] m_axi_rmem11___Mmap2Stream_11___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem11___Mmap2Stream_11___mmap_AWID;
+  wire [7:0] m_axi_rmem11___Mmap2Stream_11___mmap_AWLEN;
+  wire m_axi_rmem11___Mmap2Stream_11___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem11___Mmap2Stream_11___mmap_AWPROT;
+  wire [3:0] m_axi_rmem11___Mmap2Stream_11___mmap_AWQOS;
+  wire m_axi_rmem11___Mmap2Stream_11___mmap_AWREADY;
+  wire [2:0] m_axi_rmem11___Mmap2Stream_11___mmap_AWSIZE;
+  wire m_axi_rmem11___Mmap2Stream_11___mmap_AWVALID;
+  wire [0:0] m_axi_rmem11___Mmap2Stream_11___mmap_BID;
+  wire m_axi_rmem11___Mmap2Stream_11___mmap_BREADY;
+  wire [1:0] m_axi_rmem11___Mmap2Stream_11___mmap_BRESP;
+  wire m_axi_rmem11___Mmap2Stream_11___mmap_BVALID;
+  wire [511:0] m_axi_rmem11___Mmap2Stream_11___mmap_RDATA;
+  wire [0:0] m_axi_rmem11___Mmap2Stream_11___mmap_RID;
+  wire m_axi_rmem11___Mmap2Stream_11___mmap_RLAST;
+  wire m_axi_rmem11___Mmap2Stream_11___mmap_RREADY;
+  wire [1:0] m_axi_rmem11___Mmap2Stream_11___mmap_RRESP;
+  wire m_axi_rmem11___Mmap2Stream_11___mmap_RVALID;
+  wire [511:0] m_axi_rmem11___Mmap2Stream_11___mmap_WDATA;
+  wire m_axi_rmem11___Mmap2Stream_11___mmap_WLAST;
+  wire m_axi_rmem11___Mmap2Stream_11___mmap_WREADY;
+  wire [63:0] m_axi_rmem11___Mmap2Stream_11___mmap_WSTRB;
+  wire m_axi_rmem11___Mmap2Stream_11___mmap_WVALID;
+  wire [63:0] m_axi_rmem11___Stream2Mmap_11___mmap_ARADDR;
+  wire [1:0] m_axi_rmem11___Stream2Mmap_11___mmap_ARBURST;
+  wire [3:0] m_axi_rmem11___Stream2Mmap_11___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem11___Stream2Mmap_11___mmap_ARID;
+  wire [7:0] m_axi_rmem11___Stream2Mmap_11___mmap_ARLEN;
+  wire m_axi_rmem11___Stream2Mmap_11___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem11___Stream2Mmap_11___mmap_ARPROT;
+  wire [3:0] m_axi_rmem11___Stream2Mmap_11___mmap_ARQOS;
+  wire m_axi_rmem11___Stream2Mmap_11___mmap_ARREADY;
+  wire [2:0] m_axi_rmem11___Stream2Mmap_11___mmap_ARSIZE;
+  wire m_axi_rmem11___Stream2Mmap_11___mmap_ARVALID;
+  wire [63:0] m_axi_rmem11___Stream2Mmap_11___mmap_AWADDR;
+  wire [1:0] m_axi_rmem11___Stream2Mmap_11___mmap_AWBURST;
+  wire [3:0] m_axi_rmem11___Stream2Mmap_11___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem11___Stream2Mmap_11___mmap_AWID;
+  wire [7:0] m_axi_rmem11___Stream2Mmap_11___mmap_AWLEN;
+  wire m_axi_rmem11___Stream2Mmap_11___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem11___Stream2Mmap_11___mmap_AWPROT;
+  wire [3:0] m_axi_rmem11___Stream2Mmap_11___mmap_AWQOS;
+  wire m_axi_rmem11___Stream2Mmap_11___mmap_AWREADY;
+  wire [2:0] m_axi_rmem11___Stream2Mmap_11___mmap_AWSIZE;
+  wire m_axi_rmem11___Stream2Mmap_11___mmap_AWVALID;
+  wire [0:0] m_axi_rmem11___Stream2Mmap_11___mmap_BID;
+  wire m_axi_rmem11___Stream2Mmap_11___mmap_BREADY;
+  wire [1:0] m_axi_rmem11___Stream2Mmap_11___mmap_BRESP;
+  wire m_axi_rmem11___Stream2Mmap_11___mmap_BVALID;
+  wire [511:0] m_axi_rmem11___Stream2Mmap_11___mmap_RDATA;
+  wire [0:0] m_axi_rmem11___Stream2Mmap_11___mmap_RID;
+  wire m_axi_rmem11___Stream2Mmap_11___mmap_RLAST;
+  wire m_axi_rmem11___Stream2Mmap_11___mmap_RREADY;
+  wire [1:0] m_axi_rmem11___Stream2Mmap_11___mmap_RRESP;
+  wire m_axi_rmem11___Stream2Mmap_11___mmap_RVALID;
+  wire [511:0] m_axi_rmem11___Stream2Mmap_11___mmap_WDATA;
+  wire m_axi_rmem11___Stream2Mmap_11___mmap_WLAST;
+  wire m_axi_rmem11___Stream2Mmap_11___mmap_WREADY;
+  wire [63:0] m_axi_rmem11___Stream2Mmap_11___mmap_WSTRB;
+  wire m_axi_rmem11___Stream2Mmap_11___mmap_WVALID;
+  wire [63:0] m_axi_rmem12___Mmap2Stream_12___mmap_ARADDR;
+  wire [1:0] m_axi_rmem12___Mmap2Stream_12___mmap_ARBURST;
+  wire [3:0] m_axi_rmem12___Mmap2Stream_12___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem12___Mmap2Stream_12___mmap_ARID;
+  wire [7:0] m_axi_rmem12___Mmap2Stream_12___mmap_ARLEN;
+  wire m_axi_rmem12___Mmap2Stream_12___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem12___Mmap2Stream_12___mmap_ARPROT;
+  wire [3:0] m_axi_rmem12___Mmap2Stream_12___mmap_ARQOS;
+  wire m_axi_rmem12___Mmap2Stream_12___mmap_ARREADY;
+  wire [2:0] m_axi_rmem12___Mmap2Stream_12___mmap_ARSIZE;
+  wire m_axi_rmem12___Mmap2Stream_12___mmap_ARVALID;
+  wire [63:0] m_axi_rmem12___Mmap2Stream_12___mmap_AWADDR;
+  wire [1:0] m_axi_rmem12___Mmap2Stream_12___mmap_AWBURST;
+  wire [3:0] m_axi_rmem12___Mmap2Stream_12___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem12___Mmap2Stream_12___mmap_AWID;
+  wire [7:0] m_axi_rmem12___Mmap2Stream_12___mmap_AWLEN;
+  wire m_axi_rmem12___Mmap2Stream_12___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem12___Mmap2Stream_12___mmap_AWPROT;
+  wire [3:0] m_axi_rmem12___Mmap2Stream_12___mmap_AWQOS;
+  wire m_axi_rmem12___Mmap2Stream_12___mmap_AWREADY;
+  wire [2:0] m_axi_rmem12___Mmap2Stream_12___mmap_AWSIZE;
+  wire m_axi_rmem12___Mmap2Stream_12___mmap_AWVALID;
+  wire [0:0] m_axi_rmem12___Mmap2Stream_12___mmap_BID;
+  wire m_axi_rmem12___Mmap2Stream_12___mmap_BREADY;
+  wire [1:0] m_axi_rmem12___Mmap2Stream_12___mmap_BRESP;
+  wire m_axi_rmem12___Mmap2Stream_12___mmap_BVALID;
+  wire [511:0] m_axi_rmem12___Mmap2Stream_12___mmap_RDATA;
+  wire [0:0] m_axi_rmem12___Mmap2Stream_12___mmap_RID;
+  wire m_axi_rmem12___Mmap2Stream_12___mmap_RLAST;
+  wire m_axi_rmem12___Mmap2Stream_12___mmap_RREADY;
+  wire [1:0] m_axi_rmem12___Mmap2Stream_12___mmap_RRESP;
+  wire m_axi_rmem12___Mmap2Stream_12___mmap_RVALID;
+  wire [511:0] m_axi_rmem12___Mmap2Stream_12___mmap_WDATA;
+  wire m_axi_rmem12___Mmap2Stream_12___mmap_WLAST;
+  wire m_axi_rmem12___Mmap2Stream_12___mmap_WREADY;
+  wire [63:0] m_axi_rmem12___Mmap2Stream_12___mmap_WSTRB;
+  wire m_axi_rmem12___Mmap2Stream_12___mmap_WVALID;
+  wire [63:0] m_axi_rmem12___Stream2Mmap_12___mmap_ARADDR;
+  wire [1:0] m_axi_rmem12___Stream2Mmap_12___mmap_ARBURST;
+  wire [3:0] m_axi_rmem12___Stream2Mmap_12___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem12___Stream2Mmap_12___mmap_ARID;
+  wire [7:0] m_axi_rmem12___Stream2Mmap_12___mmap_ARLEN;
+  wire m_axi_rmem12___Stream2Mmap_12___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem12___Stream2Mmap_12___mmap_ARPROT;
+  wire [3:0] m_axi_rmem12___Stream2Mmap_12___mmap_ARQOS;
+  wire m_axi_rmem12___Stream2Mmap_12___mmap_ARREADY;
+  wire [2:0] m_axi_rmem12___Stream2Mmap_12___mmap_ARSIZE;
+  wire m_axi_rmem12___Stream2Mmap_12___mmap_ARVALID;
+  wire [63:0] m_axi_rmem12___Stream2Mmap_12___mmap_AWADDR;
+  wire [1:0] m_axi_rmem12___Stream2Mmap_12___mmap_AWBURST;
+  wire [3:0] m_axi_rmem12___Stream2Mmap_12___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem12___Stream2Mmap_12___mmap_AWID;
+  wire [7:0] m_axi_rmem12___Stream2Mmap_12___mmap_AWLEN;
+  wire m_axi_rmem12___Stream2Mmap_12___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem12___Stream2Mmap_12___mmap_AWPROT;
+  wire [3:0] m_axi_rmem12___Stream2Mmap_12___mmap_AWQOS;
+  wire m_axi_rmem12___Stream2Mmap_12___mmap_AWREADY;
+  wire [2:0] m_axi_rmem12___Stream2Mmap_12___mmap_AWSIZE;
+  wire m_axi_rmem12___Stream2Mmap_12___mmap_AWVALID;
+  wire [0:0] m_axi_rmem12___Stream2Mmap_12___mmap_BID;
+  wire m_axi_rmem12___Stream2Mmap_12___mmap_BREADY;
+  wire [1:0] m_axi_rmem12___Stream2Mmap_12___mmap_BRESP;
+  wire m_axi_rmem12___Stream2Mmap_12___mmap_BVALID;
+  wire [511:0] m_axi_rmem12___Stream2Mmap_12___mmap_RDATA;
+  wire [0:0] m_axi_rmem12___Stream2Mmap_12___mmap_RID;
+  wire m_axi_rmem12___Stream2Mmap_12___mmap_RLAST;
+  wire m_axi_rmem12___Stream2Mmap_12___mmap_RREADY;
+  wire [1:0] m_axi_rmem12___Stream2Mmap_12___mmap_RRESP;
+  wire m_axi_rmem12___Stream2Mmap_12___mmap_RVALID;
+  wire [511:0] m_axi_rmem12___Stream2Mmap_12___mmap_WDATA;
+  wire m_axi_rmem12___Stream2Mmap_12___mmap_WLAST;
+  wire m_axi_rmem12___Stream2Mmap_12___mmap_WREADY;
+  wire [63:0] m_axi_rmem12___Stream2Mmap_12___mmap_WSTRB;
+  wire m_axi_rmem12___Stream2Mmap_12___mmap_WVALID;
+  wire [63:0] m_axi_rmem13___Mmap2Stream_13___mmap_ARADDR;
+  wire [1:0] m_axi_rmem13___Mmap2Stream_13___mmap_ARBURST;
+  wire [3:0] m_axi_rmem13___Mmap2Stream_13___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem13___Mmap2Stream_13___mmap_ARID;
+  wire [7:0] m_axi_rmem13___Mmap2Stream_13___mmap_ARLEN;
+  wire m_axi_rmem13___Mmap2Stream_13___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem13___Mmap2Stream_13___mmap_ARPROT;
+  wire [3:0] m_axi_rmem13___Mmap2Stream_13___mmap_ARQOS;
+  wire m_axi_rmem13___Mmap2Stream_13___mmap_ARREADY;
+  wire [2:0] m_axi_rmem13___Mmap2Stream_13___mmap_ARSIZE;
+  wire m_axi_rmem13___Mmap2Stream_13___mmap_ARVALID;
+  wire [63:0] m_axi_rmem13___Mmap2Stream_13___mmap_AWADDR;
+  wire [1:0] m_axi_rmem13___Mmap2Stream_13___mmap_AWBURST;
+  wire [3:0] m_axi_rmem13___Mmap2Stream_13___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem13___Mmap2Stream_13___mmap_AWID;
+  wire [7:0] m_axi_rmem13___Mmap2Stream_13___mmap_AWLEN;
+  wire m_axi_rmem13___Mmap2Stream_13___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem13___Mmap2Stream_13___mmap_AWPROT;
+  wire [3:0] m_axi_rmem13___Mmap2Stream_13___mmap_AWQOS;
+  wire m_axi_rmem13___Mmap2Stream_13___mmap_AWREADY;
+  wire [2:0] m_axi_rmem13___Mmap2Stream_13___mmap_AWSIZE;
+  wire m_axi_rmem13___Mmap2Stream_13___mmap_AWVALID;
+  wire [0:0] m_axi_rmem13___Mmap2Stream_13___mmap_BID;
+  wire m_axi_rmem13___Mmap2Stream_13___mmap_BREADY;
+  wire [1:0] m_axi_rmem13___Mmap2Stream_13___mmap_BRESP;
+  wire m_axi_rmem13___Mmap2Stream_13___mmap_BVALID;
+  wire [511:0] m_axi_rmem13___Mmap2Stream_13___mmap_RDATA;
+  wire [0:0] m_axi_rmem13___Mmap2Stream_13___mmap_RID;
+  wire m_axi_rmem13___Mmap2Stream_13___mmap_RLAST;
+  wire m_axi_rmem13___Mmap2Stream_13___mmap_RREADY;
+  wire [1:0] m_axi_rmem13___Mmap2Stream_13___mmap_RRESP;
+  wire m_axi_rmem13___Mmap2Stream_13___mmap_RVALID;
+  wire [511:0] m_axi_rmem13___Mmap2Stream_13___mmap_WDATA;
+  wire m_axi_rmem13___Mmap2Stream_13___mmap_WLAST;
+  wire m_axi_rmem13___Mmap2Stream_13___mmap_WREADY;
+  wire [63:0] m_axi_rmem13___Mmap2Stream_13___mmap_WSTRB;
+  wire m_axi_rmem13___Mmap2Stream_13___mmap_WVALID;
+  wire [63:0] m_axi_rmem13___Stream2Mmap_13___mmap_ARADDR;
+  wire [1:0] m_axi_rmem13___Stream2Mmap_13___mmap_ARBURST;
+  wire [3:0] m_axi_rmem13___Stream2Mmap_13___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem13___Stream2Mmap_13___mmap_ARID;
+  wire [7:0] m_axi_rmem13___Stream2Mmap_13___mmap_ARLEN;
+  wire m_axi_rmem13___Stream2Mmap_13___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem13___Stream2Mmap_13___mmap_ARPROT;
+  wire [3:0] m_axi_rmem13___Stream2Mmap_13___mmap_ARQOS;
+  wire m_axi_rmem13___Stream2Mmap_13___mmap_ARREADY;
+  wire [2:0] m_axi_rmem13___Stream2Mmap_13___mmap_ARSIZE;
+  wire m_axi_rmem13___Stream2Mmap_13___mmap_ARVALID;
+  wire [63:0] m_axi_rmem13___Stream2Mmap_13___mmap_AWADDR;
+  wire [1:0] m_axi_rmem13___Stream2Mmap_13___mmap_AWBURST;
+  wire [3:0] m_axi_rmem13___Stream2Mmap_13___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem13___Stream2Mmap_13___mmap_AWID;
+  wire [7:0] m_axi_rmem13___Stream2Mmap_13___mmap_AWLEN;
+  wire m_axi_rmem13___Stream2Mmap_13___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem13___Stream2Mmap_13___mmap_AWPROT;
+  wire [3:0] m_axi_rmem13___Stream2Mmap_13___mmap_AWQOS;
+  wire m_axi_rmem13___Stream2Mmap_13___mmap_AWREADY;
+  wire [2:0] m_axi_rmem13___Stream2Mmap_13___mmap_AWSIZE;
+  wire m_axi_rmem13___Stream2Mmap_13___mmap_AWVALID;
+  wire [0:0] m_axi_rmem13___Stream2Mmap_13___mmap_BID;
+  wire m_axi_rmem13___Stream2Mmap_13___mmap_BREADY;
+  wire [1:0] m_axi_rmem13___Stream2Mmap_13___mmap_BRESP;
+  wire m_axi_rmem13___Stream2Mmap_13___mmap_BVALID;
+  wire [511:0] m_axi_rmem13___Stream2Mmap_13___mmap_RDATA;
+  wire [0:0] m_axi_rmem13___Stream2Mmap_13___mmap_RID;
+  wire m_axi_rmem13___Stream2Mmap_13___mmap_RLAST;
+  wire m_axi_rmem13___Stream2Mmap_13___mmap_RREADY;
+  wire [1:0] m_axi_rmem13___Stream2Mmap_13___mmap_RRESP;
+  wire m_axi_rmem13___Stream2Mmap_13___mmap_RVALID;
+  wire [511:0] m_axi_rmem13___Stream2Mmap_13___mmap_WDATA;
+  wire m_axi_rmem13___Stream2Mmap_13___mmap_WLAST;
+  wire m_axi_rmem13___Stream2Mmap_13___mmap_WREADY;
+  wire [63:0] m_axi_rmem13___Stream2Mmap_13___mmap_WSTRB;
+  wire m_axi_rmem13___Stream2Mmap_13___mmap_WVALID;
+  wire [63:0] m_axi_rmem14___Mmap2Stream_14___mmap_ARADDR;
+  wire [1:0] m_axi_rmem14___Mmap2Stream_14___mmap_ARBURST;
+  wire [3:0] m_axi_rmem14___Mmap2Stream_14___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem14___Mmap2Stream_14___mmap_ARID;
+  wire [7:0] m_axi_rmem14___Mmap2Stream_14___mmap_ARLEN;
+  wire m_axi_rmem14___Mmap2Stream_14___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem14___Mmap2Stream_14___mmap_ARPROT;
+  wire [3:0] m_axi_rmem14___Mmap2Stream_14___mmap_ARQOS;
+  wire m_axi_rmem14___Mmap2Stream_14___mmap_ARREADY;
+  wire [2:0] m_axi_rmem14___Mmap2Stream_14___mmap_ARSIZE;
+  wire m_axi_rmem14___Mmap2Stream_14___mmap_ARVALID;
+  wire [63:0] m_axi_rmem14___Mmap2Stream_14___mmap_AWADDR;
+  wire [1:0] m_axi_rmem14___Mmap2Stream_14___mmap_AWBURST;
+  wire [3:0] m_axi_rmem14___Mmap2Stream_14___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem14___Mmap2Stream_14___mmap_AWID;
+  wire [7:0] m_axi_rmem14___Mmap2Stream_14___mmap_AWLEN;
+  wire m_axi_rmem14___Mmap2Stream_14___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem14___Mmap2Stream_14___mmap_AWPROT;
+  wire [3:0] m_axi_rmem14___Mmap2Stream_14___mmap_AWQOS;
+  wire m_axi_rmem14___Mmap2Stream_14___mmap_AWREADY;
+  wire [2:0] m_axi_rmem14___Mmap2Stream_14___mmap_AWSIZE;
+  wire m_axi_rmem14___Mmap2Stream_14___mmap_AWVALID;
+  wire [0:0] m_axi_rmem14___Mmap2Stream_14___mmap_BID;
+  wire m_axi_rmem14___Mmap2Stream_14___mmap_BREADY;
+  wire [1:0] m_axi_rmem14___Mmap2Stream_14___mmap_BRESP;
+  wire m_axi_rmem14___Mmap2Stream_14___mmap_BVALID;
+  wire [511:0] m_axi_rmem14___Mmap2Stream_14___mmap_RDATA;
+  wire [0:0] m_axi_rmem14___Mmap2Stream_14___mmap_RID;
+  wire m_axi_rmem14___Mmap2Stream_14___mmap_RLAST;
+  wire m_axi_rmem14___Mmap2Stream_14___mmap_RREADY;
+  wire [1:0] m_axi_rmem14___Mmap2Stream_14___mmap_RRESP;
+  wire m_axi_rmem14___Mmap2Stream_14___mmap_RVALID;
+  wire [511:0] m_axi_rmem14___Mmap2Stream_14___mmap_WDATA;
+  wire m_axi_rmem14___Mmap2Stream_14___mmap_WLAST;
+  wire m_axi_rmem14___Mmap2Stream_14___mmap_WREADY;
+  wire [63:0] m_axi_rmem14___Mmap2Stream_14___mmap_WSTRB;
+  wire m_axi_rmem14___Mmap2Stream_14___mmap_WVALID;
+  wire [63:0] m_axi_rmem14___Stream2Mmap_14___mmap_ARADDR;
+  wire [1:0] m_axi_rmem14___Stream2Mmap_14___mmap_ARBURST;
+  wire [3:0] m_axi_rmem14___Stream2Mmap_14___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem14___Stream2Mmap_14___mmap_ARID;
+  wire [7:0] m_axi_rmem14___Stream2Mmap_14___mmap_ARLEN;
+  wire m_axi_rmem14___Stream2Mmap_14___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem14___Stream2Mmap_14___mmap_ARPROT;
+  wire [3:0] m_axi_rmem14___Stream2Mmap_14___mmap_ARQOS;
+  wire m_axi_rmem14___Stream2Mmap_14___mmap_ARREADY;
+  wire [2:0] m_axi_rmem14___Stream2Mmap_14___mmap_ARSIZE;
+  wire m_axi_rmem14___Stream2Mmap_14___mmap_ARVALID;
+  wire [63:0] m_axi_rmem14___Stream2Mmap_14___mmap_AWADDR;
+  wire [1:0] m_axi_rmem14___Stream2Mmap_14___mmap_AWBURST;
+  wire [3:0] m_axi_rmem14___Stream2Mmap_14___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem14___Stream2Mmap_14___mmap_AWID;
+  wire [7:0] m_axi_rmem14___Stream2Mmap_14___mmap_AWLEN;
+  wire m_axi_rmem14___Stream2Mmap_14___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem14___Stream2Mmap_14___mmap_AWPROT;
+  wire [3:0] m_axi_rmem14___Stream2Mmap_14___mmap_AWQOS;
+  wire m_axi_rmem14___Stream2Mmap_14___mmap_AWREADY;
+  wire [2:0] m_axi_rmem14___Stream2Mmap_14___mmap_AWSIZE;
+  wire m_axi_rmem14___Stream2Mmap_14___mmap_AWVALID;
+  wire [0:0] m_axi_rmem14___Stream2Mmap_14___mmap_BID;
+  wire m_axi_rmem14___Stream2Mmap_14___mmap_BREADY;
+  wire [1:0] m_axi_rmem14___Stream2Mmap_14___mmap_BRESP;
+  wire m_axi_rmem14___Stream2Mmap_14___mmap_BVALID;
+  wire [511:0] m_axi_rmem14___Stream2Mmap_14___mmap_RDATA;
+  wire [0:0] m_axi_rmem14___Stream2Mmap_14___mmap_RID;
+  wire m_axi_rmem14___Stream2Mmap_14___mmap_RLAST;
+  wire m_axi_rmem14___Stream2Mmap_14___mmap_RREADY;
+  wire [1:0] m_axi_rmem14___Stream2Mmap_14___mmap_RRESP;
+  wire m_axi_rmem14___Stream2Mmap_14___mmap_RVALID;
+  wire [511:0] m_axi_rmem14___Stream2Mmap_14___mmap_WDATA;
+  wire m_axi_rmem14___Stream2Mmap_14___mmap_WLAST;
+  wire m_axi_rmem14___Stream2Mmap_14___mmap_WREADY;
+  wire [63:0] m_axi_rmem14___Stream2Mmap_14___mmap_WSTRB;
+  wire m_axi_rmem14___Stream2Mmap_14___mmap_WVALID;
+  wire [63:0] m_axi_rmem15___Mmap2Stream_15___mmap_ARADDR;
+  wire [1:0] m_axi_rmem15___Mmap2Stream_15___mmap_ARBURST;
+  wire [3:0] m_axi_rmem15___Mmap2Stream_15___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem15___Mmap2Stream_15___mmap_ARID;
+  wire [7:0] m_axi_rmem15___Mmap2Stream_15___mmap_ARLEN;
+  wire m_axi_rmem15___Mmap2Stream_15___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem15___Mmap2Stream_15___mmap_ARPROT;
+  wire [3:0] m_axi_rmem15___Mmap2Stream_15___mmap_ARQOS;
+  wire m_axi_rmem15___Mmap2Stream_15___mmap_ARREADY;
+  wire [2:0] m_axi_rmem15___Mmap2Stream_15___mmap_ARSIZE;
+  wire m_axi_rmem15___Mmap2Stream_15___mmap_ARVALID;
+  wire [63:0] m_axi_rmem15___Mmap2Stream_15___mmap_AWADDR;
+  wire [1:0] m_axi_rmem15___Mmap2Stream_15___mmap_AWBURST;
+  wire [3:0] m_axi_rmem15___Mmap2Stream_15___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem15___Mmap2Stream_15___mmap_AWID;
+  wire [7:0] m_axi_rmem15___Mmap2Stream_15___mmap_AWLEN;
+  wire m_axi_rmem15___Mmap2Stream_15___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem15___Mmap2Stream_15___mmap_AWPROT;
+  wire [3:0] m_axi_rmem15___Mmap2Stream_15___mmap_AWQOS;
+  wire m_axi_rmem15___Mmap2Stream_15___mmap_AWREADY;
+  wire [2:0] m_axi_rmem15___Mmap2Stream_15___mmap_AWSIZE;
+  wire m_axi_rmem15___Mmap2Stream_15___mmap_AWVALID;
+  wire [0:0] m_axi_rmem15___Mmap2Stream_15___mmap_BID;
+  wire m_axi_rmem15___Mmap2Stream_15___mmap_BREADY;
+  wire [1:0] m_axi_rmem15___Mmap2Stream_15___mmap_BRESP;
+  wire m_axi_rmem15___Mmap2Stream_15___mmap_BVALID;
+  wire [511:0] m_axi_rmem15___Mmap2Stream_15___mmap_RDATA;
+  wire [0:0] m_axi_rmem15___Mmap2Stream_15___mmap_RID;
+  wire m_axi_rmem15___Mmap2Stream_15___mmap_RLAST;
+  wire m_axi_rmem15___Mmap2Stream_15___mmap_RREADY;
+  wire [1:0] m_axi_rmem15___Mmap2Stream_15___mmap_RRESP;
+  wire m_axi_rmem15___Mmap2Stream_15___mmap_RVALID;
+  wire [511:0] m_axi_rmem15___Mmap2Stream_15___mmap_WDATA;
+  wire m_axi_rmem15___Mmap2Stream_15___mmap_WLAST;
+  wire m_axi_rmem15___Mmap2Stream_15___mmap_WREADY;
+  wire [63:0] m_axi_rmem15___Mmap2Stream_15___mmap_WSTRB;
+  wire m_axi_rmem15___Mmap2Stream_15___mmap_WVALID;
+  wire [63:0] m_axi_rmem15___Stream2Mmap_15___mmap_ARADDR;
+  wire [1:0] m_axi_rmem15___Stream2Mmap_15___mmap_ARBURST;
+  wire [3:0] m_axi_rmem15___Stream2Mmap_15___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem15___Stream2Mmap_15___mmap_ARID;
+  wire [7:0] m_axi_rmem15___Stream2Mmap_15___mmap_ARLEN;
+  wire m_axi_rmem15___Stream2Mmap_15___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem15___Stream2Mmap_15___mmap_ARPROT;
+  wire [3:0] m_axi_rmem15___Stream2Mmap_15___mmap_ARQOS;
+  wire m_axi_rmem15___Stream2Mmap_15___mmap_ARREADY;
+  wire [2:0] m_axi_rmem15___Stream2Mmap_15___mmap_ARSIZE;
+  wire m_axi_rmem15___Stream2Mmap_15___mmap_ARVALID;
+  wire [63:0] m_axi_rmem15___Stream2Mmap_15___mmap_AWADDR;
+  wire [1:0] m_axi_rmem15___Stream2Mmap_15___mmap_AWBURST;
+  wire [3:0] m_axi_rmem15___Stream2Mmap_15___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem15___Stream2Mmap_15___mmap_AWID;
+  wire [7:0] m_axi_rmem15___Stream2Mmap_15___mmap_AWLEN;
+  wire m_axi_rmem15___Stream2Mmap_15___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem15___Stream2Mmap_15___mmap_AWPROT;
+  wire [3:0] m_axi_rmem15___Stream2Mmap_15___mmap_AWQOS;
+  wire m_axi_rmem15___Stream2Mmap_15___mmap_AWREADY;
+  wire [2:0] m_axi_rmem15___Stream2Mmap_15___mmap_AWSIZE;
+  wire m_axi_rmem15___Stream2Mmap_15___mmap_AWVALID;
+  wire [0:0] m_axi_rmem15___Stream2Mmap_15___mmap_BID;
+  wire m_axi_rmem15___Stream2Mmap_15___mmap_BREADY;
+  wire [1:0] m_axi_rmem15___Stream2Mmap_15___mmap_BRESP;
+  wire m_axi_rmem15___Stream2Mmap_15___mmap_BVALID;
+  wire [511:0] m_axi_rmem15___Stream2Mmap_15___mmap_RDATA;
+  wire [0:0] m_axi_rmem15___Stream2Mmap_15___mmap_RID;
+  wire m_axi_rmem15___Stream2Mmap_15___mmap_RLAST;
+  wire m_axi_rmem15___Stream2Mmap_15___mmap_RREADY;
+  wire [1:0] m_axi_rmem15___Stream2Mmap_15___mmap_RRESP;
+  wire m_axi_rmem15___Stream2Mmap_15___mmap_RVALID;
+  wire [511:0] m_axi_rmem15___Stream2Mmap_15___mmap_WDATA;
+  wire m_axi_rmem15___Stream2Mmap_15___mmap_WLAST;
+  wire m_axi_rmem15___Stream2Mmap_15___mmap_WREADY;
+  wire [63:0] m_axi_rmem15___Stream2Mmap_15___mmap_WSTRB;
+  wire m_axi_rmem15___Stream2Mmap_15___mmap_WVALID;
+  wire [63:0] m_axi_rmem16___Mmap2Stream_16___mmap_ARADDR;
+  wire [1:0] m_axi_rmem16___Mmap2Stream_16___mmap_ARBURST;
+  wire [3:0] m_axi_rmem16___Mmap2Stream_16___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem16___Mmap2Stream_16___mmap_ARID;
+  wire [7:0] m_axi_rmem16___Mmap2Stream_16___mmap_ARLEN;
+  wire m_axi_rmem16___Mmap2Stream_16___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem16___Mmap2Stream_16___mmap_ARPROT;
+  wire [3:0] m_axi_rmem16___Mmap2Stream_16___mmap_ARQOS;
+  wire m_axi_rmem16___Mmap2Stream_16___mmap_ARREADY;
+  wire [2:0] m_axi_rmem16___Mmap2Stream_16___mmap_ARSIZE;
+  wire m_axi_rmem16___Mmap2Stream_16___mmap_ARVALID;
+  wire [63:0] m_axi_rmem16___Mmap2Stream_16___mmap_AWADDR;
+  wire [1:0] m_axi_rmem16___Mmap2Stream_16___mmap_AWBURST;
+  wire [3:0] m_axi_rmem16___Mmap2Stream_16___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem16___Mmap2Stream_16___mmap_AWID;
+  wire [7:0] m_axi_rmem16___Mmap2Stream_16___mmap_AWLEN;
+  wire m_axi_rmem16___Mmap2Stream_16___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem16___Mmap2Stream_16___mmap_AWPROT;
+  wire [3:0] m_axi_rmem16___Mmap2Stream_16___mmap_AWQOS;
+  wire m_axi_rmem16___Mmap2Stream_16___mmap_AWREADY;
+  wire [2:0] m_axi_rmem16___Mmap2Stream_16___mmap_AWSIZE;
+  wire m_axi_rmem16___Mmap2Stream_16___mmap_AWVALID;
+  wire [0:0] m_axi_rmem16___Mmap2Stream_16___mmap_BID;
+  wire m_axi_rmem16___Mmap2Stream_16___mmap_BREADY;
+  wire [1:0] m_axi_rmem16___Mmap2Stream_16___mmap_BRESP;
+  wire m_axi_rmem16___Mmap2Stream_16___mmap_BVALID;
+  wire [511:0] m_axi_rmem16___Mmap2Stream_16___mmap_RDATA;
+  wire [0:0] m_axi_rmem16___Mmap2Stream_16___mmap_RID;
+  wire m_axi_rmem16___Mmap2Stream_16___mmap_RLAST;
+  wire m_axi_rmem16___Mmap2Stream_16___mmap_RREADY;
+  wire [1:0] m_axi_rmem16___Mmap2Stream_16___mmap_RRESP;
+  wire m_axi_rmem16___Mmap2Stream_16___mmap_RVALID;
+  wire [511:0] m_axi_rmem16___Mmap2Stream_16___mmap_WDATA;
+  wire m_axi_rmem16___Mmap2Stream_16___mmap_WLAST;
+  wire m_axi_rmem16___Mmap2Stream_16___mmap_WREADY;
+  wire [63:0] m_axi_rmem16___Mmap2Stream_16___mmap_WSTRB;
+  wire m_axi_rmem16___Mmap2Stream_16___mmap_WVALID;
+  wire [63:0] m_axi_rmem16___Stream2Mmap_16___mmap_ARADDR;
+  wire [1:0] m_axi_rmem16___Stream2Mmap_16___mmap_ARBURST;
+  wire [3:0] m_axi_rmem16___Stream2Mmap_16___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem16___Stream2Mmap_16___mmap_ARID;
+  wire [7:0] m_axi_rmem16___Stream2Mmap_16___mmap_ARLEN;
+  wire m_axi_rmem16___Stream2Mmap_16___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem16___Stream2Mmap_16___mmap_ARPROT;
+  wire [3:0] m_axi_rmem16___Stream2Mmap_16___mmap_ARQOS;
+  wire m_axi_rmem16___Stream2Mmap_16___mmap_ARREADY;
+  wire [2:0] m_axi_rmem16___Stream2Mmap_16___mmap_ARSIZE;
+  wire m_axi_rmem16___Stream2Mmap_16___mmap_ARVALID;
+  wire [63:0] m_axi_rmem16___Stream2Mmap_16___mmap_AWADDR;
+  wire [1:0] m_axi_rmem16___Stream2Mmap_16___mmap_AWBURST;
+  wire [3:0] m_axi_rmem16___Stream2Mmap_16___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem16___Stream2Mmap_16___mmap_AWID;
+  wire [7:0] m_axi_rmem16___Stream2Mmap_16___mmap_AWLEN;
+  wire m_axi_rmem16___Stream2Mmap_16___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem16___Stream2Mmap_16___mmap_AWPROT;
+  wire [3:0] m_axi_rmem16___Stream2Mmap_16___mmap_AWQOS;
+  wire m_axi_rmem16___Stream2Mmap_16___mmap_AWREADY;
+  wire [2:0] m_axi_rmem16___Stream2Mmap_16___mmap_AWSIZE;
+  wire m_axi_rmem16___Stream2Mmap_16___mmap_AWVALID;
+  wire [0:0] m_axi_rmem16___Stream2Mmap_16___mmap_BID;
+  wire m_axi_rmem16___Stream2Mmap_16___mmap_BREADY;
+  wire [1:0] m_axi_rmem16___Stream2Mmap_16___mmap_BRESP;
+  wire m_axi_rmem16___Stream2Mmap_16___mmap_BVALID;
+  wire [511:0] m_axi_rmem16___Stream2Mmap_16___mmap_RDATA;
+  wire [0:0] m_axi_rmem16___Stream2Mmap_16___mmap_RID;
+  wire m_axi_rmem16___Stream2Mmap_16___mmap_RLAST;
+  wire m_axi_rmem16___Stream2Mmap_16___mmap_RREADY;
+  wire [1:0] m_axi_rmem16___Stream2Mmap_16___mmap_RRESP;
+  wire m_axi_rmem16___Stream2Mmap_16___mmap_RVALID;
+  wire [511:0] m_axi_rmem16___Stream2Mmap_16___mmap_WDATA;
+  wire m_axi_rmem16___Stream2Mmap_16___mmap_WLAST;
+  wire m_axi_rmem16___Stream2Mmap_16___mmap_WREADY;
+  wire [63:0] m_axi_rmem16___Stream2Mmap_16___mmap_WSTRB;
+  wire m_axi_rmem16___Stream2Mmap_16___mmap_WVALID;
+  wire [63:0] m_axi_rmem17___Mmap2Stream_17___mmap_ARADDR;
+  wire [1:0] m_axi_rmem17___Mmap2Stream_17___mmap_ARBURST;
+  wire [3:0] m_axi_rmem17___Mmap2Stream_17___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem17___Mmap2Stream_17___mmap_ARID;
+  wire [7:0] m_axi_rmem17___Mmap2Stream_17___mmap_ARLEN;
+  wire m_axi_rmem17___Mmap2Stream_17___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem17___Mmap2Stream_17___mmap_ARPROT;
+  wire [3:0] m_axi_rmem17___Mmap2Stream_17___mmap_ARQOS;
+  wire m_axi_rmem17___Mmap2Stream_17___mmap_ARREADY;
+  wire [2:0] m_axi_rmem17___Mmap2Stream_17___mmap_ARSIZE;
+  wire m_axi_rmem17___Mmap2Stream_17___mmap_ARVALID;
+  wire [63:0] m_axi_rmem17___Mmap2Stream_17___mmap_AWADDR;
+  wire [1:0] m_axi_rmem17___Mmap2Stream_17___mmap_AWBURST;
+  wire [3:0] m_axi_rmem17___Mmap2Stream_17___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem17___Mmap2Stream_17___mmap_AWID;
+  wire [7:0] m_axi_rmem17___Mmap2Stream_17___mmap_AWLEN;
+  wire m_axi_rmem17___Mmap2Stream_17___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem17___Mmap2Stream_17___mmap_AWPROT;
+  wire [3:0] m_axi_rmem17___Mmap2Stream_17___mmap_AWQOS;
+  wire m_axi_rmem17___Mmap2Stream_17___mmap_AWREADY;
+  wire [2:0] m_axi_rmem17___Mmap2Stream_17___mmap_AWSIZE;
+  wire m_axi_rmem17___Mmap2Stream_17___mmap_AWVALID;
+  wire [0:0] m_axi_rmem17___Mmap2Stream_17___mmap_BID;
+  wire m_axi_rmem17___Mmap2Stream_17___mmap_BREADY;
+  wire [1:0] m_axi_rmem17___Mmap2Stream_17___mmap_BRESP;
+  wire m_axi_rmem17___Mmap2Stream_17___mmap_BVALID;
+  wire [511:0] m_axi_rmem17___Mmap2Stream_17___mmap_RDATA;
+  wire [0:0] m_axi_rmem17___Mmap2Stream_17___mmap_RID;
+  wire m_axi_rmem17___Mmap2Stream_17___mmap_RLAST;
+  wire m_axi_rmem17___Mmap2Stream_17___mmap_RREADY;
+  wire [1:0] m_axi_rmem17___Mmap2Stream_17___mmap_RRESP;
+  wire m_axi_rmem17___Mmap2Stream_17___mmap_RVALID;
+  wire [511:0] m_axi_rmem17___Mmap2Stream_17___mmap_WDATA;
+  wire m_axi_rmem17___Mmap2Stream_17___mmap_WLAST;
+  wire m_axi_rmem17___Mmap2Stream_17___mmap_WREADY;
+  wire [63:0] m_axi_rmem17___Mmap2Stream_17___mmap_WSTRB;
+  wire m_axi_rmem17___Mmap2Stream_17___mmap_WVALID;
+  wire [63:0] m_axi_rmem17___Stream2Mmap_17___mmap_ARADDR;
+  wire [1:0] m_axi_rmem17___Stream2Mmap_17___mmap_ARBURST;
+  wire [3:0] m_axi_rmem17___Stream2Mmap_17___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem17___Stream2Mmap_17___mmap_ARID;
+  wire [7:0] m_axi_rmem17___Stream2Mmap_17___mmap_ARLEN;
+  wire m_axi_rmem17___Stream2Mmap_17___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem17___Stream2Mmap_17___mmap_ARPROT;
+  wire [3:0] m_axi_rmem17___Stream2Mmap_17___mmap_ARQOS;
+  wire m_axi_rmem17___Stream2Mmap_17___mmap_ARREADY;
+  wire [2:0] m_axi_rmem17___Stream2Mmap_17___mmap_ARSIZE;
+  wire m_axi_rmem17___Stream2Mmap_17___mmap_ARVALID;
+  wire [63:0] m_axi_rmem17___Stream2Mmap_17___mmap_AWADDR;
+  wire [1:0] m_axi_rmem17___Stream2Mmap_17___mmap_AWBURST;
+  wire [3:0] m_axi_rmem17___Stream2Mmap_17___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem17___Stream2Mmap_17___mmap_AWID;
+  wire [7:0] m_axi_rmem17___Stream2Mmap_17___mmap_AWLEN;
+  wire m_axi_rmem17___Stream2Mmap_17___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem17___Stream2Mmap_17___mmap_AWPROT;
+  wire [3:0] m_axi_rmem17___Stream2Mmap_17___mmap_AWQOS;
+  wire m_axi_rmem17___Stream2Mmap_17___mmap_AWREADY;
+  wire [2:0] m_axi_rmem17___Stream2Mmap_17___mmap_AWSIZE;
+  wire m_axi_rmem17___Stream2Mmap_17___mmap_AWVALID;
+  wire [0:0] m_axi_rmem17___Stream2Mmap_17___mmap_BID;
+  wire m_axi_rmem17___Stream2Mmap_17___mmap_BREADY;
+  wire [1:0] m_axi_rmem17___Stream2Mmap_17___mmap_BRESP;
+  wire m_axi_rmem17___Stream2Mmap_17___mmap_BVALID;
+  wire [511:0] m_axi_rmem17___Stream2Mmap_17___mmap_RDATA;
+  wire [0:0] m_axi_rmem17___Stream2Mmap_17___mmap_RID;
+  wire m_axi_rmem17___Stream2Mmap_17___mmap_RLAST;
+  wire m_axi_rmem17___Stream2Mmap_17___mmap_RREADY;
+  wire [1:0] m_axi_rmem17___Stream2Mmap_17___mmap_RRESP;
+  wire m_axi_rmem17___Stream2Mmap_17___mmap_RVALID;
+  wire [511:0] m_axi_rmem17___Stream2Mmap_17___mmap_WDATA;
+  wire m_axi_rmem17___Stream2Mmap_17___mmap_WLAST;
+  wire m_axi_rmem17___Stream2Mmap_17___mmap_WREADY;
+  wire [63:0] m_axi_rmem17___Stream2Mmap_17___mmap_WSTRB;
+  wire m_axi_rmem17___Stream2Mmap_17___mmap_WVALID;
+  wire [63:0] m_axi_rmem18___Mmap2Stream_18___mmap_ARADDR;
+  wire [1:0] m_axi_rmem18___Mmap2Stream_18___mmap_ARBURST;
+  wire [3:0] m_axi_rmem18___Mmap2Stream_18___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem18___Mmap2Stream_18___mmap_ARID;
+  wire [7:0] m_axi_rmem18___Mmap2Stream_18___mmap_ARLEN;
+  wire m_axi_rmem18___Mmap2Stream_18___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem18___Mmap2Stream_18___mmap_ARPROT;
+  wire [3:0] m_axi_rmem18___Mmap2Stream_18___mmap_ARQOS;
+  wire m_axi_rmem18___Mmap2Stream_18___mmap_ARREADY;
+  wire [2:0] m_axi_rmem18___Mmap2Stream_18___mmap_ARSIZE;
+  wire m_axi_rmem18___Mmap2Stream_18___mmap_ARVALID;
+  wire [63:0] m_axi_rmem18___Mmap2Stream_18___mmap_AWADDR;
+  wire [1:0] m_axi_rmem18___Mmap2Stream_18___mmap_AWBURST;
+  wire [3:0] m_axi_rmem18___Mmap2Stream_18___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem18___Mmap2Stream_18___mmap_AWID;
+  wire [7:0] m_axi_rmem18___Mmap2Stream_18___mmap_AWLEN;
+  wire m_axi_rmem18___Mmap2Stream_18___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem18___Mmap2Stream_18___mmap_AWPROT;
+  wire [3:0] m_axi_rmem18___Mmap2Stream_18___mmap_AWQOS;
+  wire m_axi_rmem18___Mmap2Stream_18___mmap_AWREADY;
+  wire [2:0] m_axi_rmem18___Mmap2Stream_18___mmap_AWSIZE;
+  wire m_axi_rmem18___Mmap2Stream_18___mmap_AWVALID;
+  wire [0:0] m_axi_rmem18___Mmap2Stream_18___mmap_BID;
+  wire m_axi_rmem18___Mmap2Stream_18___mmap_BREADY;
+  wire [1:0] m_axi_rmem18___Mmap2Stream_18___mmap_BRESP;
+  wire m_axi_rmem18___Mmap2Stream_18___mmap_BVALID;
+  wire [511:0] m_axi_rmem18___Mmap2Stream_18___mmap_RDATA;
+  wire [0:0] m_axi_rmem18___Mmap2Stream_18___mmap_RID;
+  wire m_axi_rmem18___Mmap2Stream_18___mmap_RLAST;
+  wire m_axi_rmem18___Mmap2Stream_18___mmap_RREADY;
+  wire [1:0] m_axi_rmem18___Mmap2Stream_18___mmap_RRESP;
+  wire m_axi_rmem18___Mmap2Stream_18___mmap_RVALID;
+  wire [511:0] m_axi_rmem18___Mmap2Stream_18___mmap_WDATA;
+  wire m_axi_rmem18___Mmap2Stream_18___mmap_WLAST;
+  wire m_axi_rmem18___Mmap2Stream_18___mmap_WREADY;
+  wire [63:0] m_axi_rmem18___Mmap2Stream_18___mmap_WSTRB;
+  wire m_axi_rmem18___Mmap2Stream_18___mmap_WVALID;
+  wire [63:0] m_axi_rmem18___Stream2Mmap_18___mmap_ARADDR;
+  wire [1:0] m_axi_rmem18___Stream2Mmap_18___mmap_ARBURST;
+  wire [3:0] m_axi_rmem18___Stream2Mmap_18___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem18___Stream2Mmap_18___mmap_ARID;
+  wire [7:0] m_axi_rmem18___Stream2Mmap_18___mmap_ARLEN;
+  wire m_axi_rmem18___Stream2Mmap_18___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem18___Stream2Mmap_18___mmap_ARPROT;
+  wire [3:0] m_axi_rmem18___Stream2Mmap_18___mmap_ARQOS;
+  wire m_axi_rmem18___Stream2Mmap_18___mmap_ARREADY;
+  wire [2:0] m_axi_rmem18___Stream2Mmap_18___mmap_ARSIZE;
+  wire m_axi_rmem18___Stream2Mmap_18___mmap_ARVALID;
+  wire [63:0] m_axi_rmem18___Stream2Mmap_18___mmap_AWADDR;
+  wire [1:0] m_axi_rmem18___Stream2Mmap_18___mmap_AWBURST;
+  wire [3:0] m_axi_rmem18___Stream2Mmap_18___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem18___Stream2Mmap_18___mmap_AWID;
+  wire [7:0] m_axi_rmem18___Stream2Mmap_18___mmap_AWLEN;
+  wire m_axi_rmem18___Stream2Mmap_18___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem18___Stream2Mmap_18___mmap_AWPROT;
+  wire [3:0] m_axi_rmem18___Stream2Mmap_18___mmap_AWQOS;
+  wire m_axi_rmem18___Stream2Mmap_18___mmap_AWREADY;
+  wire [2:0] m_axi_rmem18___Stream2Mmap_18___mmap_AWSIZE;
+  wire m_axi_rmem18___Stream2Mmap_18___mmap_AWVALID;
+  wire [0:0] m_axi_rmem18___Stream2Mmap_18___mmap_BID;
+  wire m_axi_rmem18___Stream2Mmap_18___mmap_BREADY;
+  wire [1:0] m_axi_rmem18___Stream2Mmap_18___mmap_BRESP;
+  wire m_axi_rmem18___Stream2Mmap_18___mmap_BVALID;
+  wire [511:0] m_axi_rmem18___Stream2Mmap_18___mmap_RDATA;
+  wire [0:0] m_axi_rmem18___Stream2Mmap_18___mmap_RID;
+  wire m_axi_rmem18___Stream2Mmap_18___mmap_RLAST;
+  wire m_axi_rmem18___Stream2Mmap_18___mmap_RREADY;
+  wire [1:0] m_axi_rmem18___Stream2Mmap_18___mmap_RRESP;
+  wire m_axi_rmem18___Stream2Mmap_18___mmap_RVALID;
+  wire [511:0] m_axi_rmem18___Stream2Mmap_18___mmap_WDATA;
+  wire m_axi_rmem18___Stream2Mmap_18___mmap_WLAST;
+  wire m_axi_rmem18___Stream2Mmap_18___mmap_WREADY;
+  wire [63:0] m_axi_rmem18___Stream2Mmap_18___mmap_WSTRB;
+  wire m_axi_rmem18___Stream2Mmap_18___mmap_WVALID;
+  wire [63:0] m_axi_rmem19___Mmap2Stream_19___mmap_ARADDR;
+  wire [1:0] m_axi_rmem19___Mmap2Stream_19___mmap_ARBURST;
+  wire [3:0] m_axi_rmem19___Mmap2Stream_19___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem19___Mmap2Stream_19___mmap_ARID;
+  wire [7:0] m_axi_rmem19___Mmap2Stream_19___mmap_ARLEN;
+  wire m_axi_rmem19___Mmap2Stream_19___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem19___Mmap2Stream_19___mmap_ARPROT;
+  wire [3:0] m_axi_rmem19___Mmap2Stream_19___mmap_ARQOS;
+  wire m_axi_rmem19___Mmap2Stream_19___mmap_ARREADY;
+  wire [2:0] m_axi_rmem19___Mmap2Stream_19___mmap_ARSIZE;
+  wire m_axi_rmem19___Mmap2Stream_19___mmap_ARVALID;
+  wire [63:0] m_axi_rmem19___Mmap2Stream_19___mmap_AWADDR;
+  wire [1:0] m_axi_rmem19___Mmap2Stream_19___mmap_AWBURST;
+  wire [3:0] m_axi_rmem19___Mmap2Stream_19___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem19___Mmap2Stream_19___mmap_AWID;
+  wire [7:0] m_axi_rmem19___Mmap2Stream_19___mmap_AWLEN;
+  wire m_axi_rmem19___Mmap2Stream_19___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem19___Mmap2Stream_19___mmap_AWPROT;
+  wire [3:0] m_axi_rmem19___Mmap2Stream_19___mmap_AWQOS;
+  wire m_axi_rmem19___Mmap2Stream_19___mmap_AWREADY;
+  wire [2:0] m_axi_rmem19___Mmap2Stream_19___mmap_AWSIZE;
+  wire m_axi_rmem19___Mmap2Stream_19___mmap_AWVALID;
+  wire [0:0] m_axi_rmem19___Mmap2Stream_19___mmap_BID;
+  wire m_axi_rmem19___Mmap2Stream_19___mmap_BREADY;
+  wire [1:0] m_axi_rmem19___Mmap2Stream_19___mmap_BRESP;
+  wire m_axi_rmem19___Mmap2Stream_19___mmap_BVALID;
+  wire [511:0] m_axi_rmem19___Mmap2Stream_19___mmap_RDATA;
+  wire [0:0] m_axi_rmem19___Mmap2Stream_19___mmap_RID;
+  wire m_axi_rmem19___Mmap2Stream_19___mmap_RLAST;
+  wire m_axi_rmem19___Mmap2Stream_19___mmap_RREADY;
+  wire [1:0] m_axi_rmem19___Mmap2Stream_19___mmap_RRESP;
+  wire m_axi_rmem19___Mmap2Stream_19___mmap_RVALID;
+  wire [511:0] m_axi_rmem19___Mmap2Stream_19___mmap_WDATA;
+  wire m_axi_rmem19___Mmap2Stream_19___mmap_WLAST;
+  wire m_axi_rmem19___Mmap2Stream_19___mmap_WREADY;
+  wire [63:0] m_axi_rmem19___Mmap2Stream_19___mmap_WSTRB;
+  wire m_axi_rmem19___Mmap2Stream_19___mmap_WVALID;
+  wire [63:0] m_axi_rmem19___Stream2Mmap_19___mmap_ARADDR;
+  wire [1:0] m_axi_rmem19___Stream2Mmap_19___mmap_ARBURST;
+  wire [3:0] m_axi_rmem19___Stream2Mmap_19___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem19___Stream2Mmap_19___mmap_ARID;
+  wire [7:0] m_axi_rmem19___Stream2Mmap_19___mmap_ARLEN;
+  wire m_axi_rmem19___Stream2Mmap_19___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem19___Stream2Mmap_19___mmap_ARPROT;
+  wire [3:0] m_axi_rmem19___Stream2Mmap_19___mmap_ARQOS;
+  wire m_axi_rmem19___Stream2Mmap_19___mmap_ARREADY;
+  wire [2:0] m_axi_rmem19___Stream2Mmap_19___mmap_ARSIZE;
+  wire m_axi_rmem19___Stream2Mmap_19___mmap_ARVALID;
+  wire [63:0] m_axi_rmem19___Stream2Mmap_19___mmap_AWADDR;
+  wire [1:0] m_axi_rmem19___Stream2Mmap_19___mmap_AWBURST;
+  wire [3:0] m_axi_rmem19___Stream2Mmap_19___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem19___Stream2Mmap_19___mmap_AWID;
+  wire [7:0] m_axi_rmem19___Stream2Mmap_19___mmap_AWLEN;
+  wire m_axi_rmem19___Stream2Mmap_19___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem19___Stream2Mmap_19___mmap_AWPROT;
+  wire [3:0] m_axi_rmem19___Stream2Mmap_19___mmap_AWQOS;
+  wire m_axi_rmem19___Stream2Mmap_19___mmap_AWREADY;
+  wire [2:0] m_axi_rmem19___Stream2Mmap_19___mmap_AWSIZE;
+  wire m_axi_rmem19___Stream2Mmap_19___mmap_AWVALID;
+  wire [0:0] m_axi_rmem19___Stream2Mmap_19___mmap_BID;
+  wire m_axi_rmem19___Stream2Mmap_19___mmap_BREADY;
+  wire [1:0] m_axi_rmem19___Stream2Mmap_19___mmap_BRESP;
+  wire m_axi_rmem19___Stream2Mmap_19___mmap_BVALID;
+  wire [511:0] m_axi_rmem19___Stream2Mmap_19___mmap_RDATA;
+  wire [0:0] m_axi_rmem19___Stream2Mmap_19___mmap_RID;
+  wire m_axi_rmem19___Stream2Mmap_19___mmap_RLAST;
+  wire m_axi_rmem19___Stream2Mmap_19___mmap_RREADY;
+  wire [1:0] m_axi_rmem19___Stream2Mmap_19___mmap_RRESP;
+  wire m_axi_rmem19___Stream2Mmap_19___mmap_RVALID;
+  wire [511:0] m_axi_rmem19___Stream2Mmap_19___mmap_WDATA;
+  wire m_axi_rmem19___Stream2Mmap_19___mmap_WLAST;
+  wire m_axi_rmem19___Stream2Mmap_19___mmap_WREADY;
+  wire [63:0] m_axi_rmem19___Stream2Mmap_19___mmap_WSTRB;
+  wire m_axi_rmem19___Stream2Mmap_19___mmap_WVALID;
+  wire [63:0] m_axi_rmem20___Mmap2Stream_20___mmap_ARADDR;
+  wire [1:0] m_axi_rmem20___Mmap2Stream_20___mmap_ARBURST;
+  wire [3:0] m_axi_rmem20___Mmap2Stream_20___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem20___Mmap2Stream_20___mmap_ARID;
+  wire [7:0] m_axi_rmem20___Mmap2Stream_20___mmap_ARLEN;
+  wire m_axi_rmem20___Mmap2Stream_20___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem20___Mmap2Stream_20___mmap_ARPROT;
+  wire [3:0] m_axi_rmem20___Mmap2Stream_20___mmap_ARQOS;
+  wire m_axi_rmem20___Mmap2Stream_20___mmap_ARREADY;
+  wire [2:0] m_axi_rmem20___Mmap2Stream_20___mmap_ARSIZE;
+  wire m_axi_rmem20___Mmap2Stream_20___mmap_ARVALID;
+  wire [63:0] m_axi_rmem20___Mmap2Stream_20___mmap_AWADDR;
+  wire [1:0] m_axi_rmem20___Mmap2Stream_20___mmap_AWBURST;
+  wire [3:0] m_axi_rmem20___Mmap2Stream_20___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem20___Mmap2Stream_20___mmap_AWID;
+  wire [7:0] m_axi_rmem20___Mmap2Stream_20___mmap_AWLEN;
+  wire m_axi_rmem20___Mmap2Stream_20___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem20___Mmap2Stream_20___mmap_AWPROT;
+  wire [3:0] m_axi_rmem20___Mmap2Stream_20___mmap_AWQOS;
+  wire m_axi_rmem20___Mmap2Stream_20___mmap_AWREADY;
+  wire [2:0] m_axi_rmem20___Mmap2Stream_20___mmap_AWSIZE;
+  wire m_axi_rmem20___Mmap2Stream_20___mmap_AWVALID;
+  wire [0:0] m_axi_rmem20___Mmap2Stream_20___mmap_BID;
+  wire m_axi_rmem20___Mmap2Stream_20___mmap_BREADY;
+  wire [1:0] m_axi_rmem20___Mmap2Stream_20___mmap_BRESP;
+  wire m_axi_rmem20___Mmap2Stream_20___mmap_BVALID;
+  wire [511:0] m_axi_rmem20___Mmap2Stream_20___mmap_RDATA;
+  wire [0:0] m_axi_rmem20___Mmap2Stream_20___mmap_RID;
+  wire m_axi_rmem20___Mmap2Stream_20___mmap_RLAST;
+  wire m_axi_rmem20___Mmap2Stream_20___mmap_RREADY;
+  wire [1:0] m_axi_rmem20___Mmap2Stream_20___mmap_RRESP;
+  wire m_axi_rmem20___Mmap2Stream_20___mmap_RVALID;
+  wire [511:0] m_axi_rmem20___Mmap2Stream_20___mmap_WDATA;
+  wire m_axi_rmem20___Mmap2Stream_20___mmap_WLAST;
+  wire m_axi_rmem20___Mmap2Stream_20___mmap_WREADY;
+  wire [63:0] m_axi_rmem20___Mmap2Stream_20___mmap_WSTRB;
+  wire m_axi_rmem20___Mmap2Stream_20___mmap_WVALID;
+  wire [63:0] m_axi_rmem20___Stream2Mmap_20___mmap_ARADDR;
+  wire [1:0] m_axi_rmem20___Stream2Mmap_20___mmap_ARBURST;
+  wire [3:0] m_axi_rmem20___Stream2Mmap_20___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem20___Stream2Mmap_20___mmap_ARID;
+  wire [7:0] m_axi_rmem20___Stream2Mmap_20___mmap_ARLEN;
+  wire m_axi_rmem20___Stream2Mmap_20___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem20___Stream2Mmap_20___mmap_ARPROT;
+  wire [3:0] m_axi_rmem20___Stream2Mmap_20___mmap_ARQOS;
+  wire m_axi_rmem20___Stream2Mmap_20___mmap_ARREADY;
+  wire [2:0] m_axi_rmem20___Stream2Mmap_20___mmap_ARSIZE;
+  wire m_axi_rmem20___Stream2Mmap_20___mmap_ARVALID;
+  wire [63:0] m_axi_rmem20___Stream2Mmap_20___mmap_AWADDR;
+  wire [1:0] m_axi_rmem20___Stream2Mmap_20___mmap_AWBURST;
+  wire [3:0] m_axi_rmem20___Stream2Mmap_20___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem20___Stream2Mmap_20___mmap_AWID;
+  wire [7:0] m_axi_rmem20___Stream2Mmap_20___mmap_AWLEN;
+  wire m_axi_rmem20___Stream2Mmap_20___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem20___Stream2Mmap_20___mmap_AWPROT;
+  wire [3:0] m_axi_rmem20___Stream2Mmap_20___mmap_AWQOS;
+  wire m_axi_rmem20___Stream2Mmap_20___mmap_AWREADY;
+  wire [2:0] m_axi_rmem20___Stream2Mmap_20___mmap_AWSIZE;
+  wire m_axi_rmem20___Stream2Mmap_20___mmap_AWVALID;
+  wire [0:0] m_axi_rmem20___Stream2Mmap_20___mmap_BID;
+  wire m_axi_rmem20___Stream2Mmap_20___mmap_BREADY;
+  wire [1:0] m_axi_rmem20___Stream2Mmap_20___mmap_BRESP;
+  wire m_axi_rmem20___Stream2Mmap_20___mmap_BVALID;
+  wire [511:0] m_axi_rmem20___Stream2Mmap_20___mmap_RDATA;
+  wire [0:0] m_axi_rmem20___Stream2Mmap_20___mmap_RID;
+  wire m_axi_rmem20___Stream2Mmap_20___mmap_RLAST;
+  wire m_axi_rmem20___Stream2Mmap_20___mmap_RREADY;
+  wire [1:0] m_axi_rmem20___Stream2Mmap_20___mmap_RRESP;
+  wire m_axi_rmem20___Stream2Mmap_20___mmap_RVALID;
+  wire [511:0] m_axi_rmem20___Stream2Mmap_20___mmap_WDATA;
+  wire m_axi_rmem20___Stream2Mmap_20___mmap_WLAST;
+  wire m_axi_rmem20___Stream2Mmap_20___mmap_WREADY;
+  wire [63:0] m_axi_rmem20___Stream2Mmap_20___mmap_WSTRB;
+  wire m_axi_rmem20___Stream2Mmap_20___mmap_WVALID;
+  wire [63:0] m_axi_rmem21___Mmap2Stream_21___mmap_ARADDR;
+  wire [1:0] m_axi_rmem21___Mmap2Stream_21___mmap_ARBURST;
+  wire [3:0] m_axi_rmem21___Mmap2Stream_21___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem21___Mmap2Stream_21___mmap_ARID;
+  wire [7:0] m_axi_rmem21___Mmap2Stream_21___mmap_ARLEN;
+  wire m_axi_rmem21___Mmap2Stream_21___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem21___Mmap2Stream_21___mmap_ARPROT;
+  wire [3:0] m_axi_rmem21___Mmap2Stream_21___mmap_ARQOS;
+  wire m_axi_rmem21___Mmap2Stream_21___mmap_ARREADY;
+  wire [2:0] m_axi_rmem21___Mmap2Stream_21___mmap_ARSIZE;
+  wire m_axi_rmem21___Mmap2Stream_21___mmap_ARVALID;
+  wire [63:0] m_axi_rmem21___Mmap2Stream_21___mmap_AWADDR;
+  wire [1:0] m_axi_rmem21___Mmap2Stream_21___mmap_AWBURST;
+  wire [3:0] m_axi_rmem21___Mmap2Stream_21___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem21___Mmap2Stream_21___mmap_AWID;
+  wire [7:0] m_axi_rmem21___Mmap2Stream_21___mmap_AWLEN;
+  wire m_axi_rmem21___Mmap2Stream_21___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem21___Mmap2Stream_21___mmap_AWPROT;
+  wire [3:0] m_axi_rmem21___Mmap2Stream_21___mmap_AWQOS;
+  wire m_axi_rmem21___Mmap2Stream_21___mmap_AWREADY;
+  wire [2:0] m_axi_rmem21___Mmap2Stream_21___mmap_AWSIZE;
+  wire m_axi_rmem21___Mmap2Stream_21___mmap_AWVALID;
+  wire [0:0] m_axi_rmem21___Mmap2Stream_21___mmap_BID;
+  wire m_axi_rmem21___Mmap2Stream_21___mmap_BREADY;
+  wire [1:0] m_axi_rmem21___Mmap2Stream_21___mmap_BRESP;
+  wire m_axi_rmem21___Mmap2Stream_21___mmap_BVALID;
+  wire [511:0] m_axi_rmem21___Mmap2Stream_21___mmap_RDATA;
+  wire [0:0] m_axi_rmem21___Mmap2Stream_21___mmap_RID;
+  wire m_axi_rmem21___Mmap2Stream_21___mmap_RLAST;
+  wire m_axi_rmem21___Mmap2Stream_21___mmap_RREADY;
+  wire [1:0] m_axi_rmem21___Mmap2Stream_21___mmap_RRESP;
+  wire m_axi_rmem21___Mmap2Stream_21___mmap_RVALID;
+  wire [511:0] m_axi_rmem21___Mmap2Stream_21___mmap_WDATA;
+  wire m_axi_rmem21___Mmap2Stream_21___mmap_WLAST;
+  wire m_axi_rmem21___Mmap2Stream_21___mmap_WREADY;
+  wire [63:0] m_axi_rmem21___Mmap2Stream_21___mmap_WSTRB;
+  wire m_axi_rmem21___Mmap2Stream_21___mmap_WVALID;
+  wire [63:0] m_axi_rmem21___Stream2Mmap_21___mmap_ARADDR;
+  wire [1:0] m_axi_rmem21___Stream2Mmap_21___mmap_ARBURST;
+  wire [3:0] m_axi_rmem21___Stream2Mmap_21___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem21___Stream2Mmap_21___mmap_ARID;
+  wire [7:0] m_axi_rmem21___Stream2Mmap_21___mmap_ARLEN;
+  wire m_axi_rmem21___Stream2Mmap_21___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem21___Stream2Mmap_21___mmap_ARPROT;
+  wire [3:0] m_axi_rmem21___Stream2Mmap_21___mmap_ARQOS;
+  wire m_axi_rmem21___Stream2Mmap_21___mmap_ARREADY;
+  wire [2:0] m_axi_rmem21___Stream2Mmap_21___mmap_ARSIZE;
+  wire m_axi_rmem21___Stream2Mmap_21___mmap_ARVALID;
+  wire [63:0] m_axi_rmem21___Stream2Mmap_21___mmap_AWADDR;
+  wire [1:0] m_axi_rmem21___Stream2Mmap_21___mmap_AWBURST;
+  wire [3:0] m_axi_rmem21___Stream2Mmap_21___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem21___Stream2Mmap_21___mmap_AWID;
+  wire [7:0] m_axi_rmem21___Stream2Mmap_21___mmap_AWLEN;
+  wire m_axi_rmem21___Stream2Mmap_21___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem21___Stream2Mmap_21___mmap_AWPROT;
+  wire [3:0] m_axi_rmem21___Stream2Mmap_21___mmap_AWQOS;
+  wire m_axi_rmem21___Stream2Mmap_21___mmap_AWREADY;
+  wire [2:0] m_axi_rmem21___Stream2Mmap_21___mmap_AWSIZE;
+  wire m_axi_rmem21___Stream2Mmap_21___mmap_AWVALID;
+  wire [0:0] m_axi_rmem21___Stream2Mmap_21___mmap_BID;
+  wire m_axi_rmem21___Stream2Mmap_21___mmap_BREADY;
+  wire [1:0] m_axi_rmem21___Stream2Mmap_21___mmap_BRESP;
+  wire m_axi_rmem21___Stream2Mmap_21___mmap_BVALID;
+  wire [511:0] m_axi_rmem21___Stream2Mmap_21___mmap_RDATA;
+  wire [0:0] m_axi_rmem21___Stream2Mmap_21___mmap_RID;
+  wire m_axi_rmem21___Stream2Mmap_21___mmap_RLAST;
+  wire m_axi_rmem21___Stream2Mmap_21___mmap_RREADY;
+  wire [1:0] m_axi_rmem21___Stream2Mmap_21___mmap_RRESP;
+  wire m_axi_rmem21___Stream2Mmap_21___mmap_RVALID;
+  wire [511:0] m_axi_rmem21___Stream2Mmap_21___mmap_WDATA;
+  wire m_axi_rmem21___Stream2Mmap_21___mmap_WLAST;
+  wire m_axi_rmem21___Stream2Mmap_21___mmap_WREADY;
+  wire [63:0] m_axi_rmem21___Stream2Mmap_21___mmap_WSTRB;
+  wire m_axi_rmem21___Stream2Mmap_21___mmap_WVALID;
+  wire [63:0] m_axi_rmem22___Mmap2Stream_22___mmap_ARADDR;
+  wire [1:0] m_axi_rmem22___Mmap2Stream_22___mmap_ARBURST;
+  wire [3:0] m_axi_rmem22___Mmap2Stream_22___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem22___Mmap2Stream_22___mmap_ARID;
+  wire [7:0] m_axi_rmem22___Mmap2Stream_22___mmap_ARLEN;
+  wire m_axi_rmem22___Mmap2Stream_22___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem22___Mmap2Stream_22___mmap_ARPROT;
+  wire [3:0] m_axi_rmem22___Mmap2Stream_22___mmap_ARQOS;
+  wire m_axi_rmem22___Mmap2Stream_22___mmap_ARREADY;
+  wire [2:0] m_axi_rmem22___Mmap2Stream_22___mmap_ARSIZE;
+  wire m_axi_rmem22___Mmap2Stream_22___mmap_ARVALID;
+  wire [63:0] m_axi_rmem22___Mmap2Stream_22___mmap_AWADDR;
+  wire [1:0] m_axi_rmem22___Mmap2Stream_22___mmap_AWBURST;
+  wire [3:0] m_axi_rmem22___Mmap2Stream_22___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem22___Mmap2Stream_22___mmap_AWID;
+  wire [7:0] m_axi_rmem22___Mmap2Stream_22___mmap_AWLEN;
+  wire m_axi_rmem22___Mmap2Stream_22___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem22___Mmap2Stream_22___mmap_AWPROT;
+  wire [3:0] m_axi_rmem22___Mmap2Stream_22___mmap_AWQOS;
+  wire m_axi_rmem22___Mmap2Stream_22___mmap_AWREADY;
+  wire [2:0] m_axi_rmem22___Mmap2Stream_22___mmap_AWSIZE;
+  wire m_axi_rmem22___Mmap2Stream_22___mmap_AWVALID;
+  wire [0:0] m_axi_rmem22___Mmap2Stream_22___mmap_BID;
+  wire m_axi_rmem22___Mmap2Stream_22___mmap_BREADY;
+  wire [1:0] m_axi_rmem22___Mmap2Stream_22___mmap_BRESP;
+  wire m_axi_rmem22___Mmap2Stream_22___mmap_BVALID;
+  wire [511:0] m_axi_rmem22___Mmap2Stream_22___mmap_RDATA;
+  wire [0:0] m_axi_rmem22___Mmap2Stream_22___mmap_RID;
+  wire m_axi_rmem22___Mmap2Stream_22___mmap_RLAST;
+  wire m_axi_rmem22___Mmap2Stream_22___mmap_RREADY;
+  wire [1:0] m_axi_rmem22___Mmap2Stream_22___mmap_RRESP;
+  wire m_axi_rmem22___Mmap2Stream_22___mmap_RVALID;
+  wire [511:0] m_axi_rmem22___Mmap2Stream_22___mmap_WDATA;
+  wire m_axi_rmem22___Mmap2Stream_22___mmap_WLAST;
+  wire m_axi_rmem22___Mmap2Stream_22___mmap_WREADY;
+  wire [63:0] m_axi_rmem22___Mmap2Stream_22___mmap_WSTRB;
+  wire m_axi_rmem22___Mmap2Stream_22___mmap_WVALID;
+  wire [63:0] m_axi_rmem22___Stream2Mmap_22___mmap_ARADDR;
+  wire [1:0] m_axi_rmem22___Stream2Mmap_22___mmap_ARBURST;
+  wire [3:0] m_axi_rmem22___Stream2Mmap_22___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem22___Stream2Mmap_22___mmap_ARID;
+  wire [7:0] m_axi_rmem22___Stream2Mmap_22___mmap_ARLEN;
+  wire m_axi_rmem22___Stream2Mmap_22___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem22___Stream2Mmap_22___mmap_ARPROT;
+  wire [3:0] m_axi_rmem22___Stream2Mmap_22___mmap_ARQOS;
+  wire m_axi_rmem22___Stream2Mmap_22___mmap_ARREADY;
+  wire [2:0] m_axi_rmem22___Stream2Mmap_22___mmap_ARSIZE;
+  wire m_axi_rmem22___Stream2Mmap_22___mmap_ARVALID;
+  wire [63:0] m_axi_rmem22___Stream2Mmap_22___mmap_AWADDR;
+  wire [1:0] m_axi_rmem22___Stream2Mmap_22___mmap_AWBURST;
+  wire [3:0] m_axi_rmem22___Stream2Mmap_22___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem22___Stream2Mmap_22___mmap_AWID;
+  wire [7:0] m_axi_rmem22___Stream2Mmap_22___mmap_AWLEN;
+  wire m_axi_rmem22___Stream2Mmap_22___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem22___Stream2Mmap_22___mmap_AWPROT;
+  wire [3:0] m_axi_rmem22___Stream2Mmap_22___mmap_AWQOS;
+  wire m_axi_rmem22___Stream2Mmap_22___mmap_AWREADY;
+  wire [2:0] m_axi_rmem22___Stream2Mmap_22___mmap_AWSIZE;
+  wire m_axi_rmem22___Stream2Mmap_22___mmap_AWVALID;
+  wire [0:0] m_axi_rmem22___Stream2Mmap_22___mmap_BID;
+  wire m_axi_rmem22___Stream2Mmap_22___mmap_BREADY;
+  wire [1:0] m_axi_rmem22___Stream2Mmap_22___mmap_BRESP;
+  wire m_axi_rmem22___Stream2Mmap_22___mmap_BVALID;
+  wire [511:0] m_axi_rmem22___Stream2Mmap_22___mmap_RDATA;
+  wire [0:0] m_axi_rmem22___Stream2Mmap_22___mmap_RID;
+  wire m_axi_rmem22___Stream2Mmap_22___mmap_RLAST;
+  wire m_axi_rmem22___Stream2Mmap_22___mmap_RREADY;
+  wire [1:0] m_axi_rmem22___Stream2Mmap_22___mmap_RRESP;
+  wire m_axi_rmem22___Stream2Mmap_22___mmap_RVALID;
+  wire [511:0] m_axi_rmem22___Stream2Mmap_22___mmap_WDATA;
+  wire m_axi_rmem22___Stream2Mmap_22___mmap_WLAST;
+  wire m_axi_rmem22___Stream2Mmap_22___mmap_WREADY;
+  wire [63:0] m_axi_rmem22___Stream2Mmap_22___mmap_WSTRB;
+  wire m_axi_rmem22___Stream2Mmap_22___mmap_WVALID;
+  wire [63:0] m_axi_rmem23___Mmap2Stream_23___mmap_ARADDR;
+  wire [1:0] m_axi_rmem23___Mmap2Stream_23___mmap_ARBURST;
+  wire [3:0] m_axi_rmem23___Mmap2Stream_23___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem23___Mmap2Stream_23___mmap_ARID;
+  wire [7:0] m_axi_rmem23___Mmap2Stream_23___mmap_ARLEN;
+  wire m_axi_rmem23___Mmap2Stream_23___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem23___Mmap2Stream_23___mmap_ARPROT;
+  wire [3:0] m_axi_rmem23___Mmap2Stream_23___mmap_ARQOS;
+  wire m_axi_rmem23___Mmap2Stream_23___mmap_ARREADY;
+  wire [2:0] m_axi_rmem23___Mmap2Stream_23___mmap_ARSIZE;
+  wire m_axi_rmem23___Mmap2Stream_23___mmap_ARVALID;
+  wire [63:0] m_axi_rmem23___Mmap2Stream_23___mmap_AWADDR;
+  wire [1:0] m_axi_rmem23___Mmap2Stream_23___mmap_AWBURST;
+  wire [3:0] m_axi_rmem23___Mmap2Stream_23___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem23___Mmap2Stream_23___mmap_AWID;
+  wire [7:0] m_axi_rmem23___Mmap2Stream_23___mmap_AWLEN;
+  wire m_axi_rmem23___Mmap2Stream_23___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem23___Mmap2Stream_23___mmap_AWPROT;
+  wire [3:0] m_axi_rmem23___Mmap2Stream_23___mmap_AWQOS;
+  wire m_axi_rmem23___Mmap2Stream_23___mmap_AWREADY;
+  wire [2:0] m_axi_rmem23___Mmap2Stream_23___mmap_AWSIZE;
+  wire m_axi_rmem23___Mmap2Stream_23___mmap_AWVALID;
+  wire [0:0] m_axi_rmem23___Mmap2Stream_23___mmap_BID;
+  wire m_axi_rmem23___Mmap2Stream_23___mmap_BREADY;
+  wire [1:0] m_axi_rmem23___Mmap2Stream_23___mmap_BRESP;
+  wire m_axi_rmem23___Mmap2Stream_23___mmap_BVALID;
+  wire [511:0] m_axi_rmem23___Mmap2Stream_23___mmap_RDATA;
+  wire [0:0] m_axi_rmem23___Mmap2Stream_23___mmap_RID;
+  wire m_axi_rmem23___Mmap2Stream_23___mmap_RLAST;
+  wire m_axi_rmem23___Mmap2Stream_23___mmap_RREADY;
+  wire [1:0] m_axi_rmem23___Mmap2Stream_23___mmap_RRESP;
+  wire m_axi_rmem23___Mmap2Stream_23___mmap_RVALID;
+  wire [511:0] m_axi_rmem23___Mmap2Stream_23___mmap_WDATA;
+  wire m_axi_rmem23___Mmap2Stream_23___mmap_WLAST;
+  wire m_axi_rmem23___Mmap2Stream_23___mmap_WREADY;
+  wire [63:0] m_axi_rmem23___Mmap2Stream_23___mmap_WSTRB;
+  wire m_axi_rmem23___Mmap2Stream_23___mmap_WVALID;
+  wire [63:0] m_axi_rmem23___Stream2Mmap_23___mmap_ARADDR;
+  wire [1:0] m_axi_rmem23___Stream2Mmap_23___mmap_ARBURST;
+  wire [3:0] m_axi_rmem23___Stream2Mmap_23___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem23___Stream2Mmap_23___mmap_ARID;
+  wire [7:0] m_axi_rmem23___Stream2Mmap_23___mmap_ARLEN;
+  wire m_axi_rmem23___Stream2Mmap_23___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem23___Stream2Mmap_23___mmap_ARPROT;
+  wire [3:0] m_axi_rmem23___Stream2Mmap_23___mmap_ARQOS;
+  wire m_axi_rmem23___Stream2Mmap_23___mmap_ARREADY;
+  wire [2:0] m_axi_rmem23___Stream2Mmap_23___mmap_ARSIZE;
+  wire m_axi_rmem23___Stream2Mmap_23___mmap_ARVALID;
+  wire [63:0] m_axi_rmem23___Stream2Mmap_23___mmap_AWADDR;
+  wire [1:0] m_axi_rmem23___Stream2Mmap_23___mmap_AWBURST;
+  wire [3:0] m_axi_rmem23___Stream2Mmap_23___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem23___Stream2Mmap_23___mmap_AWID;
+  wire [7:0] m_axi_rmem23___Stream2Mmap_23___mmap_AWLEN;
+  wire m_axi_rmem23___Stream2Mmap_23___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem23___Stream2Mmap_23___mmap_AWPROT;
+  wire [3:0] m_axi_rmem23___Stream2Mmap_23___mmap_AWQOS;
+  wire m_axi_rmem23___Stream2Mmap_23___mmap_AWREADY;
+  wire [2:0] m_axi_rmem23___Stream2Mmap_23___mmap_AWSIZE;
+  wire m_axi_rmem23___Stream2Mmap_23___mmap_AWVALID;
+  wire [0:0] m_axi_rmem23___Stream2Mmap_23___mmap_BID;
+  wire m_axi_rmem23___Stream2Mmap_23___mmap_BREADY;
+  wire [1:0] m_axi_rmem23___Stream2Mmap_23___mmap_BRESP;
+  wire m_axi_rmem23___Stream2Mmap_23___mmap_BVALID;
+  wire [511:0] m_axi_rmem23___Stream2Mmap_23___mmap_RDATA;
+  wire [0:0] m_axi_rmem23___Stream2Mmap_23___mmap_RID;
+  wire m_axi_rmem23___Stream2Mmap_23___mmap_RLAST;
+  wire m_axi_rmem23___Stream2Mmap_23___mmap_RREADY;
+  wire [1:0] m_axi_rmem23___Stream2Mmap_23___mmap_RRESP;
+  wire m_axi_rmem23___Stream2Mmap_23___mmap_RVALID;
+  wire [511:0] m_axi_rmem23___Stream2Mmap_23___mmap_WDATA;
+  wire m_axi_rmem23___Stream2Mmap_23___mmap_WLAST;
+  wire m_axi_rmem23___Stream2Mmap_23___mmap_WREADY;
+  wire [63:0] m_axi_rmem23___Stream2Mmap_23___mmap_WSTRB;
+  wire m_axi_rmem23___Stream2Mmap_23___mmap_WVALID;
+  wire [63:0] m_axi_rmem24___Mmap2Stream_24___mmap_ARADDR;
+  wire [1:0] m_axi_rmem24___Mmap2Stream_24___mmap_ARBURST;
+  wire [3:0] m_axi_rmem24___Mmap2Stream_24___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem24___Mmap2Stream_24___mmap_ARID;
+  wire [7:0] m_axi_rmem24___Mmap2Stream_24___mmap_ARLEN;
+  wire m_axi_rmem24___Mmap2Stream_24___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem24___Mmap2Stream_24___mmap_ARPROT;
+  wire [3:0] m_axi_rmem24___Mmap2Stream_24___mmap_ARQOS;
+  wire m_axi_rmem24___Mmap2Stream_24___mmap_ARREADY;
+  wire [2:0] m_axi_rmem24___Mmap2Stream_24___mmap_ARSIZE;
+  wire m_axi_rmem24___Mmap2Stream_24___mmap_ARVALID;
+  wire [63:0] m_axi_rmem24___Mmap2Stream_24___mmap_AWADDR;
+  wire [1:0] m_axi_rmem24___Mmap2Stream_24___mmap_AWBURST;
+  wire [3:0] m_axi_rmem24___Mmap2Stream_24___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem24___Mmap2Stream_24___mmap_AWID;
+  wire [7:0] m_axi_rmem24___Mmap2Stream_24___mmap_AWLEN;
+  wire m_axi_rmem24___Mmap2Stream_24___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem24___Mmap2Stream_24___mmap_AWPROT;
+  wire [3:0] m_axi_rmem24___Mmap2Stream_24___mmap_AWQOS;
+  wire m_axi_rmem24___Mmap2Stream_24___mmap_AWREADY;
+  wire [2:0] m_axi_rmem24___Mmap2Stream_24___mmap_AWSIZE;
+  wire m_axi_rmem24___Mmap2Stream_24___mmap_AWVALID;
+  wire [0:0] m_axi_rmem24___Mmap2Stream_24___mmap_BID;
+  wire m_axi_rmem24___Mmap2Stream_24___mmap_BREADY;
+  wire [1:0] m_axi_rmem24___Mmap2Stream_24___mmap_BRESP;
+  wire m_axi_rmem24___Mmap2Stream_24___mmap_BVALID;
+  wire [511:0] m_axi_rmem24___Mmap2Stream_24___mmap_RDATA;
+  wire [0:0] m_axi_rmem24___Mmap2Stream_24___mmap_RID;
+  wire m_axi_rmem24___Mmap2Stream_24___mmap_RLAST;
+  wire m_axi_rmem24___Mmap2Stream_24___mmap_RREADY;
+  wire [1:0] m_axi_rmem24___Mmap2Stream_24___mmap_RRESP;
+  wire m_axi_rmem24___Mmap2Stream_24___mmap_RVALID;
+  wire [511:0] m_axi_rmem24___Mmap2Stream_24___mmap_WDATA;
+  wire m_axi_rmem24___Mmap2Stream_24___mmap_WLAST;
+  wire m_axi_rmem24___Mmap2Stream_24___mmap_WREADY;
+  wire [63:0] m_axi_rmem24___Mmap2Stream_24___mmap_WSTRB;
+  wire m_axi_rmem24___Mmap2Stream_24___mmap_WVALID;
+  wire [63:0] m_axi_rmem24___Stream2Mmap_24___mmap_ARADDR;
+  wire [1:0] m_axi_rmem24___Stream2Mmap_24___mmap_ARBURST;
+  wire [3:0] m_axi_rmem24___Stream2Mmap_24___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem24___Stream2Mmap_24___mmap_ARID;
+  wire [7:0] m_axi_rmem24___Stream2Mmap_24___mmap_ARLEN;
+  wire m_axi_rmem24___Stream2Mmap_24___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem24___Stream2Mmap_24___mmap_ARPROT;
+  wire [3:0] m_axi_rmem24___Stream2Mmap_24___mmap_ARQOS;
+  wire m_axi_rmem24___Stream2Mmap_24___mmap_ARREADY;
+  wire [2:0] m_axi_rmem24___Stream2Mmap_24___mmap_ARSIZE;
+  wire m_axi_rmem24___Stream2Mmap_24___mmap_ARVALID;
+  wire [63:0] m_axi_rmem24___Stream2Mmap_24___mmap_AWADDR;
+  wire [1:0] m_axi_rmem24___Stream2Mmap_24___mmap_AWBURST;
+  wire [3:0] m_axi_rmem24___Stream2Mmap_24___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem24___Stream2Mmap_24___mmap_AWID;
+  wire [7:0] m_axi_rmem24___Stream2Mmap_24___mmap_AWLEN;
+  wire m_axi_rmem24___Stream2Mmap_24___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem24___Stream2Mmap_24___mmap_AWPROT;
+  wire [3:0] m_axi_rmem24___Stream2Mmap_24___mmap_AWQOS;
+  wire m_axi_rmem24___Stream2Mmap_24___mmap_AWREADY;
+  wire [2:0] m_axi_rmem24___Stream2Mmap_24___mmap_AWSIZE;
+  wire m_axi_rmem24___Stream2Mmap_24___mmap_AWVALID;
+  wire [0:0] m_axi_rmem24___Stream2Mmap_24___mmap_BID;
+  wire m_axi_rmem24___Stream2Mmap_24___mmap_BREADY;
+  wire [1:0] m_axi_rmem24___Stream2Mmap_24___mmap_BRESP;
+  wire m_axi_rmem24___Stream2Mmap_24___mmap_BVALID;
+  wire [511:0] m_axi_rmem24___Stream2Mmap_24___mmap_RDATA;
+  wire [0:0] m_axi_rmem24___Stream2Mmap_24___mmap_RID;
+  wire m_axi_rmem24___Stream2Mmap_24___mmap_RLAST;
+  wire m_axi_rmem24___Stream2Mmap_24___mmap_RREADY;
+  wire [1:0] m_axi_rmem24___Stream2Mmap_24___mmap_RRESP;
+  wire m_axi_rmem24___Stream2Mmap_24___mmap_RVALID;
+  wire [511:0] m_axi_rmem24___Stream2Mmap_24___mmap_WDATA;
+  wire m_axi_rmem24___Stream2Mmap_24___mmap_WLAST;
+  wire m_axi_rmem24___Stream2Mmap_24___mmap_WREADY;
+  wire [63:0] m_axi_rmem24___Stream2Mmap_24___mmap_WSTRB;
+  wire m_axi_rmem24___Stream2Mmap_24___mmap_WVALID;
+  wire [63:0] m_axi_rmem25___Mmap2Stream_25___mmap_ARADDR;
+  wire [1:0] m_axi_rmem25___Mmap2Stream_25___mmap_ARBURST;
+  wire [3:0] m_axi_rmem25___Mmap2Stream_25___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem25___Mmap2Stream_25___mmap_ARID;
+  wire [7:0] m_axi_rmem25___Mmap2Stream_25___mmap_ARLEN;
+  wire m_axi_rmem25___Mmap2Stream_25___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem25___Mmap2Stream_25___mmap_ARPROT;
+  wire [3:0] m_axi_rmem25___Mmap2Stream_25___mmap_ARQOS;
+  wire m_axi_rmem25___Mmap2Stream_25___mmap_ARREADY;
+  wire [2:0] m_axi_rmem25___Mmap2Stream_25___mmap_ARSIZE;
+  wire m_axi_rmem25___Mmap2Stream_25___mmap_ARVALID;
+  wire [63:0] m_axi_rmem25___Mmap2Stream_25___mmap_AWADDR;
+  wire [1:0] m_axi_rmem25___Mmap2Stream_25___mmap_AWBURST;
+  wire [3:0] m_axi_rmem25___Mmap2Stream_25___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem25___Mmap2Stream_25___mmap_AWID;
+  wire [7:0] m_axi_rmem25___Mmap2Stream_25___mmap_AWLEN;
+  wire m_axi_rmem25___Mmap2Stream_25___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem25___Mmap2Stream_25___mmap_AWPROT;
+  wire [3:0] m_axi_rmem25___Mmap2Stream_25___mmap_AWQOS;
+  wire m_axi_rmem25___Mmap2Stream_25___mmap_AWREADY;
+  wire [2:0] m_axi_rmem25___Mmap2Stream_25___mmap_AWSIZE;
+  wire m_axi_rmem25___Mmap2Stream_25___mmap_AWVALID;
+  wire [0:0] m_axi_rmem25___Mmap2Stream_25___mmap_BID;
+  wire m_axi_rmem25___Mmap2Stream_25___mmap_BREADY;
+  wire [1:0] m_axi_rmem25___Mmap2Stream_25___mmap_BRESP;
+  wire m_axi_rmem25___Mmap2Stream_25___mmap_BVALID;
+  wire [511:0] m_axi_rmem25___Mmap2Stream_25___mmap_RDATA;
+  wire [0:0] m_axi_rmem25___Mmap2Stream_25___mmap_RID;
+  wire m_axi_rmem25___Mmap2Stream_25___mmap_RLAST;
+  wire m_axi_rmem25___Mmap2Stream_25___mmap_RREADY;
+  wire [1:0] m_axi_rmem25___Mmap2Stream_25___mmap_RRESP;
+  wire m_axi_rmem25___Mmap2Stream_25___mmap_RVALID;
+  wire [511:0] m_axi_rmem25___Mmap2Stream_25___mmap_WDATA;
+  wire m_axi_rmem25___Mmap2Stream_25___mmap_WLAST;
+  wire m_axi_rmem25___Mmap2Stream_25___mmap_WREADY;
+  wire [63:0] m_axi_rmem25___Mmap2Stream_25___mmap_WSTRB;
+  wire m_axi_rmem25___Mmap2Stream_25___mmap_WVALID;
+  wire [63:0] m_axi_rmem25___Stream2Mmap_25___mmap_ARADDR;
+  wire [1:0] m_axi_rmem25___Stream2Mmap_25___mmap_ARBURST;
+  wire [3:0] m_axi_rmem25___Stream2Mmap_25___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem25___Stream2Mmap_25___mmap_ARID;
+  wire [7:0] m_axi_rmem25___Stream2Mmap_25___mmap_ARLEN;
+  wire m_axi_rmem25___Stream2Mmap_25___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem25___Stream2Mmap_25___mmap_ARPROT;
+  wire [3:0] m_axi_rmem25___Stream2Mmap_25___mmap_ARQOS;
+  wire m_axi_rmem25___Stream2Mmap_25___mmap_ARREADY;
+  wire [2:0] m_axi_rmem25___Stream2Mmap_25___mmap_ARSIZE;
+  wire m_axi_rmem25___Stream2Mmap_25___mmap_ARVALID;
+  wire [63:0] m_axi_rmem25___Stream2Mmap_25___mmap_AWADDR;
+  wire [1:0] m_axi_rmem25___Stream2Mmap_25___mmap_AWBURST;
+  wire [3:0] m_axi_rmem25___Stream2Mmap_25___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem25___Stream2Mmap_25___mmap_AWID;
+  wire [7:0] m_axi_rmem25___Stream2Mmap_25___mmap_AWLEN;
+  wire m_axi_rmem25___Stream2Mmap_25___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem25___Stream2Mmap_25___mmap_AWPROT;
+  wire [3:0] m_axi_rmem25___Stream2Mmap_25___mmap_AWQOS;
+  wire m_axi_rmem25___Stream2Mmap_25___mmap_AWREADY;
+  wire [2:0] m_axi_rmem25___Stream2Mmap_25___mmap_AWSIZE;
+  wire m_axi_rmem25___Stream2Mmap_25___mmap_AWVALID;
+  wire [0:0] m_axi_rmem25___Stream2Mmap_25___mmap_BID;
+  wire m_axi_rmem25___Stream2Mmap_25___mmap_BREADY;
+  wire [1:0] m_axi_rmem25___Stream2Mmap_25___mmap_BRESP;
+  wire m_axi_rmem25___Stream2Mmap_25___mmap_BVALID;
+  wire [511:0] m_axi_rmem25___Stream2Mmap_25___mmap_RDATA;
+  wire [0:0] m_axi_rmem25___Stream2Mmap_25___mmap_RID;
+  wire m_axi_rmem25___Stream2Mmap_25___mmap_RLAST;
+  wire m_axi_rmem25___Stream2Mmap_25___mmap_RREADY;
+  wire [1:0] m_axi_rmem25___Stream2Mmap_25___mmap_RRESP;
+  wire m_axi_rmem25___Stream2Mmap_25___mmap_RVALID;
+  wire [511:0] m_axi_rmem25___Stream2Mmap_25___mmap_WDATA;
+  wire m_axi_rmem25___Stream2Mmap_25___mmap_WLAST;
+  wire m_axi_rmem25___Stream2Mmap_25___mmap_WREADY;
+  wire [63:0] m_axi_rmem25___Stream2Mmap_25___mmap_WSTRB;
+  wire m_axi_rmem25___Stream2Mmap_25___mmap_WVALID;
+  wire [63:0] m_axi_rmem26___Mmap2Stream_26___mmap_ARADDR;
+  wire [1:0] m_axi_rmem26___Mmap2Stream_26___mmap_ARBURST;
+  wire [3:0] m_axi_rmem26___Mmap2Stream_26___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem26___Mmap2Stream_26___mmap_ARID;
+  wire [7:0] m_axi_rmem26___Mmap2Stream_26___mmap_ARLEN;
+  wire m_axi_rmem26___Mmap2Stream_26___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem26___Mmap2Stream_26___mmap_ARPROT;
+  wire [3:0] m_axi_rmem26___Mmap2Stream_26___mmap_ARQOS;
+  wire m_axi_rmem26___Mmap2Stream_26___mmap_ARREADY;
+  wire [2:0] m_axi_rmem26___Mmap2Stream_26___mmap_ARSIZE;
+  wire m_axi_rmem26___Mmap2Stream_26___mmap_ARVALID;
+  wire [63:0] m_axi_rmem26___Mmap2Stream_26___mmap_AWADDR;
+  wire [1:0] m_axi_rmem26___Mmap2Stream_26___mmap_AWBURST;
+  wire [3:0] m_axi_rmem26___Mmap2Stream_26___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem26___Mmap2Stream_26___mmap_AWID;
+  wire [7:0] m_axi_rmem26___Mmap2Stream_26___mmap_AWLEN;
+  wire m_axi_rmem26___Mmap2Stream_26___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem26___Mmap2Stream_26___mmap_AWPROT;
+  wire [3:0] m_axi_rmem26___Mmap2Stream_26___mmap_AWQOS;
+  wire m_axi_rmem26___Mmap2Stream_26___mmap_AWREADY;
+  wire [2:0] m_axi_rmem26___Mmap2Stream_26___mmap_AWSIZE;
+  wire m_axi_rmem26___Mmap2Stream_26___mmap_AWVALID;
+  wire [0:0] m_axi_rmem26___Mmap2Stream_26___mmap_BID;
+  wire m_axi_rmem26___Mmap2Stream_26___mmap_BREADY;
+  wire [1:0] m_axi_rmem26___Mmap2Stream_26___mmap_BRESP;
+  wire m_axi_rmem26___Mmap2Stream_26___mmap_BVALID;
+  wire [511:0] m_axi_rmem26___Mmap2Stream_26___mmap_RDATA;
+  wire [0:0] m_axi_rmem26___Mmap2Stream_26___mmap_RID;
+  wire m_axi_rmem26___Mmap2Stream_26___mmap_RLAST;
+  wire m_axi_rmem26___Mmap2Stream_26___mmap_RREADY;
+  wire [1:0] m_axi_rmem26___Mmap2Stream_26___mmap_RRESP;
+  wire m_axi_rmem26___Mmap2Stream_26___mmap_RVALID;
+  wire [511:0] m_axi_rmem26___Mmap2Stream_26___mmap_WDATA;
+  wire m_axi_rmem26___Mmap2Stream_26___mmap_WLAST;
+  wire m_axi_rmem26___Mmap2Stream_26___mmap_WREADY;
+  wire [63:0] m_axi_rmem26___Mmap2Stream_26___mmap_WSTRB;
+  wire m_axi_rmem26___Mmap2Stream_26___mmap_WVALID;
+  wire [63:0] m_axi_rmem26___Stream2Mmap_26___mmap_ARADDR;
+  wire [1:0] m_axi_rmem26___Stream2Mmap_26___mmap_ARBURST;
+  wire [3:0] m_axi_rmem26___Stream2Mmap_26___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem26___Stream2Mmap_26___mmap_ARID;
+  wire [7:0] m_axi_rmem26___Stream2Mmap_26___mmap_ARLEN;
+  wire m_axi_rmem26___Stream2Mmap_26___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem26___Stream2Mmap_26___mmap_ARPROT;
+  wire [3:0] m_axi_rmem26___Stream2Mmap_26___mmap_ARQOS;
+  wire m_axi_rmem26___Stream2Mmap_26___mmap_ARREADY;
+  wire [2:0] m_axi_rmem26___Stream2Mmap_26___mmap_ARSIZE;
+  wire m_axi_rmem26___Stream2Mmap_26___mmap_ARVALID;
+  wire [63:0] m_axi_rmem26___Stream2Mmap_26___mmap_AWADDR;
+  wire [1:0] m_axi_rmem26___Stream2Mmap_26___mmap_AWBURST;
+  wire [3:0] m_axi_rmem26___Stream2Mmap_26___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem26___Stream2Mmap_26___mmap_AWID;
+  wire [7:0] m_axi_rmem26___Stream2Mmap_26___mmap_AWLEN;
+  wire m_axi_rmem26___Stream2Mmap_26___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem26___Stream2Mmap_26___mmap_AWPROT;
+  wire [3:0] m_axi_rmem26___Stream2Mmap_26___mmap_AWQOS;
+  wire m_axi_rmem26___Stream2Mmap_26___mmap_AWREADY;
+  wire [2:0] m_axi_rmem26___Stream2Mmap_26___mmap_AWSIZE;
+  wire m_axi_rmem26___Stream2Mmap_26___mmap_AWVALID;
+  wire [0:0] m_axi_rmem26___Stream2Mmap_26___mmap_BID;
+  wire m_axi_rmem26___Stream2Mmap_26___mmap_BREADY;
+  wire [1:0] m_axi_rmem26___Stream2Mmap_26___mmap_BRESP;
+  wire m_axi_rmem26___Stream2Mmap_26___mmap_BVALID;
+  wire [511:0] m_axi_rmem26___Stream2Mmap_26___mmap_RDATA;
+  wire [0:0] m_axi_rmem26___Stream2Mmap_26___mmap_RID;
+  wire m_axi_rmem26___Stream2Mmap_26___mmap_RLAST;
+  wire m_axi_rmem26___Stream2Mmap_26___mmap_RREADY;
+  wire [1:0] m_axi_rmem26___Stream2Mmap_26___mmap_RRESP;
+  wire m_axi_rmem26___Stream2Mmap_26___mmap_RVALID;
+  wire [511:0] m_axi_rmem26___Stream2Mmap_26___mmap_WDATA;
+  wire m_axi_rmem26___Stream2Mmap_26___mmap_WLAST;
+  wire m_axi_rmem26___Stream2Mmap_26___mmap_WREADY;
+  wire [63:0] m_axi_rmem26___Stream2Mmap_26___mmap_WSTRB;
+  wire m_axi_rmem26___Stream2Mmap_26___mmap_WVALID;
+  wire [63:0] m_axi_rmem27___Mmap2Stream_27___mmap_ARADDR;
+  wire [1:0] m_axi_rmem27___Mmap2Stream_27___mmap_ARBURST;
+  wire [3:0] m_axi_rmem27___Mmap2Stream_27___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem27___Mmap2Stream_27___mmap_ARID;
+  wire [7:0] m_axi_rmem27___Mmap2Stream_27___mmap_ARLEN;
+  wire m_axi_rmem27___Mmap2Stream_27___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem27___Mmap2Stream_27___mmap_ARPROT;
+  wire [3:0] m_axi_rmem27___Mmap2Stream_27___mmap_ARQOS;
+  wire m_axi_rmem27___Mmap2Stream_27___mmap_ARREADY;
+  wire [2:0] m_axi_rmem27___Mmap2Stream_27___mmap_ARSIZE;
+  wire m_axi_rmem27___Mmap2Stream_27___mmap_ARVALID;
+  wire [63:0] m_axi_rmem27___Mmap2Stream_27___mmap_AWADDR;
+  wire [1:0] m_axi_rmem27___Mmap2Stream_27___mmap_AWBURST;
+  wire [3:0] m_axi_rmem27___Mmap2Stream_27___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem27___Mmap2Stream_27___mmap_AWID;
+  wire [7:0] m_axi_rmem27___Mmap2Stream_27___mmap_AWLEN;
+  wire m_axi_rmem27___Mmap2Stream_27___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem27___Mmap2Stream_27___mmap_AWPROT;
+  wire [3:0] m_axi_rmem27___Mmap2Stream_27___mmap_AWQOS;
+  wire m_axi_rmem27___Mmap2Stream_27___mmap_AWREADY;
+  wire [2:0] m_axi_rmem27___Mmap2Stream_27___mmap_AWSIZE;
+  wire m_axi_rmem27___Mmap2Stream_27___mmap_AWVALID;
+  wire [0:0] m_axi_rmem27___Mmap2Stream_27___mmap_BID;
+  wire m_axi_rmem27___Mmap2Stream_27___mmap_BREADY;
+  wire [1:0] m_axi_rmem27___Mmap2Stream_27___mmap_BRESP;
+  wire m_axi_rmem27___Mmap2Stream_27___mmap_BVALID;
+  wire [511:0] m_axi_rmem27___Mmap2Stream_27___mmap_RDATA;
+  wire [0:0] m_axi_rmem27___Mmap2Stream_27___mmap_RID;
+  wire m_axi_rmem27___Mmap2Stream_27___mmap_RLAST;
+  wire m_axi_rmem27___Mmap2Stream_27___mmap_RREADY;
+  wire [1:0] m_axi_rmem27___Mmap2Stream_27___mmap_RRESP;
+  wire m_axi_rmem27___Mmap2Stream_27___mmap_RVALID;
+  wire [511:0] m_axi_rmem27___Mmap2Stream_27___mmap_WDATA;
+  wire m_axi_rmem27___Mmap2Stream_27___mmap_WLAST;
+  wire m_axi_rmem27___Mmap2Stream_27___mmap_WREADY;
+  wire [63:0] m_axi_rmem27___Mmap2Stream_27___mmap_WSTRB;
+  wire m_axi_rmem27___Mmap2Stream_27___mmap_WVALID;
+  wire [63:0] m_axi_rmem27___Stream2Mmap_27___mmap_ARADDR;
+  wire [1:0] m_axi_rmem27___Stream2Mmap_27___mmap_ARBURST;
+  wire [3:0] m_axi_rmem27___Stream2Mmap_27___mmap_ARCACHE;
+  wire [0:0] m_axi_rmem27___Stream2Mmap_27___mmap_ARID;
+  wire [7:0] m_axi_rmem27___Stream2Mmap_27___mmap_ARLEN;
+  wire m_axi_rmem27___Stream2Mmap_27___mmap_ARLOCK;
+  wire [2:0] m_axi_rmem27___Stream2Mmap_27___mmap_ARPROT;
+  wire [3:0] m_axi_rmem27___Stream2Mmap_27___mmap_ARQOS;
+  wire m_axi_rmem27___Stream2Mmap_27___mmap_ARREADY;
+  wire [2:0] m_axi_rmem27___Stream2Mmap_27___mmap_ARSIZE;
+  wire m_axi_rmem27___Stream2Mmap_27___mmap_ARVALID;
+  wire [63:0] m_axi_rmem27___Stream2Mmap_27___mmap_AWADDR;
+  wire [1:0] m_axi_rmem27___Stream2Mmap_27___mmap_AWBURST;
+  wire [3:0] m_axi_rmem27___Stream2Mmap_27___mmap_AWCACHE;
+  wire [0:0] m_axi_rmem27___Stream2Mmap_27___mmap_AWID;
+  wire [7:0] m_axi_rmem27___Stream2Mmap_27___mmap_AWLEN;
+  wire m_axi_rmem27___Stream2Mmap_27___mmap_AWLOCK;
+  wire [2:0] m_axi_rmem27___Stream2Mmap_27___mmap_AWPROT;
+  wire [3:0] m_axi_rmem27___Stream2Mmap_27___mmap_AWQOS;
+  wire m_axi_rmem27___Stream2Mmap_27___mmap_AWREADY;
+  wire [2:0] m_axi_rmem27___Stream2Mmap_27___mmap_AWSIZE;
+  wire m_axi_rmem27___Stream2Mmap_27___mmap_AWVALID;
+  wire [0:0] m_axi_rmem27___Stream2Mmap_27___mmap_BID;
+  wire m_axi_rmem27___Stream2Mmap_27___mmap_BREADY;
+  wire [1:0] m_axi_rmem27___Stream2Mmap_27___mmap_BRESP;
+  wire m_axi_rmem27___Stream2Mmap_27___mmap_BVALID;
+  wire [511:0] m_axi_rmem27___Stream2Mmap_27___mmap_RDATA;
+  wire [0:0] m_axi_rmem27___Stream2Mmap_27___mmap_RID;
+  wire m_axi_rmem27___Stream2Mmap_27___mmap_RLAST;
+  wire m_axi_rmem27___Stream2Mmap_27___mmap_RREADY;
+  wire [1:0] m_axi_rmem27___Stream2Mmap_27___mmap_RRESP;
+  wire m_axi_rmem27___Stream2Mmap_27___mmap_RVALID;
+  wire [511:0] m_axi_rmem27___Stream2Mmap_27___mmap_WDATA;
+  wire m_axi_rmem27___Stream2Mmap_27___mmap_WLAST;
+  wire m_axi_rmem27___Stream2Mmap_27___mmap_WREADY;
+  wire [63:0] m_axi_rmem27___Stream2Mmap_27___mmap_WSTRB;
+  wire m_axi_rmem27___Stream2Mmap_27___mmap_WVALID;
+  wire [63:0] Mmap2Stream_0___n__q0;
+  wire [63:0] Mmap2Stream_0___rmem0__q0;
+  wire Mmap2Stream_0__ap_start;
+  wire Mmap2Stream_0__ap_ready;
+  wire Mmap2Stream_0__ap_done;
+  wire Mmap2Stream_0__ap_idle;
+  wire [63:0] Mmap2Stream_1___n__q0;
+  wire [63:0] Mmap2Stream_1___rmem1__q0;
+  wire Mmap2Stream_1__ap_start;
+  wire Mmap2Stream_1__ap_ready;
+  wire Mmap2Stream_1__ap_done;
+  wire Mmap2Stream_1__ap_idle;
+  wire [63:0] Mmap2Stream_2___n__q0;
+  wire [63:0] Mmap2Stream_2___rmem2__q0;
+  wire Mmap2Stream_2__ap_start;
+  wire Mmap2Stream_2__ap_ready;
+  wire Mmap2Stream_2__ap_done;
+  wire Mmap2Stream_2__ap_idle;
+  wire [63:0] Mmap2Stream_3___n__q0;
+  wire [63:0] Mmap2Stream_3___rmem3__q0;
+  wire Mmap2Stream_3__ap_start;
+  wire Mmap2Stream_3__ap_ready;
+  wire Mmap2Stream_3__ap_done;
+  wire Mmap2Stream_3__ap_idle;
+  wire [63:0] Mmap2Stream_4___n__q0;
+  wire [63:0] Mmap2Stream_4___rmem4__q0;
+  wire Mmap2Stream_4__ap_start;
+  wire Mmap2Stream_4__ap_ready;
+  wire Mmap2Stream_4__ap_done;
+  wire Mmap2Stream_4__ap_idle;
+  wire [63:0] Mmap2Stream_5___n__q0;
+  wire [63:0] Mmap2Stream_5___rmem5__q0;
+  wire Mmap2Stream_5__ap_start;
+  wire Mmap2Stream_5__ap_ready;
+  wire Mmap2Stream_5__ap_done;
+  wire Mmap2Stream_5__ap_idle;
+  wire [63:0] Mmap2Stream_6___n__q0;
+  wire [63:0] Mmap2Stream_6___rmem6__q0;
+  wire Mmap2Stream_6__ap_start;
+  wire Mmap2Stream_6__ap_ready;
+  wire Mmap2Stream_6__ap_done;
+  wire Mmap2Stream_6__ap_idle;
+  wire [63:0] Mmap2Stream_7___n__q0;
+  wire [63:0] Mmap2Stream_7___rmem7__q0;
+  wire Mmap2Stream_7__ap_start;
+  wire Mmap2Stream_7__ap_ready;
+  wire Mmap2Stream_7__ap_done;
+  wire Mmap2Stream_7__ap_idle;
+  wire [63:0] Mmap2Stream_8___n__q0;
+  wire [63:0] Mmap2Stream_8___rmem8__q0;
+  wire Mmap2Stream_8__ap_start;
+  wire Mmap2Stream_8__ap_ready;
+  wire Mmap2Stream_8__ap_done;
+  wire Mmap2Stream_8__ap_idle;
+  wire [63:0] Mmap2Stream_9___n__q0;
+  wire [63:0] Mmap2Stream_9___rmem9__q0;
+  wire Mmap2Stream_9__ap_start;
+  wire Mmap2Stream_9__ap_ready;
+  wire Mmap2Stream_9__ap_done;
+  wire Mmap2Stream_9__ap_idle;
+  wire [63:0] Mmap2Stream_10___n__q0;
+  wire [63:0] Mmap2Stream_10___rmem10__q0;
+  wire Mmap2Stream_10__ap_start;
+  wire Mmap2Stream_10__ap_ready;
+  wire Mmap2Stream_10__ap_done;
+  wire Mmap2Stream_10__ap_idle;
+  wire [63:0] Mmap2Stream_11___n__q0;
+  wire [63:0] Mmap2Stream_11___rmem11__q0;
+  wire Mmap2Stream_11__ap_start;
+  wire Mmap2Stream_11__ap_ready;
+  wire Mmap2Stream_11__ap_done;
+  wire Mmap2Stream_11__ap_idle;
+  wire [63:0] Mmap2Stream_12___n__q0;
+  wire [63:0] Mmap2Stream_12___rmem12__q0;
+  wire Mmap2Stream_12__ap_start;
+  wire Mmap2Stream_12__ap_ready;
+  wire Mmap2Stream_12__ap_done;
+  wire Mmap2Stream_12__ap_idle;
+  wire [63:0] Mmap2Stream_13___n__q0;
+  wire [63:0] Mmap2Stream_13___rmem13__q0;
+  wire Mmap2Stream_13__ap_start;
+  wire Mmap2Stream_13__ap_ready;
+  wire Mmap2Stream_13__ap_done;
+  wire Mmap2Stream_13__ap_idle;
+  wire [63:0] Mmap2Stream_14___n__q0;
+  wire [63:0] Mmap2Stream_14___rmem14__q0;
+  wire Mmap2Stream_14__ap_start;
+  wire Mmap2Stream_14__ap_ready;
+  wire Mmap2Stream_14__ap_done;
+  wire Mmap2Stream_14__ap_idle;
+  wire [63:0] Mmap2Stream_15___n__q0;
+  wire [63:0] Mmap2Stream_15___rmem15__q0;
+  wire Mmap2Stream_15__ap_start;
+  wire Mmap2Stream_15__ap_ready;
+  wire Mmap2Stream_15__ap_done;
+  wire Mmap2Stream_15__ap_idle;
+  wire [63:0] Mmap2Stream_16___n__q0;
+  wire [63:0] Mmap2Stream_16___rmem16__q0;
+  wire Mmap2Stream_16__ap_start;
+  wire Mmap2Stream_16__ap_ready;
+  wire Mmap2Stream_16__ap_done;
+  wire Mmap2Stream_16__ap_idle;
+  wire [63:0] Mmap2Stream_17___n__q0;
+  wire [63:0] Mmap2Stream_17___rmem17__q0;
+  wire Mmap2Stream_17__ap_start;
+  wire Mmap2Stream_17__ap_ready;
+  wire Mmap2Stream_17__ap_done;
+  wire Mmap2Stream_17__ap_idle;
+  wire [63:0] Mmap2Stream_18___n__q0;
+  wire [63:0] Mmap2Stream_18___rmem18__q0;
+  wire Mmap2Stream_18__ap_start;
+  wire Mmap2Stream_18__ap_ready;
+  wire Mmap2Stream_18__ap_done;
+  wire Mmap2Stream_18__ap_idle;
+  wire [63:0] Mmap2Stream_19___n__q0;
+  wire [63:0] Mmap2Stream_19___rmem19__q0;
+  wire Mmap2Stream_19__ap_start;
+  wire Mmap2Stream_19__ap_ready;
+  wire Mmap2Stream_19__ap_done;
+  wire Mmap2Stream_19__ap_idle;
+  wire [63:0] Mmap2Stream_20___n__q0;
+  wire [63:0] Mmap2Stream_20___rmem20__q0;
+  wire Mmap2Stream_20__ap_start;
+  wire Mmap2Stream_20__ap_ready;
+  wire Mmap2Stream_20__ap_done;
+  wire Mmap2Stream_20__ap_idle;
+  wire [63:0] Mmap2Stream_21___n__q0;
+  wire [63:0] Mmap2Stream_21___rmem21__q0;
+  wire Mmap2Stream_21__ap_start;
+  wire Mmap2Stream_21__ap_ready;
+  wire Mmap2Stream_21__ap_done;
+  wire Mmap2Stream_21__ap_idle;
+  wire [63:0] Mmap2Stream_22___n__q0;
+  wire [63:0] Mmap2Stream_22___rmem22__q0;
+  wire Mmap2Stream_22__ap_start;
+  wire Mmap2Stream_22__ap_ready;
+  wire Mmap2Stream_22__ap_done;
+  wire Mmap2Stream_22__ap_idle;
+  wire [63:0] Mmap2Stream_23___n__q0;
+  wire [63:0] Mmap2Stream_23___rmem23__q0;
+  wire Mmap2Stream_23__ap_start;
+  wire Mmap2Stream_23__ap_ready;
+  wire Mmap2Stream_23__ap_done;
+  wire Mmap2Stream_23__ap_idle;
+  wire [63:0] Mmap2Stream_24___n__q0;
+  wire [63:0] Mmap2Stream_24___rmem24__q0;
+  wire Mmap2Stream_24__ap_start;
+  wire Mmap2Stream_24__ap_ready;
+  wire Mmap2Stream_24__ap_done;
+  wire Mmap2Stream_24__ap_idle;
+  wire [63:0] Mmap2Stream_25___n__q0;
+  wire [63:0] Mmap2Stream_25___rmem25__q0;
+  wire Mmap2Stream_25__ap_start;
+  wire Mmap2Stream_25__ap_ready;
+  wire Mmap2Stream_25__ap_done;
+  wire Mmap2Stream_25__ap_idle;
+  wire [63:0] Mmap2Stream_26___n__q0;
+  wire [63:0] Mmap2Stream_26___rmem26__q0;
+  wire Mmap2Stream_26__ap_start;
+  wire Mmap2Stream_26__ap_ready;
+  wire Mmap2Stream_26__ap_done;
+  wire Mmap2Stream_26__ap_idle;
+  wire [63:0] Mmap2Stream_27___n__q0;
+  wire [63:0] Mmap2Stream_27___rmem27__q0;
+  wire Mmap2Stream_27__ap_start;
+  wire Mmap2Stream_27__ap_ready;
+  wire Mmap2Stream_27__ap_done;
+  wire Mmap2Stream_27__ap_idle;
+  wire [63:0] Stream2Mmap_0___n__q0;
+  wire [63:0] Stream2Mmap_0___rmem0__q0;
+  wire Stream2Mmap_0__ap_start;
+  wire Stream2Mmap_0__ap_ready;
+  wire Stream2Mmap_0__ap_done;
+  wire Stream2Mmap_0__ap_idle;
+  wire [63:0] Stream2Mmap_1___n__q0;
+  wire [63:0] Stream2Mmap_1___rmem1__q0;
+  wire Stream2Mmap_1__ap_start;
+  wire Stream2Mmap_1__ap_ready;
+  wire Stream2Mmap_1__ap_done;
+  wire Stream2Mmap_1__ap_idle;
+  wire [63:0] Stream2Mmap_2___n__q0;
+  wire [63:0] Stream2Mmap_2___rmem2__q0;
+  wire Stream2Mmap_2__ap_start;
+  wire Stream2Mmap_2__ap_ready;
+  wire Stream2Mmap_2__ap_done;
+  wire Stream2Mmap_2__ap_idle;
+  wire [63:0] Stream2Mmap_3___n__q0;
+  wire [63:0] Stream2Mmap_3___rmem3__q0;
+  wire Stream2Mmap_3__ap_start;
+  wire Stream2Mmap_3__ap_ready;
+  wire Stream2Mmap_3__ap_done;
+  wire Stream2Mmap_3__ap_idle;
+  wire [63:0] Stream2Mmap_4___n__q0;
+  wire [63:0] Stream2Mmap_4___rmem4__q0;
+  wire Stream2Mmap_4__ap_start;
+  wire Stream2Mmap_4__ap_ready;
+  wire Stream2Mmap_4__ap_done;
+  wire Stream2Mmap_4__ap_idle;
+  wire [63:0] Stream2Mmap_5___n__q0;
+  wire [63:0] Stream2Mmap_5___rmem5__q0;
+  wire Stream2Mmap_5__ap_start;
+  wire Stream2Mmap_5__ap_ready;
+  wire Stream2Mmap_5__ap_done;
+  wire Stream2Mmap_5__ap_idle;
+  wire [63:0] Stream2Mmap_6___n__q0;
+  wire [63:0] Stream2Mmap_6___rmem6__q0;
+  wire Stream2Mmap_6__ap_start;
+  wire Stream2Mmap_6__ap_ready;
+  wire Stream2Mmap_6__ap_done;
+  wire Stream2Mmap_6__ap_idle;
+  wire [63:0] Stream2Mmap_7___n__q0;
+  wire [63:0] Stream2Mmap_7___rmem7__q0;
+  wire Stream2Mmap_7__ap_start;
+  wire Stream2Mmap_7__ap_ready;
+  wire Stream2Mmap_7__ap_done;
+  wire Stream2Mmap_7__ap_idle;
+  wire [63:0] Stream2Mmap_8___n__q0;
+  wire [63:0] Stream2Mmap_8___rmem8__q0;
+  wire Stream2Mmap_8__ap_start;
+  wire Stream2Mmap_8__ap_ready;
+  wire Stream2Mmap_8__ap_done;
+  wire Stream2Mmap_8__ap_idle;
+  wire [63:0] Stream2Mmap_9___n__q0;
+  wire [63:0] Stream2Mmap_9___rmem9__q0;
+  wire Stream2Mmap_9__ap_start;
+  wire Stream2Mmap_9__ap_ready;
+  wire Stream2Mmap_9__ap_done;
+  wire Stream2Mmap_9__ap_idle;
+  wire [63:0] Stream2Mmap_10___n__q0;
+  wire [63:0] Stream2Mmap_10___rmem10__q0;
+  wire Stream2Mmap_10__ap_start;
+  wire Stream2Mmap_10__ap_ready;
+  wire Stream2Mmap_10__ap_done;
+  wire Stream2Mmap_10__ap_idle;
+  wire [63:0] Stream2Mmap_11___n__q0;
+  wire [63:0] Stream2Mmap_11___rmem11__q0;
+  wire Stream2Mmap_11__ap_start;
+  wire Stream2Mmap_11__ap_ready;
+  wire Stream2Mmap_11__ap_done;
+  wire Stream2Mmap_11__ap_idle;
+  wire [63:0] Stream2Mmap_12___n__q0;
+  wire [63:0] Stream2Mmap_12___rmem12__q0;
+  wire Stream2Mmap_12__ap_start;
+  wire Stream2Mmap_12__ap_ready;
+  wire Stream2Mmap_12__ap_done;
+  wire Stream2Mmap_12__ap_idle;
+  wire [63:0] Stream2Mmap_13___n__q0;
+  wire [63:0] Stream2Mmap_13___rmem13__q0;
+  wire Stream2Mmap_13__ap_start;
+  wire Stream2Mmap_13__ap_ready;
+  wire Stream2Mmap_13__ap_done;
+  wire Stream2Mmap_13__ap_idle;
+  wire [63:0] Stream2Mmap_14___n__q0;
+  wire [63:0] Stream2Mmap_14___rmem14__q0;
+  wire Stream2Mmap_14__ap_start;
+  wire Stream2Mmap_14__ap_ready;
+  wire Stream2Mmap_14__ap_done;
+  wire Stream2Mmap_14__ap_idle;
+  wire [63:0] Stream2Mmap_15___n__q0;
+  wire [63:0] Stream2Mmap_15___rmem15__q0;
+  wire Stream2Mmap_15__ap_start;
+  wire Stream2Mmap_15__ap_ready;
+  wire Stream2Mmap_15__ap_done;
+  wire Stream2Mmap_15__ap_idle;
+  wire [63:0] Stream2Mmap_16___n__q0;
+  wire [63:0] Stream2Mmap_16___rmem16__q0;
+  wire Stream2Mmap_16__ap_start;
+  wire Stream2Mmap_16__ap_ready;
+  wire Stream2Mmap_16__ap_done;
+  wire Stream2Mmap_16__ap_idle;
+  wire [63:0] Stream2Mmap_17___n__q0;
+  wire [63:0] Stream2Mmap_17___rmem17__q0;
+  wire Stream2Mmap_17__ap_start;
+  wire Stream2Mmap_17__ap_ready;
+  wire Stream2Mmap_17__ap_done;
+  wire Stream2Mmap_17__ap_idle;
+  wire [63:0] Stream2Mmap_18___n__q0;
+  wire [63:0] Stream2Mmap_18___rmem18__q0;
+  wire Stream2Mmap_18__ap_start;
+  wire Stream2Mmap_18__ap_ready;
+  wire Stream2Mmap_18__ap_done;
+  wire Stream2Mmap_18__ap_idle;
+  wire [63:0] Stream2Mmap_19___n__q0;
+  wire [63:0] Stream2Mmap_19___rmem19__q0;
+  wire Stream2Mmap_19__ap_start;
+  wire Stream2Mmap_19__ap_ready;
+  wire Stream2Mmap_19__ap_done;
+  wire Stream2Mmap_19__ap_idle;
+  wire [63:0] Stream2Mmap_20___n__q0;
+  wire [63:0] Stream2Mmap_20___rmem20__q0;
+  wire Stream2Mmap_20__ap_start;
+  wire Stream2Mmap_20__ap_ready;
+  wire Stream2Mmap_20__ap_done;
+  wire Stream2Mmap_20__ap_idle;
+  wire [63:0] Stream2Mmap_21___n__q0;
+  wire [63:0] Stream2Mmap_21___rmem21__q0;
+  wire Stream2Mmap_21__ap_start;
+  wire Stream2Mmap_21__ap_ready;
+  wire Stream2Mmap_21__ap_done;
+  wire Stream2Mmap_21__ap_idle;
+  wire [63:0] Stream2Mmap_22___n__q0;
+  wire [63:0] Stream2Mmap_22___rmem22__q0;
+  wire Stream2Mmap_22__ap_start;
+  wire Stream2Mmap_22__ap_ready;
+  wire Stream2Mmap_22__ap_done;
+  wire Stream2Mmap_22__ap_idle;
+  wire [63:0] Stream2Mmap_23___n__q0;
+  wire [63:0] Stream2Mmap_23___rmem23__q0;
+  wire Stream2Mmap_23__ap_start;
+  wire Stream2Mmap_23__ap_ready;
+  wire Stream2Mmap_23__ap_done;
+  wire Stream2Mmap_23__ap_idle;
+  wire [63:0] Stream2Mmap_24___n__q0;
+  wire [63:0] Stream2Mmap_24___rmem24__q0;
+  wire Stream2Mmap_24__ap_start;
+  wire Stream2Mmap_24__ap_ready;
+  wire Stream2Mmap_24__ap_done;
+  wire Stream2Mmap_24__ap_idle;
+  wire [63:0] Stream2Mmap_25___n__q0;
+  wire [63:0] Stream2Mmap_25___rmem25__q0;
+  wire Stream2Mmap_25__ap_start;
+  wire Stream2Mmap_25__ap_ready;
+  wire Stream2Mmap_25__ap_done;
+  wire Stream2Mmap_25__ap_idle;
+  wire [63:0] Stream2Mmap_26___n__q0;
+  wire [63:0] Stream2Mmap_26___rmem26__q0;
+  wire Stream2Mmap_26__ap_start;
+  wire Stream2Mmap_26__ap_ready;
+  wire Stream2Mmap_26__ap_done;
+  wire Stream2Mmap_26__ap_idle;
+  wire [63:0] Stream2Mmap_27___n__q0;
+  wire [63:0] Stream2Mmap_27___rmem27__q0;
+  wire Stream2Mmap_27__ap_start;
+  wire Stream2Mmap_27__ap_ready;
+  wire Stream2Mmap_27__ap_done;
+  wire Stream2Mmap_27__ap_idle;
+  wire [63:0] yshift_0___n__q0;
+  wire yshift_0__ap_start;
+  wire yshift_0__ap_ready;
+  wire yshift_0__ap_done;
+  wire yshift_0__ap_idle;
+  wire [63:0] yshift_1___n__q0;
+  wire yshift_1__ap_start;
+  wire yshift_1__ap_ready;
+  wire yshift_1__ap_done;
+  wire yshift_1__ap_idle;
+  wire [63:0] yshift_2___n__q0;
+  wire yshift_2__ap_start;
+  wire yshift_2__ap_ready;
+  wire yshift_2__ap_done;
+  wire yshift_2__ap_idle;
+  wire [63:0] yshift_3___n__q0;
+  wire yshift_3__ap_start;
+  wire yshift_3__ap_ready;
+  wire yshift_3__ap_done;
+  wire yshift_3__ap_idle;
+  wire [63:0] yshift_4___n__q0;
+  wire yshift_4__ap_start;
+  wire yshift_4__ap_ready;
+  wire yshift_4__ap_done;
+  wire yshift_4__ap_idle;
+  wire [63:0] yshift_5___n__q0;
+  wire yshift_5__ap_start;
+  wire yshift_5__ap_ready;
+  wire yshift_5__ap_done;
+  wire yshift_5__ap_idle;
+  wire [63:0] yshift_6___n__q0;
+  wire yshift_6__ap_start;
+  wire yshift_6__ap_ready;
+  wire yshift_6__ap_done;
+  wire yshift_6__ap_idle;
+  wire [63:0] yshift_7___n__q0;
+  wire yshift_7__ap_start;
+  wire yshift_7__ap_ready;
+  wire yshift_7__ap_done;
+  wire yshift_7__ap_idle;
+  wire [63:0] yshift_8___n__q0;
+  wire yshift_8__ap_start;
+  wire yshift_8__ap_ready;
+  wire yshift_8__ap_done;
+  wire yshift_8__ap_idle;
+  wire [63:0] yshift_9___n__q0;
+  wire yshift_9__ap_start;
+  wire yshift_9__ap_ready;
+  wire yshift_9__ap_done;
+  wire yshift_9__ap_idle;
+  wire [63:0] yshift_10___n__q0;
+  wire yshift_10__ap_start;
+  wire yshift_10__ap_ready;
+  wire yshift_10__ap_done;
+  wire yshift_10__ap_idle;
+  wire [63:0] yshift_11___n__q0;
+  wire yshift_11__ap_start;
+  wire yshift_11__ap_ready;
+  wire yshift_11__ap_done;
+  wire yshift_11__ap_idle;
+  wire [63:0] yshift_12___n__q0;
+  wire yshift_12__ap_start;
+  wire yshift_12__ap_ready;
+  wire yshift_12__ap_done;
+  wire yshift_12__ap_idle;
+  wire [63:0] yshift_13___n__q0;
+  wire yshift_13__ap_start;
+  wire yshift_13__ap_ready;
+  wire yshift_13__ap_done;
+  wire yshift_13__ap_idle;
+  wire [63:0] yshift_14___n__q0;
+  wire yshift_14__ap_start;
+  wire yshift_14__ap_ready;
+  wire yshift_14__ap_done;
+  wire yshift_14__ap_idle;
+  wire [63:0] yshift_15___n__q0;
+  wire yshift_15__ap_start;
+  wire yshift_15__ap_ready;
+  wire yshift_15__ap_done;
+  wire yshift_15__ap_idle;
+  wire [63:0] yshift_16___n__q0;
+  wire yshift_16__ap_start;
+  wire yshift_16__ap_ready;
+  wire yshift_16__ap_done;
+  wire yshift_16__ap_idle;
+  wire [63:0] yshift_17___n__q0;
+  wire yshift_17__ap_start;
+  wire yshift_17__ap_ready;
+  wire yshift_17__ap_done;
+  wire yshift_17__ap_idle;
+  wire [63:0] yshift_18___n__q0;
+  wire yshift_18__ap_start;
+  wire yshift_18__ap_ready;
+  wire yshift_18__ap_done;
+  wire yshift_18__ap_idle;
+  wire [63:0] yshift_19___n__q0;
+  wire yshift_19__ap_start;
+  wire yshift_19__ap_ready;
+  wire yshift_19__ap_done;
+  wire yshift_19__ap_idle;
+  wire [63:0] yshift_20___n__q0;
+  wire yshift_20__ap_start;
+  wire yshift_20__ap_ready;
+  wire yshift_20__ap_done;
+  wire yshift_20__ap_idle;
+  wire [63:0] yshift_21___n__q0;
+  wire yshift_21__ap_start;
+  wire yshift_21__ap_ready;
+  wire yshift_21__ap_done;
+  wire yshift_21__ap_idle;
+  wire [63:0] yshift_22___n__q0;
+  wire yshift_22__ap_start;
+  wire yshift_22__ap_ready;
+  wire yshift_22__ap_done;
+  wire yshift_22__ap_idle;
+  wire [63:0] yshift_23___n__q0;
+  wire yshift_23__ap_start;
+  wire yshift_23__ap_ready;
+  wire yshift_23__ap_done;
+  wire yshift_23__ap_idle;
+  wire [63:0] yshift_24___n__q0;
+  wire yshift_24__ap_start;
+  wire yshift_24__ap_ready;
+  wire yshift_24__ap_done;
+  wire yshift_24__ap_idle;
+  wire [63:0] yshift_25___n__q0;
+  wire yshift_25__ap_start;
+  wire yshift_25__ap_ready;
+  wire yshift_25__ap_done;
+  wire yshift_25__ap_idle;
+  wire [63:0] yshift_26___n__q0;
+  wire yshift_26__ap_start;
+  wire yshift_26__ap_ready;
+  wire yshift_26__ap_done;
+  wire yshift_26__ap_idle;
+  wire [63:0] yshift_27___n__q0;
+  wire yshift_27__ap_start;
+  wire yshift_27__ap_ready;
+  wire yshift_27__ap_done;
+  wire yshift_27__ap_idle;
+  wire ap_rst_n_inv;
+  wire ap_done;
+  wire ap_idle;
+  wire ap_ready;
+
+  vadd_bw_control_s_axi
+  #(
+    .C_S_AXI_ADDR_WIDTH(C_S_AXI_CONTROL_ADDR_WIDTH),
+    .C_S_AXI_DATA_WIDTH(C_S_AXI_CONTROL_DATA_WIDTH)
+  )
+  control_s_axi_U
+  (
+    .AWVALID(s_axi_control_AWVALID),
+    .AWREADY(s_axi_control_AWREADY),
+    .AWADDR(s_axi_control_AWADDR),
+    .WVALID(s_axi_control_WVALID),
+    .WREADY(s_axi_control_WREADY),
+    .WDATA(s_axi_control_WDATA),
+    .WSTRB(s_axi_control_WSTRB),
+    .ARVALID(s_axi_control_ARVALID),
+    .ARREADY(s_axi_control_ARREADY),
+    .ARADDR(s_axi_control_ARADDR),
+    .RVALID(s_axi_control_RVALID),
+    .RREADY(s_axi_control_RREADY),
+    .RDATA(s_axi_control_RDATA),
+    .RRESP(s_axi_control_RRESP),
+    .BVALID(s_axi_control_BVALID),
+    .BREADY(s_axi_control_BREADY),
+    .BRESP(s_axi_control_BRESP),
+    .ACLK(ap_clk),
+    .ARESET(ap_rst_n_inv),
+    .ACLK_EN(1'b1),
+    .rmem0(rmem0),
+    .rmem1(rmem1),
+    .rmem2(rmem2),
+    .rmem3(rmem3),
+    .rmem4(rmem4),
+    .rmem5(rmem5),
+    .rmem6(rmem6),
+    .rmem7(rmem7),
+    .rmem8(rmem8),
+    .rmem9(rmem9),
+    .rmem10(rmem10),
+    .rmem11(rmem11),
+    .rmem12(rmem12),
+    .rmem13(rmem13),
+    .rmem14(rmem14),
+    .rmem15(rmem15),
+    .rmem16(rmem16),
+    .rmem17(rmem17),
+    .rmem18(rmem18),
+    .rmem19(rmem19),
+    .rmem20(rmem20),
+    .rmem21(rmem21),
+    .rmem22(rmem22),
+    .rmem23(rmem23),
+    .rmem24(rmem24),
+    .rmem25(rmem25),
+    .rmem26(rmem26),
+    .rmem27(rmem27),
+    .n(n),
+    .ap_start(ap_start),
+    .interrupt(interrupt),
+    .ap_ready(ap_ready),
+    .ap_done(ap_done),
+    .ap_idle(ap_idle)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qr0_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qr0_vadd_bw__dout),
+    .if_empty_n(qr0_vadd_bw__empty_n),
+    .if_read(qr0_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qr0_vadd_bw__din),
+    .if_full_n(qr0_vadd_bw__full_n),
+    .if_write(qr0_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qr10_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qr10_vadd_bw__dout),
+    .if_empty_n(qr10_vadd_bw__empty_n),
+    .if_read(qr10_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qr10_vadd_bw__din),
+    .if_full_n(qr10_vadd_bw__full_n),
+    .if_write(qr10_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qr11_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qr11_vadd_bw__dout),
+    .if_empty_n(qr11_vadd_bw__empty_n),
+    .if_read(qr11_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qr11_vadd_bw__din),
+    .if_full_n(qr11_vadd_bw__full_n),
+    .if_write(qr11_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qr12_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qr12_vadd_bw__dout),
+    .if_empty_n(qr12_vadd_bw__empty_n),
+    .if_read(qr12_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qr12_vadd_bw__din),
+    .if_full_n(qr12_vadd_bw__full_n),
+    .if_write(qr12_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qr13_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qr13_vadd_bw__dout),
+    .if_empty_n(qr13_vadd_bw__empty_n),
+    .if_read(qr13_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qr13_vadd_bw__din),
+    .if_full_n(qr13_vadd_bw__full_n),
+    .if_write(qr13_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qr14_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qr14_vadd_bw__dout),
+    .if_empty_n(qr14_vadd_bw__empty_n),
+    .if_read(qr14_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qr14_vadd_bw__din),
+    .if_full_n(qr14_vadd_bw__full_n),
+    .if_write(qr14_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qr15_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qr15_vadd_bw__dout),
+    .if_empty_n(qr15_vadd_bw__empty_n),
+    .if_read(qr15_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qr15_vadd_bw__din),
+    .if_full_n(qr15_vadd_bw__full_n),
+    .if_write(qr15_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qr16_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qr16_vadd_bw__dout),
+    .if_empty_n(qr16_vadd_bw__empty_n),
+    .if_read(qr16_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qr16_vadd_bw__din),
+    .if_full_n(qr16_vadd_bw__full_n),
+    .if_write(qr16_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qr17_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qr17_vadd_bw__dout),
+    .if_empty_n(qr17_vadd_bw__empty_n),
+    .if_read(qr17_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qr17_vadd_bw__din),
+    .if_full_n(qr17_vadd_bw__full_n),
+    .if_write(qr17_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qr18_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qr18_vadd_bw__dout),
+    .if_empty_n(qr18_vadd_bw__empty_n),
+    .if_read(qr18_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qr18_vadd_bw__din),
+    .if_full_n(qr18_vadd_bw__full_n),
+    .if_write(qr18_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qr19_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qr19_vadd_bw__dout),
+    .if_empty_n(qr19_vadd_bw__empty_n),
+    .if_read(qr19_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qr19_vadd_bw__din),
+    .if_full_n(qr19_vadd_bw__full_n),
+    .if_write(qr19_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qr1_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qr1_vadd_bw__dout),
+    .if_empty_n(qr1_vadd_bw__empty_n),
+    .if_read(qr1_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qr1_vadd_bw__din),
+    .if_full_n(qr1_vadd_bw__full_n),
+    .if_write(qr1_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qr20_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qr20_vadd_bw__dout),
+    .if_empty_n(qr20_vadd_bw__empty_n),
+    .if_read(qr20_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qr20_vadd_bw__din),
+    .if_full_n(qr20_vadd_bw__full_n),
+    .if_write(qr20_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qr21_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qr21_vadd_bw__dout),
+    .if_empty_n(qr21_vadd_bw__empty_n),
+    .if_read(qr21_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qr21_vadd_bw__din),
+    .if_full_n(qr21_vadd_bw__full_n),
+    .if_write(qr21_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qr22_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qr22_vadd_bw__dout),
+    .if_empty_n(qr22_vadd_bw__empty_n),
+    .if_read(qr22_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qr22_vadd_bw__din),
+    .if_full_n(qr22_vadd_bw__full_n),
+    .if_write(qr22_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qr23_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qr23_vadd_bw__dout),
+    .if_empty_n(qr23_vadd_bw__empty_n),
+    .if_read(qr23_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qr23_vadd_bw__din),
+    .if_full_n(qr23_vadd_bw__full_n),
+    .if_write(qr23_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qr24_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qr24_vadd_bw__dout),
+    .if_empty_n(qr24_vadd_bw__empty_n),
+    .if_read(qr24_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qr24_vadd_bw__din),
+    .if_full_n(qr24_vadd_bw__full_n),
+    .if_write(qr24_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qr25_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qr25_vadd_bw__dout),
+    .if_empty_n(qr25_vadd_bw__empty_n),
+    .if_read(qr25_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qr25_vadd_bw__din),
+    .if_full_n(qr25_vadd_bw__full_n),
+    .if_write(qr25_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qr26_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qr26_vadd_bw__dout),
+    .if_empty_n(qr26_vadd_bw__empty_n),
+    .if_read(qr26_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qr26_vadd_bw__din),
+    .if_full_n(qr26_vadd_bw__full_n),
+    .if_write(qr26_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qr27_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qr27_vadd_bw__dout),
+    .if_empty_n(qr27_vadd_bw__empty_n),
+    .if_read(qr27_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qr27_vadd_bw__din),
+    .if_full_n(qr27_vadd_bw__full_n),
+    .if_write(qr27_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qr2_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qr2_vadd_bw__dout),
+    .if_empty_n(qr2_vadd_bw__empty_n),
+    .if_read(qr2_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qr2_vadd_bw__din),
+    .if_full_n(qr2_vadd_bw__full_n),
+    .if_write(qr2_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qr3_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qr3_vadd_bw__dout),
+    .if_empty_n(qr3_vadd_bw__empty_n),
+    .if_read(qr3_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qr3_vadd_bw__din),
+    .if_full_n(qr3_vadd_bw__full_n),
+    .if_write(qr3_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qr4_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qr4_vadd_bw__dout),
+    .if_empty_n(qr4_vadd_bw__empty_n),
+    .if_read(qr4_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qr4_vadd_bw__din),
+    .if_full_n(qr4_vadd_bw__full_n),
+    .if_write(qr4_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qr5_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qr5_vadd_bw__dout),
+    .if_empty_n(qr5_vadd_bw__empty_n),
+    .if_read(qr5_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qr5_vadd_bw__din),
+    .if_full_n(qr5_vadd_bw__full_n),
+    .if_write(qr5_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qr6_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qr6_vadd_bw__dout),
+    .if_empty_n(qr6_vadd_bw__empty_n),
+    .if_read(qr6_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qr6_vadd_bw__din),
+    .if_full_n(qr6_vadd_bw__full_n),
+    .if_write(qr6_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qr7_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qr7_vadd_bw__dout),
+    .if_empty_n(qr7_vadd_bw__empty_n),
+    .if_read(qr7_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qr7_vadd_bw__din),
+    .if_full_n(qr7_vadd_bw__full_n),
+    .if_write(qr7_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qr8_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qr8_vadd_bw__dout),
+    .if_empty_n(qr8_vadd_bw__empty_n),
+    .if_read(qr8_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qr8_vadd_bw__din),
+    .if_full_n(qr8_vadd_bw__full_n),
+    .if_write(qr8_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qr9_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qr9_vadd_bw__dout),
+    .if_empty_n(qr9_vadd_bw__empty_n),
+    .if_read(qr9_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qr9_vadd_bw__din),
+    .if_full_n(qr9_vadd_bw__full_n),
+    .if_write(qr9_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qw0_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qw0_vadd_bw__dout),
+    .if_empty_n(qw0_vadd_bw__empty_n),
+    .if_read(qw0_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qw0_vadd_bw__din),
+    .if_full_n(qw0_vadd_bw__full_n),
+    .if_write(qw0_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qw10_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qw10_vadd_bw__dout),
+    .if_empty_n(qw10_vadd_bw__empty_n),
+    .if_read(qw10_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qw10_vadd_bw__din),
+    .if_full_n(qw10_vadd_bw__full_n),
+    .if_write(qw10_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qw11_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qw11_vadd_bw__dout),
+    .if_empty_n(qw11_vadd_bw__empty_n),
+    .if_read(qw11_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qw11_vadd_bw__din),
+    .if_full_n(qw11_vadd_bw__full_n),
+    .if_write(qw11_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qw12_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qw12_vadd_bw__dout),
+    .if_empty_n(qw12_vadd_bw__empty_n),
+    .if_read(qw12_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qw12_vadd_bw__din),
+    .if_full_n(qw12_vadd_bw__full_n),
+    .if_write(qw12_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qw13_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qw13_vadd_bw__dout),
+    .if_empty_n(qw13_vadd_bw__empty_n),
+    .if_read(qw13_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qw13_vadd_bw__din),
+    .if_full_n(qw13_vadd_bw__full_n),
+    .if_write(qw13_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qw14_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qw14_vadd_bw__dout),
+    .if_empty_n(qw14_vadd_bw__empty_n),
+    .if_read(qw14_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qw14_vadd_bw__din),
+    .if_full_n(qw14_vadd_bw__full_n),
+    .if_write(qw14_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qw15_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qw15_vadd_bw__dout),
+    .if_empty_n(qw15_vadd_bw__empty_n),
+    .if_read(qw15_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qw15_vadd_bw__din),
+    .if_full_n(qw15_vadd_bw__full_n),
+    .if_write(qw15_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qw16_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qw16_vadd_bw__dout),
+    .if_empty_n(qw16_vadd_bw__empty_n),
+    .if_read(qw16_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qw16_vadd_bw__din),
+    .if_full_n(qw16_vadd_bw__full_n),
+    .if_write(qw16_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qw17_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qw17_vadd_bw__dout),
+    .if_empty_n(qw17_vadd_bw__empty_n),
+    .if_read(qw17_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qw17_vadd_bw__din),
+    .if_full_n(qw17_vadd_bw__full_n),
+    .if_write(qw17_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qw18_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qw18_vadd_bw__dout),
+    .if_empty_n(qw18_vadd_bw__empty_n),
+    .if_read(qw18_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qw18_vadd_bw__din),
+    .if_full_n(qw18_vadd_bw__full_n),
+    .if_write(qw18_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qw19_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qw19_vadd_bw__dout),
+    .if_empty_n(qw19_vadd_bw__empty_n),
+    .if_read(qw19_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qw19_vadd_bw__din),
+    .if_full_n(qw19_vadd_bw__full_n),
+    .if_write(qw19_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qw1_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qw1_vadd_bw__dout),
+    .if_empty_n(qw1_vadd_bw__empty_n),
+    .if_read(qw1_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qw1_vadd_bw__din),
+    .if_full_n(qw1_vadd_bw__full_n),
+    .if_write(qw1_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qw20_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qw20_vadd_bw__dout),
+    .if_empty_n(qw20_vadd_bw__empty_n),
+    .if_read(qw20_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qw20_vadd_bw__din),
+    .if_full_n(qw20_vadd_bw__full_n),
+    .if_write(qw20_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qw21_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qw21_vadd_bw__dout),
+    .if_empty_n(qw21_vadd_bw__empty_n),
+    .if_read(qw21_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qw21_vadd_bw__din),
+    .if_full_n(qw21_vadd_bw__full_n),
+    .if_write(qw21_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qw22_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qw22_vadd_bw__dout),
+    .if_empty_n(qw22_vadd_bw__empty_n),
+    .if_read(qw22_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qw22_vadd_bw__din),
+    .if_full_n(qw22_vadd_bw__full_n),
+    .if_write(qw22_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qw23_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qw23_vadd_bw__dout),
+    .if_empty_n(qw23_vadd_bw__empty_n),
+    .if_read(qw23_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qw23_vadd_bw__din),
+    .if_full_n(qw23_vadd_bw__full_n),
+    .if_write(qw23_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qw24_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qw24_vadd_bw__dout),
+    .if_empty_n(qw24_vadd_bw__empty_n),
+    .if_read(qw24_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qw24_vadd_bw__din),
+    .if_full_n(qw24_vadd_bw__full_n),
+    .if_write(qw24_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qw25_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qw25_vadd_bw__dout),
+    .if_empty_n(qw25_vadd_bw__empty_n),
+    .if_read(qw25_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qw25_vadd_bw__din),
+    .if_full_n(qw25_vadd_bw__full_n),
+    .if_write(qw25_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qw26_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qw26_vadd_bw__dout),
+    .if_empty_n(qw26_vadd_bw__empty_n),
+    .if_read(qw26_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qw26_vadd_bw__din),
+    .if_full_n(qw26_vadd_bw__full_n),
+    .if_write(qw26_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qw27_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qw27_vadd_bw__dout),
+    .if_empty_n(qw27_vadd_bw__empty_n),
+    .if_read(qw27_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qw27_vadd_bw__din),
+    .if_full_n(qw27_vadd_bw__full_n),
+    .if_write(qw27_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qw2_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qw2_vadd_bw__dout),
+    .if_empty_n(qw2_vadd_bw__empty_n),
+    .if_read(qw2_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qw2_vadd_bw__din),
+    .if_full_n(qw2_vadd_bw__full_n),
+    .if_write(qw2_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qw3_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qw3_vadd_bw__dout),
+    .if_empty_n(qw3_vadd_bw__empty_n),
+    .if_read(qw3_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qw3_vadd_bw__din),
+    .if_full_n(qw3_vadd_bw__full_n),
+    .if_write(qw3_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qw4_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qw4_vadd_bw__dout),
+    .if_empty_n(qw4_vadd_bw__empty_n),
+    .if_read(qw4_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qw4_vadd_bw__din),
+    .if_full_n(qw4_vadd_bw__full_n),
+    .if_write(qw4_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qw5_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qw5_vadd_bw__dout),
+    .if_empty_n(qw5_vadd_bw__empty_n),
+    .if_read(qw5_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qw5_vadd_bw__din),
+    .if_full_n(qw5_vadd_bw__full_n),
+    .if_write(qw5_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qw6_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qw6_vadd_bw__dout),
+    .if_empty_n(qw6_vadd_bw__empty_n),
+    .if_read(qw6_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qw6_vadd_bw__din),
+    .if_full_n(qw6_vadd_bw__full_n),
+    .if_write(qw6_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qw7_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qw7_vadd_bw__dout),
+    .if_empty_n(qw7_vadd_bw__empty_n),
+    .if_read(qw7_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qw7_vadd_bw__din),
+    .if_full_n(qw7_vadd_bw__full_n),
+    .if_write(qw7_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qw8_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qw8_vadd_bw__dout),
+    .if_empty_n(qw8_vadd_bw__empty_n),
+    .if_read(qw8_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qw8_vadd_bw__din),
+    .if_full_n(qw8_vadd_bw__full_n),
+    .if_write(qw8_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) fifo
+  #(
+    .DATA_WIDTH(513),
+    .ADDR_WIDTH(1),
+    .DEPTH(2)
+  )
+  qw9_vadd_bw
+  (
+    .clk(ap_clk),
+    .reset(~ap_rst_n),
+    .if_dout(qw9_vadd_bw__dout),
+    .if_empty_n(qw9_vadd_bw__empty_n),
+    .if_read(qw9_vadd_bw__read),
+    .if_read_ce(1'b1),
+    .if_din(qw9_vadd_bw__din),
+    .if_full_n(qw9_vadd_bw__full_n),
+    .if_write(qw9_vadd_bw__write),
+    .if_write_ce(1'b1)
+  );
+
+
+  (* keep_hierarchy = "yes" *) axi_crossbar_2x1
+  #(
+    .DATA_WIDTH(512),
+    .ADDR_WIDTH(64),
+    .S_ID_WIDTH(1),
+    .M_ID_WIDTH(2),
+    .M00_ADDR_WIDTH(64),
+    .M00_ISSUE(16),
+    .S00_THREADS(1),
+    .S01_THREADS(1)
+  )
+  axi_crossbar_2x1__rmem0
+  (
+    .clk(ap_clk),
+    .rst(ap_rst_n_inv),
+    .m00_axi_araddr(m_axi_rmem0_ARADDR),
+    .m00_axi_arburst(m_axi_rmem0_ARBURST),
+    .m00_axi_arcache(m_axi_rmem0_ARCACHE),
+    .m00_axi_arid(m_axi_rmem0_ARID),
+    .m00_axi_arlen(m_axi_rmem0_ARLEN),
+    .m00_axi_arlock(m_axi_rmem0_ARLOCK),
+    .m00_axi_arprot(m_axi_rmem0_ARPROT),
+    .m00_axi_arqos(m_axi_rmem0_ARQOS),
+    .m00_axi_arready(m_axi_rmem0_ARREADY),
+    .m00_axi_arsize(m_axi_rmem0_ARSIZE),
+    .m00_axi_arvalid(m_axi_rmem0_ARVALID),
+    .m00_axi_awaddr(m_axi_rmem0_AWADDR),
+    .m00_axi_awburst(m_axi_rmem0_AWBURST),
+    .m00_axi_awcache(m_axi_rmem0_AWCACHE),
+    .m00_axi_awid(m_axi_rmem0_AWID),
+    .m00_axi_awlen(m_axi_rmem0_AWLEN),
+    .m00_axi_awlock(m_axi_rmem0_AWLOCK),
+    .m00_axi_awprot(m_axi_rmem0_AWPROT),
+    .m00_axi_awqos(m_axi_rmem0_AWQOS),
+    .m00_axi_awready(m_axi_rmem0_AWREADY),
+    .m00_axi_awsize(m_axi_rmem0_AWSIZE),
+    .m00_axi_awvalid(m_axi_rmem0_AWVALID),
+    .m00_axi_bid(m_axi_rmem0_BID),
+    .m00_axi_bready(m_axi_rmem0_BREADY),
+    .m00_axi_bresp(m_axi_rmem0_BRESP),
+    .m00_axi_bvalid(m_axi_rmem0_BVALID),
+    .m00_axi_rdata(m_axi_rmem0_RDATA),
+    .m00_axi_rid(m_axi_rmem0_RID),
+    .m00_axi_rlast(m_axi_rmem0_RLAST),
+    .m00_axi_rready(m_axi_rmem0_RREADY),
+    .m00_axi_rresp(m_axi_rmem0_RRESP),
+    .m00_axi_rvalid(m_axi_rmem0_RVALID),
+    .m00_axi_wdata(m_axi_rmem0_WDATA),
+    .m00_axi_wlast(m_axi_rmem0_WLAST),
+    .m00_axi_wready(m_axi_rmem0_WREADY),
+    .m00_axi_wstrb(m_axi_rmem0_WSTRB),
+    .m00_axi_wvalid(m_axi_rmem0_WVALID),
+    .s00_axi_araddr(m_axi_rmem0___Mmap2Stream_0___mmap_ARADDR),
+    .s00_axi_arburst(m_axi_rmem0___Mmap2Stream_0___mmap_ARBURST),
+    .s00_axi_arcache(m_axi_rmem0___Mmap2Stream_0___mmap_ARCACHE),
+    .s00_axi_arid(m_axi_rmem0___Mmap2Stream_0___mmap_ARID),
+    .s00_axi_arlen(m_axi_rmem0___Mmap2Stream_0___mmap_ARLEN),
+    .s00_axi_arlock(m_axi_rmem0___Mmap2Stream_0___mmap_ARLOCK),
+    .s00_axi_arprot(m_axi_rmem0___Mmap2Stream_0___mmap_ARPROT),
+    .s00_axi_arqos(m_axi_rmem0___Mmap2Stream_0___mmap_ARQOS),
+    .s00_axi_arready(m_axi_rmem0___Mmap2Stream_0___mmap_ARREADY),
+    .s00_axi_arsize(m_axi_rmem0___Mmap2Stream_0___mmap_ARSIZE),
+    .s00_axi_arvalid(m_axi_rmem0___Mmap2Stream_0___mmap_ARVALID),
+    .s00_axi_awaddr(m_axi_rmem0___Mmap2Stream_0___mmap_AWADDR),
+    .s00_axi_awburst(m_axi_rmem0___Mmap2Stream_0___mmap_AWBURST),
+    .s00_axi_awcache(m_axi_rmem0___Mmap2Stream_0___mmap_AWCACHE),
+    .s00_axi_awid(m_axi_rmem0___Mmap2Stream_0___mmap_AWID),
+    .s00_axi_awlen(m_axi_rmem0___Mmap2Stream_0___mmap_AWLEN),
+    .s00_axi_awlock(m_axi_rmem0___Mmap2Stream_0___mmap_AWLOCK),
+    .s00_axi_awprot(m_axi_rmem0___Mmap2Stream_0___mmap_AWPROT),
+    .s00_axi_awqos(m_axi_rmem0___Mmap2Stream_0___mmap_AWQOS),
+    .s00_axi_awready(m_axi_rmem0___Mmap2Stream_0___mmap_AWREADY),
+    .s00_axi_awsize(m_axi_rmem0___Mmap2Stream_0___mmap_AWSIZE),
+    .s00_axi_awvalid(m_axi_rmem0___Mmap2Stream_0___mmap_AWVALID),
+    .s00_axi_bid(m_axi_rmem0___Mmap2Stream_0___mmap_BID),
+    .s00_axi_bready(m_axi_rmem0___Mmap2Stream_0___mmap_BREADY),
+    .s00_axi_bresp(m_axi_rmem0___Mmap2Stream_0___mmap_BRESP),
+    .s00_axi_bvalid(m_axi_rmem0___Mmap2Stream_0___mmap_BVALID),
+    .s00_axi_rdata(m_axi_rmem0___Mmap2Stream_0___mmap_RDATA),
+    .s00_axi_rid(m_axi_rmem0___Mmap2Stream_0___mmap_RID),
+    .s00_axi_rlast(m_axi_rmem0___Mmap2Stream_0___mmap_RLAST),
+    .s00_axi_rready(m_axi_rmem0___Mmap2Stream_0___mmap_RREADY),
+    .s00_axi_rresp(m_axi_rmem0___Mmap2Stream_0___mmap_RRESP),
+    .s00_axi_rvalid(m_axi_rmem0___Mmap2Stream_0___mmap_RVALID),
+    .s00_axi_wdata(m_axi_rmem0___Mmap2Stream_0___mmap_WDATA),
+    .s00_axi_wlast(m_axi_rmem0___Mmap2Stream_0___mmap_WLAST),
+    .s00_axi_wready(m_axi_rmem0___Mmap2Stream_0___mmap_WREADY),
+    .s00_axi_wstrb(m_axi_rmem0___Mmap2Stream_0___mmap_WSTRB),
+    .s00_axi_wvalid(m_axi_rmem0___Mmap2Stream_0___mmap_WVALID),
+    .s01_axi_araddr(m_axi_rmem0___Stream2Mmap_0___mmap_ARADDR),
+    .s01_axi_arburst(m_axi_rmem0___Stream2Mmap_0___mmap_ARBURST),
+    .s01_axi_arcache(m_axi_rmem0___Stream2Mmap_0___mmap_ARCACHE),
+    .s01_axi_arid(m_axi_rmem0___Stream2Mmap_0___mmap_ARID),
+    .s01_axi_arlen(m_axi_rmem0___Stream2Mmap_0___mmap_ARLEN),
+    .s01_axi_arlock(m_axi_rmem0___Stream2Mmap_0___mmap_ARLOCK),
+    .s01_axi_arprot(m_axi_rmem0___Stream2Mmap_0___mmap_ARPROT),
+    .s01_axi_arqos(m_axi_rmem0___Stream2Mmap_0___mmap_ARQOS),
+    .s01_axi_arready(m_axi_rmem0___Stream2Mmap_0___mmap_ARREADY),
+    .s01_axi_arsize(m_axi_rmem0___Stream2Mmap_0___mmap_ARSIZE),
+    .s01_axi_arvalid(m_axi_rmem0___Stream2Mmap_0___mmap_ARVALID),
+    .s01_axi_awaddr(m_axi_rmem0___Stream2Mmap_0___mmap_AWADDR),
+    .s01_axi_awburst(m_axi_rmem0___Stream2Mmap_0___mmap_AWBURST),
+    .s01_axi_awcache(m_axi_rmem0___Stream2Mmap_0___mmap_AWCACHE),
+    .s01_axi_awid(m_axi_rmem0___Stream2Mmap_0___mmap_AWID),
+    .s01_axi_awlen(m_axi_rmem0___Stream2Mmap_0___mmap_AWLEN),
+    .s01_axi_awlock(m_axi_rmem0___Stream2Mmap_0___mmap_AWLOCK),
+    .s01_axi_awprot(m_axi_rmem0___Stream2Mmap_0___mmap_AWPROT),
+    .s01_axi_awqos(m_axi_rmem0___Stream2Mmap_0___mmap_AWQOS),
+    .s01_axi_awready(m_axi_rmem0___Stream2Mmap_0___mmap_AWREADY),
+    .s01_axi_awsize(m_axi_rmem0___Stream2Mmap_0___mmap_AWSIZE),
+    .s01_axi_awvalid(m_axi_rmem0___Stream2Mmap_0___mmap_AWVALID),
+    .s01_axi_bid(m_axi_rmem0___Stream2Mmap_0___mmap_BID),
+    .s01_axi_bready(m_axi_rmem0___Stream2Mmap_0___mmap_BREADY),
+    .s01_axi_bresp(m_axi_rmem0___Stream2Mmap_0___mmap_BRESP),
+    .s01_axi_bvalid(m_axi_rmem0___Stream2Mmap_0___mmap_BVALID),
+    .s01_axi_rdata(m_axi_rmem0___Stream2Mmap_0___mmap_RDATA),
+    .s01_axi_rid(m_axi_rmem0___Stream2Mmap_0___mmap_RID),
+    .s01_axi_rlast(m_axi_rmem0___Stream2Mmap_0___mmap_RLAST),
+    .s01_axi_rready(m_axi_rmem0___Stream2Mmap_0___mmap_RREADY),
+    .s01_axi_rresp(m_axi_rmem0___Stream2Mmap_0___mmap_RRESP),
+    .s01_axi_rvalid(m_axi_rmem0___Stream2Mmap_0___mmap_RVALID),
+    .s01_axi_wdata(m_axi_rmem0___Stream2Mmap_0___mmap_WDATA),
+    .s01_axi_wlast(m_axi_rmem0___Stream2Mmap_0___mmap_WLAST),
+    .s01_axi_wready(m_axi_rmem0___Stream2Mmap_0___mmap_WREADY),
+    .s01_axi_wstrb(m_axi_rmem0___Stream2Mmap_0___mmap_WSTRB),
+    .s01_axi_wvalid(m_axi_rmem0___Stream2Mmap_0___mmap_WVALID)
+  );
+
+
+  (* keep_hierarchy = "yes" *) axi_crossbar_2x1
+  #(
+    .DATA_WIDTH(512),
+    .ADDR_WIDTH(64),
+    .S_ID_WIDTH(1),
+    .M_ID_WIDTH(2),
+    .M00_ADDR_WIDTH(64),
+    .M00_ISSUE(16),
+    .S00_THREADS(1),
+    .S01_THREADS(1)
+  )
+  axi_crossbar_2x1__rmem1
+  (
+    .clk(ap_clk),
+    .rst(ap_rst_n_inv),
+    .m00_axi_araddr(m_axi_rmem1_ARADDR),
+    .m00_axi_arburst(m_axi_rmem1_ARBURST),
+    .m00_axi_arcache(m_axi_rmem1_ARCACHE),
+    .m00_axi_arid(m_axi_rmem1_ARID),
+    .m00_axi_arlen(m_axi_rmem1_ARLEN),
+    .m00_axi_arlock(m_axi_rmem1_ARLOCK),
+    .m00_axi_arprot(m_axi_rmem1_ARPROT),
+    .m00_axi_arqos(m_axi_rmem1_ARQOS),
+    .m00_axi_arready(m_axi_rmem1_ARREADY),
+    .m00_axi_arsize(m_axi_rmem1_ARSIZE),
+    .m00_axi_arvalid(m_axi_rmem1_ARVALID),
+    .m00_axi_awaddr(m_axi_rmem1_AWADDR),
+    .m00_axi_awburst(m_axi_rmem1_AWBURST),
+    .m00_axi_awcache(m_axi_rmem1_AWCACHE),
+    .m00_axi_awid(m_axi_rmem1_AWID),
+    .m00_axi_awlen(m_axi_rmem1_AWLEN),
+    .m00_axi_awlock(m_axi_rmem1_AWLOCK),
+    .m00_axi_awprot(m_axi_rmem1_AWPROT),
+    .m00_axi_awqos(m_axi_rmem1_AWQOS),
+    .m00_axi_awready(m_axi_rmem1_AWREADY),
+    .m00_axi_awsize(m_axi_rmem1_AWSIZE),
+    .m00_axi_awvalid(m_axi_rmem1_AWVALID),
+    .m00_axi_bid(m_axi_rmem1_BID),
+    .m00_axi_bready(m_axi_rmem1_BREADY),
+    .m00_axi_bresp(m_axi_rmem1_BRESP),
+    .m00_axi_bvalid(m_axi_rmem1_BVALID),
+    .m00_axi_rdata(m_axi_rmem1_RDATA),
+    .m00_axi_rid(m_axi_rmem1_RID),
+    .m00_axi_rlast(m_axi_rmem1_RLAST),
+    .m00_axi_rready(m_axi_rmem1_RREADY),
+    .m00_axi_rresp(m_axi_rmem1_RRESP),
+    .m00_axi_rvalid(m_axi_rmem1_RVALID),
+    .m00_axi_wdata(m_axi_rmem1_WDATA),
+    .m00_axi_wlast(m_axi_rmem1_WLAST),
+    .m00_axi_wready(m_axi_rmem1_WREADY),
+    .m00_axi_wstrb(m_axi_rmem1_WSTRB),
+    .m00_axi_wvalid(m_axi_rmem1_WVALID),
+    .s00_axi_araddr(m_axi_rmem1___Mmap2Stream_1___mmap_ARADDR),
+    .s00_axi_arburst(m_axi_rmem1___Mmap2Stream_1___mmap_ARBURST),
+    .s00_axi_arcache(m_axi_rmem1___Mmap2Stream_1___mmap_ARCACHE),
+    .s00_axi_arid(m_axi_rmem1___Mmap2Stream_1___mmap_ARID),
+    .s00_axi_arlen(m_axi_rmem1___Mmap2Stream_1___mmap_ARLEN),
+    .s00_axi_arlock(m_axi_rmem1___Mmap2Stream_1___mmap_ARLOCK),
+    .s00_axi_arprot(m_axi_rmem1___Mmap2Stream_1___mmap_ARPROT),
+    .s00_axi_arqos(m_axi_rmem1___Mmap2Stream_1___mmap_ARQOS),
+    .s00_axi_arready(m_axi_rmem1___Mmap2Stream_1___mmap_ARREADY),
+    .s00_axi_arsize(m_axi_rmem1___Mmap2Stream_1___mmap_ARSIZE),
+    .s00_axi_arvalid(m_axi_rmem1___Mmap2Stream_1___mmap_ARVALID),
+    .s00_axi_awaddr(m_axi_rmem1___Mmap2Stream_1___mmap_AWADDR),
+    .s00_axi_awburst(m_axi_rmem1___Mmap2Stream_1___mmap_AWBURST),
+    .s00_axi_awcache(m_axi_rmem1___Mmap2Stream_1___mmap_AWCACHE),
+    .s00_axi_awid(m_axi_rmem1___Mmap2Stream_1___mmap_AWID),
+    .s00_axi_awlen(m_axi_rmem1___Mmap2Stream_1___mmap_AWLEN),
+    .s00_axi_awlock(m_axi_rmem1___Mmap2Stream_1___mmap_AWLOCK),
+    .s00_axi_awprot(m_axi_rmem1___Mmap2Stream_1___mmap_AWPROT),
+    .s00_axi_awqos(m_axi_rmem1___Mmap2Stream_1___mmap_AWQOS),
+    .s00_axi_awready(m_axi_rmem1___Mmap2Stream_1___mmap_AWREADY),
+    .s00_axi_awsize(m_axi_rmem1___Mmap2Stream_1___mmap_AWSIZE),
+    .s00_axi_awvalid(m_axi_rmem1___Mmap2Stream_1___mmap_AWVALID),
+    .s00_axi_bid(m_axi_rmem1___Mmap2Stream_1___mmap_BID),
+    .s00_axi_bready(m_axi_rmem1___Mmap2Stream_1___mmap_BREADY),
+    .s00_axi_bresp(m_axi_rmem1___Mmap2Stream_1___mmap_BRESP),
+    .s00_axi_bvalid(m_axi_rmem1___Mmap2Stream_1___mmap_BVALID),
+    .s00_axi_rdata(m_axi_rmem1___Mmap2Stream_1___mmap_RDATA),
+    .s00_axi_rid(m_axi_rmem1___Mmap2Stream_1___mmap_RID),
+    .s00_axi_rlast(m_axi_rmem1___Mmap2Stream_1___mmap_RLAST),
+    .s00_axi_rready(m_axi_rmem1___Mmap2Stream_1___mmap_RREADY),
+    .s00_axi_rresp(m_axi_rmem1___Mmap2Stream_1___mmap_RRESP),
+    .s00_axi_rvalid(m_axi_rmem1___Mmap2Stream_1___mmap_RVALID),
+    .s00_axi_wdata(m_axi_rmem1___Mmap2Stream_1___mmap_WDATA),
+    .s00_axi_wlast(m_axi_rmem1___Mmap2Stream_1___mmap_WLAST),
+    .s00_axi_wready(m_axi_rmem1___Mmap2Stream_1___mmap_WREADY),
+    .s00_axi_wstrb(m_axi_rmem1___Mmap2Stream_1___mmap_WSTRB),
+    .s00_axi_wvalid(m_axi_rmem1___Mmap2Stream_1___mmap_WVALID),
+    .s01_axi_araddr(m_axi_rmem1___Stream2Mmap_1___mmap_ARADDR),
+    .s01_axi_arburst(m_axi_rmem1___Stream2Mmap_1___mmap_ARBURST),
+    .s01_axi_arcache(m_axi_rmem1___Stream2Mmap_1___mmap_ARCACHE),
+    .s01_axi_arid(m_axi_rmem1___Stream2Mmap_1___mmap_ARID),
+    .s01_axi_arlen(m_axi_rmem1___Stream2Mmap_1___mmap_ARLEN),
+    .s01_axi_arlock(m_axi_rmem1___Stream2Mmap_1___mmap_ARLOCK),
+    .s01_axi_arprot(m_axi_rmem1___Stream2Mmap_1___mmap_ARPROT),
+    .s01_axi_arqos(m_axi_rmem1___Stream2Mmap_1___mmap_ARQOS),
+    .s01_axi_arready(m_axi_rmem1___Stream2Mmap_1___mmap_ARREADY),
+    .s01_axi_arsize(m_axi_rmem1___Stream2Mmap_1___mmap_ARSIZE),
+    .s01_axi_arvalid(m_axi_rmem1___Stream2Mmap_1___mmap_ARVALID),
+    .s01_axi_awaddr(m_axi_rmem1___Stream2Mmap_1___mmap_AWADDR),
+    .s01_axi_awburst(m_axi_rmem1___Stream2Mmap_1___mmap_AWBURST),
+    .s01_axi_awcache(m_axi_rmem1___Stream2Mmap_1___mmap_AWCACHE),
+    .s01_axi_awid(m_axi_rmem1___Stream2Mmap_1___mmap_AWID),
+    .s01_axi_awlen(m_axi_rmem1___Stream2Mmap_1___mmap_AWLEN),
+    .s01_axi_awlock(m_axi_rmem1___Stream2Mmap_1___mmap_AWLOCK),
+    .s01_axi_awprot(m_axi_rmem1___Stream2Mmap_1___mmap_AWPROT),
+    .s01_axi_awqos(m_axi_rmem1___Stream2Mmap_1___mmap_AWQOS),
+    .s01_axi_awready(m_axi_rmem1___Stream2Mmap_1___mmap_AWREADY),
+    .s01_axi_awsize(m_axi_rmem1___Stream2Mmap_1___mmap_AWSIZE),
+    .s01_axi_awvalid(m_axi_rmem1___Stream2Mmap_1___mmap_AWVALID),
+    .s01_axi_bid(m_axi_rmem1___Stream2Mmap_1___mmap_BID),
+    .s01_axi_bready(m_axi_rmem1___Stream2Mmap_1___mmap_BREADY),
+    .s01_axi_bresp(m_axi_rmem1___Stream2Mmap_1___mmap_BRESP),
+    .s01_axi_bvalid(m_axi_rmem1___Stream2Mmap_1___mmap_BVALID),
+    .s01_axi_rdata(m_axi_rmem1___Stream2Mmap_1___mmap_RDATA),
+    .s01_axi_rid(m_axi_rmem1___Stream2Mmap_1___mmap_RID),
+    .s01_axi_rlast(m_axi_rmem1___Stream2Mmap_1___mmap_RLAST),
+    .s01_axi_rready(m_axi_rmem1___Stream2Mmap_1___mmap_RREADY),
+    .s01_axi_rresp(m_axi_rmem1___Stream2Mmap_1___mmap_RRESP),
+    .s01_axi_rvalid(m_axi_rmem1___Stream2Mmap_1___mmap_RVALID),
+    .s01_axi_wdata(m_axi_rmem1___Stream2Mmap_1___mmap_WDATA),
+    .s01_axi_wlast(m_axi_rmem1___Stream2Mmap_1___mmap_WLAST),
+    .s01_axi_wready(m_axi_rmem1___Stream2Mmap_1___mmap_WREADY),
+    .s01_axi_wstrb(m_axi_rmem1___Stream2Mmap_1___mmap_WSTRB),
+    .s01_axi_wvalid(m_axi_rmem1___Stream2Mmap_1___mmap_WVALID)
+  );
+
+
+  (* keep_hierarchy = "yes" *) axi_crossbar_2x1
+  #(
+    .DATA_WIDTH(512),
+    .ADDR_WIDTH(64),
+    .S_ID_WIDTH(1),
+    .M_ID_WIDTH(2),
+    .M00_ADDR_WIDTH(64),
+    .M00_ISSUE(16),
+    .S00_THREADS(1),
+    .S01_THREADS(1)
+  )
+  axi_crossbar_2x1__rmem2
+  (
+    .clk(ap_clk),
+    .rst(ap_rst_n_inv),
+    .m00_axi_araddr(m_axi_rmem2_ARADDR),
+    .m00_axi_arburst(m_axi_rmem2_ARBURST),
+    .m00_axi_arcache(m_axi_rmem2_ARCACHE),
+    .m00_axi_arid(m_axi_rmem2_ARID),
+    .m00_axi_arlen(m_axi_rmem2_ARLEN),
+    .m00_axi_arlock(m_axi_rmem2_ARLOCK),
+    .m00_axi_arprot(m_axi_rmem2_ARPROT),
+    .m00_axi_arqos(m_axi_rmem2_ARQOS),
+    .m00_axi_arready(m_axi_rmem2_ARREADY),
+    .m00_axi_arsize(m_axi_rmem2_ARSIZE),
+    .m00_axi_arvalid(m_axi_rmem2_ARVALID),
+    .m00_axi_awaddr(m_axi_rmem2_AWADDR),
+    .m00_axi_awburst(m_axi_rmem2_AWBURST),
+    .m00_axi_awcache(m_axi_rmem2_AWCACHE),
+    .m00_axi_awid(m_axi_rmem2_AWID),
+    .m00_axi_awlen(m_axi_rmem2_AWLEN),
+    .m00_axi_awlock(m_axi_rmem2_AWLOCK),
+    .m00_axi_awprot(m_axi_rmem2_AWPROT),
+    .m00_axi_awqos(m_axi_rmem2_AWQOS),
+    .m00_axi_awready(m_axi_rmem2_AWREADY),
+    .m00_axi_awsize(m_axi_rmem2_AWSIZE),
+    .m00_axi_awvalid(m_axi_rmem2_AWVALID),
+    .m00_axi_bid(m_axi_rmem2_BID),
+    .m00_axi_bready(m_axi_rmem2_BREADY),
+    .m00_axi_bresp(m_axi_rmem2_BRESP),
+    .m00_axi_bvalid(m_axi_rmem2_BVALID),
+    .m00_axi_rdata(m_axi_rmem2_RDATA),
+    .m00_axi_rid(m_axi_rmem2_RID),
+    .m00_axi_rlast(m_axi_rmem2_RLAST),
+    .m00_axi_rready(m_axi_rmem2_RREADY),
+    .m00_axi_rresp(m_axi_rmem2_RRESP),
+    .m00_axi_rvalid(m_axi_rmem2_RVALID),
+    .m00_axi_wdata(m_axi_rmem2_WDATA),
+    .m00_axi_wlast(m_axi_rmem2_WLAST),
+    .m00_axi_wready(m_axi_rmem2_WREADY),
+    .m00_axi_wstrb(m_axi_rmem2_WSTRB),
+    .m00_axi_wvalid(m_axi_rmem2_WVALID),
+    .s00_axi_araddr(m_axi_rmem2___Mmap2Stream_2___mmap_ARADDR),
+    .s00_axi_arburst(m_axi_rmem2___Mmap2Stream_2___mmap_ARBURST),
+    .s00_axi_arcache(m_axi_rmem2___Mmap2Stream_2___mmap_ARCACHE),
+    .s00_axi_arid(m_axi_rmem2___Mmap2Stream_2___mmap_ARID),
+    .s00_axi_arlen(m_axi_rmem2___Mmap2Stream_2___mmap_ARLEN),
+    .s00_axi_arlock(m_axi_rmem2___Mmap2Stream_2___mmap_ARLOCK),
+    .s00_axi_arprot(m_axi_rmem2___Mmap2Stream_2___mmap_ARPROT),
+    .s00_axi_arqos(m_axi_rmem2___Mmap2Stream_2___mmap_ARQOS),
+    .s00_axi_arready(m_axi_rmem2___Mmap2Stream_2___mmap_ARREADY),
+    .s00_axi_arsize(m_axi_rmem2___Mmap2Stream_2___mmap_ARSIZE),
+    .s00_axi_arvalid(m_axi_rmem2___Mmap2Stream_2___mmap_ARVALID),
+    .s00_axi_awaddr(m_axi_rmem2___Mmap2Stream_2___mmap_AWADDR),
+    .s00_axi_awburst(m_axi_rmem2___Mmap2Stream_2___mmap_AWBURST),
+    .s00_axi_awcache(m_axi_rmem2___Mmap2Stream_2___mmap_AWCACHE),
+    .s00_axi_awid(m_axi_rmem2___Mmap2Stream_2___mmap_AWID),
+    .s00_axi_awlen(m_axi_rmem2___Mmap2Stream_2___mmap_AWLEN),
+    .s00_axi_awlock(m_axi_rmem2___Mmap2Stream_2___mmap_AWLOCK),
+    .s00_axi_awprot(m_axi_rmem2___Mmap2Stream_2___mmap_AWPROT),
+    .s00_axi_awqos(m_axi_rmem2___Mmap2Stream_2___mmap_AWQOS),
+    .s00_axi_awready(m_axi_rmem2___Mmap2Stream_2___mmap_AWREADY),
+    .s00_axi_awsize(m_axi_rmem2___Mmap2Stream_2___mmap_AWSIZE),
+    .s00_axi_awvalid(m_axi_rmem2___Mmap2Stream_2___mmap_AWVALID),
+    .s00_axi_bid(m_axi_rmem2___Mmap2Stream_2___mmap_BID),
+    .s00_axi_bready(m_axi_rmem2___Mmap2Stream_2___mmap_BREADY),
+    .s00_axi_bresp(m_axi_rmem2___Mmap2Stream_2___mmap_BRESP),
+    .s00_axi_bvalid(m_axi_rmem2___Mmap2Stream_2___mmap_BVALID),
+    .s00_axi_rdata(m_axi_rmem2___Mmap2Stream_2___mmap_RDATA),
+    .s00_axi_rid(m_axi_rmem2___Mmap2Stream_2___mmap_RID),
+    .s00_axi_rlast(m_axi_rmem2___Mmap2Stream_2___mmap_RLAST),
+    .s00_axi_rready(m_axi_rmem2___Mmap2Stream_2___mmap_RREADY),
+    .s00_axi_rresp(m_axi_rmem2___Mmap2Stream_2___mmap_RRESP),
+    .s00_axi_rvalid(m_axi_rmem2___Mmap2Stream_2___mmap_RVALID),
+    .s00_axi_wdata(m_axi_rmem2___Mmap2Stream_2___mmap_WDATA),
+    .s00_axi_wlast(m_axi_rmem2___Mmap2Stream_2___mmap_WLAST),
+    .s00_axi_wready(m_axi_rmem2___Mmap2Stream_2___mmap_WREADY),
+    .s00_axi_wstrb(m_axi_rmem2___Mmap2Stream_2___mmap_WSTRB),
+    .s00_axi_wvalid(m_axi_rmem2___Mmap2Stream_2___mmap_WVALID),
+    .s01_axi_araddr(m_axi_rmem2___Stream2Mmap_2___mmap_ARADDR),
+    .s01_axi_arburst(m_axi_rmem2___Stream2Mmap_2___mmap_ARBURST),
+    .s01_axi_arcache(m_axi_rmem2___Stream2Mmap_2___mmap_ARCACHE),
+    .s01_axi_arid(m_axi_rmem2___Stream2Mmap_2___mmap_ARID),
+    .s01_axi_arlen(m_axi_rmem2___Stream2Mmap_2___mmap_ARLEN),
+    .s01_axi_arlock(m_axi_rmem2___Stream2Mmap_2___mmap_ARLOCK),
+    .s01_axi_arprot(m_axi_rmem2___Stream2Mmap_2___mmap_ARPROT),
+    .s01_axi_arqos(m_axi_rmem2___Stream2Mmap_2___mmap_ARQOS),
+    .s01_axi_arready(m_axi_rmem2___Stream2Mmap_2___mmap_ARREADY),
+    .s01_axi_arsize(m_axi_rmem2___Stream2Mmap_2___mmap_ARSIZE),
+    .s01_axi_arvalid(m_axi_rmem2___Stream2Mmap_2___mmap_ARVALID),
+    .s01_axi_awaddr(m_axi_rmem2___Stream2Mmap_2___mmap_AWADDR),
+    .s01_axi_awburst(m_axi_rmem2___Stream2Mmap_2___mmap_AWBURST),
+    .s01_axi_awcache(m_axi_rmem2___Stream2Mmap_2___mmap_AWCACHE),
+    .s01_axi_awid(m_axi_rmem2___Stream2Mmap_2___mmap_AWID),
+    .s01_axi_awlen(m_axi_rmem2___Stream2Mmap_2___mmap_AWLEN),
+    .s01_axi_awlock(m_axi_rmem2___Stream2Mmap_2___mmap_AWLOCK),
+    .s01_axi_awprot(m_axi_rmem2___Stream2Mmap_2___mmap_AWPROT),
+    .s01_axi_awqos(m_axi_rmem2___Stream2Mmap_2___mmap_AWQOS),
+    .s01_axi_awready(m_axi_rmem2___Stream2Mmap_2___mmap_AWREADY),
+    .s01_axi_awsize(m_axi_rmem2___Stream2Mmap_2___mmap_AWSIZE),
+    .s01_axi_awvalid(m_axi_rmem2___Stream2Mmap_2___mmap_AWVALID),
+    .s01_axi_bid(m_axi_rmem2___Stream2Mmap_2___mmap_BID),
+    .s01_axi_bready(m_axi_rmem2___Stream2Mmap_2___mmap_BREADY),
+    .s01_axi_bresp(m_axi_rmem2___Stream2Mmap_2___mmap_BRESP),
+    .s01_axi_bvalid(m_axi_rmem2___Stream2Mmap_2___mmap_BVALID),
+    .s01_axi_rdata(m_axi_rmem2___Stream2Mmap_2___mmap_RDATA),
+    .s01_axi_rid(m_axi_rmem2___Stream2Mmap_2___mmap_RID),
+    .s01_axi_rlast(m_axi_rmem2___Stream2Mmap_2___mmap_RLAST),
+    .s01_axi_rready(m_axi_rmem2___Stream2Mmap_2___mmap_RREADY),
+    .s01_axi_rresp(m_axi_rmem2___Stream2Mmap_2___mmap_RRESP),
+    .s01_axi_rvalid(m_axi_rmem2___Stream2Mmap_2___mmap_RVALID),
+    .s01_axi_wdata(m_axi_rmem2___Stream2Mmap_2___mmap_WDATA),
+    .s01_axi_wlast(m_axi_rmem2___Stream2Mmap_2___mmap_WLAST),
+    .s01_axi_wready(m_axi_rmem2___Stream2Mmap_2___mmap_WREADY),
+    .s01_axi_wstrb(m_axi_rmem2___Stream2Mmap_2___mmap_WSTRB),
+    .s01_axi_wvalid(m_axi_rmem2___Stream2Mmap_2___mmap_WVALID)
+  );
+
+
+  (* keep_hierarchy = "yes" *) axi_crossbar_2x1
+  #(
+    .DATA_WIDTH(512),
+    .ADDR_WIDTH(64),
+    .S_ID_WIDTH(1),
+    .M_ID_WIDTH(2),
+    .M00_ADDR_WIDTH(64),
+    .M00_ISSUE(16),
+    .S00_THREADS(1),
+    .S01_THREADS(1)
+  )
+  axi_crossbar_2x1__rmem3
+  (
+    .clk(ap_clk),
+    .rst(ap_rst_n_inv),
+    .m00_axi_araddr(m_axi_rmem3_ARADDR),
+    .m00_axi_arburst(m_axi_rmem3_ARBURST),
+    .m00_axi_arcache(m_axi_rmem3_ARCACHE),
+    .m00_axi_arid(m_axi_rmem3_ARID),
+    .m00_axi_arlen(m_axi_rmem3_ARLEN),
+    .m00_axi_arlock(m_axi_rmem3_ARLOCK),
+    .m00_axi_arprot(m_axi_rmem3_ARPROT),
+    .m00_axi_arqos(m_axi_rmem3_ARQOS),
+    .m00_axi_arready(m_axi_rmem3_ARREADY),
+    .m00_axi_arsize(m_axi_rmem3_ARSIZE),
+    .m00_axi_arvalid(m_axi_rmem3_ARVALID),
+    .m00_axi_awaddr(m_axi_rmem3_AWADDR),
+    .m00_axi_awburst(m_axi_rmem3_AWBURST),
+    .m00_axi_awcache(m_axi_rmem3_AWCACHE),
+    .m00_axi_awid(m_axi_rmem3_AWID),
+    .m00_axi_awlen(m_axi_rmem3_AWLEN),
+    .m00_axi_awlock(m_axi_rmem3_AWLOCK),
+    .m00_axi_awprot(m_axi_rmem3_AWPROT),
+    .m00_axi_awqos(m_axi_rmem3_AWQOS),
+    .m00_axi_awready(m_axi_rmem3_AWREADY),
+    .m00_axi_awsize(m_axi_rmem3_AWSIZE),
+    .m00_axi_awvalid(m_axi_rmem3_AWVALID),
+    .m00_axi_bid(m_axi_rmem3_BID),
+    .m00_axi_bready(m_axi_rmem3_BREADY),
+    .m00_axi_bresp(m_axi_rmem3_BRESP),
+    .m00_axi_bvalid(m_axi_rmem3_BVALID),
+    .m00_axi_rdata(m_axi_rmem3_RDATA),
+    .m00_axi_rid(m_axi_rmem3_RID),
+    .m00_axi_rlast(m_axi_rmem3_RLAST),
+    .m00_axi_rready(m_axi_rmem3_RREADY),
+    .m00_axi_rresp(m_axi_rmem3_RRESP),
+    .m00_axi_rvalid(m_axi_rmem3_RVALID),
+    .m00_axi_wdata(m_axi_rmem3_WDATA),
+    .m00_axi_wlast(m_axi_rmem3_WLAST),
+    .m00_axi_wready(m_axi_rmem3_WREADY),
+    .m00_axi_wstrb(m_axi_rmem3_WSTRB),
+    .m00_axi_wvalid(m_axi_rmem3_WVALID),
+    .s00_axi_araddr(m_axi_rmem3___Mmap2Stream_3___mmap_ARADDR),
+    .s00_axi_arburst(m_axi_rmem3___Mmap2Stream_3___mmap_ARBURST),
+    .s00_axi_arcache(m_axi_rmem3___Mmap2Stream_3___mmap_ARCACHE),
+    .s00_axi_arid(m_axi_rmem3___Mmap2Stream_3___mmap_ARID),
+    .s00_axi_arlen(m_axi_rmem3___Mmap2Stream_3___mmap_ARLEN),
+    .s00_axi_arlock(m_axi_rmem3___Mmap2Stream_3___mmap_ARLOCK),
+    .s00_axi_arprot(m_axi_rmem3___Mmap2Stream_3___mmap_ARPROT),
+    .s00_axi_arqos(m_axi_rmem3___Mmap2Stream_3___mmap_ARQOS),
+    .s00_axi_arready(m_axi_rmem3___Mmap2Stream_3___mmap_ARREADY),
+    .s00_axi_arsize(m_axi_rmem3___Mmap2Stream_3___mmap_ARSIZE),
+    .s00_axi_arvalid(m_axi_rmem3___Mmap2Stream_3___mmap_ARVALID),
+    .s00_axi_awaddr(m_axi_rmem3___Mmap2Stream_3___mmap_AWADDR),
+    .s00_axi_awburst(m_axi_rmem3___Mmap2Stream_3___mmap_AWBURST),
+    .s00_axi_awcache(m_axi_rmem3___Mmap2Stream_3___mmap_AWCACHE),
+    .s00_axi_awid(m_axi_rmem3___Mmap2Stream_3___mmap_AWID),
+    .s00_axi_awlen(m_axi_rmem3___Mmap2Stream_3___mmap_AWLEN),
+    .s00_axi_awlock(m_axi_rmem3___Mmap2Stream_3___mmap_AWLOCK),
+    .s00_axi_awprot(m_axi_rmem3___Mmap2Stream_3___mmap_AWPROT),
+    .s00_axi_awqos(m_axi_rmem3___Mmap2Stream_3___mmap_AWQOS),
+    .s00_axi_awready(m_axi_rmem3___Mmap2Stream_3___mmap_AWREADY),
+    .s00_axi_awsize(m_axi_rmem3___Mmap2Stream_3___mmap_AWSIZE),
+    .s00_axi_awvalid(m_axi_rmem3___Mmap2Stream_3___mmap_AWVALID),
+    .s00_axi_bid(m_axi_rmem3___Mmap2Stream_3___mmap_BID),
+    .s00_axi_bready(m_axi_rmem3___Mmap2Stream_3___mmap_BREADY),
+    .s00_axi_bresp(m_axi_rmem3___Mmap2Stream_3___mmap_BRESP),
+    .s00_axi_bvalid(m_axi_rmem3___Mmap2Stream_3___mmap_BVALID),
+    .s00_axi_rdata(m_axi_rmem3___Mmap2Stream_3___mmap_RDATA),
+    .s00_axi_rid(m_axi_rmem3___Mmap2Stream_3___mmap_RID),
+    .s00_axi_rlast(m_axi_rmem3___Mmap2Stream_3___mmap_RLAST),
+    .s00_axi_rready(m_axi_rmem3___Mmap2Stream_3___mmap_RREADY),
+    .s00_axi_rresp(m_axi_rmem3___Mmap2Stream_3___mmap_RRESP),
+    .s00_axi_rvalid(m_axi_rmem3___Mmap2Stream_3___mmap_RVALID),
+    .s00_axi_wdata(m_axi_rmem3___Mmap2Stream_3___mmap_WDATA),
+    .s00_axi_wlast(m_axi_rmem3___Mmap2Stream_3___mmap_WLAST),
+    .s00_axi_wready(m_axi_rmem3___Mmap2Stream_3___mmap_WREADY),
+    .s00_axi_wstrb(m_axi_rmem3___Mmap2Stream_3___mmap_WSTRB),
+    .s00_axi_wvalid(m_axi_rmem3___Mmap2Stream_3___mmap_WVALID),
+    .s01_axi_araddr(m_axi_rmem3___Stream2Mmap_3___mmap_ARADDR),
+    .s01_axi_arburst(m_axi_rmem3___Stream2Mmap_3___mmap_ARBURST),
+    .s01_axi_arcache(m_axi_rmem3___Stream2Mmap_3___mmap_ARCACHE),
+    .s01_axi_arid(m_axi_rmem3___Stream2Mmap_3___mmap_ARID),
+    .s01_axi_arlen(m_axi_rmem3___Stream2Mmap_3___mmap_ARLEN),
+    .s01_axi_arlock(m_axi_rmem3___Stream2Mmap_3___mmap_ARLOCK),
+    .s01_axi_arprot(m_axi_rmem3___Stream2Mmap_3___mmap_ARPROT),
+    .s01_axi_arqos(m_axi_rmem3___Stream2Mmap_3___mmap_ARQOS),
+    .s01_axi_arready(m_axi_rmem3___Stream2Mmap_3___mmap_ARREADY),
+    .s01_axi_arsize(m_axi_rmem3___Stream2Mmap_3___mmap_ARSIZE),
+    .s01_axi_arvalid(m_axi_rmem3___Stream2Mmap_3___mmap_ARVALID),
+    .s01_axi_awaddr(m_axi_rmem3___Stream2Mmap_3___mmap_AWADDR),
+    .s01_axi_awburst(m_axi_rmem3___Stream2Mmap_3___mmap_AWBURST),
+    .s01_axi_awcache(m_axi_rmem3___Stream2Mmap_3___mmap_AWCACHE),
+    .s01_axi_awid(m_axi_rmem3___Stream2Mmap_3___mmap_AWID),
+    .s01_axi_awlen(m_axi_rmem3___Stream2Mmap_3___mmap_AWLEN),
+    .s01_axi_awlock(m_axi_rmem3___Stream2Mmap_3___mmap_AWLOCK),
+    .s01_axi_awprot(m_axi_rmem3___Stream2Mmap_3___mmap_AWPROT),
+    .s01_axi_awqos(m_axi_rmem3___Stream2Mmap_3___mmap_AWQOS),
+    .s01_axi_awready(m_axi_rmem3___Stream2Mmap_3___mmap_AWREADY),
+    .s01_axi_awsize(m_axi_rmem3___Stream2Mmap_3___mmap_AWSIZE),
+    .s01_axi_awvalid(m_axi_rmem3___Stream2Mmap_3___mmap_AWVALID),
+    .s01_axi_bid(m_axi_rmem3___Stream2Mmap_3___mmap_BID),
+    .s01_axi_bready(m_axi_rmem3___Stream2Mmap_3___mmap_BREADY),
+    .s01_axi_bresp(m_axi_rmem3___Stream2Mmap_3___mmap_BRESP),
+    .s01_axi_bvalid(m_axi_rmem3___Stream2Mmap_3___mmap_BVALID),
+    .s01_axi_rdata(m_axi_rmem3___Stream2Mmap_3___mmap_RDATA),
+    .s01_axi_rid(m_axi_rmem3___Stream2Mmap_3___mmap_RID),
+    .s01_axi_rlast(m_axi_rmem3___Stream2Mmap_3___mmap_RLAST),
+    .s01_axi_rready(m_axi_rmem3___Stream2Mmap_3___mmap_RREADY),
+    .s01_axi_rresp(m_axi_rmem3___Stream2Mmap_3___mmap_RRESP),
+    .s01_axi_rvalid(m_axi_rmem3___Stream2Mmap_3___mmap_RVALID),
+    .s01_axi_wdata(m_axi_rmem3___Stream2Mmap_3___mmap_WDATA),
+    .s01_axi_wlast(m_axi_rmem3___Stream2Mmap_3___mmap_WLAST),
+    .s01_axi_wready(m_axi_rmem3___Stream2Mmap_3___mmap_WREADY),
+    .s01_axi_wstrb(m_axi_rmem3___Stream2Mmap_3___mmap_WSTRB),
+    .s01_axi_wvalid(m_axi_rmem3___Stream2Mmap_3___mmap_WVALID)
+  );
+
+
+  (* keep_hierarchy = "yes" *) axi_crossbar_2x1
+  #(
+    .DATA_WIDTH(512),
+    .ADDR_WIDTH(64),
+    .S_ID_WIDTH(1),
+    .M_ID_WIDTH(2),
+    .M00_ADDR_WIDTH(64),
+    .M00_ISSUE(16),
+    .S00_THREADS(1),
+    .S01_THREADS(1)
+  )
+  axi_crossbar_2x1__rmem4
+  (
+    .clk(ap_clk),
+    .rst(ap_rst_n_inv),
+    .m00_axi_araddr(m_axi_rmem4_ARADDR),
+    .m00_axi_arburst(m_axi_rmem4_ARBURST),
+    .m00_axi_arcache(m_axi_rmem4_ARCACHE),
+    .m00_axi_arid(m_axi_rmem4_ARID),
+    .m00_axi_arlen(m_axi_rmem4_ARLEN),
+    .m00_axi_arlock(m_axi_rmem4_ARLOCK),
+    .m00_axi_arprot(m_axi_rmem4_ARPROT),
+    .m00_axi_arqos(m_axi_rmem4_ARQOS),
+    .m00_axi_arready(m_axi_rmem4_ARREADY),
+    .m00_axi_arsize(m_axi_rmem4_ARSIZE),
+    .m00_axi_arvalid(m_axi_rmem4_ARVALID),
+    .m00_axi_awaddr(m_axi_rmem4_AWADDR),
+    .m00_axi_awburst(m_axi_rmem4_AWBURST),
+    .m00_axi_awcache(m_axi_rmem4_AWCACHE),
+    .m00_axi_awid(m_axi_rmem4_AWID),
+    .m00_axi_awlen(m_axi_rmem4_AWLEN),
+    .m00_axi_awlock(m_axi_rmem4_AWLOCK),
+    .m00_axi_awprot(m_axi_rmem4_AWPROT),
+    .m00_axi_awqos(m_axi_rmem4_AWQOS),
+    .m00_axi_awready(m_axi_rmem4_AWREADY),
+    .m00_axi_awsize(m_axi_rmem4_AWSIZE),
+    .m00_axi_awvalid(m_axi_rmem4_AWVALID),
+    .m00_axi_bid(m_axi_rmem4_BID),
+    .m00_axi_bready(m_axi_rmem4_BREADY),
+    .m00_axi_bresp(m_axi_rmem4_BRESP),
+    .m00_axi_bvalid(m_axi_rmem4_BVALID),
+    .m00_axi_rdata(m_axi_rmem4_RDATA),
+    .m00_axi_rid(m_axi_rmem4_RID),
+    .m00_axi_rlast(m_axi_rmem4_RLAST),
+    .m00_axi_rready(m_axi_rmem4_RREADY),
+    .m00_axi_rresp(m_axi_rmem4_RRESP),
+    .m00_axi_rvalid(m_axi_rmem4_RVALID),
+    .m00_axi_wdata(m_axi_rmem4_WDATA),
+    .m00_axi_wlast(m_axi_rmem4_WLAST),
+    .m00_axi_wready(m_axi_rmem4_WREADY),
+    .m00_axi_wstrb(m_axi_rmem4_WSTRB),
+    .m00_axi_wvalid(m_axi_rmem4_WVALID),
+    .s00_axi_araddr(m_axi_rmem4___Mmap2Stream_4___mmap_ARADDR),
+    .s00_axi_arburst(m_axi_rmem4___Mmap2Stream_4___mmap_ARBURST),
+    .s00_axi_arcache(m_axi_rmem4___Mmap2Stream_4___mmap_ARCACHE),
+    .s00_axi_arid(m_axi_rmem4___Mmap2Stream_4___mmap_ARID),
+    .s00_axi_arlen(m_axi_rmem4___Mmap2Stream_4___mmap_ARLEN),
+    .s00_axi_arlock(m_axi_rmem4___Mmap2Stream_4___mmap_ARLOCK),
+    .s00_axi_arprot(m_axi_rmem4___Mmap2Stream_4___mmap_ARPROT),
+    .s00_axi_arqos(m_axi_rmem4___Mmap2Stream_4___mmap_ARQOS),
+    .s00_axi_arready(m_axi_rmem4___Mmap2Stream_4___mmap_ARREADY),
+    .s00_axi_arsize(m_axi_rmem4___Mmap2Stream_4___mmap_ARSIZE),
+    .s00_axi_arvalid(m_axi_rmem4___Mmap2Stream_4___mmap_ARVALID),
+    .s00_axi_awaddr(m_axi_rmem4___Mmap2Stream_4___mmap_AWADDR),
+    .s00_axi_awburst(m_axi_rmem4___Mmap2Stream_4___mmap_AWBURST),
+    .s00_axi_awcache(m_axi_rmem4___Mmap2Stream_4___mmap_AWCACHE),
+    .s00_axi_awid(m_axi_rmem4___Mmap2Stream_4___mmap_AWID),
+    .s00_axi_awlen(m_axi_rmem4___Mmap2Stream_4___mmap_AWLEN),
+    .s00_axi_awlock(m_axi_rmem4___Mmap2Stream_4___mmap_AWLOCK),
+    .s00_axi_awprot(m_axi_rmem4___Mmap2Stream_4___mmap_AWPROT),
+    .s00_axi_awqos(m_axi_rmem4___Mmap2Stream_4___mmap_AWQOS),
+    .s00_axi_awready(m_axi_rmem4___Mmap2Stream_4___mmap_AWREADY),
+    .s00_axi_awsize(m_axi_rmem4___Mmap2Stream_4___mmap_AWSIZE),
+    .s00_axi_awvalid(m_axi_rmem4___Mmap2Stream_4___mmap_AWVALID),
+    .s00_axi_bid(m_axi_rmem4___Mmap2Stream_4___mmap_BID),
+    .s00_axi_bready(m_axi_rmem4___Mmap2Stream_4___mmap_BREADY),
+    .s00_axi_bresp(m_axi_rmem4___Mmap2Stream_4___mmap_BRESP),
+    .s00_axi_bvalid(m_axi_rmem4___Mmap2Stream_4___mmap_BVALID),
+    .s00_axi_rdata(m_axi_rmem4___Mmap2Stream_4___mmap_RDATA),
+    .s00_axi_rid(m_axi_rmem4___Mmap2Stream_4___mmap_RID),
+    .s00_axi_rlast(m_axi_rmem4___Mmap2Stream_4___mmap_RLAST),
+    .s00_axi_rready(m_axi_rmem4___Mmap2Stream_4___mmap_RREADY),
+    .s00_axi_rresp(m_axi_rmem4___Mmap2Stream_4___mmap_RRESP),
+    .s00_axi_rvalid(m_axi_rmem4___Mmap2Stream_4___mmap_RVALID),
+    .s00_axi_wdata(m_axi_rmem4___Mmap2Stream_4___mmap_WDATA),
+    .s00_axi_wlast(m_axi_rmem4___Mmap2Stream_4___mmap_WLAST),
+    .s00_axi_wready(m_axi_rmem4___Mmap2Stream_4___mmap_WREADY),
+    .s00_axi_wstrb(m_axi_rmem4___Mmap2Stream_4___mmap_WSTRB),
+    .s00_axi_wvalid(m_axi_rmem4___Mmap2Stream_4___mmap_WVALID),
+    .s01_axi_araddr(m_axi_rmem4___Stream2Mmap_4___mmap_ARADDR),
+    .s01_axi_arburst(m_axi_rmem4___Stream2Mmap_4___mmap_ARBURST),
+    .s01_axi_arcache(m_axi_rmem4___Stream2Mmap_4___mmap_ARCACHE),
+    .s01_axi_arid(m_axi_rmem4___Stream2Mmap_4___mmap_ARID),
+    .s01_axi_arlen(m_axi_rmem4___Stream2Mmap_4___mmap_ARLEN),
+    .s01_axi_arlock(m_axi_rmem4___Stream2Mmap_4___mmap_ARLOCK),
+    .s01_axi_arprot(m_axi_rmem4___Stream2Mmap_4___mmap_ARPROT),
+    .s01_axi_arqos(m_axi_rmem4___Stream2Mmap_4___mmap_ARQOS),
+    .s01_axi_arready(m_axi_rmem4___Stream2Mmap_4___mmap_ARREADY),
+    .s01_axi_arsize(m_axi_rmem4___Stream2Mmap_4___mmap_ARSIZE),
+    .s01_axi_arvalid(m_axi_rmem4___Stream2Mmap_4___mmap_ARVALID),
+    .s01_axi_awaddr(m_axi_rmem4___Stream2Mmap_4___mmap_AWADDR),
+    .s01_axi_awburst(m_axi_rmem4___Stream2Mmap_4___mmap_AWBURST),
+    .s01_axi_awcache(m_axi_rmem4___Stream2Mmap_4___mmap_AWCACHE),
+    .s01_axi_awid(m_axi_rmem4___Stream2Mmap_4___mmap_AWID),
+    .s01_axi_awlen(m_axi_rmem4___Stream2Mmap_4___mmap_AWLEN),
+    .s01_axi_awlock(m_axi_rmem4___Stream2Mmap_4___mmap_AWLOCK),
+    .s01_axi_awprot(m_axi_rmem4___Stream2Mmap_4___mmap_AWPROT),
+    .s01_axi_awqos(m_axi_rmem4___Stream2Mmap_4___mmap_AWQOS),
+    .s01_axi_awready(m_axi_rmem4___Stream2Mmap_4___mmap_AWREADY),
+    .s01_axi_awsize(m_axi_rmem4___Stream2Mmap_4___mmap_AWSIZE),
+    .s01_axi_awvalid(m_axi_rmem4___Stream2Mmap_4___mmap_AWVALID),
+    .s01_axi_bid(m_axi_rmem4___Stream2Mmap_4___mmap_BID),
+    .s01_axi_bready(m_axi_rmem4___Stream2Mmap_4___mmap_BREADY),
+    .s01_axi_bresp(m_axi_rmem4___Stream2Mmap_4___mmap_BRESP),
+    .s01_axi_bvalid(m_axi_rmem4___Stream2Mmap_4___mmap_BVALID),
+    .s01_axi_rdata(m_axi_rmem4___Stream2Mmap_4___mmap_RDATA),
+    .s01_axi_rid(m_axi_rmem4___Stream2Mmap_4___mmap_RID),
+    .s01_axi_rlast(m_axi_rmem4___Stream2Mmap_4___mmap_RLAST),
+    .s01_axi_rready(m_axi_rmem4___Stream2Mmap_4___mmap_RREADY),
+    .s01_axi_rresp(m_axi_rmem4___Stream2Mmap_4___mmap_RRESP),
+    .s01_axi_rvalid(m_axi_rmem4___Stream2Mmap_4___mmap_RVALID),
+    .s01_axi_wdata(m_axi_rmem4___Stream2Mmap_4___mmap_WDATA),
+    .s01_axi_wlast(m_axi_rmem4___Stream2Mmap_4___mmap_WLAST),
+    .s01_axi_wready(m_axi_rmem4___Stream2Mmap_4___mmap_WREADY),
+    .s01_axi_wstrb(m_axi_rmem4___Stream2Mmap_4___mmap_WSTRB),
+    .s01_axi_wvalid(m_axi_rmem4___Stream2Mmap_4___mmap_WVALID)
+  );
+
+
+  (* keep_hierarchy = "yes" *) axi_crossbar_2x1
+  #(
+    .DATA_WIDTH(512),
+    .ADDR_WIDTH(64),
+    .S_ID_WIDTH(1),
+    .M_ID_WIDTH(2),
+    .M00_ADDR_WIDTH(64),
+    .M00_ISSUE(16),
+    .S00_THREADS(1),
+    .S01_THREADS(1)
+  )
+  axi_crossbar_2x1__rmem5
+  (
+    .clk(ap_clk),
+    .rst(ap_rst_n_inv),
+    .m00_axi_araddr(m_axi_rmem5_ARADDR),
+    .m00_axi_arburst(m_axi_rmem5_ARBURST),
+    .m00_axi_arcache(m_axi_rmem5_ARCACHE),
+    .m00_axi_arid(m_axi_rmem5_ARID),
+    .m00_axi_arlen(m_axi_rmem5_ARLEN),
+    .m00_axi_arlock(m_axi_rmem5_ARLOCK),
+    .m00_axi_arprot(m_axi_rmem5_ARPROT),
+    .m00_axi_arqos(m_axi_rmem5_ARQOS),
+    .m00_axi_arready(m_axi_rmem5_ARREADY),
+    .m00_axi_arsize(m_axi_rmem5_ARSIZE),
+    .m00_axi_arvalid(m_axi_rmem5_ARVALID),
+    .m00_axi_awaddr(m_axi_rmem5_AWADDR),
+    .m00_axi_awburst(m_axi_rmem5_AWBURST),
+    .m00_axi_awcache(m_axi_rmem5_AWCACHE),
+    .m00_axi_awid(m_axi_rmem5_AWID),
+    .m00_axi_awlen(m_axi_rmem5_AWLEN),
+    .m00_axi_awlock(m_axi_rmem5_AWLOCK),
+    .m00_axi_awprot(m_axi_rmem5_AWPROT),
+    .m00_axi_awqos(m_axi_rmem5_AWQOS),
+    .m00_axi_awready(m_axi_rmem5_AWREADY),
+    .m00_axi_awsize(m_axi_rmem5_AWSIZE),
+    .m00_axi_awvalid(m_axi_rmem5_AWVALID),
+    .m00_axi_bid(m_axi_rmem5_BID),
+    .m00_axi_bready(m_axi_rmem5_BREADY),
+    .m00_axi_bresp(m_axi_rmem5_BRESP),
+    .m00_axi_bvalid(m_axi_rmem5_BVALID),
+    .m00_axi_rdata(m_axi_rmem5_RDATA),
+    .m00_axi_rid(m_axi_rmem5_RID),
+    .m00_axi_rlast(m_axi_rmem5_RLAST),
+    .m00_axi_rready(m_axi_rmem5_RREADY),
+    .m00_axi_rresp(m_axi_rmem5_RRESP),
+    .m00_axi_rvalid(m_axi_rmem5_RVALID),
+    .m00_axi_wdata(m_axi_rmem5_WDATA),
+    .m00_axi_wlast(m_axi_rmem5_WLAST),
+    .m00_axi_wready(m_axi_rmem5_WREADY),
+    .m00_axi_wstrb(m_axi_rmem5_WSTRB),
+    .m00_axi_wvalid(m_axi_rmem5_WVALID),
+    .s00_axi_araddr(m_axi_rmem5___Mmap2Stream_5___mmap_ARADDR),
+    .s00_axi_arburst(m_axi_rmem5___Mmap2Stream_5___mmap_ARBURST),
+    .s00_axi_arcache(m_axi_rmem5___Mmap2Stream_5___mmap_ARCACHE),
+    .s00_axi_arid(m_axi_rmem5___Mmap2Stream_5___mmap_ARID),
+    .s00_axi_arlen(m_axi_rmem5___Mmap2Stream_5___mmap_ARLEN),
+    .s00_axi_arlock(m_axi_rmem5___Mmap2Stream_5___mmap_ARLOCK),
+    .s00_axi_arprot(m_axi_rmem5___Mmap2Stream_5___mmap_ARPROT),
+    .s00_axi_arqos(m_axi_rmem5___Mmap2Stream_5___mmap_ARQOS),
+    .s00_axi_arready(m_axi_rmem5___Mmap2Stream_5___mmap_ARREADY),
+    .s00_axi_arsize(m_axi_rmem5___Mmap2Stream_5___mmap_ARSIZE),
+    .s00_axi_arvalid(m_axi_rmem5___Mmap2Stream_5___mmap_ARVALID),
+    .s00_axi_awaddr(m_axi_rmem5___Mmap2Stream_5___mmap_AWADDR),
+    .s00_axi_awburst(m_axi_rmem5___Mmap2Stream_5___mmap_AWBURST),
+    .s00_axi_awcache(m_axi_rmem5___Mmap2Stream_5___mmap_AWCACHE),
+    .s00_axi_awid(m_axi_rmem5___Mmap2Stream_5___mmap_AWID),
+    .s00_axi_awlen(m_axi_rmem5___Mmap2Stream_5___mmap_AWLEN),
+    .s00_axi_awlock(m_axi_rmem5___Mmap2Stream_5___mmap_AWLOCK),
+    .s00_axi_awprot(m_axi_rmem5___Mmap2Stream_5___mmap_AWPROT),
+    .s00_axi_awqos(m_axi_rmem5___Mmap2Stream_5___mmap_AWQOS),
+    .s00_axi_awready(m_axi_rmem5___Mmap2Stream_5___mmap_AWREADY),
+    .s00_axi_awsize(m_axi_rmem5___Mmap2Stream_5___mmap_AWSIZE),
+    .s00_axi_awvalid(m_axi_rmem5___Mmap2Stream_5___mmap_AWVALID),
+    .s00_axi_bid(m_axi_rmem5___Mmap2Stream_5___mmap_BID),
+    .s00_axi_bready(m_axi_rmem5___Mmap2Stream_5___mmap_BREADY),
+    .s00_axi_bresp(m_axi_rmem5___Mmap2Stream_5___mmap_BRESP),
+    .s00_axi_bvalid(m_axi_rmem5___Mmap2Stream_5___mmap_BVALID),
+    .s00_axi_rdata(m_axi_rmem5___Mmap2Stream_5___mmap_RDATA),
+    .s00_axi_rid(m_axi_rmem5___Mmap2Stream_5___mmap_RID),
+    .s00_axi_rlast(m_axi_rmem5___Mmap2Stream_5___mmap_RLAST),
+    .s00_axi_rready(m_axi_rmem5___Mmap2Stream_5___mmap_RREADY),
+    .s00_axi_rresp(m_axi_rmem5___Mmap2Stream_5___mmap_RRESP),
+    .s00_axi_rvalid(m_axi_rmem5___Mmap2Stream_5___mmap_RVALID),
+    .s00_axi_wdata(m_axi_rmem5___Mmap2Stream_5___mmap_WDATA),
+    .s00_axi_wlast(m_axi_rmem5___Mmap2Stream_5___mmap_WLAST),
+    .s00_axi_wready(m_axi_rmem5___Mmap2Stream_5___mmap_WREADY),
+    .s00_axi_wstrb(m_axi_rmem5___Mmap2Stream_5___mmap_WSTRB),
+    .s00_axi_wvalid(m_axi_rmem5___Mmap2Stream_5___mmap_WVALID),
+    .s01_axi_araddr(m_axi_rmem5___Stream2Mmap_5___mmap_ARADDR),
+    .s01_axi_arburst(m_axi_rmem5___Stream2Mmap_5___mmap_ARBURST),
+    .s01_axi_arcache(m_axi_rmem5___Stream2Mmap_5___mmap_ARCACHE),
+    .s01_axi_arid(m_axi_rmem5___Stream2Mmap_5___mmap_ARID),
+    .s01_axi_arlen(m_axi_rmem5___Stream2Mmap_5___mmap_ARLEN),
+    .s01_axi_arlock(m_axi_rmem5___Stream2Mmap_5___mmap_ARLOCK),
+    .s01_axi_arprot(m_axi_rmem5___Stream2Mmap_5___mmap_ARPROT),
+    .s01_axi_arqos(m_axi_rmem5___Stream2Mmap_5___mmap_ARQOS),
+    .s01_axi_arready(m_axi_rmem5___Stream2Mmap_5___mmap_ARREADY),
+    .s01_axi_arsize(m_axi_rmem5___Stream2Mmap_5___mmap_ARSIZE),
+    .s01_axi_arvalid(m_axi_rmem5___Stream2Mmap_5___mmap_ARVALID),
+    .s01_axi_awaddr(m_axi_rmem5___Stream2Mmap_5___mmap_AWADDR),
+    .s01_axi_awburst(m_axi_rmem5___Stream2Mmap_5___mmap_AWBURST),
+    .s01_axi_awcache(m_axi_rmem5___Stream2Mmap_5___mmap_AWCACHE),
+    .s01_axi_awid(m_axi_rmem5___Stream2Mmap_5___mmap_AWID),
+    .s01_axi_awlen(m_axi_rmem5___Stream2Mmap_5___mmap_AWLEN),
+    .s01_axi_awlock(m_axi_rmem5___Stream2Mmap_5___mmap_AWLOCK),
+    .s01_axi_awprot(m_axi_rmem5___Stream2Mmap_5___mmap_AWPROT),
+    .s01_axi_awqos(m_axi_rmem5___Stream2Mmap_5___mmap_AWQOS),
+    .s01_axi_awready(m_axi_rmem5___Stream2Mmap_5___mmap_AWREADY),
+    .s01_axi_awsize(m_axi_rmem5___Stream2Mmap_5___mmap_AWSIZE),
+    .s01_axi_awvalid(m_axi_rmem5___Stream2Mmap_5___mmap_AWVALID),
+    .s01_axi_bid(m_axi_rmem5___Stream2Mmap_5___mmap_BID),
+    .s01_axi_bready(m_axi_rmem5___Stream2Mmap_5___mmap_BREADY),
+    .s01_axi_bresp(m_axi_rmem5___Stream2Mmap_5___mmap_BRESP),
+    .s01_axi_bvalid(m_axi_rmem5___Stream2Mmap_5___mmap_BVALID),
+    .s01_axi_rdata(m_axi_rmem5___Stream2Mmap_5___mmap_RDATA),
+    .s01_axi_rid(m_axi_rmem5___Stream2Mmap_5___mmap_RID),
+    .s01_axi_rlast(m_axi_rmem5___Stream2Mmap_5___mmap_RLAST),
+    .s01_axi_rready(m_axi_rmem5___Stream2Mmap_5___mmap_RREADY),
+    .s01_axi_rresp(m_axi_rmem5___Stream2Mmap_5___mmap_RRESP),
+    .s01_axi_rvalid(m_axi_rmem5___Stream2Mmap_5___mmap_RVALID),
+    .s01_axi_wdata(m_axi_rmem5___Stream2Mmap_5___mmap_WDATA),
+    .s01_axi_wlast(m_axi_rmem5___Stream2Mmap_5___mmap_WLAST),
+    .s01_axi_wready(m_axi_rmem5___Stream2Mmap_5___mmap_WREADY),
+    .s01_axi_wstrb(m_axi_rmem5___Stream2Mmap_5___mmap_WSTRB),
+    .s01_axi_wvalid(m_axi_rmem5___Stream2Mmap_5___mmap_WVALID)
+  );
+
+
+  (* keep_hierarchy = "yes" *) axi_crossbar_2x1
+  #(
+    .DATA_WIDTH(512),
+    .ADDR_WIDTH(64),
+    .S_ID_WIDTH(1),
+    .M_ID_WIDTH(2),
+    .M00_ADDR_WIDTH(64),
+    .M00_ISSUE(16),
+    .S00_THREADS(1),
+    .S01_THREADS(1)
+  )
+  axi_crossbar_2x1__rmem6
+  (
+    .clk(ap_clk),
+    .rst(ap_rst_n_inv),
+    .m00_axi_araddr(m_axi_rmem6_ARADDR),
+    .m00_axi_arburst(m_axi_rmem6_ARBURST),
+    .m00_axi_arcache(m_axi_rmem6_ARCACHE),
+    .m00_axi_arid(m_axi_rmem6_ARID),
+    .m00_axi_arlen(m_axi_rmem6_ARLEN),
+    .m00_axi_arlock(m_axi_rmem6_ARLOCK),
+    .m00_axi_arprot(m_axi_rmem6_ARPROT),
+    .m00_axi_arqos(m_axi_rmem6_ARQOS),
+    .m00_axi_arready(m_axi_rmem6_ARREADY),
+    .m00_axi_arsize(m_axi_rmem6_ARSIZE),
+    .m00_axi_arvalid(m_axi_rmem6_ARVALID),
+    .m00_axi_awaddr(m_axi_rmem6_AWADDR),
+    .m00_axi_awburst(m_axi_rmem6_AWBURST),
+    .m00_axi_awcache(m_axi_rmem6_AWCACHE),
+    .m00_axi_awid(m_axi_rmem6_AWID),
+    .m00_axi_awlen(m_axi_rmem6_AWLEN),
+    .m00_axi_awlock(m_axi_rmem6_AWLOCK),
+    .m00_axi_awprot(m_axi_rmem6_AWPROT),
+    .m00_axi_awqos(m_axi_rmem6_AWQOS),
+    .m00_axi_awready(m_axi_rmem6_AWREADY),
+    .m00_axi_awsize(m_axi_rmem6_AWSIZE),
+    .m00_axi_awvalid(m_axi_rmem6_AWVALID),
+    .m00_axi_bid(m_axi_rmem6_BID),
+    .m00_axi_bready(m_axi_rmem6_BREADY),
+    .m00_axi_bresp(m_axi_rmem6_BRESP),
+    .m00_axi_bvalid(m_axi_rmem6_BVALID),
+    .m00_axi_rdata(m_axi_rmem6_RDATA),
+    .m00_axi_rid(m_axi_rmem6_RID),
+    .m00_axi_rlast(m_axi_rmem6_RLAST),
+    .m00_axi_rready(m_axi_rmem6_RREADY),
+    .m00_axi_rresp(m_axi_rmem6_RRESP),
+    .m00_axi_rvalid(m_axi_rmem6_RVALID),
+    .m00_axi_wdata(m_axi_rmem6_WDATA),
+    .m00_axi_wlast(m_axi_rmem6_WLAST),
+    .m00_axi_wready(m_axi_rmem6_WREADY),
+    .m00_axi_wstrb(m_axi_rmem6_WSTRB),
+    .m00_axi_wvalid(m_axi_rmem6_WVALID),
+    .s00_axi_araddr(m_axi_rmem6___Mmap2Stream_6___mmap_ARADDR),
+    .s00_axi_arburst(m_axi_rmem6___Mmap2Stream_6___mmap_ARBURST),
+    .s00_axi_arcache(m_axi_rmem6___Mmap2Stream_6___mmap_ARCACHE),
+    .s00_axi_arid(m_axi_rmem6___Mmap2Stream_6___mmap_ARID),
+    .s00_axi_arlen(m_axi_rmem6___Mmap2Stream_6___mmap_ARLEN),
+    .s00_axi_arlock(m_axi_rmem6___Mmap2Stream_6___mmap_ARLOCK),
+    .s00_axi_arprot(m_axi_rmem6___Mmap2Stream_6___mmap_ARPROT),
+    .s00_axi_arqos(m_axi_rmem6___Mmap2Stream_6___mmap_ARQOS),
+    .s00_axi_arready(m_axi_rmem6___Mmap2Stream_6___mmap_ARREADY),
+    .s00_axi_arsize(m_axi_rmem6___Mmap2Stream_6___mmap_ARSIZE),
+    .s00_axi_arvalid(m_axi_rmem6___Mmap2Stream_6___mmap_ARVALID),
+    .s00_axi_awaddr(m_axi_rmem6___Mmap2Stream_6___mmap_AWADDR),
+    .s00_axi_awburst(m_axi_rmem6___Mmap2Stream_6___mmap_AWBURST),
+    .s00_axi_awcache(m_axi_rmem6___Mmap2Stream_6___mmap_AWCACHE),
+    .s00_axi_awid(m_axi_rmem6___Mmap2Stream_6___mmap_AWID),
+    .s00_axi_awlen(m_axi_rmem6___Mmap2Stream_6___mmap_AWLEN),
+    .s00_axi_awlock(m_axi_rmem6___Mmap2Stream_6___mmap_AWLOCK),
+    .s00_axi_awprot(m_axi_rmem6___Mmap2Stream_6___mmap_AWPROT),
+    .s00_axi_awqos(m_axi_rmem6___Mmap2Stream_6___mmap_AWQOS),
+    .s00_axi_awready(m_axi_rmem6___Mmap2Stream_6___mmap_AWREADY),
+    .s00_axi_awsize(m_axi_rmem6___Mmap2Stream_6___mmap_AWSIZE),
+    .s00_axi_awvalid(m_axi_rmem6___Mmap2Stream_6___mmap_AWVALID),
+    .s00_axi_bid(m_axi_rmem6___Mmap2Stream_6___mmap_BID),
+    .s00_axi_bready(m_axi_rmem6___Mmap2Stream_6___mmap_BREADY),
+    .s00_axi_bresp(m_axi_rmem6___Mmap2Stream_6___mmap_BRESP),
+    .s00_axi_bvalid(m_axi_rmem6___Mmap2Stream_6___mmap_BVALID),
+    .s00_axi_rdata(m_axi_rmem6___Mmap2Stream_6___mmap_RDATA),
+    .s00_axi_rid(m_axi_rmem6___Mmap2Stream_6___mmap_RID),
+    .s00_axi_rlast(m_axi_rmem6___Mmap2Stream_6___mmap_RLAST),
+    .s00_axi_rready(m_axi_rmem6___Mmap2Stream_6___mmap_RREADY),
+    .s00_axi_rresp(m_axi_rmem6___Mmap2Stream_6___mmap_RRESP),
+    .s00_axi_rvalid(m_axi_rmem6___Mmap2Stream_6___mmap_RVALID),
+    .s00_axi_wdata(m_axi_rmem6___Mmap2Stream_6___mmap_WDATA),
+    .s00_axi_wlast(m_axi_rmem6___Mmap2Stream_6___mmap_WLAST),
+    .s00_axi_wready(m_axi_rmem6___Mmap2Stream_6___mmap_WREADY),
+    .s00_axi_wstrb(m_axi_rmem6___Mmap2Stream_6___mmap_WSTRB),
+    .s00_axi_wvalid(m_axi_rmem6___Mmap2Stream_6___mmap_WVALID),
+    .s01_axi_araddr(m_axi_rmem6___Stream2Mmap_6___mmap_ARADDR),
+    .s01_axi_arburst(m_axi_rmem6___Stream2Mmap_6___mmap_ARBURST),
+    .s01_axi_arcache(m_axi_rmem6___Stream2Mmap_6___mmap_ARCACHE),
+    .s01_axi_arid(m_axi_rmem6___Stream2Mmap_6___mmap_ARID),
+    .s01_axi_arlen(m_axi_rmem6___Stream2Mmap_6___mmap_ARLEN),
+    .s01_axi_arlock(m_axi_rmem6___Stream2Mmap_6___mmap_ARLOCK),
+    .s01_axi_arprot(m_axi_rmem6___Stream2Mmap_6___mmap_ARPROT),
+    .s01_axi_arqos(m_axi_rmem6___Stream2Mmap_6___mmap_ARQOS),
+    .s01_axi_arready(m_axi_rmem6___Stream2Mmap_6___mmap_ARREADY),
+    .s01_axi_arsize(m_axi_rmem6___Stream2Mmap_6___mmap_ARSIZE),
+    .s01_axi_arvalid(m_axi_rmem6___Stream2Mmap_6___mmap_ARVALID),
+    .s01_axi_awaddr(m_axi_rmem6___Stream2Mmap_6___mmap_AWADDR),
+    .s01_axi_awburst(m_axi_rmem6___Stream2Mmap_6___mmap_AWBURST),
+    .s01_axi_awcache(m_axi_rmem6___Stream2Mmap_6___mmap_AWCACHE),
+    .s01_axi_awid(m_axi_rmem6___Stream2Mmap_6___mmap_AWID),
+    .s01_axi_awlen(m_axi_rmem6___Stream2Mmap_6___mmap_AWLEN),
+    .s01_axi_awlock(m_axi_rmem6___Stream2Mmap_6___mmap_AWLOCK),
+    .s01_axi_awprot(m_axi_rmem6___Stream2Mmap_6___mmap_AWPROT),
+    .s01_axi_awqos(m_axi_rmem6___Stream2Mmap_6___mmap_AWQOS),
+    .s01_axi_awready(m_axi_rmem6___Stream2Mmap_6___mmap_AWREADY),
+    .s01_axi_awsize(m_axi_rmem6___Stream2Mmap_6___mmap_AWSIZE),
+    .s01_axi_awvalid(m_axi_rmem6___Stream2Mmap_6___mmap_AWVALID),
+    .s01_axi_bid(m_axi_rmem6___Stream2Mmap_6___mmap_BID),
+    .s01_axi_bready(m_axi_rmem6___Stream2Mmap_6___mmap_BREADY),
+    .s01_axi_bresp(m_axi_rmem6___Stream2Mmap_6___mmap_BRESP),
+    .s01_axi_bvalid(m_axi_rmem6___Stream2Mmap_6___mmap_BVALID),
+    .s01_axi_rdata(m_axi_rmem6___Stream2Mmap_6___mmap_RDATA),
+    .s01_axi_rid(m_axi_rmem6___Stream2Mmap_6___mmap_RID),
+    .s01_axi_rlast(m_axi_rmem6___Stream2Mmap_6___mmap_RLAST),
+    .s01_axi_rready(m_axi_rmem6___Stream2Mmap_6___mmap_RREADY),
+    .s01_axi_rresp(m_axi_rmem6___Stream2Mmap_6___mmap_RRESP),
+    .s01_axi_rvalid(m_axi_rmem6___Stream2Mmap_6___mmap_RVALID),
+    .s01_axi_wdata(m_axi_rmem6___Stream2Mmap_6___mmap_WDATA),
+    .s01_axi_wlast(m_axi_rmem6___Stream2Mmap_6___mmap_WLAST),
+    .s01_axi_wready(m_axi_rmem6___Stream2Mmap_6___mmap_WREADY),
+    .s01_axi_wstrb(m_axi_rmem6___Stream2Mmap_6___mmap_WSTRB),
+    .s01_axi_wvalid(m_axi_rmem6___Stream2Mmap_6___mmap_WVALID)
+  );
+
+
+  (* keep_hierarchy = "yes" *) axi_crossbar_2x1
+  #(
+    .DATA_WIDTH(512),
+    .ADDR_WIDTH(64),
+    .S_ID_WIDTH(1),
+    .M_ID_WIDTH(2),
+    .M00_ADDR_WIDTH(64),
+    .M00_ISSUE(16),
+    .S00_THREADS(1),
+    .S01_THREADS(1)
+  )
+  axi_crossbar_2x1__rmem7
+  (
+    .clk(ap_clk),
+    .rst(ap_rst_n_inv),
+    .m00_axi_araddr(m_axi_rmem7_ARADDR),
+    .m00_axi_arburst(m_axi_rmem7_ARBURST),
+    .m00_axi_arcache(m_axi_rmem7_ARCACHE),
+    .m00_axi_arid(m_axi_rmem7_ARID),
+    .m00_axi_arlen(m_axi_rmem7_ARLEN),
+    .m00_axi_arlock(m_axi_rmem7_ARLOCK),
+    .m00_axi_arprot(m_axi_rmem7_ARPROT),
+    .m00_axi_arqos(m_axi_rmem7_ARQOS),
+    .m00_axi_arready(m_axi_rmem7_ARREADY),
+    .m00_axi_arsize(m_axi_rmem7_ARSIZE),
+    .m00_axi_arvalid(m_axi_rmem7_ARVALID),
+    .m00_axi_awaddr(m_axi_rmem7_AWADDR),
+    .m00_axi_awburst(m_axi_rmem7_AWBURST),
+    .m00_axi_awcache(m_axi_rmem7_AWCACHE),
+    .m00_axi_awid(m_axi_rmem7_AWID),
+    .m00_axi_awlen(m_axi_rmem7_AWLEN),
+    .m00_axi_awlock(m_axi_rmem7_AWLOCK),
+    .m00_axi_awprot(m_axi_rmem7_AWPROT),
+    .m00_axi_awqos(m_axi_rmem7_AWQOS),
+    .m00_axi_awready(m_axi_rmem7_AWREADY),
+    .m00_axi_awsize(m_axi_rmem7_AWSIZE),
+    .m00_axi_awvalid(m_axi_rmem7_AWVALID),
+    .m00_axi_bid(m_axi_rmem7_BID),
+    .m00_axi_bready(m_axi_rmem7_BREADY),
+    .m00_axi_bresp(m_axi_rmem7_BRESP),
+    .m00_axi_bvalid(m_axi_rmem7_BVALID),
+    .m00_axi_rdata(m_axi_rmem7_RDATA),
+    .m00_axi_rid(m_axi_rmem7_RID),
+    .m00_axi_rlast(m_axi_rmem7_RLAST),
+    .m00_axi_rready(m_axi_rmem7_RREADY),
+    .m00_axi_rresp(m_axi_rmem7_RRESP),
+    .m00_axi_rvalid(m_axi_rmem7_RVALID),
+    .m00_axi_wdata(m_axi_rmem7_WDATA),
+    .m00_axi_wlast(m_axi_rmem7_WLAST),
+    .m00_axi_wready(m_axi_rmem7_WREADY),
+    .m00_axi_wstrb(m_axi_rmem7_WSTRB),
+    .m00_axi_wvalid(m_axi_rmem7_WVALID),
+    .s00_axi_araddr(m_axi_rmem7___Mmap2Stream_7___mmap_ARADDR),
+    .s00_axi_arburst(m_axi_rmem7___Mmap2Stream_7___mmap_ARBURST),
+    .s00_axi_arcache(m_axi_rmem7___Mmap2Stream_7___mmap_ARCACHE),
+    .s00_axi_arid(m_axi_rmem7___Mmap2Stream_7___mmap_ARID),
+    .s00_axi_arlen(m_axi_rmem7___Mmap2Stream_7___mmap_ARLEN),
+    .s00_axi_arlock(m_axi_rmem7___Mmap2Stream_7___mmap_ARLOCK),
+    .s00_axi_arprot(m_axi_rmem7___Mmap2Stream_7___mmap_ARPROT),
+    .s00_axi_arqos(m_axi_rmem7___Mmap2Stream_7___mmap_ARQOS),
+    .s00_axi_arready(m_axi_rmem7___Mmap2Stream_7___mmap_ARREADY),
+    .s00_axi_arsize(m_axi_rmem7___Mmap2Stream_7___mmap_ARSIZE),
+    .s00_axi_arvalid(m_axi_rmem7___Mmap2Stream_7___mmap_ARVALID),
+    .s00_axi_awaddr(m_axi_rmem7___Mmap2Stream_7___mmap_AWADDR),
+    .s00_axi_awburst(m_axi_rmem7___Mmap2Stream_7___mmap_AWBURST),
+    .s00_axi_awcache(m_axi_rmem7___Mmap2Stream_7___mmap_AWCACHE),
+    .s00_axi_awid(m_axi_rmem7___Mmap2Stream_7___mmap_AWID),
+    .s00_axi_awlen(m_axi_rmem7___Mmap2Stream_7___mmap_AWLEN),
+    .s00_axi_awlock(m_axi_rmem7___Mmap2Stream_7___mmap_AWLOCK),
+    .s00_axi_awprot(m_axi_rmem7___Mmap2Stream_7___mmap_AWPROT),
+    .s00_axi_awqos(m_axi_rmem7___Mmap2Stream_7___mmap_AWQOS),
+    .s00_axi_awready(m_axi_rmem7___Mmap2Stream_7___mmap_AWREADY),
+    .s00_axi_awsize(m_axi_rmem7___Mmap2Stream_7___mmap_AWSIZE),
+    .s00_axi_awvalid(m_axi_rmem7___Mmap2Stream_7___mmap_AWVALID),
+    .s00_axi_bid(m_axi_rmem7___Mmap2Stream_7___mmap_BID),
+    .s00_axi_bready(m_axi_rmem7___Mmap2Stream_7___mmap_BREADY),
+    .s00_axi_bresp(m_axi_rmem7___Mmap2Stream_7___mmap_BRESP),
+    .s00_axi_bvalid(m_axi_rmem7___Mmap2Stream_7___mmap_BVALID),
+    .s00_axi_rdata(m_axi_rmem7___Mmap2Stream_7___mmap_RDATA),
+    .s00_axi_rid(m_axi_rmem7___Mmap2Stream_7___mmap_RID),
+    .s00_axi_rlast(m_axi_rmem7___Mmap2Stream_7___mmap_RLAST),
+    .s00_axi_rready(m_axi_rmem7___Mmap2Stream_7___mmap_RREADY),
+    .s00_axi_rresp(m_axi_rmem7___Mmap2Stream_7___mmap_RRESP),
+    .s00_axi_rvalid(m_axi_rmem7___Mmap2Stream_7___mmap_RVALID),
+    .s00_axi_wdata(m_axi_rmem7___Mmap2Stream_7___mmap_WDATA),
+    .s00_axi_wlast(m_axi_rmem7___Mmap2Stream_7___mmap_WLAST),
+    .s00_axi_wready(m_axi_rmem7___Mmap2Stream_7___mmap_WREADY),
+    .s00_axi_wstrb(m_axi_rmem7___Mmap2Stream_7___mmap_WSTRB),
+    .s00_axi_wvalid(m_axi_rmem7___Mmap2Stream_7___mmap_WVALID),
+    .s01_axi_araddr(m_axi_rmem7___Stream2Mmap_7___mmap_ARADDR),
+    .s01_axi_arburst(m_axi_rmem7___Stream2Mmap_7___mmap_ARBURST),
+    .s01_axi_arcache(m_axi_rmem7___Stream2Mmap_7___mmap_ARCACHE),
+    .s01_axi_arid(m_axi_rmem7___Stream2Mmap_7___mmap_ARID),
+    .s01_axi_arlen(m_axi_rmem7___Stream2Mmap_7___mmap_ARLEN),
+    .s01_axi_arlock(m_axi_rmem7___Stream2Mmap_7___mmap_ARLOCK),
+    .s01_axi_arprot(m_axi_rmem7___Stream2Mmap_7___mmap_ARPROT),
+    .s01_axi_arqos(m_axi_rmem7___Stream2Mmap_7___mmap_ARQOS),
+    .s01_axi_arready(m_axi_rmem7___Stream2Mmap_7___mmap_ARREADY),
+    .s01_axi_arsize(m_axi_rmem7___Stream2Mmap_7___mmap_ARSIZE),
+    .s01_axi_arvalid(m_axi_rmem7___Stream2Mmap_7___mmap_ARVALID),
+    .s01_axi_awaddr(m_axi_rmem7___Stream2Mmap_7___mmap_AWADDR),
+    .s01_axi_awburst(m_axi_rmem7___Stream2Mmap_7___mmap_AWBURST),
+    .s01_axi_awcache(m_axi_rmem7___Stream2Mmap_7___mmap_AWCACHE),
+    .s01_axi_awid(m_axi_rmem7___Stream2Mmap_7___mmap_AWID),
+    .s01_axi_awlen(m_axi_rmem7___Stream2Mmap_7___mmap_AWLEN),
+    .s01_axi_awlock(m_axi_rmem7___Stream2Mmap_7___mmap_AWLOCK),
+    .s01_axi_awprot(m_axi_rmem7___Stream2Mmap_7___mmap_AWPROT),
+    .s01_axi_awqos(m_axi_rmem7___Stream2Mmap_7___mmap_AWQOS),
+    .s01_axi_awready(m_axi_rmem7___Stream2Mmap_7___mmap_AWREADY),
+    .s01_axi_awsize(m_axi_rmem7___Stream2Mmap_7___mmap_AWSIZE),
+    .s01_axi_awvalid(m_axi_rmem7___Stream2Mmap_7___mmap_AWVALID),
+    .s01_axi_bid(m_axi_rmem7___Stream2Mmap_7___mmap_BID),
+    .s01_axi_bready(m_axi_rmem7___Stream2Mmap_7___mmap_BREADY),
+    .s01_axi_bresp(m_axi_rmem7___Stream2Mmap_7___mmap_BRESP),
+    .s01_axi_bvalid(m_axi_rmem7___Stream2Mmap_7___mmap_BVALID),
+    .s01_axi_rdata(m_axi_rmem7___Stream2Mmap_7___mmap_RDATA),
+    .s01_axi_rid(m_axi_rmem7___Stream2Mmap_7___mmap_RID),
+    .s01_axi_rlast(m_axi_rmem7___Stream2Mmap_7___mmap_RLAST),
+    .s01_axi_rready(m_axi_rmem7___Stream2Mmap_7___mmap_RREADY),
+    .s01_axi_rresp(m_axi_rmem7___Stream2Mmap_7___mmap_RRESP),
+    .s01_axi_rvalid(m_axi_rmem7___Stream2Mmap_7___mmap_RVALID),
+    .s01_axi_wdata(m_axi_rmem7___Stream2Mmap_7___mmap_WDATA),
+    .s01_axi_wlast(m_axi_rmem7___Stream2Mmap_7___mmap_WLAST),
+    .s01_axi_wready(m_axi_rmem7___Stream2Mmap_7___mmap_WREADY),
+    .s01_axi_wstrb(m_axi_rmem7___Stream2Mmap_7___mmap_WSTRB),
+    .s01_axi_wvalid(m_axi_rmem7___Stream2Mmap_7___mmap_WVALID)
+  );
+
+
+  (* keep_hierarchy = "yes" *) axi_crossbar_2x1
+  #(
+    .DATA_WIDTH(512),
+    .ADDR_WIDTH(64),
+    .S_ID_WIDTH(1),
+    .M_ID_WIDTH(2),
+    .M00_ADDR_WIDTH(64),
+    .M00_ISSUE(16),
+    .S00_THREADS(1),
+    .S01_THREADS(1)
+  )
+  axi_crossbar_2x1__rmem8
+  (
+    .clk(ap_clk),
+    .rst(ap_rst_n_inv),
+    .m00_axi_araddr(m_axi_rmem8_ARADDR),
+    .m00_axi_arburst(m_axi_rmem8_ARBURST),
+    .m00_axi_arcache(m_axi_rmem8_ARCACHE),
+    .m00_axi_arid(m_axi_rmem8_ARID),
+    .m00_axi_arlen(m_axi_rmem8_ARLEN),
+    .m00_axi_arlock(m_axi_rmem8_ARLOCK),
+    .m00_axi_arprot(m_axi_rmem8_ARPROT),
+    .m00_axi_arqos(m_axi_rmem8_ARQOS),
+    .m00_axi_arready(m_axi_rmem8_ARREADY),
+    .m00_axi_arsize(m_axi_rmem8_ARSIZE),
+    .m00_axi_arvalid(m_axi_rmem8_ARVALID),
+    .m00_axi_awaddr(m_axi_rmem8_AWADDR),
+    .m00_axi_awburst(m_axi_rmem8_AWBURST),
+    .m00_axi_awcache(m_axi_rmem8_AWCACHE),
+    .m00_axi_awid(m_axi_rmem8_AWID),
+    .m00_axi_awlen(m_axi_rmem8_AWLEN),
+    .m00_axi_awlock(m_axi_rmem8_AWLOCK),
+    .m00_axi_awprot(m_axi_rmem8_AWPROT),
+    .m00_axi_awqos(m_axi_rmem8_AWQOS),
+    .m00_axi_awready(m_axi_rmem8_AWREADY),
+    .m00_axi_awsize(m_axi_rmem8_AWSIZE),
+    .m00_axi_awvalid(m_axi_rmem8_AWVALID),
+    .m00_axi_bid(m_axi_rmem8_BID),
+    .m00_axi_bready(m_axi_rmem8_BREADY),
+    .m00_axi_bresp(m_axi_rmem8_BRESP),
+    .m00_axi_bvalid(m_axi_rmem8_BVALID),
+    .m00_axi_rdata(m_axi_rmem8_RDATA),
+    .m00_axi_rid(m_axi_rmem8_RID),
+    .m00_axi_rlast(m_axi_rmem8_RLAST),
+    .m00_axi_rready(m_axi_rmem8_RREADY),
+    .m00_axi_rresp(m_axi_rmem8_RRESP),
+    .m00_axi_rvalid(m_axi_rmem8_RVALID),
+    .m00_axi_wdata(m_axi_rmem8_WDATA),
+    .m00_axi_wlast(m_axi_rmem8_WLAST),
+    .m00_axi_wready(m_axi_rmem8_WREADY),
+    .m00_axi_wstrb(m_axi_rmem8_WSTRB),
+    .m00_axi_wvalid(m_axi_rmem8_WVALID),
+    .s00_axi_araddr(m_axi_rmem8___Mmap2Stream_8___mmap_ARADDR),
+    .s00_axi_arburst(m_axi_rmem8___Mmap2Stream_8___mmap_ARBURST),
+    .s00_axi_arcache(m_axi_rmem8___Mmap2Stream_8___mmap_ARCACHE),
+    .s00_axi_arid(m_axi_rmem8___Mmap2Stream_8___mmap_ARID),
+    .s00_axi_arlen(m_axi_rmem8___Mmap2Stream_8___mmap_ARLEN),
+    .s00_axi_arlock(m_axi_rmem8___Mmap2Stream_8___mmap_ARLOCK),
+    .s00_axi_arprot(m_axi_rmem8___Mmap2Stream_8___mmap_ARPROT),
+    .s00_axi_arqos(m_axi_rmem8___Mmap2Stream_8___mmap_ARQOS),
+    .s00_axi_arready(m_axi_rmem8___Mmap2Stream_8___mmap_ARREADY),
+    .s00_axi_arsize(m_axi_rmem8___Mmap2Stream_8___mmap_ARSIZE),
+    .s00_axi_arvalid(m_axi_rmem8___Mmap2Stream_8___mmap_ARVALID),
+    .s00_axi_awaddr(m_axi_rmem8___Mmap2Stream_8___mmap_AWADDR),
+    .s00_axi_awburst(m_axi_rmem8___Mmap2Stream_8___mmap_AWBURST),
+    .s00_axi_awcache(m_axi_rmem8___Mmap2Stream_8___mmap_AWCACHE),
+    .s00_axi_awid(m_axi_rmem8___Mmap2Stream_8___mmap_AWID),
+    .s00_axi_awlen(m_axi_rmem8___Mmap2Stream_8___mmap_AWLEN),
+    .s00_axi_awlock(m_axi_rmem8___Mmap2Stream_8___mmap_AWLOCK),
+    .s00_axi_awprot(m_axi_rmem8___Mmap2Stream_8___mmap_AWPROT),
+    .s00_axi_awqos(m_axi_rmem8___Mmap2Stream_8___mmap_AWQOS),
+    .s00_axi_awready(m_axi_rmem8___Mmap2Stream_8___mmap_AWREADY),
+    .s00_axi_awsize(m_axi_rmem8___Mmap2Stream_8___mmap_AWSIZE),
+    .s00_axi_awvalid(m_axi_rmem8___Mmap2Stream_8___mmap_AWVALID),
+    .s00_axi_bid(m_axi_rmem8___Mmap2Stream_8___mmap_BID),
+    .s00_axi_bready(m_axi_rmem8___Mmap2Stream_8___mmap_BREADY),
+    .s00_axi_bresp(m_axi_rmem8___Mmap2Stream_8___mmap_BRESP),
+    .s00_axi_bvalid(m_axi_rmem8___Mmap2Stream_8___mmap_BVALID),
+    .s00_axi_rdata(m_axi_rmem8___Mmap2Stream_8___mmap_RDATA),
+    .s00_axi_rid(m_axi_rmem8___Mmap2Stream_8___mmap_RID),
+    .s00_axi_rlast(m_axi_rmem8___Mmap2Stream_8___mmap_RLAST),
+    .s00_axi_rready(m_axi_rmem8___Mmap2Stream_8___mmap_RREADY),
+    .s00_axi_rresp(m_axi_rmem8___Mmap2Stream_8___mmap_RRESP),
+    .s00_axi_rvalid(m_axi_rmem8___Mmap2Stream_8___mmap_RVALID),
+    .s00_axi_wdata(m_axi_rmem8___Mmap2Stream_8___mmap_WDATA),
+    .s00_axi_wlast(m_axi_rmem8___Mmap2Stream_8___mmap_WLAST),
+    .s00_axi_wready(m_axi_rmem8___Mmap2Stream_8___mmap_WREADY),
+    .s00_axi_wstrb(m_axi_rmem8___Mmap2Stream_8___mmap_WSTRB),
+    .s00_axi_wvalid(m_axi_rmem8___Mmap2Stream_8___mmap_WVALID),
+    .s01_axi_araddr(m_axi_rmem8___Stream2Mmap_8___mmap_ARADDR),
+    .s01_axi_arburst(m_axi_rmem8___Stream2Mmap_8___mmap_ARBURST),
+    .s01_axi_arcache(m_axi_rmem8___Stream2Mmap_8___mmap_ARCACHE),
+    .s01_axi_arid(m_axi_rmem8___Stream2Mmap_8___mmap_ARID),
+    .s01_axi_arlen(m_axi_rmem8___Stream2Mmap_8___mmap_ARLEN),
+    .s01_axi_arlock(m_axi_rmem8___Stream2Mmap_8___mmap_ARLOCK),
+    .s01_axi_arprot(m_axi_rmem8___Stream2Mmap_8___mmap_ARPROT),
+    .s01_axi_arqos(m_axi_rmem8___Stream2Mmap_8___mmap_ARQOS),
+    .s01_axi_arready(m_axi_rmem8___Stream2Mmap_8___mmap_ARREADY),
+    .s01_axi_arsize(m_axi_rmem8___Stream2Mmap_8___mmap_ARSIZE),
+    .s01_axi_arvalid(m_axi_rmem8___Stream2Mmap_8___mmap_ARVALID),
+    .s01_axi_awaddr(m_axi_rmem8___Stream2Mmap_8___mmap_AWADDR),
+    .s01_axi_awburst(m_axi_rmem8___Stream2Mmap_8___mmap_AWBURST),
+    .s01_axi_awcache(m_axi_rmem8___Stream2Mmap_8___mmap_AWCACHE),
+    .s01_axi_awid(m_axi_rmem8___Stream2Mmap_8___mmap_AWID),
+    .s01_axi_awlen(m_axi_rmem8___Stream2Mmap_8___mmap_AWLEN),
+    .s01_axi_awlock(m_axi_rmem8___Stream2Mmap_8___mmap_AWLOCK),
+    .s01_axi_awprot(m_axi_rmem8___Stream2Mmap_8___mmap_AWPROT),
+    .s01_axi_awqos(m_axi_rmem8___Stream2Mmap_8___mmap_AWQOS),
+    .s01_axi_awready(m_axi_rmem8___Stream2Mmap_8___mmap_AWREADY),
+    .s01_axi_awsize(m_axi_rmem8___Stream2Mmap_8___mmap_AWSIZE),
+    .s01_axi_awvalid(m_axi_rmem8___Stream2Mmap_8___mmap_AWVALID),
+    .s01_axi_bid(m_axi_rmem8___Stream2Mmap_8___mmap_BID),
+    .s01_axi_bready(m_axi_rmem8___Stream2Mmap_8___mmap_BREADY),
+    .s01_axi_bresp(m_axi_rmem8___Stream2Mmap_8___mmap_BRESP),
+    .s01_axi_bvalid(m_axi_rmem8___Stream2Mmap_8___mmap_BVALID),
+    .s01_axi_rdata(m_axi_rmem8___Stream2Mmap_8___mmap_RDATA),
+    .s01_axi_rid(m_axi_rmem8___Stream2Mmap_8___mmap_RID),
+    .s01_axi_rlast(m_axi_rmem8___Stream2Mmap_8___mmap_RLAST),
+    .s01_axi_rready(m_axi_rmem8___Stream2Mmap_8___mmap_RREADY),
+    .s01_axi_rresp(m_axi_rmem8___Stream2Mmap_8___mmap_RRESP),
+    .s01_axi_rvalid(m_axi_rmem8___Stream2Mmap_8___mmap_RVALID),
+    .s01_axi_wdata(m_axi_rmem8___Stream2Mmap_8___mmap_WDATA),
+    .s01_axi_wlast(m_axi_rmem8___Stream2Mmap_8___mmap_WLAST),
+    .s01_axi_wready(m_axi_rmem8___Stream2Mmap_8___mmap_WREADY),
+    .s01_axi_wstrb(m_axi_rmem8___Stream2Mmap_8___mmap_WSTRB),
+    .s01_axi_wvalid(m_axi_rmem8___Stream2Mmap_8___mmap_WVALID)
+  );
+
+
+  (* keep_hierarchy = "yes" *) axi_crossbar_2x1
+  #(
+    .DATA_WIDTH(512),
+    .ADDR_WIDTH(64),
+    .S_ID_WIDTH(1),
+    .M_ID_WIDTH(2),
+    .M00_ADDR_WIDTH(64),
+    .M00_ISSUE(16),
+    .S00_THREADS(1),
+    .S01_THREADS(1)
+  )
+  axi_crossbar_2x1__rmem9
+  (
+    .clk(ap_clk),
+    .rst(ap_rst_n_inv),
+    .m00_axi_araddr(m_axi_rmem9_ARADDR),
+    .m00_axi_arburst(m_axi_rmem9_ARBURST),
+    .m00_axi_arcache(m_axi_rmem9_ARCACHE),
+    .m00_axi_arid(m_axi_rmem9_ARID),
+    .m00_axi_arlen(m_axi_rmem9_ARLEN),
+    .m00_axi_arlock(m_axi_rmem9_ARLOCK),
+    .m00_axi_arprot(m_axi_rmem9_ARPROT),
+    .m00_axi_arqos(m_axi_rmem9_ARQOS),
+    .m00_axi_arready(m_axi_rmem9_ARREADY),
+    .m00_axi_arsize(m_axi_rmem9_ARSIZE),
+    .m00_axi_arvalid(m_axi_rmem9_ARVALID),
+    .m00_axi_awaddr(m_axi_rmem9_AWADDR),
+    .m00_axi_awburst(m_axi_rmem9_AWBURST),
+    .m00_axi_awcache(m_axi_rmem9_AWCACHE),
+    .m00_axi_awid(m_axi_rmem9_AWID),
+    .m00_axi_awlen(m_axi_rmem9_AWLEN),
+    .m00_axi_awlock(m_axi_rmem9_AWLOCK),
+    .m00_axi_awprot(m_axi_rmem9_AWPROT),
+    .m00_axi_awqos(m_axi_rmem9_AWQOS),
+    .m00_axi_awready(m_axi_rmem9_AWREADY),
+    .m00_axi_awsize(m_axi_rmem9_AWSIZE),
+    .m00_axi_awvalid(m_axi_rmem9_AWVALID),
+    .m00_axi_bid(m_axi_rmem9_BID),
+    .m00_axi_bready(m_axi_rmem9_BREADY),
+    .m00_axi_bresp(m_axi_rmem9_BRESP),
+    .m00_axi_bvalid(m_axi_rmem9_BVALID),
+    .m00_axi_rdata(m_axi_rmem9_RDATA),
+    .m00_axi_rid(m_axi_rmem9_RID),
+    .m00_axi_rlast(m_axi_rmem9_RLAST),
+    .m00_axi_rready(m_axi_rmem9_RREADY),
+    .m00_axi_rresp(m_axi_rmem9_RRESP),
+    .m00_axi_rvalid(m_axi_rmem9_RVALID),
+    .m00_axi_wdata(m_axi_rmem9_WDATA),
+    .m00_axi_wlast(m_axi_rmem9_WLAST),
+    .m00_axi_wready(m_axi_rmem9_WREADY),
+    .m00_axi_wstrb(m_axi_rmem9_WSTRB),
+    .m00_axi_wvalid(m_axi_rmem9_WVALID),
+    .s00_axi_araddr(m_axi_rmem9___Mmap2Stream_9___mmap_ARADDR),
+    .s00_axi_arburst(m_axi_rmem9___Mmap2Stream_9___mmap_ARBURST),
+    .s00_axi_arcache(m_axi_rmem9___Mmap2Stream_9___mmap_ARCACHE),
+    .s00_axi_arid(m_axi_rmem9___Mmap2Stream_9___mmap_ARID),
+    .s00_axi_arlen(m_axi_rmem9___Mmap2Stream_9___mmap_ARLEN),
+    .s00_axi_arlock(m_axi_rmem9___Mmap2Stream_9___mmap_ARLOCK),
+    .s00_axi_arprot(m_axi_rmem9___Mmap2Stream_9___mmap_ARPROT),
+    .s00_axi_arqos(m_axi_rmem9___Mmap2Stream_9___mmap_ARQOS),
+    .s00_axi_arready(m_axi_rmem9___Mmap2Stream_9___mmap_ARREADY),
+    .s00_axi_arsize(m_axi_rmem9___Mmap2Stream_9___mmap_ARSIZE),
+    .s00_axi_arvalid(m_axi_rmem9___Mmap2Stream_9___mmap_ARVALID),
+    .s00_axi_awaddr(m_axi_rmem9___Mmap2Stream_9___mmap_AWADDR),
+    .s00_axi_awburst(m_axi_rmem9___Mmap2Stream_9___mmap_AWBURST),
+    .s00_axi_awcache(m_axi_rmem9___Mmap2Stream_9___mmap_AWCACHE),
+    .s00_axi_awid(m_axi_rmem9___Mmap2Stream_9___mmap_AWID),
+    .s00_axi_awlen(m_axi_rmem9___Mmap2Stream_9___mmap_AWLEN),
+    .s00_axi_awlock(m_axi_rmem9___Mmap2Stream_9___mmap_AWLOCK),
+    .s00_axi_awprot(m_axi_rmem9___Mmap2Stream_9___mmap_AWPROT),
+    .s00_axi_awqos(m_axi_rmem9___Mmap2Stream_9___mmap_AWQOS),
+    .s00_axi_awready(m_axi_rmem9___Mmap2Stream_9___mmap_AWREADY),
+    .s00_axi_awsize(m_axi_rmem9___Mmap2Stream_9___mmap_AWSIZE),
+    .s00_axi_awvalid(m_axi_rmem9___Mmap2Stream_9___mmap_AWVALID),
+    .s00_axi_bid(m_axi_rmem9___Mmap2Stream_9___mmap_BID),
+    .s00_axi_bready(m_axi_rmem9___Mmap2Stream_9___mmap_BREADY),
+    .s00_axi_bresp(m_axi_rmem9___Mmap2Stream_9___mmap_BRESP),
+    .s00_axi_bvalid(m_axi_rmem9___Mmap2Stream_9___mmap_BVALID),
+    .s00_axi_rdata(m_axi_rmem9___Mmap2Stream_9___mmap_RDATA),
+    .s00_axi_rid(m_axi_rmem9___Mmap2Stream_9___mmap_RID),
+    .s00_axi_rlast(m_axi_rmem9___Mmap2Stream_9___mmap_RLAST),
+    .s00_axi_rready(m_axi_rmem9___Mmap2Stream_9___mmap_RREADY),
+    .s00_axi_rresp(m_axi_rmem9___Mmap2Stream_9___mmap_RRESP),
+    .s00_axi_rvalid(m_axi_rmem9___Mmap2Stream_9___mmap_RVALID),
+    .s00_axi_wdata(m_axi_rmem9___Mmap2Stream_9___mmap_WDATA),
+    .s00_axi_wlast(m_axi_rmem9___Mmap2Stream_9___mmap_WLAST),
+    .s00_axi_wready(m_axi_rmem9___Mmap2Stream_9___mmap_WREADY),
+    .s00_axi_wstrb(m_axi_rmem9___Mmap2Stream_9___mmap_WSTRB),
+    .s00_axi_wvalid(m_axi_rmem9___Mmap2Stream_9___mmap_WVALID),
+    .s01_axi_araddr(m_axi_rmem9___Stream2Mmap_9___mmap_ARADDR),
+    .s01_axi_arburst(m_axi_rmem9___Stream2Mmap_9___mmap_ARBURST),
+    .s01_axi_arcache(m_axi_rmem9___Stream2Mmap_9___mmap_ARCACHE),
+    .s01_axi_arid(m_axi_rmem9___Stream2Mmap_9___mmap_ARID),
+    .s01_axi_arlen(m_axi_rmem9___Stream2Mmap_9___mmap_ARLEN),
+    .s01_axi_arlock(m_axi_rmem9___Stream2Mmap_9___mmap_ARLOCK),
+    .s01_axi_arprot(m_axi_rmem9___Stream2Mmap_9___mmap_ARPROT),
+    .s01_axi_arqos(m_axi_rmem9___Stream2Mmap_9___mmap_ARQOS),
+    .s01_axi_arready(m_axi_rmem9___Stream2Mmap_9___mmap_ARREADY),
+    .s01_axi_arsize(m_axi_rmem9___Stream2Mmap_9___mmap_ARSIZE),
+    .s01_axi_arvalid(m_axi_rmem9___Stream2Mmap_9___mmap_ARVALID),
+    .s01_axi_awaddr(m_axi_rmem9___Stream2Mmap_9___mmap_AWADDR),
+    .s01_axi_awburst(m_axi_rmem9___Stream2Mmap_9___mmap_AWBURST),
+    .s01_axi_awcache(m_axi_rmem9___Stream2Mmap_9___mmap_AWCACHE),
+    .s01_axi_awid(m_axi_rmem9___Stream2Mmap_9___mmap_AWID),
+    .s01_axi_awlen(m_axi_rmem9___Stream2Mmap_9___mmap_AWLEN),
+    .s01_axi_awlock(m_axi_rmem9___Stream2Mmap_9___mmap_AWLOCK),
+    .s01_axi_awprot(m_axi_rmem9___Stream2Mmap_9___mmap_AWPROT),
+    .s01_axi_awqos(m_axi_rmem9___Stream2Mmap_9___mmap_AWQOS),
+    .s01_axi_awready(m_axi_rmem9___Stream2Mmap_9___mmap_AWREADY),
+    .s01_axi_awsize(m_axi_rmem9___Stream2Mmap_9___mmap_AWSIZE),
+    .s01_axi_awvalid(m_axi_rmem9___Stream2Mmap_9___mmap_AWVALID),
+    .s01_axi_bid(m_axi_rmem9___Stream2Mmap_9___mmap_BID),
+    .s01_axi_bready(m_axi_rmem9___Stream2Mmap_9___mmap_BREADY),
+    .s01_axi_bresp(m_axi_rmem9___Stream2Mmap_9___mmap_BRESP),
+    .s01_axi_bvalid(m_axi_rmem9___Stream2Mmap_9___mmap_BVALID),
+    .s01_axi_rdata(m_axi_rmem9___Stream2Mmap_9___mmap_RDATA),
+    .s01_axi_rid(m_axi_rmem9___Stream2Mmap_9___mmap_RID),
+    .s01_axi_rlast(m_axi_rmem9___Stream2Mmap_9___mmap_RLAST),
+    .s01_axi_rready(m_axi_rmem9___Stream2Mmap_9___mmap_RREADY),
+    .s01_axi_rresp(m_axi_rmem9___Stream2Mmap_9___mmap_RRESP),
+    .s01_axi_rvalid(m_axi_rmem9___Stream2Mmap_9___mmap_RVALID),
+    .s01_axi_wdata(m_axi_rmem9___Stream2Mmap_9___mmap_WDATA),
+    .s01_axi_wlast(m_axi_rmem9___Stream2Mmap_9___mmap_WLAST),
+    .s01_axi_wready(m_axi_rmem9___Stream2Mmap_9___mmap_WREADY),
+    .s01_axi_wstrb(m_axi_rmem9___Stream2Mmap_9___mmap_WSTRB),
+    .s01_axi_wvalid(m_axi_rmem9___Stream2Mmap_9___mmap_WVALID)
+  );
+
+
+  (* keep_hierarchy = "yes" *) axi_crossbar_2x1
+  #(
+    .DATA_WIDTH(512),
+    .ADDR_WIDTH(64),
+    .S_ID_WIDTH(1),
+    .M_ID_WIDTH(2),
+    .M00_ADDR_WIDTH(64),
+    .M00_ISSUE(16),
+    .S00_THREADS(1),
+    .S01_THREADS(1)
+  )
+  axi_crossbar_2x1__rmem10
+  (
+    .clk(ap_clk),
+    .rst(ap_rst_n_inv),
+    .m00_axi_araddr(m_axi_rmem10_ARADDR),
+    .m00_axi_arburst(m_axi_rmem10_ARBURST),
+    .m00_axi_arcache(m_axi_rmem10_ARCACHE),
+    .m00_axi_arid(m_axi_rmem10_ARID),
+    .m00_axi_arlen(m_axi_rmem10_ARLEN),
+    .m00_axi_arlock(m_axi_rmem10_ARLOCK),
+    .m00_axi_arprot(m_axi_rmem10_ARPROT),
+    .m00_axi_arqos(m_axi_rmem10_ARQOS),
+    .m00_axi_arready(m_axi_rmem10_ARREADY),
+    .m00_axi_arsize(m_axi_rmem10_ARSIZE),
+    .m00_axi_arvalid(m_axi_rmem10_ARVALID),
+    .m00_axi_awaddr(m_axi_rmem10_AWADDR),
+    .m00_axi_awburst(m_axi_rmem10_AWBURST),
+    .m00_axi_awcache(m_axi_rmem10_AWCACHE),
+    .m00_axi_awid(m_axi_rmem10_AWID),
+    .m00_axi_awlen(m_axi_rmem10_AWLEN),
+    .m00_axi_awlock(m_axi_rmem10_AWLOCK),
+    .m00_axi_awprot(m_axi_rmem10_AWPROT),
+    .m00_axi_awqos(m_axi_rmem10_AWQOS),
+    .m00_axi_awready(m_axi_rmem10_AWREADY),
+    .m00_axi_awsize(m_axi_rmem10_AWSIZE),
+    .m00_axi_awvalid(m_axi_rmem10_AWVALID),
+    .m00_axi_bid(m_axi_rmem10_BID),
+    .m00_axi_bready(m_axi_rmem10_BREADY),
+    .m00_axi_bresp(m_axi_rmem10_BRESP),
+    .m00_axi_bvalid(m_axi_rmem10_BVALID),
+    .m00_axi_rdata(m_axi_rmem10_RDATA),
+    .m00_axi_rid(m_axi_rmem10_RID),
+    .m00_axi_rlast(m_axi_rmem10_RLAST),
+    .m00_axi_rready(m_axi_rmem10_RREADY),
+    .m00_axi_rresp(m_axi_rmem10_RRESP),
+    .m00_axi_rvalid(m_axi_rmem10_RVALID),
+    .m00_axi_wdata(m_axi_rmem10_WDATA),
+    .m00_axi_wlast(m_axi_rmem10_WLAST),
+    .m00_axi_wready(m_axi_rmem10_WREADY),
+    .m00_axi_wstrb(m_axi_rmem10_WSTRB),
+    .m00_axi_wvalid(m_axi_rmem10_WVALID),
+    .s00_axi_araddr(m_axi_rmem10___Mmap2Stream_10___mmap_ARADDR),
+    .s00_axi_arburst(m_axi_rmem10___Mmap2Stream_10___mmap_ARBURST),
+    .s00_axi_arcache(m_axi_rmem10___Mmap2Stream_10___mmap_ARCACHE),
+    .s00_axi_arid(m_axi_rmem10___Mmap2Stream_10___mmap_ARID),
+    .s00_axi_arlen(m_axi_rmem10___Mmap2Stream_10___mmap_ARLEN),
+    .s00_axi_arlock(m_axi_rmem10___Mmap2Stream_10___mmap_ARLOCK),
+    .s00_axi_arprot(m_axi_rmem10___Mmap2Stream_10___mmap_ARPROT),
+    .s00_axi_arqos(m_axi_rmem10___Mmap2Stream_10___mmap_ARQOS),
+    .s00_axi_arready(m_axi_rmem10___Mmap2Stream_10___mmap_ARREADY),
+    .s00_axi_arsize(m_axi_rmem10___Mmap2Stream_10___mmap_ARSIZE),
+    .s00_axi_arvalid(m_axi_rmem10___Mmap2Stream_10___mmap_ARVALID),
+    .s00_axi_awaddr(m_axi_rmem10___Mmap2Stream_10___mmap_AWADDR),
+    .s00_axi_awburst(m_axi_rmem10___Mmap2Stream_10___mmap_AWBURST),
+    .s00_axi_awcache(m_axi_rmem10___Mmap2Stream_10___mmap_AWCACHE),
+    .s00_axi_awid(m_axi_rmem10___Mmap2Stream_10___mmap_AWID),
+    .s00_axi_awlen(m_axi_rmem10___Mmap2Stream_10___mmap_AWLEN),
+    .s00_axi_awlock(m_axi_rmem10___Mmap2Stream_10___mmap_AWLOCK),
+    .s00_axi_awprot(m_axi_rmem10___Mmap2Stream_10___mmap_AWPROT),
+    .s00_axi_awqos(m_axi_rmem10___Mmap2Stream_10___mmap_AWQOS),
+    .s00_axi_awready(m_axi_rmem10___Mmap2Stream_10___mmap_AWREADY),
+    .s00_axi_awsize(m_axi_rmem10___Mmap2Stream_10___mmap_AWSIZE),
+    .s00_axi_awvalid(m_axi_rmem10___Mmap2Stream_10___mmap_AWVALID),
+    .s00_axi_bid(m_axi_rmem10___Mmap2Stream_10___mmap_BID),
+    .s00_axi_bready(m_axi_rmem10___Mmap2Stream_10___mmap_BREADY),
+    .s00_axi_bresp(m_axi_rmem10___Mmap2Stream_10___mmap_BRESP),
+    .s00_axi_bvalid(m_axi_rmem10___Mmap2Stream_10___mmap_BVALID),
+    .s00_axi_rdata(m_axi_rmem10___Mmap2Stream_10___mmap_RDATA),
+    .s00_axi_rid(m_axi_rmem10___Mmap2Stream_10___mmap_RID),
+    .s00_axi_rlast(m_axi_rmem10___Mmap2Stream_10___mmap_RLAST),
+    .s00_axi_rready(m_axi_rmem10___Mmap2Stream_10___mmap_RREADY),
+    .s00_axi_rresp(m_axi_rmem10___Mmap2Stream_10___mmap_RRESP),
+    .s00_axi_rvalid(m_axi_rmem10___Mmap2Stream_10___mmap_RVALID),
+    .s00_axi_wdata(m_axi_rmem10___Mmap2Stream_10___mmap_WDATA),
+    .s00_axi_wlast(m_axi_rmem10___Mmap2Stream_10___mmap_WLAST),
+    .s00_axi_wready(m_axi_rmem10___Mmap2Stream_10___mmap_WREADY),
+    .s00_axi_wstrb(m_axi_rmem10___Mmap2Stream_10___mmap_WSTRB),
+    .s00_axi_wvalid(m_axi_rmem10___Mmap2Stream_10___mmap_WVALID),
+    .s01_axi_araddr(m_axi_rmem10___Stream2Mmap_10___mmap_ARADDR),
+    .s01_axi_arburst(m_axi_rmem10___Stream2Mmap_10___mmap_ARBURST),
+    .s01_axi_arcache(m_axi_rmem10___Stream2Mmap_10___mmap_ARCACHE),
+    .s01_axi_arid(m_axi_rmem10___Stream2Mmap_10___mmap_ARID),
+    .s01_axi_arlen(m_axi_rmem10___Stream2Mmap_10___mmap_ARLEN),
+    .s01_axi_arlock(m_axi_rmem10___Stream2Mmap_10___mmap_ARLOCK),
+    .s01_axi_arprot(m_axi_rmem10___Stream2Mmap_10___mmap_ARPROT),
+    .s01_axi_arqos(m_axi_rmem10___Stream2Mmap_10___mmap_ARQOS),
+    .s01_axi_arready(m_axi_rmem10___Stream2Mmap_10___mmap_ARREADY),
+    .s01_axi_arsize(m_axi_rmem10___Stream2Mmap_10___mmap_ARSIZE),
+    .s01_axi_arvalid(m_axi_rmem10___Stream2Mmap_10___mmap_ARVALID),
+    .s01_axi_awaddr(m_axi_rmem10___Stream2Mmap_10___mmap_AWADDR),
+    .s01_axi_awburst(m_axi_rmem10___Stream2Mmap_10___mmap_AWBURST),
+    .s01_axi_awcache(m_axi_rmem10___Stream2Mmap_10___mmap_AWCACHE),
+    .s01_axi_awid(m_axi_rmem10___Stream2Mmap_10___mmap_AWID),
+    .s01_axi_awlen(m_axi_rmem10___Stream2Mmap_10___mmap_AWLEN),
+    .s01_axi_awlock(m_axi_rmem10___Stream2Mmap_10___mmap_AWLOCK),
+    .s01_axi_awprot(m_axi_rmem10___Stream2Mmap_10___mmap_AWPROT),
+    .s01_axi_awqos(m_axi_rmem10___Stream2Mmap_10___mmap_AWQOS),
+    .s01_axi_awready(m_axi_rmem10___Stream2Mmap_10___mmap_AWREADY),
+    .s01_axi_awsize(m_axi_rmem10___Stream2Mmap_10___mmap_AWSIZE),
+    .s01_axi_awvalid(m_axi_rmem10___Stream2Mmap_10___mmap_AWVALID),
+    .s01_axi_bid(m_axi_rmem10___Stream2Mmap_10___mmap_BID),
+    .s01_axi_bready(m_axi_rmem10___Stream2Mmap_10___mmap_BREADY),
+    .s01_axi_bresp(m_axi_rmem10___Stream2Mmap_10___mmap_BRESP),
+    .s01_axi_bvalid(m_axi_rmem10___Stream2Mmap_10___mmap_BVALID),
+    .s01_axi_rdata(m_axi_rmem10___Stream2Mmap_10___mmap_RDATA),
+    .s01_axi_rid(m_axi_rmem10___Stream2Mmap_10___mmap_RID),
+    .s01_axi_rlast(m_axi_rmem10___Stream2Mmap_10___mmap_RLAST),
+    .s01_axi_rready(m_axi_rmem10___Stream2Mmap_10___mmap_RREADY),
+    .s01_axi_rresp(m_axi_rmem10___Stream2Mmap_10___mmap_RRESP),
+    .s01_axi_rvalid(m_axi_rmem10___Stream2Mmap_10___mmap_RVALID),
+    .s01_axi_wdata(m_axi_rmem10___Stream2Mmap_10___mmap_WDATA),
+    .s01_axi_wlast(m_axi_rmem10___Stream2Mmap_10___mmap_WLAST),
+    .s01_axi_wready(m_axi_rmem10___Stream2Mmap_10___mmap_WREADY),
+    .s01_axi_wstrb(m_axi_rmem10___Stream2Mmap_10___mmap_WSTRB),
+    .s01_axi_wvalid(m_axi_rmem10___Stream2Mmap_10___mmap_WVALID)
+  );
+
+
+  (* keep_hierarchy = "yes" *) axi_crossbar_2x1
+  #(
+    .DATA_WIDTH(512),
+    .ADDR_WIDTH(64),
+    .S_ID_WIDTH(1),
+    .M_ID_WIDTH(2),
+    .M00_ADDR_WIDTH(64),
+    .M00_ISSUE(16),
+    .S00_THREADS(1),
+    .S01_THREADS(1)
+  )
+  axi_crossbar_2x1__rmem11
+  (
+    .clk(ap_clk),
+    .rst(ap_rst_n_inv),
+    .m00_axi_araddr(m_axi_rmem11_ARADDR),
+    .m00_axi_arburst(m_axi_rmem11_ARBURST),
+    .m00_axi_arcache(m_axi_rmem11_ARCACHE),
+    .m00_axi_arid(m_axi_rmem11_ARID),
+    .m00_axi_arlen(m_axi_rmem11_ARLEN),
+    .m00_axi_arlock(m_axi_rmem11_ARLOCK),
+    .m00_axi_arprot(m_axi_rmem11_ARPROT),
+    .m00_axi_arqos(m_axi_rmem11_ARQOS),
+    .m00_axi_arready(m_axi_rmem11_ARREADY),
+    .m00_axi_arsize(m_axi_rmem11_ARSIZE),
+    .m00_axi_arvalid(m_axi_rmem11_ARVALID),
+    .m00_axi_awaddr(m_axi_rmem11_AWADDR),
+    .m00_axi_awburst(m_axi_rmem11_AWBURST),
+    .m00_axi_awcache(m_axi_rmem11_AWCACHE),
+    .m00_axi_awid(m_axi_rmem11_AWID),
+    .m00_axi_awlen(m_axi_rmem11_AWLEN),
+    .m00_axi_awlock(m_axi_rmem11_AWLOCK),
+    .m00_axi_awprot(m_axi_rmem11_AWPROT),
+    .m00_axi_awqos(m_axi_rmem11_AWQOS),
+    .m00_axi_awready(m_axi_rmem11_AWREADY),
+    .m00_axi_awsize(m_axi_rmem11_AWSIZE),
+    .m00_axi_awvalid(m_axi_rmem11_AWVALID),
+    .m00_axi_bid(m_axi_rmem11_BID),
+    .m00_axi_bready(m_axi_rmem11_BREADY),
+    .m00_axi_bresp(m_axi_rmem11_BRESP),
+    .m00_axi_bvalid(m_axi_rmem11_BVALID),
+    .m00_axi_rdata(m_axi_rmem11_RDATA),
+    .m00_axi_rid(m_axi_rmem11_RID),
+    .m00_axi_rlast(m_axi_rmem11_RLAST),
+    .m00_axi_rready(m_axi_rmem11_RREADY),
+    .m00_axi_rresp(m_axi_rmem11_RRESP),
+    .m00_axi_rvalid(m_axi_rmem11_RVALID),
+    .m00_axi_wdata(m_axi_rmem11_WDATA),
+    .m00_axi_wlast(m_axi_rmem11_WLAST),
+    .m00_axi_wready(m_axi_rmem11_WREADY),
+    .m00_axi_wstrb(m_axi_rmem11_WSTRB),
+    .m00_axi_wvalid(m_axi_rmem11_WVALID),
+    .s00_axi_araddr(m_axi_rmem11___Mmap2Stream_11___mmap_ARADDR),
+    .s00_axi_arburst(m_axi_rmem11___Mmap2Stream_11___mmap_ARBURST),
+    .s00_axi_arcache(m_axi_rmem11___Mmap2Stream_11___mmap_ARCACHE),
+    .s00_axi_arid(m_axi_rmem11___Mmap2Stream_11___mmap_ARID),
+    .s00_axi_arlen(m_axi_rmem11___Mmap2Stream_11___mmap_ARLEN),
+    .s00_axi_arlock(m_axi_rmem11___Mmap2Stream_11___mmap_ARLOCK),
+    .s00_axi_arprot(m_axi_rmem11___Mmap2Stream_11___mmap_ARPROT),
+    .s00_axi_arqos(m_axi_rmem11___Mmap2Stream_11___mmap_ARQOS),
+    .s00_axi_arready(m_axi_rmem11___Mmap2Stream_11___mmap_ARREADY),
+    .s00_axi_arsize(m_axi_rmem11___Mmap2Stream_11___mmap_ARSIZE),
+    .s00_axi_arvalid(m_axi_rmem11___Mmap2Stream_11___mmap_ARVALID),
+    .s00_axi_awaddr(m_axi_rmem11___Mmap2Stream_11___mmap_AWADDR),
+    .s00_axi_awburst(m_axi_rmem11___Mmap2Stream_11___mmap_AWBURST),
+    .s00_axi_awcache(m_axi_rmem11___Mmap2Stream_11___mmap_AWCACHE),
+    .s00_axi_awid(m_axi_rmem11___Mmap2Stream_11___mmap_AWID),
+    .s00_axi_awlen(m_axi_rmem11___Mmap2Stream_11___mmap_AWLEN),
+    .s00_axi_awlock(m_axi_rmem11___Mmap2Stream_11___mmap_AWLOCK),
+    .s00_axi_awprot(m_axi_rmem11___Mmap2Stream_11___mmap_AWPROT),
+    .s00_axi_awqos(m_axi_rmem11___Mmap2Stream_11___mmap_AWQOS),
+    .s00_axi_awready(m_axi_rmem11___Mmap2Stream_11___mmap_AWREADY),
+    .s00_axi_awsize(m_axi_rmem11___Mmap2Stream_11___mmap_AWSIZE),
+    .s00_axi_awvalid(m_axi_rmem11___Mmap2Stream_11___mmap_AWVALID),
+    .s00_axi_bid(m_axi_rmem11___Mmap2Stream_11___mmap_BID),
+    .s00_axi_bready(m_axi_rmem11___Mmap2Stream_11___mmap_BREADY),
+    .s00_axi_bresp(m_axi_rmem11___Mmap2Stream_11___mmap_BRESP),
+    .s00_axi_bvalid(m_axi_rmem11___Mmap2Stream_11___mmap_BVALID),
+    .s00_axi_rdata(m_axi_rmem11___Mmap2Stream_11___mmap_RDATA),
+    .s00_axi_rid(m_axi_rmem11___Mmap2Stream_11___mmap_RID),
+    .s00_axi_rlast(m_axi_rmem11___Mmap2Stream_11___mmap_RLAST),
+    .s00_axi_rready(m_axi_rmem11___Mmap2Stream_11___mmap_RREADY),
+    .s00_axi_rresp(m_axi_rmem11___Mmap2Stream_11___mmap_RRESP),
+    .s00_axi_rvalid(m_axi_rmem11___Mmap2Stream_11___mmap_RVALID),
+    .s00_axi_wdata(m_axi_rmem11___Mmap2Stream_11___mmap_WDATA),
+    .s00_axi_wlast(m_axi_rmem11___Mmap2Stream_11___mmap_WLAST),
+    .s00_axi_wready(m_axi_rmem11___Mmap2Stream_11___mmap_WREADY),
+    .s00_axi_wstrb(m_axi_rmem11___Mmap2Stream_11___mmap_WSTRB),
+    .s00_axi_wvalid(m_axi_rmem11___Mmap2Stream_11___mmap_WVALID),
+    .s01_axi_araddr(m_axi_rmem11___Stream2Mmap_11___mmap_ARADDR),
+    .s01_axi_arburst(m_axi_rmem11___Stream2Mmap_11___mmap_ARBURST),
+    .s01_axi_arcache(m_axi_rmem11___Stream2Mmap_11___mmap_ARCACHE),
+    .s01_axi_arid(m_axi_rmem11___Stream2Mmap_11___mmap_ARID),
+    .s01_axi_arlen(m_axi_rmem11___Stream2Mmap_11___mmap_ARLEN),
+    .s01_axi_arlock(m_axi_rmem11___Stream2Mmap_11___mmap_ARLOCK),
+    .s01_axi_arprot(m_axi_rmem11___Stream2Mmap_11___mmap_ARPROT),
+    .s01_axi_arqos(m_axi_rmem11___Stream2Mmap_11___mmap_ARQOS),
+    .s01_axi_arready(m_axi_rmem11___Stream2Mmap_11___mmap_ARREADY),
+    .s01_axi_arsize(m_axi_rmem11___Stream2Mmap_11___mmap_ARSIZE),
+    .s01_axi_arvalid(m_axi_rmem11___Stream2Mmap_11___mmap_ARVALID),
+    .s01_axi_awaddr(m_axi_rmem11___Stream2Mmap_11___mmap_AWADDR),
+    .s01_axi_awburst(m_axi_rmem11___Stream2Mmap_11___mmap_AWBURST),
+    .s01_axi_awcache(m_axi_rmem11___Stream2Mmap_11___mmap_AWCACHE),
+    .s01_axi_awid(m_axi_rmem11___Stream2Mmap_11___mmap_AWID),
+    .s01_axi_awlen(m_axi_rmem11___Stream2Mmap_11___mmap_AWLEN),
+    .s01_axi_awlock(m_axi_rmem11___Stream2Mmap_11___mmap_AWLOCK),
+    .s01_axi_awprot(m_axi_rmem11___Stream2Mmap_11___mmap_AWPROT),
+    .s01_axi_awqos(m_axi_rmem11___Stream2Mmap_11___mmap_AWQOS),
+    .s01_axi_awready(m_axi_rmem11___Stream2Mmap_11___mmap_AWREADY),
+    .s01_axi_awsize(m_axi_rmem11___Stream2Mmap_11___mmap_AWSIZE),
+    .s01_axi_awvalid(m_axi_rmem11___Stream2Mmap_11___mmap_AWVALID),
+    .s01_axi_bid(m_axi_rmem11___Stream2Mmap_11___mmap_BID),
+    .s01_axi_bready(m_axi_rmem11___Stream2Mmap_11___mmap_BREADY),
+    .s01_axi_bresp(m_axi_rmem11___Stream2Mmap_11___mmap_BRESP),
+    .s01_axi_bvalid(m_axi_rmem11___Stream2Mmap_11___mmap_BVALID),
+    .s01_axi_rdata(m_axi_rmem11___Stream2Mmap_11___mmap_RDATA),
+    .s01_axi_rid(m_axi_rmem11___Stream2Mmap_11___mmap_RID),
+    .s01_axi_rlast(m_axi_rmem11___Stream2Mmap_11___mmap_RLAST),
+    .s01_axi_rready(m_axi_rmem11___Stream2Mmap_11___mmap_RREADY),
+    .s01_axi_rresp(m_axi_rmem11___Stream2Mmap_11___mmap_RRESP),
+    .s01_axi_rvalid(m_axi_rmem11___Stream2Mmap_11___mmap_RVALID),
+    .s01_axi_wdata(m_axi_rmem11___Stream2Mmap_11___mmap_WDATA),
+    .s01_axi_wlast(m_axi_rmem11___Stream2Mmap_11___mmap_WLAST),
+    .s01_axi_wready(m_axi_rmem11___Stream2Mmap_11___mmap_WREADY),
+    .s01_axi_wstrb(m_axi_rmem11___Stream2Mmap_11___mmap_WSTRB),
+    .s01_axi_wvalid(m_axi_rmem11___Stream2Mmap_11___mmap_WVALID)
+  );
+
+
+  (* keep_hierarchy = "yes" *) axi_crossbar_2x1
+  #(
+    .DATA_WIDTH(512),
+    .ADDR_WIDTH(64),
+    .S_ID_WIDTH(1),
+    .M_ID_WIDTH(2),
+    .M00_ADDR_WIDTH(64),
+    .M00_ISSUE(16),
+    .S00_THREADS(1),
+    .S01_THREADS(1)
+  )
+  axi_crossbar_2x1__rmem12
+  (
+    .clk(ap_clk),
+    .rst(ap_rst_n_inv),
+    .m00_axi_araddr(m_axi_rmem12_ARADDR),
+    .m00_axi_arburst(m_axi_rmem12_ARBURST),
+    .m00_axi_arcache(m_axi_rmem12_ARCACHE),
+    .m00_axi_arid(m_axi_rmem12_ARID),
+    .m00_axi_arlen(m_axi_rmem12_ARLEN),
+    .m00_axi_arlock(m_axi_rmem12_ARLOCK),
+    .m00_axi_arprot(m_axi_rmem12_ARPROT),
+    .m00_axi_arqos(m_axi_rmem12_ARQOS),
+    .m00_axi_arready(m_axi_rmem12_ARREADY),
+    .m00_axi_arsize(m_axi_rmem12_ARSIZE),
+    .m00_axi_arvalid(m_axi_rmem12_ARVALID),
+    .m00_axi_awaddr(m_axi_rmem12_AWADDR),
+    .m00_axi_awburst(m_axi_rmem12_AWBURST),
+    .m00_axi_awcache(m_axi_rmem12_AWCACHE),
+    .m00_axi_awid(m_axi_rmem12_AWID),
+    .m00_axi_awlen(m_axi_rmem12_AWLEN),
+    .m00_axi_awlock(m_axi_rmem12_AWLOCK),
+    .m00_axi_awprot(m_axi_rmem12_AWPROT),
+    .m00_axi_awqos(m_axi_rmem12_AWQOS),
+    .m00_axi_awready(m_axi_rmem12_AWREADY),
+    .m00_axi_awsize(m_axi_rmem12_AWSIZE),
+    .m00_axi_awvalid(m_axi_rmem12_AWVALID),
+    .m00_axi_bid(m_axi_rmem12_BID),
+    .m00_axi_bready(m_axi_rmem12_BREADY),
+    .m00_axi_bresp(m_axi_rmem12_BRESP),
+    .m00_axi_bvalid(m_axi_rmem12_BVALID),
+    .m00_axi_rdata(m_axi_rmem12_RDATA),
+    .m00_axi_rid(m_axi_rmem12_RID),
+    .m00_axi_rlast(m_axi_rmem12_RLAST),
+    .m00_axi_rready(m_axi_rmem12_RREADY),
+    .m00_axi_rresp(m_axi_rmem12_RRESP),
+    .m00_axi_rvalid(m_axi_rmem12_RVALID),
+    .m00_axi_wdata(m_axi_rmem12_WDATA),
+    .m00_axi_wlast(m_axi_rmem12_WLAST),
+    .m00_axi_wready(m_axi_rmem12_WREADY),
+    .m00_axi_wstrb(m_axi_rmem12_WSTRB),
+    .m00_axi_wvalid(m_axi_rmem12_WVALID),
+    .s00_axi_araddr(m_axi_rmem12___Mmap2Stream_12___mmap_ARADDR),
+    .s00_axi_arburst(m_axi_rmem12___Mmap2Stream_12___mmap_ARBURST),
+    .s00_axi_arcache(m_axi_rmem12___Mmap2Stream_12___mmap_ARCACHE),
+    .s00_axi_arid(m_axi_rmem12___Mmap2Stream_12___mmap_ARID),
+    .s00_axi_arlen(m_axi_rmem12___Mmap2Stream_12___mmap_ARLEN),
+    .s00_axi_arlock(m_axi_rmem12___Mmap2Stream_12___mmap_ARLOCK),
+    .s00_axi_arprot(m_axi_rmem12___Mmap2Stream_12___mmap_ARPROT),
+    .s00_axi_arqos(m_axi_rmem12___Mmap2Stream_12___mmap_ARQOS),
+    .s00_axi_arready(m_axi_rmem12___Mmap2Stream_12___mmap_ARREADY),
+    .s00_axi_arsize(m_axi_rmem12___Mmap2Stream_12___mmap_ARSIZE),
+    .s00_axi_arvalid(m_axi_rmem12___Mmap2Stream_12___mmap_ARVALID),
+    .s00_axi_awaddr(m_axi_rmem12___Mmap2Stream_12___mmap_AWADDR),
+    .s00_axi_awburst(m_axi_rmem12___Mmap2Stream_12___mmap_AWBURST),
+    .s00_axi_awcache(m_axi_rmem12___Mmap2Stream_12___mmap_AWCACHE),
+    .s00_axi_awid(m_axi_rmem12___Mmap2Stream_12___mmap_AWID),
+    .s00_axi_awlen(m_axi_rmem12___Mmap2Stream_12___mmap_AWLEN),
+    .s00_axi_awlock(m_axi_rmem12___Mmap2Stream_12___mmap_AWLOCK),
+    .s00_axi_awprot(m_axi_rmem12___Mmap2Stream_12___mmap_AWPROT),
+    .s00_axi_awqos(m_axi_rmem12___Mmap2Stream_12___mmap_AWQOS),
+    .s00_axi_awready(m_axi_rmem12___Mmap2Stream_12___mmap_AWREADY),
+    .s00_axi_awsize(m_axi_rmem12___Mmap2Stream_12___mmap_AWSIZE),
+    .s00_axi_awvalid(m_axi_rmem12___Mmap2Stream_12___mmap_AWVALID),
+    .s00_axi_bid(m_axi_rmem12___Mmap2Stream_12___mmap_BID),
+    .s00_axi_bready(m_axi_rmem12___Mmap2Stream_12___mmap_BREADY),
+    .s00_axi_bresp(m_axi_rmem12___Mmap2Stream_12___mmap_BRESP),
+    .s00_axi_bvalid(m_axi_rmem12___Mmap2Stream_12___mmap_BVALID),
+    .s00_axi_rdata(m_axi_rmem12___Mmap2Stream_12___mmap_RDATA),
+    .s00_axi_rid(m_axi_rmem12___Mmap2Stream_12___mmap_RID),
+    .s00_axi_rlast(m_axi_rmem12___Mmap2Stream_12___mmap_RLAST),
+    .s00_axi_rready(m_axi_rmem12___Mmap2Stream_12___mmap_RREADY),
+    .s00_axi_rresp(m_axi_rmem12___Mmap2Stream_12___mmap_RRESP),
+    .s00_axi_rvalid(m_axi_rmem12___Mmap2Stream_12___mmap_RVALID),
+    .s00_axi_wdata(m_axi_rmem12___Mmap2Stream_12___mmap_WDATA),
+    .s00_axi_wlast(m_axi_rmem12___Mmap2Stream_12___mmap_WLAST),
+    .s00_axi_wready(m_axi_rmem12___Mmap2Stream_12___mmap_WREADY),
+    .s00_axi_wstrb(m_axi_rmem12___Mmap2Stream_12___mmap_WSTRB),
+    .s00_axi_wvalid(m_axi_rmem12___Mmap2Stream_12___mmap_WVALID),
+    .s01_axi_araddr(m_axi_rmem12___Stream2Mmap_12___mmap_ARADDR),
+    .s01_axi_arburst(m_axi_rmem12___Stream2Mmap_12___mmap_ARBURST),
+    .s01_axi_arcache(m_axi_rmem12___Stream2Mmap_12___mmap_ARCACHE),
+    .s01_axi_arid(m_axi_rmem12___Stream2Mmap_12___mmap_ARID),
+    .s01_axi_arlen(m_axi_rmem12___Stream2Mmap_12___mmap_ARLEN),
+    .s01_axi_arlock(m_axi_rmem12___Stream2Mmap_12___mmap_ARLOCK),
+    .s01_axi_arprot(m_axi_rmem12___Stream2Mmap_12___mmap_ARPROT),
+    .s01_axi_arqos(m_axi_rmem12___Stream2Mmap_12___mmap_ARQOS),
+    .s01_axi_arready(m_axi_rmem12___Stream2Mmap_12___mmap_ARREADY),
+    .s01_axi_arsize(m_axi_rmem12___Stream2Mmap_12___mmap_ARSIZE),
+    .s01_axi_arvalid(m_axi_rmem12___Stream2Mmap_12___mmap_ARVALID),
+    .s01_axi_awaddr(m_axi_rmem12___Stream2Mmap_12___mmap_AWADDR),
+    .s01_axi_awburst(m_axi_rmem12___Stream2Mmap_12___mmap_AWBURST),
+    .s01_axi_awcache(m_axi_rmem12___Stream2Mmap_12___mmap_AWCACHE),
+    .s01_axi_awid(m_axi_rmem12___Stream2Mmap_12___mmap_AWID),
+    .s01_axi_awlen(m_axi_rmem12___Stream2Mmap_12___mmap_AWLEN),
+    .s01_axi_awlock(m_axi_rmem12___Stream2Mmap_12___mmap_AWLOCK),
+    .s01_axi_awprot(m_axi_rmem12___Stream2Mmap_12___mmap_AWPROT),
+    .s01_axi_awqos(m_axi_rmem12___Stream2Mmap_12___mmap_AWQOS),
+    .s01_axi_awready(m_axi_rmem12___Stream2Mmap_12___mmap_AWREADY),
+    .s01_axi_awsize(m_axi_rmem12___Stream2Mmap_12___mmap_AWSIZE),
+    .s01_axi_awvalid(m_axi_rmem12___Stream2Mmap_12___mmap_AWVALID),
+    .s01_axi_bid(m_axi_rmem12___Stream2Mmap_12___mmap_BID),
+    .s01_axi_bready(m_axi_rmem12___Stream2Mmap_12___mmap_BREADY),
+    .s01_axi_bresp(m_axi_rmem12___Stream2Mmap_12___mmap_BRESP),
+    .s01_axi_bvalid(m_axi_rmem12___Stream2Mmap_12___mmap_BVALID),
+    .s01_axi_rdata(m_axi_rmem12___Stream2Mmap_12___mmap_RDATA),
+    .s01_axi_rid(m_axi_rmem12___Stream2Mmap_12___mmap_RID),
+    .s01_axi_rlast(m_axi_rmem12___Stream2Mmap_12___mmap_RLAST),
+    .s01_axi_rready(m_axi_rmem12___Stream2Mmap_12___mmap_RREADY),
+    .s01_axi_rresp(m_axi_rmem12___Stream2Mmap_12___mmap_RRESP),
+    .s01_axi_rvalid(m_axi_rmem12___Stream2Mmap_12___mmap_RVALID),
+    .s01_axi_wdata(m_axi_rmem12___Stream2Mmap_12___mmap_WDATA),
+    .s01_axi_wlast(m_axi_rmem12___Stream2Mmap_12___mmap_WLAST),
+    .s01_axi_wready(m_axi_rmem12___Stream2Mmap_12___mmap_WREADY),
+    .s01_axi_wstrb(m_axi_rmem12___Stream2Mmap_12___mmap_WSTRB),
+    .s01_axi_wvalid(m_axi_rmem12___Stream2Mmap_12___mmap_WVALID)
+  );
+
+
+  (* keep_hierarchy = "yes" *) axi_crossbar_2x1
+  #(
+    .DATA_WIDTH(512),
+    .ADDR_WIDTH(64),
+    .S_ID_WIDTH(1),
+    .M_ID_WIDTH(2),
+    .M00_ADDR_WIDTH(64),
+    .M00_ISSUE(16),
+    .S00_THREADS(1),
+    .S01_THREADS(1)
+  )
+  axi_crossbar_2x1__rmem13
+  (
+    .clk(ap_clk),
+    .rst(ap_rst_n_inv),
+    .m00_axi_araddr(m_axi_rmem13_ARADDR),
+    .m00_axi_arburst(m_axi_rmem13_ARBURST),
+    .m00_axi_arcache(m_axi_rmem13_ARCACHE),
+    .m00_axi_arid(m_axi_rmem13_ARID),
+    .m00_axi_arlen(m_axi_rmem13_ARLEN),
+    .m00_axi_arlock(m_axi_rmem13_ARLOCK),
+    .m00_axi_arprot(m_axi_rmem13_ARPROT),
+    .m00_axi_arqos(m_axi_rmem13_ARQOS),
+    .m00_axi_arready(m_axi_rmem13_ARREADY),
+    .m00_axi_arsize(m_axi_rmem13_ARSIZE),
+    .m00_axi_arvalid(m_axi_rmem13_ARVALID),
+    .m00_axi_awaddr(m_axi_rmem13_AWADDR),
+    .m00_axi_awburst(m_axi_rmem13_AWBURST),
+    .m00_axi_awcache(m_axi_rmem13_AWCACHE),
+    .m00_axi_awid(m_axi_rmem13_AWID),
+    .m00_axi_awlen(m_axi_rmem13_AWLEN),
+    .m00_axi_awlock(m_axi_rmem13_AWLOCK),
+    .m00_axi_awprot(m_axi_rmem13_AWPROT),
+    .m00_axi_awqos(m_axi_rmem13_AWQOS),
+    .m00_axi_awready(m_axi_rmem13_AWREADY),
+    .m00_axi_awsize(m_axi_rmem13_AWSIZE),
+    .m00_axi_awvalid(m_axi_rmem13_AWVALID),
+    .m00_axi_bid(m_axi_rmem13_BID),
+    .m00_axi_bready(m_axi_rmem13_BREADY),
+    .m00_axi_bresp(m_axi_rmem13_BRESP),
+    .m00_axi_bvalid(m_axi_rmem13_BVALID),
+    .m00_axi_rdata(m_axi_rmem13_RDATA),
+    .m00_axi_rid(m_axi_rmem13_RID),
+    .m00_axi_rlast(m_axi_rmem13_RLAST),
+    .m00_axi_rready(m_axi_rmem13_RREADY),
+    .m00_axi_rresp(m_axi_rmem13_RRESP),
+    .m00_axi_rvalid(m_axi_rmem13_RVALID),
+    .m00_axi_wdata(m_axi_rmem13_WDATA),
+    .m00_axi_wlast(m_axi_rmem13_WLAST),
+    .m00_axi_wready(m_axi_rmem13_WREADY),
+    .m00_axi_wstrb(m_axi_rmem13_WSTRB),
+    .m00_axi_wvalid(m_axi_rmem13_WVALID),
+    .s00_axi_araddr(m_axi_rmem13___Mmap2Stream_13___mmap_ARADDR),
+    .s00_axi_arburst(m_axi_rmem13___Mmap2Stream_13___mmap_ARBURST),
+    .s00_axi_arcache(m_axi_rmem13___Mmap2Stream_13___mmap_ARCACHE),
+    .s00_axi_arid(m_axi_rmem13___Mmap2Stream_13___mmap_ARID),
+    .s00_axi_arlen(m_axi_rmem13___Mmap2Stream_13___mmap_ARLEN),
+    .s00_axi_arlock(m_axi_rmem13___Mmap2Stream_13___mmap_ARLOCK),
+    .s00_axi_arprot(m_axi_rmem13___Mmap2Stream_13___mmap_ARPROT),
+    .s00_axi_arqos(m_axi_rmem13___Mmap2Stream_13___mmap_ARQOS),
+    .s00_axi_arready(m_axi_rmem13___Mmap2Stream_13___mmap_ARREADY),
+    .s00_axi_arsize(m_axi_rmem13___Mmap2Stream_13___mmap_ARSIZE),
+    .s00_axi_arvalid(m_axi_rmem13___Mmap2Stream_13___mmap_ARVALID),
+    .s00_axi_awaddr(m_axi_rmem13___Mmap2Stream_13___mmap_AWADDR),
+    .s00_axi_awburst(m_axi_rmem13___Mmap2Stream_13___mmap_AWBURST),
+    .s00_axi_awcache(m_axi_rmem13___Mmap2Stream_13___mmap_AWCACHE),
+    .s00_axi_awid(m_axi_rmem13___Mmap2Stream_13___mmap_AWID),
+    .s00_axi_awlen(m_axi_rmem13___Mmap2Stream_13___mmap_AWLEN),
+    .s00_axi_awlock(m_axi_rmem13___Mmap2Stream_13___mmap_AWLOCK),
+    .s00_axi_awprot(m_axi_rmem13___Mmap2Stream_13___mmap_AWPROT),
+    .s00_axi_awqos(m_axi_rmem13___Mmap2Stream_13___mmap_AWQOS),
+    .s00_axi_awready(m_axi_rmem13___Mmap2Stream_13___mmap_AWREADY),
+    .s00_axi_awsize(m_axi_rmem13___Mmap2Stream_13___mmap_AWSIZE),
+    .s00_axi_awvalid(m_axi_rmem13___Mmap2Stream_13___mmap_AWVALID),
+    .s00_axi_bid(m_axi_rmem13___Mmap2Stream_13___mmap_BID),
+    .s00_axi_bready(m_axi_rmem13___Mmap2Stream_13___mmap_BREADY),
+    .s00_axi_bresp(m_axi_rmem13___Mmap2Stream_13___mmap_BRESP),
+    .s00_axi_bvalid(m_axi_rmem13___Mmap2Stream_13___mmap_BVALID),
+    .s00_axi_rdata(m_axi_rmem13___Mmap2Stream_13___mmap_RDATA),
+    .s00_axi_rid(m_axi_rmem13___Mmap2Stream_13___mmap_RID),
+    .s00_axi_rlast(m_axi_rmem13___Mmap2Stream_13___mmap_RLAST),
+    .s00_axi_rready(m_axi_rmem13___Mmap2Stream_13___mmap_RREADY),
+    .s00_axi_rresp(m_axi_rmem13___Mmap2Stream_13___mmap_RRESP),
+    .s00_axi_rvalid(m_axi_rmem13___Mmap2Stream_13___mmap_RVALID),
+    .s00_axi_wdata(m_axi_rmem13___Mmap2Stream_13___mmap_WDATA),
+    .s00_axi_wlast(m_axi_rmem13___Mmap2Stream_13___mmap_WLAST),
+    .s00_axi_wready(m_axi_rmem13___Mmap2Stream_13___mmap_WREADY),
+    .s00_axi_wstrb(m_axi_rmem13___Mmap2Stream_13___mmap_WSTRB),
+    .s00_axi_wvalid(m_axi_rmem13___Mmap2Stream_13___mmap_WVALID),
+    .s01_axi_araddr(m_axi_rmem13___Stream2Mmap_13___mmap_ARADDR),
+    .s01_axi_arburst(m_axi_rmem13___Stream2Mmap_13___mmap_ARBURST),
+    .s01_axi_arcache(m_axi_rmem13___Stream2Mmap_13___mmap_ARCACHE),
+    .s01_axi_arid(m_axi_rmem13___Stream2Mmap_13___mmap_ARID),
+    .s01_axi_arlen(m_axi_rmem13___Stream2Mmap_13___mmap_ARLEN),
+    .s01_axi_arlock(m_axi_rmem13___Stream2Mmap_13___mmap_ARLOCK),
+    .s01_axi_arprot(m_axi_rmem13___Stream2Mmap_13___mmap_ARPROT),
+    .s01_axi_arqos(m_axi_rmem13___Stream2Mmap_13___mmap_ARQOS),
+    .s01_axi_arready(m_axi_rmem13___Stream2Mmap_13___mmap_ARREADY),
+    .s01_axi_arsize(m_axi_rmem13___Stream2Mmap_13___mmap_ARSIZE),
+    .s01_axi_arvalid(m_axi_rmem13___Stream2Mmap_13___mmap_ARVALID),
+    .s01_axi_awaddr(m_axi_rmem13___Stream2Mmap_13___mmap_AWADDR),
+    .s01_axi_awburst(m_axi_rmem13___Stream2Mmap_13___mmap_AWBURST),
+    .s01_axi_awcache(m_axi_rmem13___Stream2Mmap_13___mmap_AWCACHE),
+    .s01_axi_awid(m_axi_rmem13___Stream2Mmap_13___mmap_AWID),
+    .s01_axi_awlen(m_axi_rmem13___Stream2Mmap_13___mmap_AWLEN),
+    .s01_axi_awlock(m_axi_rmem13___Stream2Mmap_13___mmap_AWLOCK),
+    .s01_axi_awprot(m_axi_rmem13___Stream2Mmap_13___mmap_AWPROT),
+    .s01_axi_awqos(m_axi_rmem13___Stream2Mmap_13___mmap_AWQOS),
+    .s01_axi_awready(m_axi_rmem13___Stream2Mmap_13___mmap_AWREADY),
+    .s01_axi_awsize(m_axi_rmem13___Stream2Mmap_13___mmap_AWSIZE),
+    .s01_axi_awvalid(m_axi_rmem13___Stream2Mmap_13___mmap_AWVALID),
+    .s01_axi_bid(m_axi_rmem13___Stream2Mmap_13___mmap_BID),
+    .s01_axi_bready(m_axi_rmem13___Stream2Mmap_13___mmap_BREADY),
+    .s01_axi_bresp(m_axi_rmem13___Stream2Mmap_13___mmap_BRESP),
+    .s01_axi_bvalid(m_axi_rmem13___Stream2Mmap_13___mmap_BVALID),
+    .s01_axi_rdata(m_axi_rmem13___Stream2Mmap_13___mmap_RDATA),
+    .s01_axi_rid(m_axi_rmem13___Stream2Mmap_13___mmap_RID),
+    .s01_axi_rlast(m_axi_rmem13___Stream2Mmap_13___mmap_RLAST),
+    .s01_axi_rready(m_axi_rmem13___Stream2Mmap_13___mmap_RREADY),
+    .s01_axi_rresp(m_axi_rmem13___Stream2Mmap_13___mmap_RRESP),
+    .s01_axi_rvalid(m_axi_rmem13___Stream2Mmap_13___mmap_RVALID),
+    .s01_axi_wdata(m_axi_rmem13___Stream2Mmap_13___mmap_WDATA),
+    .s01_axi_wlast(m_axi_rmem13___Stream2Mmap_13___mmap_WLAST),
+    .s01_axi_wready(m_axi_rmem13___Stream2Mmap_13___mmap_WREADY),
+    .s01_axi_wstrb(m_axi_rmem13___Stream2Mmap_13___mmap_WSTRB),
+    .s01_axi_wvalid(m_axi_rmem13___Stream2Mmap_13___mmap_WVALID)
+  );
+
+
+  (* keep_hierarchy = "yes" *) axi_crossbar_2x1
+  #(
+    .DATA_WIDTH(512),
+    .ADDR_WIDTH(64),
+    .S_ID_WIDTH(1),
+    .M_ID_WIDTH(2),
+    .M00_ADDR_WIDTH(64),
+    .M00_ISSUE(16),
+    .S00_THREADS(1),
+    .S01_THREADS(1)
+  )
+  axi_crossbar_2x1__rmem14
+  (
+    .clk(ap_clk),
+    .rst(ap_rst_n_inv),
+    .m00_axi_araddr(m_axi_rmem14_ARADDR),
+    .m00_axi_arburst(m_axi_rmem14_ARBURST),
+    .m00_axi_arcache(m_axi_rmem14_ARCACHE),
+    .m00_axi_arid(m_axi_rmem14_ARID),
+    .m00_axi_arlen(m_axi_rmem14_ARLEN),
+    .m00_axi_arlock(m_axi_rmem14_ARLOCK),
+    .m00_axi_arprot(m_axi_rmem14_ARPROT),
+    .m00_axi_arqos(m_axi_rmem14_ARQOS),
+    .m00_axi_arready(m_axi_rmem14_ARREADY),
+    .m00_axi_arsize(m_axi_rmem14_ARSIZE),
+    .m00_axi_arvalid(m_axi_rmem14_ARVALID),
+    .m00_axi_awaddr(m_axi_rmem14_AWADDR),
+    .m00_axi_awburst(m_axi_rmem14_AWBURST),
+    .m00_axi_awcache(m_axi_rmem14_AWCACHE),
+    .m00_axi_awid(m_axi_rmem14_AWID),
+    .m00_axi_awlen(m_axi_rmem14_AWLEN),
+    .m00_axi_awlock(m_axi_rmem14_AWLOCK),
+    .m00_axi_awprot(m_axi_rmem14_AWPROT),
+    .m00_axi_awqos(m_axi_rmem14_AWQOS),
+    .m00_axi_awready(m_axi_rmem14_AWREADY),
+    .m00_axi_awsize(m_axi_rmem14_AWSIZE),
+    .m00_axi_awvalid(m_axi_rmem14_AWVALID),
+    .m00_axi_bid(m_axi_rmem14_BID),
+    .m00_axi_bready(m_axi_rmem14_BREADY),
+    .m00_axi_bresp(m_axi_rmem14_BRESP),
+    .m00_axi_bvalid(m_axi_rmem14_BVALID),
+    .m00_axi_rdata(m_axi_rmem14_RDATA),
+    .m00_axi_rid(m_axi_rmem14_RID),
+    .m00_axi_rlast(m_axi_rmem14_RLAST),
+    .m00_axi_rready(m_axi_rmem14_RREADY),
+    .m00_axi_rresp(m_axi_rmem14_RRESP),
+    .m00_axi_rvalid(m_axi_rmem14_RVALID),
+    .m00_axi_wdata(m_axi_rmem14_WDATA),
+    .m00_axi_wlast(m_axi_rmem14_WLAST),
+    .m00_axi_wready(m_axi_rmem14_WREADY),
+    .m00_axi_wstrb(m_axi_rmem14_WSTRB),
+    .m00_axi_wvalid(m_axi_rmem14_WVALID),
+    .s00_axi_araddr(m_axi_rmem14___Mmap2Stream_14___mmap_ARADDR),
+    .s00_axi_arburst(m_axi_rmem14___Mmap2Stream_14___mmap_ARBURST),
+    .s00_axi_arcache(m_axi_rmem14___Mmap2Stream_14___mmap_ARCACHE),
+    .s00_axi_arid(m_axi_rmem14___Mmap2Stream_14___mmap_ARID),
+    .s00_axi_arlen(m_axi_rmem14___Mmap2Stream_14___mmap_ARLEN),
+    .s00_axi_arlock(m_axi_rmem14___Mmap2Stream_14___mmap_ARLOCK),
+    .s00_axi_arprot(m_axi_rmem14___Mmap2Stream_14___mmap_ARPROT),
+    .s00_axi_arqos(m_axi_rmem14___Mmap2Stream_14___mmap_ARQOS),
+    .s00_axi_arready(m_axi_rmem14___Mmap2Stream_14___mmap_ARREADY),
+    .s00_axi_arsize(m_axi_rmem14___Mmap2Stream_14___mmap_ARSIZE),
+    .s00_axi_arvalid(m_axi_rmem14___Mmap2Stream_14___mmap_ARVALID),
+    .s00_axi_awaddr(m_axi_rmem14___Mmap2Stream_14___mmap_AWADDR),
+    .s00_axi_awburst(m_axi_rmem14___Mmap2Stream_14___mmap_AWBURST),
+    .s00_axi_awcache(m_axi_rmem14___Mmap2Stream_14___mmap_AWCACHE),
+    .s00_axi_awid(m_axi_rmem14___Mmap2Stream_14___mmap_AWID),
+    .s00_axi_awlen(m_axi_rmem14___Mmap2Stream_14___mmap_AWLEN),
+    .s00_axi_awlock(m_axi_rmem14___Mmap2Stream_14___mmap_AWLOCK),
+    .s00_axi_awprot(m_axi_rmem14___Mmap2Stream_14___mmap_AWPROT),
+    .s00_axi_awqos(m_axi_rmem14___Mmap2Stream_14___mmap_AWQOS),
+    .s00_axi_awready(m_axi_rmem14___Mmap2Stream_14___mmap_AWREADY),
+    .s00_axi_awsize(m_axi_rmem14___Mmap2Stream_14___mmap_AWSIZE),
+    .s00_axi_awvalid(m_axi_rmem14___Mmap2Stream_14___mmap_AWVALID),
+    .s00_axi_bid(m_axi_rmem14___Mmap2Stream_14___mmap_BID),
+    .s00_axi_bready(m_axi_rmem14___Mmap2Stream_14___mmap_BREADY),
+    .s00_axi_bresp(m_axi_rmem14___Mmap2Stream_14___mmap_BRESP),
+    .s00_axi_bvalid(m_axi_rmem14___Mmap2Stream_14___mmap_BVALID),
+    .s00_axi_rdata(m_axi_rmem14___Mmap2Stream_14___mmap_RDATA),
+    .s00_axi_rid(m_axi_rmem14___Mmap2Stream_14___mmap_RID),
+    .s00_axi_rlast(m_axi_rmem14___Mmap2Stream_14___mmap_RLAST),
+    .s00_axi_rready(m_axi_rmem14___Mmap2Stream_14___mmap_RREADY),
+    .s00_axi_rresp(m_axi_rmem14___Mmap2Stream_14___mmap_RRESP),
+    .s00_axi_rvalid(m_axi_rmem14___Mmap2Stream_14___mmap_RVALID),
+    .s00_axi_wdata(m_axi_rmem14___Mmap2Stream_14___mmap_WDATA),
+    .s00_axi_wlast(m_axi_rmem14___Mmap2Stream_14___mmap_WLAST),
+    .s00_axi_wready(m_axi_rmem14___Mmap2Stream_14___mmap_WREADY),
+    .s00_axi_wstrb(m_axi_rmem14___Mmap2Stream_14___mmap_WSTRB),
+    .s00_axi_wvalid(m_axi_rmem14___Mmap2Stream_14___mmap_WVALID),
+    .s01_axi_araddr(m_axi_rmem14___Stream2Mmap_14___mmap_ARADDR),
+    .s01_axi_arburst(m_axi_rmem14___Stream2Mmap_14___mmap_ARBURST),
+    .s01_axi_arcache(m_axi_rmem14___Stream2Mmap_14___mmap_ARCACHE),
+    .s01_axi_arid(m_axi_rmem14___Stream2Mmap_14___mmap_ARID),
+    .s01_axi_arlen(m_axi_rmem14___Stream2Mmap_14___mmap_ARLEN),
+    .s01_axi_arlock(m_axi_rmem14___Stream2Mmap_14___mmap_ARLOCK),
+    .s01_axi_arprot(m_axi_rmem14___Stream2Mmap_14___mmap_ARPROT),
+    .s01_axi_arqos(m_axi_rmem14___Stream2Mmap_14___mmap_ARQOS),
+    .s01_axi_arready(m_axi_rmem14___Stream2Mmap_14___mmap_ARREADY),
+    .s01_axi_arsize(m_axi_rmem14___Stream2Mmap_14___mmap_ARSIZE),
+    .s01_axi_arvalid(m_axi_rmem14___Stream2Mmap_14___mmap_ARVALID),
+    .s01_axi_awaddr(m_axi_rmem14___Stream2Mmap_14___mmap_AWADDR),
+    .s01_axi_awburst(m_axi_rmem14___Stream2Mmap_14___mmap_AWBURST),
+    .s01_axi_awcache(m_axi_rmem14___Stream2Mmap_14___mmap_AWCACHE),
+    .s01_axi_awid(m_axi_rmem14___Stream2Mmap_14___mmap_AWID),
+    .s01_axi_awlen(m_axi_rmem14___Stream2Mmap_14___mmap_AWLEN),
+    .s01_axi_awlock(m_axi_rmem14___Stream2Mmap_14___mmap_AWLOCK),
+    .s01_axi_awprot(m_axi_rmem14___Stream2Mmap_14___mmap_AWPROT),
+    .s01_axi_awqos(m_axi_rmem14___Stream2Mmap_14___mmap_AWQOS),
+    .s01_axi_awready(m_axi_rmem14___Stream2Mmap_14___mmap_AWREADY),
+    .s01_axi_awsize(m_axi_rmem14___Stream2Mmap_14___mmap_AWSIZE),
+    .s01_axi_awvalid(m_axi_rmem14___Stream2Mmap_14___mmap_AWVALID),
+    .s01_axi_bid(m_axi_rmem14___Stream2Mmap_14___mmap_BID),
+    .s01_axi_bready(m_axi_rmem14___Stream2Mmap_14___mmap_BREADY),
+    .s01_axi_bresp(m_axi_rmem14___Stream2Mmap_14___mmap_BRESP),
+    .s01_axi_bvalid(m_axi_rmem14___Stream2Mmap_14___mmap_BVALID),
+    .s01_axi_rdata(m_axi_rmem14___Stream2Mmap_14___mmap_RDATA),
+    .s01_axi_rid(m_axi_rmem14___Stream2Mmap_14___mmap_RID),
+    .s01_axi_rlast(m_axi_rmem14___Stream2Mmap_14___mmap_RLAST),
+    .s01_axi_rready(m_axi_rmem14___Stream2Mmap_14___mmap_RREADY),
+    .s01_axi_rresp(m_axi_rmem14___Stream2Mmap_14___mmap_RRESP),
+    .s01_axi_rvalid(m_axi_rmem14___Stream2Mmap_14___mmap_RVALID),
+    .s01_axi_wdata(m_axi_rmem14___Stream2Mmap_14___mmap_WDATA),
+    .s01_axi_wlast(m_axi_rmem14___Stream2Mmap_14___mmap_WLAST),
+    .s01_axi_wready(m_axi_rmem14___Stream2Mmap_14___mmap_WREADY),
+    .s01_axi_wstrb(m_axi_rmem14___Stream2Mmap_14___mmap_WSTRB),
+    .s01_axi_wvalid(m_axi_rmem14___Stream2Mmap_14___mmap_WVALID)
+  );
+
+
+  (* keep_hierarchy = "yes" *) axi_crossbar_2x1
+  #(
+    .DATA_WIDTH(512),
+    .ADDR_WIDTH(64),
+    .S_ID_WIDTH(1),
+    .M_ID_WIDTH(2),
+    .M00_ADDR_WIDTH(64),
+    .M00_ISSUE(16),
+    .S00_THREADS(1),
+    .S01_THREADS(1)
+  )
+  axi_crossbar_2x1__rmem15
+  (
+    .clk(ap_clk),
+    .rst(ap_rst_n_inv),
+    .m00_axi_araddr(m_axi_rmem15_ARADDR),
+    .m00_axi_arburst(m_axi_rmem15_ARBURST),
+    .m00_axi_arcache(m_axi_rmem15_ARCACHE),
+    .m00_axi_arid(m_axi_rmem15_ARID),
+    .m00_axi_arlen(m_axi_rmem15_ARLEN),
+    .m00_axi_arlock(m_axi_rmem15_ARLOCK),
+    .m00_axi_arprot(m_axi_rmem15_ARPROT),
+    .m00_axi_arqos(m_axi_rmem15_ARQOS),
+    .m00_axi_arready(m_axi_rmem15_ARREADY),
+    .m00_axi_arsize(m_axi_rmem15_ARSIZE),
+    .m00_axi_arvalid(m_axi_rmem15_ARVALID),
+    .m00_axi_awaddr(m_axi_rmem15_AWADDR),
+    .m00_axi_awburst(m_axi_rmem15_AWBURST),
+    .m00_axi_awcache(m_axi_rmem15_AWCACHE),
+    .m00_axi_awid(m_axi_rmem15_AWID),
+    .m00_axi_awlen(m_axi_rmem15_AWLEN),
+    .m00_axi_awlock(m_axi_rmem15_AWLOCK),
+    .m00_axi_awprot(m_axi_rmem15_AWPROT),
+    .m00_axi_awqos(m_axi_rmem15_AWQOS),
+    .m00_axi_awready(m_axi_rmem15_AWREADY),
+    .m00_axi_awsize(m_axi_rmem15_AWSIZE),
+    .m00_axi_awvalid(m_axi_rmem15_AWVALID),
+    .m00_axi_bid(m_axi_rmem15_BID),
+    .m00_axi_bready(m_axi_rmem15_BREADY),
+    .m00_axi_bresp(m_axi_rmem15_BRESP),
+    .m00_axi_bvalid(m_axi_rmem15_BVALID),
+    .m00_axi_rdata(m_axi_rmem15_RDATA),
+    .m00_axi_rid(m_axi_rmem15_RID),
+    .m00_axi_rlast(m_axi_rmem15_RLAST),
+    .m00_axi_rready(m_axi_rmem15_RREADY),
+    .m00_axi_rresp(m_axi_rmem15_RRESP),
+    .m00_axi_rvalid(m_axi_rmem15_RVALID),
+    .m00_axi_wdata(m_axi_rmem15_WDATA),
+    .m00_axi_wlast(m_axi_rmem15_WLAST),
+    .m00_axi_wready(m_axi_rmem15_WREADY),
+    .m00_axi_wstrb(m_axi_rmem15_WSTRB),
+    .m00_axi_wvalid(m_axi_rmem15_WVALID),
+    .s00_axi_araddr(m_axi_rmem15___Mmap2Stream_15___mmap_ARADDR),
+    .s00_axi_arburst(m_axi_rmem15___Mmap2Stream_15___mmap_ARBURST),
+    .s00_axi_arcache(m_axi_rmem15___Mmap2Stream_15___mmap_ARCACHE),
+    .s00_axi_arid(m_axi_rmem15___Mmap2Stream_15___mmap_ARID),
+    .s00_axi_arlen(m_axi_rmem15___Mmap2Stream_15___mmap_ARLEN),
+    .s00_axi_arlock(m_axi_rmem15___Mmap2Stream_15___mmap_ARLOCK),
+    .s00_axi_arprot(m_axi_rmem15___Mmap2Stream_15___mmap_ARPROT),
+    .s00_axi_arqos(m_axi_rmem15___Mmap2Stream_15___mmap_ARQOS),
+    .s00_axi_arready(m_axi_rmem15___Mmap2Stream_15___mmap_ARREADY),
+    .s00_axi_arsize(m_axi_rmem15___Mmap2Stream_15___mmap_ARSIZE),
+    .s00_axi_arvalid(m_axi_rmem15___Mmap2Stream_15___mmap_ARVALID),
+    .s00_axi_awaddr(m_axi_rmem15___Mmap2Stream_15___mmap_AWADDR),
+    .s00_axi_awburst(m_axi_rmem15___Mmap2Stream_15___mmap_AWBURST),
+    .s00_axi_awcache(m_axi_rmem15___Mmap2Stream_15___mmap_AWCACHE),
+    .s00_axi_awid(m_axi_rmem15___Mmap2Stream_15___mmap_AWID),
+    .s00_axi_awlen(m_axi_rmem15___Mmap2Stream_15___mmap_AWLEN),
+    .s00_axi_awlock(m_axi_rmem15___Mmap2Stream_15___mmap_AWLOCK),
+    .s00_axi_awprot(m_axi_rmem15___Mmap2Stream_15___mmap_AWPROT),
+    .s00_axi_awqos(m_axi_rmem15___Mmap2Stream_15___mmap_AWQOS),
+    .s00_axi_awready(m_axi_rmem15___Mmap2Stream_15___mmap_AWREADY),
+    .s00_axi_awsize(m_axi_rmem15___Mmap2Stream_15___mmap_AWSIZE),
+    .s00_axi_awvalid(m_axi_rmem15___Mmap2Stream_15___mmap_AWVALID),
+    .s00_axi_bid(m_axi_rmem15___Mmap2Stream_15___mmap_BID),
+    .s00_axi_bready(m_axi_rmem15___Mmap2Stream_15___mmap_BREADY),
+    .s00_axi_bresp(m_axi_rmem15___Mmap2Stream_15___mmap_BRESP),
+    .s00_axi_bvalid(m_axi_rmem15___Mmap2Stream_15___mmap_BVALID),
+    .s00_axi_rdata(m_axi_rmem15___Mmap2Stream_15___mmap_RDATA),
+    .s00_axi_rid(m_axi_rmem15___Mmap2Stream_15___mmap_RID),
+    .s00_axi_rlast(m_axi_rmem15___Mmap2Stream_15___mmap_RLAST),
+    .s00_axi_rready(m_axi_rmem15___Mmap2Stream_15___mmap_RREADY),
+    .s00_axi_rresp(m_axi_rmem15___Mmap2Stream_15___mmap_RRESP),
+    .s00_axi_rvalid(m_axi_rmem15___Mmap2Stream_15___mmap_RVALID),
+    .s00_axi_wdata(m_axi_rmem15___Mmap2Stream_15___mmap_WDATA),
+    .s00_axi_wlast(m_axi_rmem15___Mmap2Stream_15___mmap_WLAST),
+    .s00_axi_wready(m_axi_rmem15___Mmap2Stream_15___mmap_WREADY),
+    .s00_axi_wstrb(m_axi_rmem15___Mmap2Stream_15___mmap_WSTRB),
+    .s00_axi_wvalid(m_axi_rmem15___Mmap2Stream_15___mmap_WVALID),
+    .s01_axi_araddr(m_axi_rmem15___Stream2Mmap_15___mmap_ARADDR),
+    .s01_axi_arburst(m_axi_rmem15___Stream2Mmap_15___mmap_ARBURST),
+    .s01_axi_arcache(m_axi_rmem15___Stream2Mmap_15___mmap_ARCACHE),
+    .s01_axi_arid(m_axi_rmem15___Stream2Mmap_15___mmap_ARID),
+    .s01_axi_arlen(m_axi_rmem15___Stream2Mmap_15___mmap_ARLEN),
+    .s01_axi_arlock(m_axi_rmem15___Stream2Mmap_15___mmap_ARLOCK),
+    .s01_axi_arprot(m_axi_rmem15___Stream2Mmap_15___mmap_ARPROT),
+    .s01_axi_arqos(m_axi_rmem15___Stream2Mmap_15___mmap_ARQOS),
+    .s01_axi_arready(m_axi_rmem15___Stream2Mmap_15___mmap_ARREADY),
+    .s01_axi_arsize(m_axi_rmem15___Stream2Mmap_15___mmap_ARSIZE),
+    .s01_axi_arvalid(m_axi_rmem15___Stream2Mmap_15___mmap_ARVALID),
+    .s01_axi_awaddr(m_axi_rmem15___Stream2Mmap_15___mmap_AWADDR),
+    .s01_axi_awburst(m_axi_rmem15___Stream2Mmap_15___mmap_AWBURST),
+    .s01_axi_awcache(m_axi_rmem15___Stream2Mmap_15___mmap_AWCACHE),
+    .s01_axi_awid(m_axi_rmem15___Stream2Mmap_15___mmap_AWID),
+    .s01_axi_awlen(m_axi_rmem15___Stream2Mmap_15___mmap_AWLEN),
+    .s01_axi_awlock(m_axi_rmem15___Stream2Mmap_15___mmap_AWLOCK),
+    .s01_axi_awprot(m_axi_rmem15___Stream2Mmap_15___mmap_AWPROT),
+    .s01_axi_awqos(m_axi_rmem15___Stream2Mmap_15___mmap_AWQOS),
+    .s01_axi_awready(m_axi_rmem15___Stream2Mmap_15___mmap_AWREADY),
+    .s01_axi_awsize(m_axi_rmem15___Stream2Mmap_15___mmap_AWSIZE),
+    .s01_axi_awvalid(m_axi_rmem15___Stream2Mmap_15___mmap_AWVALID),
+    .s01_axi_bid(m_axi_rmem15___Stream2Mmap_15___mmap_BID),
+    .s01_axi_bready(m_axi_rmem15___Stream2Mmap_15___mmap_BREADY),
+    .s01_axi_bresp(m_axi_rmem15___Stream2Mmap_15___mmap_BRESP),
+    .s01_axi_bvalid(m_axi_rmem15___Stream2Mmap_15___mmap_BVALID),
+    .s01_axi_rdata(m_axi_rmem15___Stream2Mmap_15___mmap_RDATA),
+    .s01_axi_rid(m_axi_rmem15___Stream2Mmap_15___mmap_RID),
+    .s01_axi_rlast(m_axi_rmem15___Stream2Mmap_15___mmap_RLAST),
+    .s01_axi_rready(m_axi_rmem15___Stream2Mmap_15___mmap_RREADY),
+    .s01_axi_rresp(m_axi_rmem15___Stream2Mmap_15___mmap_RRESP),
+    .s01_axi_rvalid(m_axi_rmem15___Stream2Mmap_15___mmap_RVALID),
+    .s01_axi_wdata(m_axi_rmem15___Stream2Mmap_15___mmap_WDATA),
+    .s01_axi_wlast(m_axi_rmem15___Stream2Mmap_15___mmap_WLAST),
+    .s01_axi_wready(m_axi_rmem15___Stream2Mmap_15___mmap_WREADY),
+    .s01_axi_wstrb(m_axi_rmem15___Stream2Mmap_15___mmap_WSTRB),
+    .s01_axi_wvalid(m_axi_rmem15___Stream2Mmap_15___mmap_WVALID)
+  );
+
+
+  (* keep_hierarchy = "yes" *) axi_crossbar_2x1
+  #(
+    .DATA_WIDTH(512),
+    .ADDR_WIDTH(64),
+    .S_ID_WIDTH(1),
+    .M_ID_WIDTH(2),
+    .M00_ADDR_WIDTH(64),
+    .M00_ISSUE(16),
+    .S00_THREADS(1),
+    .S01_THREADS(1)
+  )
+  axi_crossbar_2x1__rmem16
+  (
+    .clk(ap_clk),
+    .rst(ap_rst_n_inv),
+    .m00_axi_araddr(m_axi_rmem16_ARADDR),
+    .m00_axi_arburst(m_axi_rmem16_ARBURST),
+    .m00_axi_arcache(m_axi_rmem16_ARCACHE),
+    .m00_axi_arid(m_axi_rmem16_ARID),
+    .m00_axi_arlen(m_axi_rmem16_ARLEN),
+    .m00_axi_arlock(m_axi_rmem16_ARLOCK),
+    .m00_axi_arprot(m_axi_rmem16_ARPROT),
+    .m00_axi_arqos(m_axi_rmem16_ARQOS),
+    .m00_axi_arready(m_axi_rmem16_ARREADY),
+    .m00_axi_arsize(m_axi_rmem16_ARSIZE),
+    .m00_axi_arvalid(m_axi_rmem16_ARVALID),
+    .m00_axi_awaddr(m_axi_rmem16_AWADDR),
+    .m00_axi_awburst(m_axi_rmem16_AWBURST),
+    .m00_axi_awcache(m_axi_rmem16_AWCACHE),
+    .m00_axi_awid(m_axi_rmem16_AWID),
+    .m00_axi_awlen(m_axi_rmem16_AWLEN),
+    .m00_axi_awlock(m_axi_rmem16_AWLOCK),
+    .m00_axi_awprot(m_axi_rmem16_AWPROT),
+    .m00_axi_awqos(m_axi_rmem16_AWQOS),
+    .m00_axi_awready(m_axi_rmem16_AWREADY),
+    .m00_axi_awsize(m_axi_rmem16_AWSIZE),
+    .m00_axi_awvalid(m_axi_rmem16_AWVALID),
+    .m00_axi_bid(m_axi_rmem16_BID),
+    .m00_axi_bready(m_axi_rmem16_BREADY),
+    .m00_axi_bresp(m_axi_rmem16_BRESP),
+    .m00_axi_bvalid(m_axi_rmem16_BVALID),
+    .m00_axi_rdata(m_axi_rmem16_RDATA),
+    .m00_axi_rid(m_axi_rmem16_RID),
+    .m00_axi_rlast(m_axi_rmem16_RLAST),
+    .m00_axi_rready(m_axi_rmem16_RREADY),
+    .m00_axi_rresp(m_axi_rmem16_RRESP),
+    .m00_axi_rvalid(m_axi_rmem16_RVALID),
+    .m00_axi_wdata(m_axi_rmem16_WDATA),
+    .m00_axi_wlast(m_axi_rmem16_WLAST),
+    .m00_axi_wready(m_axi_rmem16_WREADY),
+    .m00_axi_wstrb(m_axi_rmem16_WSTRB),
+    .m00_axi_wvalid(m_axi_rmem16_WVALID),
+    .s00_axi_araddr(m_axi_rmem16___Mmap2Stream_16___mmap_ARADDR),
+    .s00_axi_arburst(m_axi_rmem16___Mmap2Stream_16___mmap_ARBURST),
+    .s00_axi_arcache(m_axi_rmem16___Mmap2Stream_16___mmap_ARCACHE),
+    .s00_axi_arid(m_axi_rmem16___Mmap2Stream_16___mmap_ARID),
+    .s00_axi_arlen(m_axi_rmem16___Mmap2Stream_16___mmap_ARLEN),
+    .s00_axi_arlock(m_axi_rmem16___Mmap2Stream_16___mmap_ARLOCK),
+    .s00_axi_arprot(m_axi_rmem16___Mmap2Stream_16___mmap_ARPROT),
+    .s00_axi_arqos(m_axi_rmem16___Mmap2Stream_16___mmap_ARQOS),
+    .s00_axi_arready(m_axi_rmem16___Mmap2Stream_16___mmap_ARREADY),
+    .s00_axi_arsize(m_axi_rmem16___Mmap2Stream_16___mmap_ARSIZE),
+    .s00_axi_arvalid(m_axi_rmem16___Mmap2Stream_16___mmap_ARVALID),
+    .s00_axi_awaddr(m_axi_rmem16___Mmap2Stream_16___mmap_AWADDR),
+    .s00_axi_awburst(m_axi_rmem16___Mmap2Stream_16___mmap_AWBURST),
+    .s00_axi_awcache(m_axi_rmem16___Mmap2Stream_16___mmap_AWCACHE),
+    .s00_axi_awid(m_axi_rmem16___Mmap2Stream_16___mmap_AWID),
+    .s00_axi_awlen(m_axi_rmem16___Mmap2Stream_16___mmap_AWLEN),
+    .s00_axi_awlock(m_axi_rmem16___Mmap2Stream_16___mmap_AWLOCK),
+    .s00_axi_awprot(m_axi_rmem16___Mmap2Stream_16___mmap_AWPROT),
+    .s00_axi_awqos(m_axi_rmem16___Mmap2Stream_16___mmap_AWQOS),
+    .s00_axi_awready(m_axi_rmem16___Mmap2Stream_16___mmap_AWREADY),
+    .s00_axi_awsize(m_axi_rmem16___Mmap2Stream_16___mmap_AWSIZE),
+    .s00_axi_awvalid(m_axi_rmem16___Mmap2Stream_16___mmap_AWVALID),
+    .s00_axi_bid(m_axi_rmem16___Mmap2Stream_16___mmap_BID),
+    .s00_axi_bready(m_axi_rmem16___Mmap2Stream_16___mmap_BREADY),
+    .s00_axi_bresp(m_axi_rmem16___Mmap2Stream_16___mmap_BRESP),
+    .s00_axi_bvalid(m_axi_rmem16___Mmap2Stream_16___mmap_BVALID),
+    .s00_axi_rdata(m_axi_rmem16___Mmap2Stream_16___mmap_RDATA),
+    .s00_axi_rid(m_axi_rmem16___Mmap2Stream_16___mmap_RID),
+    .s00_axi_rlast(m_axi_rmem16___Mmap2Stream_16___mmap_RLAST),
+    .s00_axi_rready(m_axi_rmem16___Mmap2Stream_16___mmap_RREADY),
+    .s00_axi_rresp(m_axi_rmem16___Mmap2Stream_16___mmap_RRESP),
+    .s00_axi_rvalid(m_axi_rmem16___Mmap2Stream_16___mmap_RVALID),
+    .s00_axi_wdata(m_axi_rmem16___Mmap2Stream_16___mmap_WDATA),
+    .s00_axi_wlast(m_axi_rmem16___Mmap2Stream_16___mmap_WLAST),
+    .s00_axi_wready(m_axi_rmem16___Mmap2Stream_16___mmap_WREADY),
+    .s00_axi_wstrb(m_axi_rmem16___Mmap2Stream_16___mmap_WSTRB),
+    .s00_axi_wvalid(m_axi_rmem16___Mmap2Stream_16___mmap_WVALID),
+    .s01_axi_araddr(m_axi_rmem16___Stream2Mmap_16___mmap_ARADDR),
+    .s01_axi_arburst(m_axi_rmem16___Stream2Mmap_16___mmap_ARBURST),
+    .s01_axi_arcache(m_axi_rmem16___Stream2Mmap_16___mmap_ARCACHE),
+    .s01_axi_arid(m_axi_rmem16___Stream2Mmap_16___mmap_ARID),
+    .s01_axi_arlen(m_axi_rmem16___Stream2Mmap_16___mmap_ARLEN),
+    .s01_axi_arlock(m_axi_rmem16___Stream2Mmap_16___mmap_ARLOCK),
+    .s01_axi_arprot(m_axi_rmem16___Stream2Mmap_16___mmap_ARPROT),
+    .s01_axi_arqos(m_axi_rmem16___Stream2Mmap_16___mmap_ARQOS),
+    .s01_axi_arready(m_axi_rmem16___Stream2Mmap_16___mmap_ARREADY),
+    .s01_axi_arsize(m_axi_rmem16___Stream2Mmap_16___mmap_ARSIZE),
+    .s01_axi_arvalid(m_axi_rmem16___Stream2Mmap_16___mmap_ARVALID),
+    .s01_axi_awaddr(m_axi_rmem16___Stream2Mmap_16___mmap_AWADDR),
+    .s01_axi_awburst(m_axi_rmem16___Stream2Mmap_16___mmap_AWBURST),
+    .s01_axi_awcache(m_axi_rmem16___Stream2Mmap_16___mmap_AWCACHE),
+    .s01_axi_awid(m_axi_rmem16___Stream2Mmap_16___mmap_AWID),
+    .s01_axi_awlen(m_axi_rmem16___Stream2Mmap_16___mmap_AWLEN),
+    .s01_axi_awlock(m_axi_rmem16___Stream2Mmap_16___mmap_AWLOCK),
+    .s01_axi_awprot(m_axi_rmem16___Stream2Mmap_16___mmap_AWPROT),
+    .s01_axi_awqos(m_axi_rmem16___Stream2Mmap_16___mmap_AWQOS),
+    .s01_axi_awready(m_axi_rmem16___Stream2Mmap_16___mmap_AWREADY),
+    .s01_axi_awsize(m_axi_rmem16___Stream2Mmap_16___mmap_AWSIZE),
+    .s01_axi_awvalid(m_axi_rmem16___Stream2Mmap_16___mmap_AWVALID),
+    .s01_axi_bid(m_axi_rmem16___Stream2Mmap_16___mmap_BID),
+    .s01_axi_bready(m_axi_rmem16___Stream2Mmap_16___mmap_BREADY),
+    .s01_axi_bresp(m_axi_rmem16___Stream2Mmap_16___mmap_BRESP),
+    .s01_axi_bvalid(m_axi_rmem16___Stream2Mmap_16___mmap_BVALID),
+    .s01_axi_rdata(m_axi_rmem16___Stream2Mmap_16___mmap_RDATA),
+    .s01_axi_rid(m_axi_rmem16___Stream2Mmap_16___mmap_RID),
+    .s01_axi_rlast(m_axi_rmem16___Stream2Mmap_16___mmap_RLAST),
+    .s01_axi_rready(m_axi_rmem16___Stream2Mmap_16___mmap_RREADY),
+    .s01_axi_rresp(m_axi_rmem16___Stream2Mmap_16___mmap_RRESP),
+    .s01_axi_rvalid(m_axi_rmem16___Stream2Mmap_16___mmap_RVALID),
+    .s01_axi_wdata(m_axi_rmem16___Stream2Mmap_16___mmap_WDATA),
+    .s01_axi_wlast(m_axi_rmem16___Stream2Mmap_16___mmap_WLAST),
+    .s01_axi_wready(m_axi_rmem16___Stream2Mmap_16___mmap_WREADY),
+    .s01_axi_wstrb(m_axi_rmem16___Stream2Mmap_16___mmap_WSTRB),
+    .s01_axi_wvalid(m_axi_rmem16___Stream2Mmap_16___mmap_WVALID)
+  );
+
+
+  (* keep_hierarchy = "yes" *) axi_crossbar_2x1
+  #(
+    .DATA_WIDTH(512),
+    .ADDR_WIDTH(64),
+    .S_ID_WIDTH(1),
+    .M_ID_WIDTH(2),
+    .M00_ADDR_WIDTH(64),
+    .M00_ISSUE(16),
+    .S00_THREADS(1),
+    .S01_THREADS(1)
+  )
+  axi_crossbar_2x1__rmem17
+  (
+    .clk(ap_clk),
+    .rst(ap_rst_n_inv),
+    .m00_axi_araddr(m_axi_rmem17_ARADDR),
+    .m00_axi_arburst(m_axi_rmem17_ARBURST),
+    .m00_axi_arcache(m_axi_rmem17_ARCACHE),
+    .m00_axi_arid(m_axi_rmem17_ARID),
+    .m00_axi_arlen(m_axi_rmem17_ARLEN),
+    .m00_axi_arlock(m_axi_rmem17_ARLOCK),
+    .m00_axi_arprot(m_axi_rmem17_ARPROT),
+    .m00_axi_arqos(m_axi_rmem17_ARQOS),
+    .m00_axi_arready(m_axi_rmem17_ARREADY),
+    .m00_axi_arsize(m_axi_rmem17_ARSIZE),
+    .m00_axi_arvalid(m_axi_rmem17_ARVALID),
+    .m00_axi_awaddr(m_axi_rmem17_AWADDR),
+    .m00_axi_awburst(m_axi_rmem17_AWBURST),
+    .m00_axi_awcache(m_axi_rmem17_AWCACHE),
+    .m00_axi_awid(m_axi_rmem17_AWID),
+    .m00_axi_awlen(m_axi_rmem17_AWLEN),
+    .m00_axi_awlock(m_axi_rmem17_AWLOCK),
+    .m00_axi_awprot(m_axi_rmem17_AWPROT),
+    .m00_axi_awqos(m_axi_rmem17_AWQOS),
+    .m00_axi_awready(m_axi_rmem17_AWREADY),
+    .m00_axi_awsize(m_axi_rmem17_AWSIZE),
+    .m00_axi_awvalid(m_axi_rmem17_AWVALID),
+    .m00_axi_bid(m_axi_rmem17_BID),
+    .m00_axi_bready(m_axi_rmem17_BREADY),
+    .m00_axi_bresp(m_axi_rmem17_BRESP),
+    .m00_axi_bvalid(m_axi_rmem17_BVALID),
+    .m00_axi_rdata(m_axi_rmem17_RDATA),
+    .m00_axi_rid(m_axi_rmem17_RID),
+    .m00_axi_rlast(m_axi_rmem17_RLAST),
+    .m00_axi_rready(m_axi_rmem17_RREADY),
+    .m00_axi_rresp(m_axi_rmem17_RRESP),
+    .m00_axi_rvalid(m_axi_rmem17_RVALID),
+    .m00_axi_wdata(m_axi_rmem17_WDATA),
+    .m00_axi_wlast(m_axi_rmem17_WLAST),
+    .m00_axi_wready(m_axi_rmem17_WREADY),
+    .m00_axi_wstrb(m_axi_rmem17_WSTRB),
+    .m00_axi_wvalid(m_axi_rmem17_WVALID),
+    .s00_axi_araddr(m_axi_rmem17___Mmap2Stream_17___mmap_ARADDR),
+    .s00_axi_arburst(m_axi_rmem17___Mmap2Stream_17___mmap_ARBURST),
+    .s00_axi_arcache(m_axi_rmem17___Mmap2Stream_17___mmap_ARCACHE),
+    .s00_axi_arid(m_axi_rmem17___Mmap2Stream_17___mmap_ARID),
+    .s00_axi_arlen(m_axi_rmem17___Mmap2Stream_17___mmap_ARLEN),
+    .s00_axi_arlock(m_axi_rmem17___Mmap2Stream_17___mmap_ARLOCK),
+    .s00_axi_arprot(m_axi_rmem17___Mmap2Stream_17___mmap_ARPROT),
+    .s00_axi_arqos(m_axi_rmem17___Mmap2Stream_17___mmap_ARQOS),
+    .s00_axi_arready(m_axi_rmem17___Mmap2Stream_17___mmap_ARREADY),
+    .s00_axi_arsize(m_axi_rmem17___Mmap2Stream_17___mmap_ARSIZE),
+    .s00_axi_arvalid(m_axi_rmem17___Mmap2Stream_17___mmap_ARVALID),
+    .s00_axi_awaddr(m_axi_rmem17___Mmap2Stream_17___mmap_AWADDR),
+    .s00_axi_awburst(m_axi_rmem17___Mmap2Stream_17___mmap_AWBURST),
+    .s00_axi_awcache(m_axi_rmem17___Mmap2Stream_17___mmap_AWCACHE),
+    .s00_axi_awid(m_axi_rmem17___Mmap2Stream_17___mmap_AWID),
+    .s00_axi_awlen(m_axi_rmem17___Mmap2Stream_17___mmap_AWLEN),
+    .s00_axi_awlock(m_axi_rmem17___Mmap2Stream_17___mmap_AWLOCK),
+    .s00_axi_awprot(m_axi_rmem17___Mmap2Stream_17___mmap_AWPROT),
+    .s00_axi_awqos(m_axi_rmem17___Mmap2Stream_17___mmap_AWQOS),
+    .s00_axi_awready(m_axi_rmem17___Mmap2Stream_17___mmap_AWREADY),
+    .s00_axi_awsize(m_axi_rmem17___Mmap2Stream_17___mmap_AWSIZE),
+    .s00_axi_awvalid(m_axi_rmem17___Mmap2Stream_17___mmap_AWVALID),
+    .s00_axi_bid(m_axi_rmem17___Mmap2Stream_17___mmap_BID),
+    .s00_axi_bready(m_axi_rmem17___Mmap2Stream_17___mmap_BREADY),
+    .s00_axi_bresp(m_axi_rmem17___Mmap2Stream_17___mmap_BRESP),
+    .s00_axi_bvalid(m_axi_rmem17___Mmap2Stream_17___mmap_BVALID),
+    .s00_axi_rdata(m_axi_rmem17___Mmap2Stream_17___mmap_RDATA),
+    .s00_axi_rid(m_axi_rmem17___Mmap2Stream_17___mmap_RID),
+    .s00_axi_rlast(m_axi_rmem17___Mmap2Stream_17___mmap_RLAST),
+    .s00_axi_rready(m_axi_rmem17___Mmap2Stream_17___mmap_RREADY),
+    .s00_axi_rresp(m_axi_rmem17___Mmap2Stream_17___mmap_RRESP),
+    .s00_axi_rvalid(m_axi_rmem17___Mmap2Stream_17___mmap_RVALID),
+    .s00_axi_wdata(m_axi_rmem17___Mmap2Stream_17___mmap_WDATA),
+    .s00_axi_wlast(m_axi_rmem17___Mmap2Stream_17___mmap_WLAST),
+    .s00_axi_wready(m_axi_rmem17___Mmap2Stream_17___mmap_WREADY),
+    .s00_axi_wstrb(m_axi_rmem17___Mmap2Stream_17___mmap_WSTRB),
+    .s00_axi_wvalid(m_axi_rmem17___Mmap2Stream_17___mmap_WVALID),
+    .s01_axi_araddr(m_axi_rmem17___Stream2Mmap_17___mmap_ARADDR),
+    .s01_axi_arburst(m_axi_rmem17___Stream2Mmap_17___mmap_ARBURST),
+    .s01_axi_arcache(m_axi_rmem17___Stream2Mmap_17___mmap_ARCACHE),
+    .s01_axi_arid(m_axi_rmem17___Stream2Mmap_17___mmap_ARID),
+    .s01_axi_arlen(m_axi_rmem17___Stream2Mmap_17___mmap_ARLEN),
+    .s01_axi_arlock(m_axi_rmem17___Stream2Mmap_17___mmap_ARLOCK),
+    .s01_axi_arprot(m_axi_rmem17___Stream2Mmap_17___mmap_ARPROT),
+    .s01_axi_arqos(m_axi_rmem17___Stream2Mmap_17___mmap_ARQOS),
+    .s01_axi_arready(m_axi_rmem17___Stream2Mmap_17___mmap_ARREADY),
+    .s01_axi_arsize(m_axi_rmem17___Stream2Mmap_17___mmap_ARSIZE),
+    .s01_axi_arvalid(m_axi_rmem17___Stream2Mmap_17___mmap_ARVALID),
+    .s01_axi_awaddr(m_axi_rmem17___Stream2Mmap_17___mmap_AWADDR),
+    .s01_axi_awburst(m_axi_rmem17___Stream2Mmap_17___mmap_AWBURST),
+    .s01_axi_awcache(m_axi_rmem17___Stream2Mmap_17___mmap_AWCACHE),
+    .s01_axi_awid(m_axi_rmem17___Stream2Mmap_17___mmap_AWID),
+    .s01_axi_awlen(m_axi_rmem17___Stream2Mmap_17___mmap_AWLEN),
+    .s01_axi_awlock(m_axi_rmem17___Stream2Mmap_17___mmap_AWLOCK),
+    .s01_axi_awprot(m_axi_rmem17___Stream2Mmap_17___mmap_AWPROT),
+    .s01_axi_awqos(m_axi_rmem17___Stream2Mmap_17___mmap_AWQOS),
+    .s01_axi_awready(m_axi_rmem17___Stream2Mmap_17___mmap_AWREADY),
+    .s01_axi_awsize(m_axi_rmem17___Stream2Mmap_17___mmap_AWSIZE),
+    .s01_axi_awvalid(m_axi_rmem17___Stream2Mmap_17___mmap_AWVALID),
+    .s01_axi_bid(m_axi_rmem17___Stream2Mmap_17___mmap_BID),
+    .s01_axi_bready(m_axi_rmem17___Stream2Mmap_17___mmap_BREADY),
+    .s01_axi_bresp(m_axi_rmem17___Stream2Mmap_17___mmap_BRESP),
+    .s01_axi_bvalid(m_axi_rmem17___Stream2Mmap_17___mmap_BVALID),
+    .s01_axi_rdata(m_axi_rmem17___Stream2Mmap_17___mmap_RDATA),
+    .s01_axi_rid(m_axi_rmem17___Stream2Mmap_17___mmap_RID),
+    .s01_axi_rlast(m_axi_rmem17___Stream2Mmap_17___mmap_RLAST),
+    .s01_axi_rready(m_axi_rmem17___Stream2Mmap_17___mmap_RREADY),
+    .s01_axi_rresp(m_axi_rmem17___Stream2Mmap_17___mmap_RRESP),
+    .s01_axi_rvalid(m_axi_rmem17___Stream2Mmap_17___mmap_RVALID),
+    .s01_axi_wdata(m_axi_rmem17___Stream2Mmap_17___mmap_WDATA),
+    .s01_axi_wlast(m_axi_rmem17___Stream2Mmap_17___mmap_WLAST),
+    .s01_axi_wready(m_axi_rmem17___Stream2Mmap_17___mmap_WREADY),
+    .s01_axi_wstrb(m_axi_rmem17___Stream2Mmap_17___mmap_WSTRB),
+    .s01_axi_wvalid(m_axi_rmem17___Stream2Mmap_17___mmap_WVALID)
+  );
+
+
+  (* keep_hierarchy = "yes" *) axi_crossbar_2x1
+  #(
+    .DATA_WIDTH(512),
+    .ADDR_WIDTH(64),
+    .S_ID_WIDTH(1),
+    .M_ID_WIDTH(2),
+    .M00_ADDR_WIDTH(64),
+    .M00_ISSUE(16),
+    .S00_THREADS(1),
+    .S01_THREADS(1)
+  )
+  axi_crossbar_2x1__rmem18
+  (
+    .clk(ap_clk),
+    .rst(ap_rst_n_inv),
+    .m00_axi_araddr(m_axi_rmem18_ARADDR),
+    .m00_axi_arburst(m_axi_rmem18_ARBURST),
+    .m00_axi_arcache(m_axi_rmem18_ARCACHE),
+    .m00_axi_arid(m_axi_rmem18_ARID),
+    .m00_axi_arlen(m_axi_rmem18_ARLEN),
+    .m00_axi_arlock(m_axi_rmem18_ARLOCK),
+    .m00_axi_arprot(m_axi_rmem18_ARPROT),
+    .m00_axi_arqos(m_axi_rmem18_ARQOS),
+    .m00_axi_arready(m_axi_rmem18_ARREADY),
+    .m00_axi_arsize(m_axi_rmem18_ARSIZE),
+    .m00_axi_arvalid(m_axi_rmem18_ARVALID),
+    .m00_axi_awaddr(m_axi_rmem18_AWADDR),
+    .m00_axi_awburst(m_axi_rmem18_AWBURST),
+    .m00_axi_awcache(m_axi_rmem18_AWCACHE),
+    .m00_axi_awid(m_axi_rmem18_AWID),
+    .m00_axi_awlen(m_axi_rmem18_AWLEN),
+    .m00_axi_awlock(m_axi_rmem18_AWLOCK),
+    .m00_axi_awprot(m_axi_rmem18_AWPROT),
+    .m00_axi_awqos(m_axi_rmem18_AWQOS),
+    .m00_axi_awready(m_axi_rmem18_AWREADY),
+    .m00_axi_awsize(m_axi_rmem18_AWSIZE),
+    .m00_axi_awvalid(m_axi_rmem18_AWVALID),
+    .m00_axi_bid(m_axi_rmem18_BID),
+    .m00_axi_bready(m_axi_rmem18_BREADY),
+    .m00_axi_bresp(m_axi_rmem18_BRESP),
+    .m00_axi_bvalid(m_axi_rmem18_BVALID),
+    .m00_axi_rdata(m_axi_rmem18_RDATA),
+    .m00_axi_rid(m_axi_rmem18_RID),
+    .m00_axi_rlast(m_axi_rmem18_RLAST),
+    .m00_axi_rready(m_axi_rmem18_RREADY),
+    .m00_axi_rresp(m_axi_rmem18_RRESP),
+    .m00_axi_rvalid(m_axi_rmem18_RVALID),
+    .m00_axi_wdata(m_axi_rmem18_WDATA),
+    .m00_axi_wlast(m_axi_rmem18_WLAST),
+    .m00_axi_wready(m_axi_rmem18_WREADY),
+    .m00_axi_wstrb(m_axi_rmem18_WSTRB),
+    .m00_axi_wvalid(m_axi_rmem18_WVALID),
+    .s00_axi_araddr(m_axi_rmem18___Mmap2Stream_18___mmap_ARADDR),
+    .s00_axi_arburst(m_axi_rmem18___Mmap2Stream_18___mmap_ARBURST),
+    .s00_axi_arcache(m_axi_rmem18___Mmap2Stream_18___mmap_ARCACHE),
+    .s00_axi_arid(m_axi_rmem18___Mmap2Stream_18___mmap_ARID),
+    .s00_axi_arlen(m_axi_rmem18___Mmap2Stream_18___mmap_ARLEN),
+    .s00_axi_arlock(m_axi_rmem18___Mmap2Stream_18___mmap_ARLOCK),
+    .s00_axi_arprot(m_axi_rmem18___Mmap2Stream_18___mmap_ARPROT),
+    .s00_axi_arqos(m_axi_rmem18___Mmap2Stream_18___mmap_ARQOS),
+    .s00_axi_arready(m_axi_rmem18___Mmap2Stream_18___mmap_ARREADY),
+    .s00_axi_arsize(m_axi_rmem18___Mmap2Stream_18___mmap_ARSIZE),
+    .s00_axi_arvalid(m_axi_rmem18___Mmap2Stream_18___mmap_ARVALID),
+    .s00_axi_awaddr(m_axi_rmem18___Mmap2Stream_18___mmap_AWADDR),
+    .s00_axi_awburst(m_axi_rmem18___Mmap2Stream_18___mmap_AWBURST),
+    .s00_axi_awcache(m_axi_rmem18___Mmap2Stream_18___mmap_AWCACHE),
+    .s00_axi_awid(m_axi_rmem18___Mmap2Stream_18___mmap_AWID),
+    .s00_axi_awlen(m_axi_rmem18___Mmap2Stream_18___mmap_AWLEN),
+    .s00_axi_awlock(m_axi_rmem18___Mmap2Stream_18___mmap_AWLOCK),
+    .s00_axi_awprot(m_axi_rmem18___Mmap2Stream_18___mmap_AWPROT),
+    .s00_axi_awqos(m_axi_rmem18___Mmap2Stream_18___mmap_AWQOS),
+    .s00_axi_awready(m_axi_rmem18___Mmap2Stream_18___mmap_AWREADY),
+    .s00_axi_awsize(m_axi_rmem18___Mmap2Stream_18___mmap_AWSIZE),
+    .s00_axi_awvalid(m_axi_rmem18___Mmap2Stream_18___mmap_AWVALID),
+    .s00_axi_bid(m_axi_rmem18___Mmap2Stream_18___mmap_BID),
+    .s00_axi_bready(m_axi_rmem18___Mmap2Stream_18___mmap_BREADY),
+    .s00_axi_bresp(m_axi_rmem18___Mmap2Stream_18___mmap_BRESP),
+    .s00_axi_bvalid(m_axi_rmem18___Mmap2Stream_18___mmap_BVALID),
+    .s00_axi_rdata(m_axi_rmem18___Mmap2Stream_18___mmap_RDATA),
+    .s00_axi_rid(m_axi_rmem18___Mmap2Stream_18___mmap_RID),
+    .s00_axi_rlast(m_axi_rmem18___Mmap2Stream_18___mmap_RLAST),
+    .s00_axi_rready(m_axi_rmem18___Mmap2Stream_18___mmap_RREADY),
+    .s00_axi_rresp(m_axi_rmem18___Mmap2Stream_18___mmap_RRESP),
+    .s00_axi_rvalid(m_axi_rmem18___Mmap2Stream_18___mmap_RVALID),
+    .s00_axi_wdata(m_axi_rmem18___Mmap2Stream_18___mmap_WDATA),
+    .s00_axi_wlast(m_axi_rmem18___Mmap2Stream_18___mmap_WLAST),
+    .s00_axi_wready(m_axi_rmem18___Mmap2Stream_18___mmap_WREADY),
+    .s00_axi_wstrb(m_axi_rmem18___Mmap2Stream_18___mmap_WSTRB),
+    .s00_axi_wvalid(m_axi_rmem18___Mmap2Stream_18___mmap_WVALID),
+    .s01_axi_araddr(m_axi_rmem18___Stream2Mmap_18___mmap_ARADDR),
+    .s01_axi_arburst(m_axi_rmem18___Stream2Mmap_18___mmap_ARBURST),
+    .s01_axi_arcache(m_axi_rmem18___Stream2Mmap_18___mmap_ARCACHE),
+    .s01_axi_arid(m_axi_rmem18___Stream2Mmap_18___mmap_ARID),
+    .s01_axi_arlen(m_axi_rmem18___Stream2Mmap_18___mmap_ARLEN),
+    .s01_axi_arlock(m_axi_rmem18___Stream2Mmap_18___mmap_ARLOCK),
+    .s01_axi_arprot(m_axi_rmem18___Stream2Mmap_18___mmap_ARPROT),
+    .s01_axi_arqos(m_axi_rmem18___Stream2Mmap_18___mmap_ARQOS),
+    .s01_axi_arready(m_axi_rmem18___Stream2Mmap_18___mmap_ARREADY),
+    .s01_axi_arsize(m_axi_rmem18___Stream2Mmap_18___mmap_ARSIZE),
+    .s01_axi_arvalid(m_axi_rmem18___Stream2Mmap_18___mmap_ARVALID),
+    .s01_axi_awaddr(m_axi_rmem18___Stream2Mmap_18___mmap_AWADDR),
+    .s01_axi_awburst(m_axi_rmem18___Stream2Mmap_18___mmap_AWBURST),
+    .s01_axi_awcache(m_axi_rmem18___Stream2Mmap_18___mmap_AWCACHE),
+    .s01_axi_awid(m_axi_rmem18___Stream2Mmap_18___mmap_AWID),
+    .s01_axi_awlen(m_axi_rmem18___Stream2Mmap_18___mmap_AWLEN),
+    .s01_axi_awlock(m_axi_rmem18___Stream2Mmap_18___mmap_AWLOCK),
+    .s01_axi_awprot(m_axi_rmem18___Stream2Mmap_18___mmap_AWPROT),
+    .s01_axi_awqos(m_axi_rmem18___Stream2Mmap_18___mmap_AWQOS),
+    .s01_axi_awready(m_axi_rmem18___Stream2Mmap_18___mmap_AWREADY),
+    .s01_axi_awsize(m_axi_rmem18___Stream2Mmap_18___mmap_AWSIZE),
+    .s01_axi_awvalid(m_axi_rmem18___Stream2Mmap_18___mmap_AWVALID),
+    .s01_axi_bid(m_axi_rmem18___Stream2Mmap_18___mmap_BID),
+    .s01_axi_bready(m_axi_rmem18___Stream2Mmap_18___mmap_BREADY),
+    .s01_axi_bresp(m_axi_rmem18___Stream2Mmap_18___mmap_BRESP),
+    .s01_axi_bvalid(m_axi_rmem18___Stream2Mmap_18___mmap_BVALID),
+    .s01_axi_rdata(m_axi_rmem18___Stream2Mmap_18___mmap_RDATA),
+    .s01_axi_rid(m_axi_rmem18___Stream2Mmap_18___mmap_RID),
+    .s01_axi_rlast(m_axi_rmem18___Stream2Mmap_18___mmap_RLAST),
+    .s01_axi_rready(m_axi_rmem18___Stream2Mmap_18___mmap_RREADY),
+    .s01_axi_rresp(m_axi_rmem18___Stream2Mmap_18___mmap_RRESP),
+    .s01_axi_rvalid(m_axi_rmem18___Stream2Mmap_18___mmap_RVALID),
+    .s01_axi_wdata(m_axi_rmem18___Stream2Mmap_18___mmap_WDATA),
+    .s01_axi_wlast(m_axi_rmem18___Stream2Mmap_18___mmap_WLAST),
+    .s01_axi_wready(m_axi_rmem18___Stream2Mmap_18___mmap_WREADY),
+    .s01_axi_wstrb(m_axi_rmem18___Stream2Mmap_18___mmap_WSTRB),
+    .s01_axi_wvalid(m_axi_rmem18___Stream2Mmap_18___mmap_WVALID)
+  );
+
+
+  (* keep_hierarchy = "yes" *) axi_crossbar_2x1
+  #(
+    .DATA_WIDTH(512),
+    .ADDR_WIDTH(64),
+    .S_ID_WIDTH(1),
+    .M_ID_WIDTH(2),
+    .M00_ADDR_WIDTH(64),
+    .M00_ISSUE(16),
+    .S00_THREADS(1),
+    .S01_THREADS(1)
+  )
+  axi_crossbar_2x1__rmem19
+  (
+    .clk(ap_clk),
+    .rst(ap_rst_n_inv),
+    .m00_axi_araddr(m_axi_rmem19_ARADDR),
+    .m00_axi_arburst(m_axi_rmem19_ARBURST),
+    .m00_axi_arcache(m_axi_rmem19_ARCACHE),
+    .m00_axi_arid(m_axi_rmem19_ARID),
+    .m00_axi_arlen(m_axi_rmem19_ARLEN),
+    .m00_axi_arlock(m_axi_rmem19_ARLOCK),
+    .m00_axi_arprot(m_axi_rmem19_ARPROT),
+    .m00_axi_arqos(m_axi_rmem19_ARQOS),
+    .m00_axi_arready(m_axi_rmem19_ARREADY),
+    .m00_axi_arsize(m_axi_rmem19_ARSIZE),
+    .m00_axi_arvalid(m_axi_rmem19_ARVALID),
+    .m00_axi_awaddr(m_axi_rmem19_AWADDR),
+    .m00_axi_awburst(m_axi_rmem19_AWBURST),
+    .m00_axi_awcache(m_axi_rmem19_AWCACHE),
+    .m00_axi_awid(m_axi_rmem19_AWID),
+    .m00_axi_awlen(m_axi_rmem19_AWLEN),
+    .m00_axi_awlock(m_axi_rmem19_AWLOCK),
+    .m00_axi_awprot(m_axi_rmem19_AWPROT),
+    .m00_axi_awqos(m_axi_rmem19_AWQOS),
+    .m00_axi_awready(m_axi_rmem19_AWREADY),
+    .m00_axi_awsize(m_axi_rmem19_AWSIZE),
+    .m00_axi_awvalid(m_axi_rmem19_AWVALID),
+    .m00_axi_bid(m_axi_rmem19_BID),
+    .m00_axi_bready(m_axi_rmem19_BREADY),
+    .m00_axi_bresp(m_axi_rmem19_BRESP),
+    .m00_axi_bvalid(m_axi_rmem19_BVALID),
+    .m00_axi_rdata(m_axi_rmem19_RDATA),
+    .m00_axi_rid(m_axi_rmem19_RID),
+    .m00_axi_rlast(m_axi_rmem19_RLAST),
+    .m00_axi_rready(m_axi_rmem19_RREADY),
+    .m00_axi_rresp(m_axi_rmem19_RRESP),
+    .m00_axi_rvalid(m_axi_rmem19_RVALID),
+    .m00_axi_wdata(m_axi_rmem19_WDATA),
+    .m00_axi_wlast(m_axi_rmem19_WLAST),
+    .m00_axi_wready(m_axi_rmem19_WREADY),
+    .m00_axi_wstrb(m_axi_rmem19_WSTRB),
+    .m00_axi_wvalid(m_axi_rmem19_WVALID),
+    .s00_axi_araddr(m_axi_rmem19___Mmap2Stream_19___mmap_ARADDR),
+    .s00_axi_arburst(m_axi_rmem19___Mmap2Stream_19___mmap_ARBURST),
+    .s00_axi_arcache(m_axi_rmem19___Mmap2Stream_19___mmap_ARCACHE),
+    .s00_axi_arid(m_axi_rmem19___Mmap2Stream_19___mmap_ARID),
+    .s00_axi_arlen(m_axi_rmem19___Mmap2Stream_19___mmap_ARLEN),
+    .s00_axi_arlock(m_axi_rmem19___Mmap2Stream_19___mmap_ARLOCK),
+    .s00_axi_arprot(m_axi_rmem19___Mmap2Stream_19___mmap_ARPROT),
+    .s00_axi_arqos(m_axi_rmem19___Mmap2Stream_19___mmap_ARQOS),
+    .s00_axi_arready(m_axi_rmem19___Mmap2Stream_19___mmap_ARREADY),
+    .s00_axi_arsize(m_axi_rmem19___Mmap2Stream_19___mmap_ARSIZE),
+    .s00_axi_arvalid(m_axi_rmem19___Mmap2Stream_19___mmap_ARVALID),
+    .s00_axi_awaddr(m_axi_rmem19___Mmap2Stream_19___mmap_AWADDR),
+    .s00_axi_awburst(m_axi_rmem19___Mmap2Stream_19___mmap_AWBURST),
+    .s00_axi_awcache(m_axi_rmem19___Mmap2Stream_19___mmap_AWCACHE),
+    .s00_axi_awid(m_axi_rmem19___Mmap2Stream_19___mmap_AWID),
+    .s00_axi_awlen(m_axi_rmem19___Mmap2Stream_19___mmap_AWLEN),
+    .s00_axi_awlock(m_axi_rmem19___Mmap2Stream_19___mmap_AWLOCK),
+    .s00_axi_awprot(m_axi_rmem19___Mmap2Stream_19___mmap_AWPROT),
+    .s00_axi_awqos(m_axi_rmem19___Mmap2Stream_19___mmap_AWQOS),
+    .s00_axi_awready(m_axi_rmem19___Mmap2Stream_19___mmap_AWREADY),
+    .s00_axi_awsize(m_axi_rmem19___Mmap2Stream_19___mmap_AWSIZE),
+    .s00_axi_awvalid(m_axi_rmem19___Mmap2Stream_19___mmap_AWVALID),
+    .s00_axi_bid(m_axi_rmem19___Mmap2Stream_19___mmap_BID),
+    .s00_axi_bready(m_axi_rmem19___Mmap2Stream_19___mmap_BREADY),
+    .s00_axi_bresp(m_axi_rmem19___Mmap2Stream_19___mmap_BRESP),
+    .s00_axi_bvalid(m_axi_rmem19___Mmap2Stream_19___mmap_BVALID),
+    .s00_axi_rdata(m_axi_rmem19___Mmap2Stream_19___mmap_RDATA),
+    .s00_axi_rid(m_axi_rmem19___Mmap2Stream_19___mmap_RID),
+    .s00_axi_rlast(m_axi_rmem19___Mmap2Stream_19___mmap_RLAST),
+    .s00_axi_rready(m_axi_rmem19___Mmap2Stream_19___mmap_RREADY),
+    .s00_axi_rresp(m_axi_rmem19___Mmap2Stream_19___mmap_RRESP),
+    .s00_axi_rvalid(m_axi_rmem19___Mmap2Stream_19___mmap_RVALID),
+    .s00_axi_wdata(m_axi_rmem19___Mmap2Stream_19___mmap_WDATA),
+    .s00_axi_wlast(m_axi_rmem19___Mmap2Stream_19___mmap_WLAST),
+    .s00_axi_wready(m_axi_rmem19___Mmap2Stream_19___mmap_WREADY),
+    .s00_axi_wstrb(m_axi_rmem19___Mmap2Stream_19___mmap_WSTRB),
+    .s00_axi_wvalid(m_axi_rmem19___Mmap2Stream_19___mmap_WVALID),
+    .s01_axi_araddr(m_axi_rmem19___Stream2Mmap_19___mmap_ARADDR),
+    .s01_axi_arburst(m_axi_rmem19___Stream2Mmap_19___mmap_ARBURST),
+    .s01_axi_arcache(m_axi_rmem19___Stream2Mmap_19___mmap_ARCACHE),
+    .s01_axi_arid(m_axi_rmem19___Stream2Mmap_19___mmap_ARID),
+    .s01_axi_arlen(m_axi_rmem19___Stream2Mmap_19___mmap_ARLEN),
+    .s01_axi_arlock(m_axi_rmem19___Stream2Mmap_19___mmap_ARLOCK),
+    .s01_axi_arprot(m_axi_rmem19___Stream2Mmap_19___mmap_ARPROT),
+    .s01_axi_arqos(m_axi_rmem19___Stream2Mmap_19___mmap_ARQOS),
+    .s01_axi_arready(m_axi_rmem19___Stream2Mmap_19___mmap_ARREADY),
+    .s01_axi_arsize(m_axi_rmem19___Stream2Mmap_19___mmap_ARSIZE),
+    .s01_axi_arvalid(m_axi_rmem19___Stream2Mmap_19___mmap_ARVALID),
+    .s01_axi_awaddr(m_axi_rmem19___Stream2Mmap_19___mmap_AWADDR),
+    .s01_axi_awburst(m_axi_rmem19___Stream2Mmap_19___mmap_AWBURST),
+    .s01_axi_awcache(m_axi_rmem19___Stream2Mmap_19___mmap_AWCACHE),
+    .s01_axi_awid(m_axi_rmem19___Stream2Mmap_19___mmap_AWID),
+    .s01_axi_awlen(m_axi_rmem19___Stream2Mmap_19___mmap_AWLEN),
+    .s01_axi_awlock(m_axi_rmem19___Stream2Mmap_19___mmap_AWLOCK),
+    .s01_axi_awprot(m_axi_rmem19___Stream2Mmap_19___mmap_AWPROT),
+    .s01_axi_awqos(m_axi_rmem19___Stream2Mmap_19___mmap_AWQOS),
+    .s01_axi_awready(m_axi_rmem19___Stream2Mmap_19___mmap_AWREADY),
+    .s01_axi_awsize(m_axi_rmem19___Stream2Mmap_19___mmap_AWSIZE),
+    .s01_axi_awvalid(m_axi_rmem19___Stream2Mmap_19___mmap_AWVALID),
+    .s01_axi_bid(m_axi_rmem19___Stream2Mmap_19___mmap_BID),
+    .s01_axi_bready(m_axi_rmem19___Stream2Mmap_19___mmap_BREADY),
+    .s01_axi_bresp(m_axi_rmem19___Stream2Mmap_19___mmap_BRESP),
+    .s01_axi_bvalid(m_axi_rmem19___Stream2Mmap_19___mmap_BVALID),
+    .s01_axi_rdata(m_axi_rmem19___Stream2Mmap_19___mmap_RDATA),
+    .s01_axi_rid(m_axi_rmem19___Stream2Mmap_19___mmap_RID),
+    .s01_axi_rlast(m_axi_rmem19___Stream2Mmap_19___mmap_RLAST),
+    .s01_axi_rready(m_axi_rmem19___Stream2Mmap_19___mmap_RREADY),
+    .s01_axi_rresp(m_axi_rmem19___Stream2Mmap_19___mmap_RRESP),
+    .s01_axi_rvalid(m_axi_rmem19___Stream2Mmap_19___mmap_RVALID),
+    .s01_axi_wdata(m_axi_rmem19___Stream2Mmap_19___mmap_WDATA),
+    .s01_axi_wlast(m_axi_rmem19___Stream2Mmap_19___mmap_WLAST),
+    .s01_axi_wready(m_axi_rmem19___Stream2Mmap_19___mmap_WREADY),
+    .s01_axi_wstrb(m_axi_rmem19___Stream2Mmap_19___mmap_WSTRB),
+    .s01_axi_wvalid(m_axi_rmem19___Stream2Mmap_19___mmap_WVALID)
+  );
+
+
+  (* keep_hierarchy = "yes" *) axi_crossbar_2x1
+  #(
+    .DATA_WIDTH(512),
+    .ADDR_WIDTH(64),
+    .S_ID_WIDTH(1),
+    .M_ID_WIDTH(2),
+    .M00_ADDR_WIDTH(64),
+    .M00_ISSUE(16),
+    .S00_THREADS(1),
+    .S01_THREADS(1)
+  )
+  axi_crossbar_2x1__rmem20
+  (
+    .clk(ap_clk),
+    .rst(ap_rst_n_inv),
+    .m00_axi_araddr(m_axi_rmem20_ARADDR),
+    .m00_axi_arburst(m_axi_rmem20_ARBURST),
+    .m00_axi_arcache(m_axi_rmem20_ARCACHE),
+    .m00_axi_arid(m_axi_rmem20_ARID),
+    .m00_axi_arlen(m_axi_rmem20_ARLEN),
+    .m00_axi_arlock(m_axi_rmem20_ARLOCK),
+    .m00_axi_arprot(m_axi_rmem20_ARPROT),
+    .m00_axi_arqos(m_axi_rmem20_ARQOS),
+    .m00_axi_arready(m_axi_rmem20_ARREADY),
+    .m00_axi_arsize(m_axi_rmem20_ARSIZE),
+    .m00_axi_arvalid(m_axi_rmem20_ARVALID),
+    .m00_axi_awaddr(m_axi_rmem20_AWADDR),
+    .m00_axi_awburst(m_axi_rmem20_AWBURST),
+    .m00_axi_awcache(m_axi_rmem20_AWCACHE),
+    .m00_axi_awid(m_axi_rmem20_AWID),
+    .m00_axi_awlen(m_axi_rmem20_AWLEN),
+    .m00_axi_awlock(m_axi_rmem20_AWLOCK),
+    .m00_axi_awprot(m_axi_rmem20_AWPROT),
+    .m00_axi_awqos(m_axi_rmem20_AWQOS),
+    .m00_axi_awready(m_axi_rmem20_AWREADY),
+    .m00_axi_awsize(m_axi_rmem20_AWSIZE),
+    .m00_axi_awvalid(m_axi_rmem20_AWVALID),
+    .m00_axi_bid(m_axi_rmem20_BID),
+    .m00_axi_bready(m_axi_rmem20_BREADY),
+    .m00_axi_bresp(m_axi_rmem20_BRESP),
+    .m00_axi_bvalid(m_axi_rmem20_BVALID),
+    .m00_axi_rdata(m_axi_rmem20_RDATA),
+    .m00_axi_rid(m_axi_rmem20_RID),
+    .m00_axi_rlast(m_axi_rmem20_RLAST),
+    .m00_axi_rready(m_axi_rmem20_RREADY),
+    .m00_axi_rresp(m_axi_rmem20_RRESP),
+    .m00_axi_rvalid(m_axi_rmem20_RVALID),
+    .m00_axi_wdata(m_axi_rmem20_WDATA),
+    .m00_axi_wlast(m_axi_rmem20_WLAST),
+    .m00_axi_wready(m_axi_rmem20_WREADY),
+    .m00_axi_wstrb(m_axi_rmem20_WSTRB),
+    .m00_axi_wvalid(m_axi_rmem20_WVALID),
+    .s00_axi_araddr(m_axi_rmem20___Mmap2Stream_20___mmap_ARADDR),
+    .s00_axi_arburst(m_axi_rmem20___Mmap2Stream_20___mmap_ARBURST),
+    .s00_axi_arcache(m_axi_rmem20___Mmap2Stream_20___mmap_ARCACHE),
+    .s00_axi_arid(m_axi_rmem20___Mmap2Stream_20___mmap_ARID),
+    .s00_axi_arlen(m_axi_rmem20___Mmap2Stream_20___mmap_ARLEN),
+    .s00_axi_arlock(m_axi_rmem20___Mmap2Stream_20___mmap_ARLOCK),
+    .s00_axi_arprot(m_axi_rmem20___Mmap2Stream_20___mmap_ARPROT),
+    .s00_axi_arqos(m_axi_rmem20___Mmap2Stream_20___mmap_ARQOS),
+    .s00_axi_arready(m_axi_rmem20___Mmap2Stream_20___mmap_ARREADY),
+    .s00_axi_arsize(m_axi_rmem20___Mmap2Stream_20___mmap_ARSIZE),
+    .s00_axi_arvalid(m_axi_rmem20___Mmap2Stream_20___mmap_ARVALID),
+    .s00_axi_awaddr(m_axi_rmem20___Mmap2Stream_20___mmap_AWADDR),
+    .s00_axi_awburst(m_axi_rmem20___Mmap2Stream_20___mmap_AWBURST),
+    .s00_axi_awcache(m_axi_rmem20___Mmap2Stream_20___mmap_AWCACHE),
+    .s00_axi_awid(m_axi_rmem20___Mmap2Stream_20___mmap_AWID),
+    .s00_axi_awlen(m_axi_rmem20___Mmap2Stream_20___mmap_AWLEN),
+    .s00_axi_awlock(m_axi_rmem20___Mmap2Stream_20___mmap_AWLOCK),
+    .s00_axi_awprot(m_axi_rmem20___Mmap2Stream_20___mmap_AWPROT),
+    .s00_axi_awqos(m_axi_rmem20___Mmap2Stream_20___mmap_AWQOS),
+    .s00_axi_awready(m_axi_rmem20___Mmap2Stream_20___mmap_AWREADY),
+    .s00_axi_awsize(m_axi_rmem20___Mmap2Stream_20___mmap_AWSIZE),
+    .s00_axi_awvalid(m_axi_rmem20___Mmap2Stream_20___mmap_AWVALID),
+    .s00_axi_bid(m_axi_rmem20___Mmap2Stream_20___mmap_BID),
+    .s00_axi_bready(m_axi_rmem20___Mmap2Stream_20___mmap_BREADY),
+    .s00_axi_bresp(m_axi_rmem20___Mmap2Stream_20___mmap_BRESP),
+    .s00_axi_bvalid(m_axi_rmem20___Mmap2Stream_20___mmap_BVALID),
+    .s00_axi_rdata(m_axi_rmem20___Mmap2Stream_20___mmap_RDATA),
+    .s00_axi_rid(m_axi_rmem20___Mmap2Stream_20___mmap_RID),
+    .s00_axi_rlast(m_axi_rmem20___Mmap2Stream_20___mmap_RLAST),
+    .s00_axi_rready(m_axi_rmem20___Mmap2Stream_20___mmap_RREADY),
+    .s00_axi_rresp(m_axi_rmem20___Mmap2Stream_20___mmap_RRESP),
+    .s00_axi_rvalid(m_axi_rmem20___Mmap2Stream_20___mmap_RVALID),
+    .s00_axi_wdata(m_axi_rmem20___Mmap2Stream_20___mmap_WDATA),
+    .s00_axi_wlast(m_axi_rmem20___Mmap2Stream_20___mmap_WLAST),
+    .s00_axi_wready(m_axi_rmem20___Mmap2Stream_20___mmap_WREADY),
+    .s00_axi_wstrb(m_axi_rmem20___Mmap2Stream_20___mmap_WSTRB),
+    .s00_axi_wvalid(m_axi_rmem20___Mmap2Stream_20___mmap_WVALID),
+    .s01_axi_araddr(m_axi_rmem20___Stream2Mmap_20___mmap_ARADDR),
+    .s01_axi_arburst(m_axi_rmem20___Stream2Mmap_20___mmap_ARBURST),
+    .s01_axi_arcache(m_axi_rmem20___Stream2Mmap_20___mmap_ARCACHE),
+    .s01_axi_arid(m_axi_rmem20___Stream2Mmap_20___mmap_ARID),
+    .s01_axi_arlen(m_axi_rmem20___Stream2Mmap_20___mmap_ARLEN),
+    .s01_axi_arlock(m_axi_rmem20___Stream2Mmap_20___mmap_ARLOCK),
+    .s01_axi_arprot(m_axi_rmem20___Stream2Mmap_20___mmap_ARPROT),
+    .s01_axi_arqos(m_axi_rmem20___Stream2Mmap_20___mmap_ARQOS),
+    .s01_axi_arready(m_axi_rmem20___Stream2Mmap_20___mmap_ARREADY),
+    .s01_axi_arsize(m_axi_rmem20___Stream2Mmap_20___mmap_ARSIZE),
+    .s01_axi_arvalid(m_axi_rmem20___Stream2Mmap_20___mmap_ARVALID),
+    .s01_axi_awaddr(m_axi_rmem20___Stream2Mmap_20___mmap_AWADDR),
+    .s01_axi_awburst(m_axi_rmem20___Stream2Mmap_20___mmap_AWBURST),
+    .s01_axi_awcache(m_axi_rmem20___Stream2Mmap_20___mmap_AWCACHE),
+    .s01_axi_awid(m_axi_rmem20___Stream2Mmap_20___mmap_AWID),
+    .s01_axi_awlen(m_axi_rmem20___Stream2Mmap_20___mmap_AWLEN),
+    .s01_axi_awlock(m_axi_rmem20___Stream2Mmap_20___mmap_AWLOCK),
+    .s01_axi_awprot(m_axi_rmem20___Stream2Mmap_20___mmap_AWPROT),
+    .s01_axi_awqos(m_axi_rmem20___Stream2Mmap_20___mmap_AWQOS),
+    .s01_axi_awready(m_axi_rmem20___Stream2Mmap_20___mmap_AWREADY),
+    .s01_axi_awsize(m_axi_rmem20___Stream2Mmap_20___mmap_AWSIZE),
+    .s01_axi_awvalid(m_axi_rmem20___Stream2Mmap_20___mmap_AWVALID),
+    .s01_axi_bid(m_axi_rmem20___Stream2Mmap_20___mmap_BID),
+    .s01_axi_bready(m_axi_rmem20___Stream2Mmap_20___mmap_BREADY),
+    .s01_axi_bresp(m_axi_rmem20___Stream2Mmap_20___mmap_BRESP),
+    .s01_axi_bvalid(m_axi_rmem20___Stream2Mmap_20___mmap_BVALID),
+    .s01_axi_rdata(m_axi_rmem20___Stream2Mmap_20___mmap_RDATA),
+    .s01_axi_rid(m_axi_rmem20___Stream2Mmap_20___mmap_RID),
+    .s01_axi_rlast(m_axi_rmem20___Stream2Mmap_20___mmap_RLAST),
+    .s01_axi_rready(m_axi_rmem20___Stream2Mmap_20___mmap_RREADY),
+    .s01_axi_rresp(m_axi_rmem20___Stream2Mmap_20___mmap_RRESP),
+    .s01_axi_rvalid(m_axi_rmem20___Stream2Mmap_20___mmap_RVALID),
+    .s01_axi_wdata(m_axi_rmem20___Stream2Mmap_20___mmap_WDATA),
+    .s01_axi_wlast(m_axi_rmem20___Stream2Mmap_20___mmap_WLAST),
+    .s01_axi_wready(m_axi_rmem20___Stream2Mmap_20___mmap_WREADY),
+    .s01_axi_wstrb(m_axi_rmem20___Stream2Mmap_20___mmap_WSTRB),
+    .s01_axi_wvalid(m_axi_rmem20___Stream2Mmap_20___mmap_WVALID)
+  );
+
+
+  (* keep_hierarchy = "yes" *) axi_crossbar_2x1
+  #(
+    .DATA_WIDTH(512),
+    .ADDR_WIDTH(64),
+    .S_ID_WIDTH(1),
+    .M_ID_WIDTH(2),
+    .M00_ADDR_WIDTH(64),
+    .M00_ISSUE(16),
+    .S00_THREADS(1),
+    .S01_THREADS(1)
+  )
+  axi_crossbar_2x1__rmem21
+  (
+    .clk(ap_clk),
+    .rst(ap_rst_n_inv),
+    .m00_axi_araddr(m_axi_rmem21_ARADDR),
+    .m00_axi_arburst(m_axi_rmem21_ARBURST),
+    .m00_axi_arcache(m_axi_rmem21_ARCACHE),
+    .m00_axi_arid(m_axi_rmem21_ARID),
+    .m00_axi_arlen(m_axi_rmem21_ARLEN),
+    .m00_axi_arlock(m_axi_rmem21_ARLOCK),
+    .m00_axi_arprot(m_axi_rmem21_ARPROT),
+    .m00_axi_arqos(m_axi_rmem21_ARQOS),
+    .m00_axi_arready(m_axi_rmem21_ARREADY),
+    .m00_axi_arsize(m_axi_rmem21_ARSIZE),
+    .m00_axi_arvalid(m_axi_rmem21_ARVALID),
+    .m00_axi_awaddr(m_axi_rmem21_AWADDR),
+    .m00_axi_awburst(m_axi_rmem21_AWBURST),
+    .m00_axi_awcache(m_axi_rmem21_AWCACHE),
+    .m00_axi_awid(m_axi_rmem21_AWID),
+    .m00_axi_awlen(m_axi_rmem21_AWLEN),
+    .m00_axi_awlock(m_axi_rmem21_AWLOCK),
+    .m00_axi_awprot(m_axi_rmem21_AWPROT),
+    .m00_axi_awqos(m_axi_rmem21_AWQOS),
+    .m00_axi_awready(m_axi_rmem21_AWREADY),
+    .m00_axi_awsize(m_axi_rmem21_AWSIZE),
+    .m00_axi_awvalid(m_axi_rmem21_AWVALID),
+    .m00_axi_bid(m_axi_rmem21_BID),
+    .m00_axi_bready(m_axi_rmem21_BREADY),
+    .m00_axi_bresp(m_axi_rmem21_BRESP),
+    .m00_axi_bvalid(m_axi_rmem21_BVALID),
+    .m00_axi_rdata(m_axi_rmem21_RDATA),
+    .m00_axi_rid(m_axi_rmem21_RID),
+    .m00_axi_rlast(m_axi_rmem21_RLAST),
+    .m00_axi_rready(m_axi_rmem21_RREADY),
+    .m00_axi_rresp(m_axi_rmem21_RRESP),
+    .m00_axi_rvalid(m_axi_rmem21_RVALID),
+    .m00_axi_wdata(m_axi_rmem21_WDATA),
+    .m00_axi_wlast(m_axi_rmem21_WLAST),
+    .m00_axi_wready(m_axi_rmem21_WREADY),
+    .m00_axi_wstrb(m_axi_rmem21_WSTRB),
+    .m00_axi_wvalid(m_axi_rmem21_WVALID),
+    .s00_axi_araddr(m_axi_rmem21___Mmap2Stream_21___mmap_ARADDR),
+    .s00_axi_arburst(m_axi_rmem21___Mmap2Stream_21___mmap_ARBURST),
+    .s00_axi_arcache(m_axi_rmem21___Mmap2Stream_21___mmap_ARCACHE),
+    .s00_axi_arid(m_axi_rmem21___Mmap2Stream_21___mmap_ARID),
+    .s00_axi_arlen(m_axi_rmem21___Mmap2Stream_21___mmap_ARLEN),
+    .s00_axi_arlock(m_axi_rmem21___Mmap2Stream_21___mmap_ARLOCK),
+    .s00_axi_arprot(m_axi_rmem21___Mmap2Stream_21___mmap_ARPROT),
+    .s00_axi_arqos(m_axi_rmem21___Mmap2Stream_21___mmap_ARQOS),
+    .s00_axi_arready(m_axi_rmem21___Mmap2Stream_21___mmap_ARREADY),
+    .s00_axi_arsize(m_axi_rmem21___Mmap2Stream_21___mmap_ARSIZE),
+    .s00_axi_arvalid(m_axi_rmem21___Mmap2Stream_21___mmap_ARVALID),
+    .s00_axi_awaddr(m_axi_rmem21___Mmap2Stream_21___mmap_AWADDR),
+    .s00_axi_awburst(m_axi_rmem21___Mmap2Stream_21___mmap_AWBURST),
+    .s00_axi_awcache(m_axi_rmem21___Mmap2Stream_21___mmap_AWCACHE),
+    .s00_axi_awid(m_axi_rmem21___Mmap2Stream_21___mmap_AWID),
+    .s00_axi_awlen(m_axi_rmem21___Mmap2Stream_21___mmap_AWLEN),
+    .s00_axi_awlock(m_axi_rmem21___Mmap2Stream_21___mmap_AWLOCK),
+    .s00_axi_awprot(m_axi_rmem21___Mmap2Stream_21___mmap_AWPROT),
+    .s00_axi_awqos(m_axi_rmem21___Mmap2Stream_21___mmap_AWQOS),
+    .s00_axi_awready(m_axi_rmem21___Mmap2Stream_21___mmap_AWREADY),
+    .s00_axi_awsize(m_axi_rmem21___Mmap2Stream_21___mmap_AWSIZE),
+    .s00_axi_awvalid(m_axi_rmem21___Mmap2Stream_21___mmap_AWVALID),
+    .s00_axi_bid(m_axi_rmem21___Mmap2Stream_21___mmap_BID),
+    .s00_axi_bready(m_axi_rmem21___Mmap2Stream_21___mmap_BREADY),
+    .s00_axi_bresp(m_axi_rmem21___Mmap2Stream_21___mmap_BRESP),
+    .s00_axi_bvalid(m_axi_rmem21___Mmap2Stream_21___mmap_BVALID),
+    .s00_axi_rdata(m_axi_rmem21___Mmap2Stream_21___mmap_RDATA),
+    .s00_axi_rid(m_axi_rmem21___Mmap2Stream_21___mmap_RID),
+    .s00_axi_rlast(m_axi_rmem21___Mmap2Stream_21___mmap_RLAST),
+    .s00_axi_rready(m_axi_rmem21___Mmap2Stream_21___mmap_RREADY),
+    .s00_axi_rresp(m_axi_rmem21___Mmap2Stream_21___mmap_RRESP),
+    .s00_axi_rvalid(m_axi_rmem21___Mmap2Stream_21___mmap_RVALID),
+    .s00_axi_wdata(m_axi_rmem21___Mmap2Stream_21___mmap_WDATA),
+    .s00_axi_wlast(m_axi_rmem21___Mmap2Stream_21___mmap_WLAST),
+    .s00_axi_wready(m_axi_rmem21___Mmap2Stream_21___mmap_WREADY),
+    .s00_axi_wstrb(m_axi_rmem21___Mmap2Stream_21___mmap_WSTRB),
+    .s00_axi_wvalid(m_axi_rmem21___Mmap2Stream_21___mmap_WVALID),
+    .s01_axi_araddr(m_axi_rmem21___Stream2Mmap_21___mmap_ARADDR),
+    .s01_axi_arburst(m_axi_rmem21___Stream2Mmap_21___mmap_ARBURST),
+    .s01_axi_arcache(m_axi_rmem21___Stream2Mmap_21___mmap_ARCACHE),
+    .s01_axi_arid(m_axi_rmem21___Stream2Mmap_21___mmap_ARID),
+    .s01_axi_arlen(m_axi_rmem21___Stream2Mmap_21___mmap_ARLEN),
+    .s01_axi_arlock(m_axi_rmem21___Stream2Mmap_21___mmap_ARLOCK),
+    .s01_axi_arprot(m_axi_rmem21___Stream2Mmap_21___mmap_ARPROT),
+    .s01_axi_arqos(m_axi_rmem21___Stream2Mmap_21___mmap_ARQOS),
+    .s01_axi_arready(m_axi_rmem21___Stream2Mmap_21___mmap_ARREADY),
+    .s01_axi_arsize(m_axi_rmem21___Stream2Mmap_21___mmap_ARSIZE),
+    .s01_axi_arvalid(m_axi_rmem21___Stream2Mmap_21___mmap_ARVALID),
+    .s01_axi_awaddr(m_axi_rmem21___Stream2Mmap_21___mmap_AWADDR),
+    .s01_axi_awburst(m_axi_rmem21___Stream2Mmap_21___mmap_AWBURST),
+    .s01_axi_awcache(m_axi_rmem21___Stream2Mmap_21___mmap_AWCACHE),
+    .s01_axi_awid(m_axi_rmem21___Stream2Mmap_21___mmap_AWID),
+    .s01_axi_awlen(m_axi_rmem21___Stream2Mmap_21___mmap_AWLEN),
+    .s01_axi_awlock(m_axi_rmem21___Stream2Mmap_21___mmap_AWLOCK),
+    .s01_axi_awprot(m_axi_rmem21___Stream2Mmap_21___mmap_AWPROT),
+    .s01_axi_awqos(m_axi_rmem21___Stream2Mmap_21___mmap_AWQOS),
+    .s01_axi_awready(m_axi_rmem21___Stream2Mmap_21___mmap_AWREADY),
+    .s01_axi_awsize(m_axi_rmem21___Stream2Mmap_21___mmap_AWSIZE),
+    .s01_axi_awvalid(m_axi_rmem21___Stream2Mmap_21___mmap_AWVALID),
+    .s01_axi_bid(m_axi_rmem21___Stream2Mmap_21___mmap_BID),
+    .s01_axi_bready(m_axi_rmem21___Stream2Mmap_21___mmap_BREADY),
+    .s01_axi_bresp(m_axi_rmem21___Stream2Mmap_21___mmap_BRESP),
+    .s01_axi_bvalid(m_axi_rmem21___Stream2Mmap_21___mmap_BVALID),
+    .s01_axi_rdata(m_axi_rmem21___Stream2Mmap_21___mmap_RDATA),
+    .s01_axi_rid(m_axi_rmem21___Stream2Mmap_21___mmap_RID),
+    .s01_axi_rlast(m_axi_rmem21___Stream2Mmap_21___mmap_RLAST),
+    .s01_axi_rready(m_axi_rmem21___Stream2Mmap_21___mmap_RREADY),
+    .s01_axi_rresp(m_axi_rmem21___Stream2Mmap_21___mmap_RRESP),
+    .s01_axi_rvalid(m_axi_rmem21___Stream2Mmap_21___mmap_RVALID),
+    .s01_axi_wdata(m_axi_rmem21___Stream2Mmap_21___mmap_WDATA),
+    .s01_axi_wlast(m_axi_rmem21___Stream2Mmap_21___mmap_WLAST),
+    .s01_axi_wready(m_axi_rmem21___Stream2Mmap_21___mmap_WREADY),
+    .s01_axi_wstrb(m_axi_rmem21___Stream2Mmap_21___mmap_WSTRB),
+    .s01_axi_wvalid(m_axi_rmem21___Stream2Mmap_21___mmap_WVALID)
+  );
+
+
+  (* keep_hierarchy = "yes" *) axi_crossbar_2x1
+  #(
+    .DATA_WIDTH(512),
+    .ADDR_WIDTH(64),
+    .S_ID_WIDTH(1),
+    .M_ID_WIDTH(2),
+    .M00_ADDR_WIDTH(64),
+    .M00_ISSUE(16),
+    .S00_THREADS(1),
+    .S01_THREADS(1)
+  )
+  axi_crossbar_2x1__rmem22
+  (
+    .clk(ap_clk),
+    .rst(ap_rst_n_inv),
+    .m00_axi_araddr(m_axi_rmem22_ARADDR),
+    .m00_axi_arburst(m_axi_rmem22_ARBURST),
+    .m00_axi_arcache(m_axi_rmem22_ARCACHE),
+    .m00_axi_arid(m_axi_rmem22_ARID),
+    .m00_axi_arlen(m_axi_rmem22_ARLEN),
+    .m00_axi_arlock(m_axi_rmem22_ARLOCK),
+    .m00_axi_arprot(m_axi_rmem22_ARPROT),
+    .m00_axi_arqos(m_axi_rmem22_ARQOS),
+    .m00_axi_arready(m_axi_rmem22_ARREADY),
+    .m00_axi_arsize(m_axi_rmem22_ARSIZE),
+    .m00_axi_arvalid(m_axi_rmem22_ARVALID),
+    .m00_axi_awaddr(m_axi_rmem22_AWADDR),
+    .m00_axi_awburst(m_axi_rmem22_AWBURST),
+    .m00_axi_awcache(m_axi_rmem22_AWCACHE),
+    .m00_axi_awid(m_axi_rmem22_AWID),
+    .m00_axi_awlen(m_axi_rmem22_AWLEN),
+    .m00_axi_awlock(m_axi_rmem22_AWLOCK),
+    .m00_axi_awprot(m_axi_rmem22_AWPROT),
+    .m00_axi_awqos(m_axi_rmem22_AWQOS),
+    .m00_axi_awready(m_axi_rmem22_AWREADY),
+    .m00_axi_awsize(m_axi_rmem22_AWSIZE),
+    .m00_axi_awvalid(m_axi_rmem22_AWVALID),
+    .m00_axi_bid(m_axi_rmem22_BID),
+    .m00_axi_bready(m_axi_rmem22_BREADY),
+    .m00_axi_bresp(m_axi_rmem22_BRESP),
+    .m00_axi_bvalid(m_axi_rmem22_BVALID),
+    .m00_axi_rdata(m_axi_rmem22_RDATA),
+    .m00_axi_rid(m_axi_rmem22_RID),
+    .m00_axi_rlast(m_axi_rmem22_RLAST),
+    .m00_axi_rready(m_axi_rmem22_RREADY),
+    .m00_axi_rresp(m_axi_rmem22_RRESP),
+    .m00_axi_rvalid(m_axi_rmem22_RVALID),
+    .m00_axi_wdata(m_axi_rmem22_WDATA),
+    .m00_axi_wlast(m_axi_rmem22_WLAST),
+    .m00_axi_wready(m_axi_rmem22_WREADY),
+    .m00_axi_wstrb(m_axi_rmem22_WSTRB),
+    .m00_axi_wvalid(m_axi_rmem22_WVALID),
+    .s00_axi_araddr(m_axi_rmem22___Mmap2Stream_22___mmap_ARADDR),
+    .s00_axi_arburst(m_axi_rmem22___Mmap2Stream_22___mmap_ARBURST),
+    .s00_axi_arcache(m_axi_rmem22___Mmap2Stream_22___mmap_ARCACHE),
+    .s00_axi_arid(m_axi_rmem22___Mmap2Stream_22___mmap_ARID),
+    .s00_axi_arlen(m_axi_rmem22___Mmap2Stream_22___mmap_ARLEN),
+    .s00_axi_arlock(m_axi_rmem22___Mmap2Stream_22___mmap_ARLOCK),
+    .s00_axi_arprot(m_axi_rmem22___Mmap2Stream_22___mmap_ARPROT),
+    .s00_axi_arqos(m_axi_rmem22___Mmap2Stream_22___mmap_ARQOS),
+    .s00_axi_arready(m_axi_rmem22___Mmap2Stream_22___mmap_ARREADY),
+    .s00_axi_arsize(m_axi_rmem22___Mmap2Stream_22___mmap_ARSIZE),
+    .s00_axi_arvalid(m_axi_rmem22___Mmap2Stream_22___mmap_ARVALID),
+    .s00_axi_awaddr(m_axi_rmem22___Mmap2Stream_22___mmap_AWADDR),
+    .s00_axi_awburst(m_axi_rmem22___Mmap2Stream_22___mmap_AWBURST),
+    .s00_axi_awcache(m_axi_rmem22___Mmap2Stream_22___mmap_AWCACHE),
+    .s00_axi_awid(m_axi_rmem22___Mmap2Stream_22___mmap_AWID),
+    .s00_axi_awlen(m_axi_rmem22___Mmap2Stream_22___mmap_AWLEN),
+    .s00_axi_awlock(m_axi_rmem22___Mmap2Stream_22___mmap_AWLOCK),
+    .s00_axi_awprot(m_axi_rmem22___Mmap2Stream_22___mmap_AWPROT),
+    .s00_axi_awqos(m_axi_rmem22___Mmap2Stream_22___mmap_AWQOS),
+    .s00_axi_awready(m_axi_rmem22___Mmap2Stream_22___mmap_AWREADY),
+    .s00_axi_awsize(m_axi_rmem22___Mmap2Stream_22___mmap_AWSIZE),
+    .s00_axi_awvalid(m_axi_rmem22___Mmap2Stream_22___mmap_AWVALID),
+    .s00_axi_bid(m_axi_rmem22___Mmap2Stream_22___mmap_BID),
+    .s00_axi_bready(m_axi_rmem22___Mmap2Stream_22___mmap_BREADY),
+    .s00_axi_bresp(m_axi_rmem22___Mmap2Stream_22___mmap_BRESP),
+    .s00_axi_bvalid(m_axi_rmem22___Mmap2Stream_22___mmap_BVALID),
+    .s00_axi_rdata(m_axi_rmem22___Mmap2Stream_22___mmap_RDATA),
+    .s00_axi_rid(m_axi_rmem22___Mmap2Stream_22___mmap_RID),
+    .s00_axi_rlast(m_axi_rmem22___Mmap2Stream_22___mmap_RLAST),
+    .s00_axi_rready(m_axi_rmem22___Mmap2Stream_22___mmap_RREADY),
+    .s00_axi_rresp(m_axi_rmem22___Mmap2Stream_22___mmap_RRESP),
+    .s00_axi_rvalid(m_axi_rmem22___Mmap2Stream_22___mmap_RVALID),
+    .s00_axi_wdata(m_axi_rmem22___Mmap2Stream_22___mmap_WDATA),
+    .s00_axi_wlast(m_axi_rmem22___Mmap2Stream_22___mmap_WLAST),
+    .s00_axi_wready(m_axi_rmem22___Mmap2Stream_22___mmap_WREADY),
+    .s00_axi_wstrb(m_axi_rmem22___Mmap2Stream_22___mmap_WSTRB),
+    .s00_axi_wvalid(m_axi_rmem22___Mmap2Stream_22___mmap_WVALID),
+    .s01_axi_araddr(m_axi_rmem22___Stream2Mmap_22___mmap_ARADDR),
+    .s01_axi_arburst(m_axi_rmem22___Stream2Mmap_22___mmap_ARBURST),
+    .s01_axi_arcache(m_axi_rmem22___Stream2Mmap_22___mmap_ARCACHE),
+    .s01_axi_arid(m_axi_rmem22___Stream2Mmap_22___mmap_ARID),
+    .s01_axi_arlen(m_axi_rmem22___Stream2Mmap_22___mmap_ARLEN),
+    .s01_axi_arlock(m_axi_rmem22___Stream2Mmap_22___mmap_ARLOCK),
+    .s01_axi_arprot(m_axi_rmem22___Stream2Mmap_22___mmap_ARPROT),
+    .s01_axi_arqos(m_axi_rmem22___Stream2Mmap_22___mmap_ARQOS),
+    .s01_axi_arready(m_axi_rmem22___Stream2Mmap_22___mmap_ARREADY),
+    .s01_axi_arsize(m_axi_rmem22___Stream2Mmap_22___mmap_ARSIZE),
+    .s01_axi_arvalid(m_axi_rmem22___Stream2Mmap_22___mmap_ARVALID),
+    .s01_axi_awaddr(m_axi_rmem22___Stream2Mmap_22___mmap_AWADDR),
+    .s01_axi_awburst(m_axi_rmem22___Stream2Mmap_22___mmap_AWBURST),
+    .s01_axi_awcache(m_axi_rmem22___Stream2Mmap_22___mmap_AWCACHE),
+    .s01_axi_awid(m_axi_rmem22___Stream2Mmap_22___mmap_AWID),
+    .s01_axi_awlen(m_axi_rmem22___Stream2Mmap_22___mmap_AWLEN),
+    .s01_axi_awlock(m_axi_rmem22___Stream2Mmap_22___mmap_AWLOCK),
+    .s01_axi_awprot(m_axi_rmem22___Stream2Mmap_22___mmap_AWPROT),
+    .s01_axi_awqos(m_axi_rmem22___Stream2Mmap_22___mmap_AWQOS),
+    .s01_axi_awready(m_axi_rmem22___Stream2Mmap_22___mmap_AWREADY),
+    .s01_axi_awsize(m_axi_rmem22___Stream2Mmap_22___mmap_AWSIZE),
+    .s01_axi_awvalid(m_axi_rmem22___Stream2Mmap_22___mmap_AWVALID),
+    .s01_axi_bid(m_axi_rmem22___Stream2Mmap_22___mmap_BID),
+    .s01_axi_bready(m_axi_rmem22___Stream2Mmap_22___mmap_BREADY),
+    .s01_axi_bresp(m_axi_rmem22___Stream2Mmap_22___mmap_BRESP),
+    .s01_axi_bvalid(m_axi_rmem22___Stream2Mmap_22___mmap_BVALID),
+    .s01_axi_rdata(m_axi_rmem22___Stream2Mmap_22___mmap_RDATA),
+    .s01_axi_rid(m_axi_rmem22___Stream2Mmap_22___mmap_RID),
+    .s01_axi_rlast(m_axi_rmem22___Stream2Mmap_22___mmap_RLAST),
+    .s01_axi_rready(m_axi_rmem22___Stream2Mmap_22___mmap_RREADY),
+    .s01_axi_rresp(m_axi_rmem22___Stream2Mmap_22___mmap_RRESP),
+    .s01_axi_rvalid(m_axi_rmem22___Stream2Mmap_22___mmap_RVALID),
+    .s01_axi_wdata(m_axi_rmem22___Stream2Mmap_22___mmap_WDATA),
+    .s01_axi_wlast(m_axi_rmem22___Stream2Mmap_22___mmap_WLAST),
+    .s01_axi_wready(m_axi_rmem22___Stream2Mmap_22___mmap_WREADY),
+    .s01_axi_wstrb(m_axi_rmem22___Stream2Mmap_22___mmap_WSTRB),
+    .s01_axi_wvalid(m_axi_rmem22___Stream2Mmap_22___mmap_WVALID)
+  );
+
+
+  (* keep_hierarchy = "yes" *) axi_crossbar_2x1
+  #(
+    .DATA_WIDTH(512),
+    .ADDR_WIDTH(64),
+    .S_ID_WIDTH(1),
+    .M_ID_WIDTH(2),
+    .M00_ADDR_WIDTH(64),
+    .M00_ISSUE(16),
+    .S00_THREADS(1),
+    .S01_THREADS(1)
+  )
+  axi_crossbar_2x1__rmem23
+  (
+    .clk(ap_clk),
+    .rst(ap_rst_n_inv),
+    .m00_axi_araddr(m_axi_rmem23_ARADDR),
+    .m00_axi_arburst(m_axi_rmem23_ARBURST),
+    .m00_axi_arcache(m_axi_rmem23_ARCACHE),
+    .m00_axi_arid(m_axi_rmem23_ARID),
+    .m00_axi_arlen(m_axi_rmem23_ARLEN),
+    .m00_axi_arlock(m_axi_rmem23_ARLOCK),
+    .m00_axi_arprot(m_axi_rmem23_ARPROT),
+    .m00_axi_arqos(m_axi_rmem23_ARQOS),
+    .m00_axi_arready(m_axi_rmem23_ARREADY),
+    .m00_axi_arsize(m_axi_rmem23_ARSIZE),
+    .m00_axi_arvalid(m_axi_rmem23_ARVALID),
+    .m00_axi_awaddr(m_axi_rmem23_AWADDR),
+    .m00_axi_awburst(m_axi_rmem23_AWBURST),
+    .m00_axi_awcache(m_axi_rmem23_AWCACHE),
+    .m00_axi_awid(m_axi_rmem23_AWID),
+    .m00_axi_awlen(m_axi_rmem23_AWLEN),
+    .m00_axi_awlock(m_axi_rmem23_AWLOCK),
+    .m00_axi_awprot(m_axi_rmem23_AWPROT),
+    .m00_axi_awqos(m_axi_rmem23_AWQOS),
+    .m00_axi_awready(m_axi_rmem23_AWREADY),
+    .m00_axi_awsize(m_axi_rmem23_AWSIZE),
+    .m00_axi_awvalid(m_axi_rmem23_AWVALID),
+    .m00_axi_bid(m_axi_rmem23_BID),
+    .m00_axi_bready(m_axi_rmem23_BREADY),
+    .m00_axi_bresp(m_axi_rmem23_BRESP),
+    .m00_axi_bvalid(m_axi_rmem23_BVALID),
+    .m00_axi_rdata(m_axi_rmem23_RDATA),
+    .m00_axi_rid(m_axi_rmem23_RID),
+    .m00_axi_rlast(m_axi_rmem23_RLAST),
+    .m00_axi_rready(m_axi_rmem23_RREADY),
+    .m00_axi_rresp(m_axi_rmem23_RRESP),
+    .m00_axi_rvalid(m_axi_rmem23_RVALID),
+    .m00_axi_wdata(m_axi_rmem23_WDATA),
+    .m00_axi_wlast(m_axi_rmem23_WLAST),
+    .m00_axi_wready(m_axi_rmem23_WREADY),
+    .m00_axi_wstrb(m_axi_rmem23_WSTRB),
+    .m00_axi_wvalid(m_axi_rmem23_WVALID),
+    .s00_axi_araddr(m_axi_rmem23___Mmap2Stream_23___mmap_ARADDR),
+    .s00_axi_arburst(m_axi_rmem23___Mmap2Stream_23___mmap_ARBURST),
+    .s00_axi_arcache(m_axi_rmem23___Mmap2Stream_23___mmap_ARCACHE),
+    .s00_axi_arid(m_axi_rmem23___Mmap2Stream_23___mmap_ARID),
+    .s00_axi_arlen(m_axi_rmem23___Mmap2Stream_23___mmap_ARLEN),
+    .s00_axi_arlock(m_axi_rmem23___Mmap2Stream_23___mmap_ARLOCK),
+    .s00_axi_arprot(m_axi_rmem23___Mmap2Stream_23___mmap_ARPROT),
+    .s00_axi_arqos(m_axi_rmem23___Mmap2Stream_23___mmap_ARQOS),
+    .s00_axi_arready(m_axi_rmem23___Mmap2Stream_23___mmap_ARREADY),
+    .s00_axi_arsize(m_axi_rmem23___Mmap2Stream_23___mmap_ARSIZE),
+    .s00_axi_arvalid(m_axi_rmem23___Mmap2Stream_23___mmap_ARVALID),
+    .s00_axi_awaddr(m_axi_rmem23___Mmap2Stream_23___mmap_AWADDR),
+    .s00_axi_awburst(m_axi_rmem23___Mmap2Stream_23___mmap_AWBURST),
+    .s00_axi_awcache(m_axi_rmem23___Mmap2Stream_23___mmap_AWCACHE),
+    .s00_axi_awid(m_axi_rmem23___Mmap2Stream_23___mmap_AWID),
+    .s00_axi_awlen(m_axi_rmem23___Mmap2Stream_23___mmap_AWLEN),
+    .s00_axi_awlock(m_axi_rmem23___Mmap2Stream_23___mmap_AWLOCK),
+    .s00_axi_awprot(m_axi_rmem23___Mmap2Stream_23___mmap_AWPROT),
+    .s00_axi_awqos(m_axi_rmem23___Mmap2Stream_23___mmap_AWQOS),
+    .s00_axi_awready(m_axi_rmem23___Mmap2Stream_23___mmap_AWREADY),
+    .s00_axi_awsize(m_axi_rmem23___Mmap2Stream_23___mmap_AWSIZE),
+    .s00_axi_awvalid(m_axi_rmem23___Mmap2Stream_23___mmap_AWVALID),
+    .s00_axi_bid(m_axi_rmem23___Mmap2Stream_23___mmap_BID),
+    .s00_axi_bready(m_axi_rmem23___Mmap2Stream_23___mmap_BREADY),
+    .s00_axi_bresp(m_axi_rmem23___Mmap2Stream_23___mmap_BRESP),
+    .s00_axi_bvalid(m_axi_rmem23___Mmap2Stream_23___mmap_BVALID),
+    .s00_axi_rdata(m_axi_rmem23___Mmap2Stream_23___mmap_RDATA),
+    .s00_axi_rid(m_axi_rmem23___Mmap2Stream_23___mmap_RID),
+    .s00_axi_rlast(m_axi_rmem23___Mmap2Stream_23___mmap_RLAST),
+    .s00_axi_rready(m_axi_rmem23___Mmap2Stream_23___mmap_RREADY),
+    .s00_axi_rresp(m_axi_rmem23___Mmap2Stream_23___mmap_RRESP),
+    .s00_axi_rvalid(m_axi_rmem23___Mmap2Stream_23___mmap_RVALID),
+    .s00_axi_wdata(m_axi_rmem23___Mmap2Stream_23___mmap_WDATA),
+    .s00_axi_wlast(m_axi_rmem23___Mmap2Stream_23___mmap_WLAST),
+    .s00_axi_wready(m_axi_rmem23___Mmap2Stream_23___mmap_WREADY),
+    .s00_axi_wstrb(m_axi_rmem23___Mmap2Stream_23___mmap_WSTRB),
+    .s00_axi_wvalid(m_axi_rmem23___Mmap2Stream_23___mmap_WVALID),
+    .s01_axi_araddr(m_axi_rmem23___Stream2Mmap_23___mmap_ARADDR),
+    .s01_axi_arburst(m_axi_rmem23___Stream2Mmap_23___mmap_ARBURST),
+    .s01_axi_arcache(m_axi_rmem23___Stream2Mmap_23___mmap_ARCACHE),
+    .s01_axi_arid(m_axi_rmem23___Stream2Mmap_23___mmap_ARID),
+    .s01_axi_arlen(m_axi_rmem23___Stream2Mmap_23___mmap_ARLEN),
+    .s01_axi_arlock(m_axi_rmem23___Stream2Mmap_23___mmap_ARLOCK),
+    .s01_axi_arprot(m_axi_rmem23___Stream2Mmap_23___mmap_ARPROT),
+    .s01_axi_arqos(m_axi_rmem23___Stream2Mmap_23___mmap_ARQOS),
+    .s01_axi_arready(m_axi_rmem23___Stream2Mmap_23___mmap_ARREADY),
+    .s01_axi_arsize(m_axi_rmem23___Stream2Mmap_23___mmap_ARSIZE),
+    .s01_axi_arvalid(m_axi_rmem23___Stream2Mmap_23___mmap_ARVALID),
+    .s01_axi_awaddr(m_axi_rmem23___Stream2Mmap_23___mmap_AWADDR),
+    .s01_axi_awburst(m_axi_rmem23___Stream2Mmap_23___mmap_AWBURST),
+    .s01_axi_awcache(m_axi_rmem23___Stream2Mmap_23___mmap_AWCACHE),
+    .s01_axi_awid(m_axi_rmem23___Stream2Mmap_23___mmap_AWID),
+    .s01_axi_awlen(m_axi_rmem23___Stream2Mmap_23___mmap_AWLEN),
+    .s01_axi_awlock(m_axi_rmem23___Stream2Mmap_23___mmap_AWLOCK),
+    .s01_axi_awprot(m_axi_rmem23___Stream2Mmap_23___mmap_AWPROT),
+    .s01_axi_awqos(m_axi_rmem23___Stream2Mmap_23___mmap_AWQOS),
+    .s01_axi_awready(m_axi_rmem23___Stream2Mmap_23___mmap_AWREADY),
+    .s01_axi_awsize(m_axi_rmem23___Stream2Mmap_23___mmap_AWSIZE),
+    .s01_axi_awvalid(m_axi_rmem23___Stream2Mmap_23___mmap_AWVALID),
+    .s01_axi_bid(m_axi_rmem23___Stream2Mmap_23___mmap_BID),
+    .s01_axi_bready(m_axi_rmem23___Stream2Mmap_23___mmap_BREADY),
+    .s01_axi_bresp(m_axi_rmem23___Stream2Mmap_23___mmap_BRESP),
+    .s01_axi_bvalid(m_axi_rmem23___Stream2Mmap_23___mmap_BVALID),
+    .s01_axi_rdata(m_axi_rmem23___Stream2Mmap_23___mmap_RDATA),
+    .s01_axi_rid(m_axi_rmem23___Stream2Mmap_23___mmap_RID),
+    .s01_axi_rlast(m_axi_rmem23___Stream2Mmap_23___mmap_RLAST),
+    .s01_axi_rready(m_axi_rmem23___Stream2Mmap_23___mmap_RREADY),
+    .s01_axi_rresp(m_axi_rmem23___Stream2Mmap_23___mmap_RRESP),
+    .s01_axi_rvalid(m_axi_rmem23___Stream2Mmap_23___mmap_RVALID),
+    .s01_axi_wdata(m_axi_rmem23___Stream2Mmap_23___mmap_WDATA),
+    .s01_axi_wlast(m_axi_rmem23___Stream2Mmap_23___mmap_WLAST),
+    .s01_axi_wready(m_axi_rmem23___Stream2Mmap_23___mmap_WREADY),
+    .s01_axi_wstrb(m_axi_rmem23___Stream2Mmap_23___mmap_WSTRB),
+    .s01_axi_wvalid(m_axi_rmem23___Stream2Mmap_23___mmap_WVALID)
+  );
+
+
+  (* keep_hierarchy = "yes" *) axi_crossbar_2x1
+  #(
+    .DATA_WIDTH(512),
+    .ADDR_WIDTH(64),
+    .S_ID_WIDTH(1),
+    .M_ID_WIDTH(2),
+    .M00_ADDR_WIDTH(64),
+    .M00_ISSUE(16),
+    .S00_THREADS(1),
+    .S01_THREADS(1)
+  )
+  axi_crossbar_2x1__rmem24
+  (
+    .clk(ap_clk),
+    .rst(ap_rst_n_inv),
+    .m00_axi_araddr(m_axi_rmem24_ARADDR),
+    .m00_axi_arburst(m_axi_rmem24_ARBURST),
+    .m00_axi_arcache(m_axi_rmem24_ARCACHE),
+    .m00_axi_arid(m_axi_rmem24_ARID),
+    .m00_axi_arlen(m_axi_rmem24_ARLEN),
+    .m00_axi_arlock(m_axi_rmem24_ARLOCK),
+    .m00_axi_arprot(m_axi_rmem24_ARPROT),
+    .m00_axi_arqos(m_axi_rmem24_ARQOS),
+    .m00_axi_arready(m_axi_rmem24_ARREADY),
+    .m00_axi_arsize(m_axi_rmem24_ARSIZE),
+    .m00_axi_arvalid(m_axi_rmem24_ARVALID),
+    .m00_axi_awaddr(m_axi_rmem24_AWADDR),
+    .m00_axi_awburst(m_axi_rmem24_AWBURST),
+    .m00_axi_awcache(m_axi_rmem24_AWCACHE),
+    .m00_axi_awid(m_axi_rmem24_AWID),
+    .m00_axi_awlen(m_axi_rmem24_AWLEN),
+    .m00_axi_awlock(m_axi_rmem24_AWLOCK),
+    .m00_axi_awprot(m_axi_rmem24_AWPROT),
+    .m00_axi_awqos(m_axi_rmem24_AWQOS),
+    .m00_axi_awready(m_axi_rmem24_AWREADY),
+    .m00_axi_awsize(m_axi_rmem24_AWSIZE),
+    .m00_axi_awvalid(m_axi_rmem24_AWVALID),
+    .m00_axi_bid(m_axi_rmem24_BID),
+    .m00_axi_bready(m_axi_rmem24_BREADY),
+    .m00_axi_bresp(m_axi_rmem24_BRESP),
+    .m00_axi_bvalid(m_axi_rmem24_BVALID),
+    .m00_axi_rdata(m_axi_rmem24_RDATA),
+    .m00_axi_rid(m_axi_rmem24_RID),
+    .m00_axi_rlast(m_axi_rmem24_RLAST),
+    .m00_axi_rready(m_axi_rmem24_RREADY),
+    .m00_axi_rresp(m_axi_rmem24_RRESP),
+    .m00_axi_rvalid(m_axi_rmem24_RVALID),
+    .m00_axi_wdata(m_axi_rmem24_WDATA),
+    .m00_axi_wlast(m_axi_rmem24_WLAST),
+    .m00_axi_wready(m_axi_rmem24_WREADY),
+    .m00_axi_wstrb(m_axi_rmem24_WSTRB),
+    .m00_axi_wvalid(m_axi_rmem24_WVALID),
+    .s00_axi_araddr(m_axi_rmem24___Mmap2Stream_24___mmap_ARADDR),
+    .s00_axi_arburst(m_axi_rmem24___Mmap2Stream_24___mmap_ARBURST),
+    .s00_axi_arcache(m_axi_rmem24___Mmap2Stream_24___mmap_ARCACHE),
+    .s00_axi_arid(m_axi_rmem24___Mmap2Stream_24___mmap_ARID),
+    .s00_axi_arlen(m_axi_rmem24___Mmap2Stream_24___mmap_ARLEN),
+    .s00_axi_arlock(m_axi_rmem24___Mmap2Stream_24___mmap_ARLOCK),
+    .s00_axi_arprot(m_axi_rmem24___Mmap2Stream_24___mmap_ARPROT),
+    .s00_axi_arqos(m_axi_rmem24___Mmap2Stream_24___mmap_ARQOS),
+    .s00_axi_arready(m_axi_rmem24___Mmap2Stream_24___mmap_ARREADY),
+    .s00_axi_arsize(m_axi_rmem24___Mmap2Stream_24___mmap_ARSIZE),
+    .s00_axi_arvalid(m_axi_rmem24___Mmap2Stream_24___mmap_ARVALID),
+    .s00_axi_awaddr(m_axi_rmem24___Mmap2Stream_24___mmap_AWADDR),
+    .s00_axi_awburst(m_axi_rmem24___Mmap2Stream_24___mmap_AWBURST),
+    .s00_axi_awcache(m_axi_rmem24___Mmap2Stream_24___mmap_AWCACHE),
+    .s00_axi_awid(m_axi_rmem24___Mmap2Stream_24___mmap_AWID),
+    .s00_axi_awlen(m_axi_rmem24___Mmap2Stream_24___mmap_AWLEN),
+    .s00_axi_awlock(m_axi_rmem24___Mmap2Stream_24___mmap_AWLOCK),
+    .s00_axi_awprot(m_axi_rmem24___Mmap2Stream_24___mmap_AWPROT),
+    .s00_axi_awqos(m_axi_rmem24___Mmap2Stream_24___mmap_AWQOS),
+    .s00_axi_awready(m_axi_rmem24___Mmap2Stream_24___mmap_AWREADY),
+    .s00_axi_awsize(m_axi_rmem24___Mmap2Stream_24___mmap_AWSIZE),
+    .s00_axi_awvalid(m_axi_rmem24___Mmap2Stream_24___mmap_AWVALID),
+    .s00_axi_bid(m_axi_rmem24___Mmap2Stream_24___mmap_BID),
+    .s00_axi_bready(m_axi_rmem24___Mmap2Stream_24___mmap_BREADY),
+    .s00_axi_bresp(m_axi_rmem24___Mmap2Stream_24___mmap_BRESP),
+    .s00_axi_bvalid(m_axi_rmem24___Mmap2Stream_24___mmap_BVALID),
+    .s00_axi_rdata(m_axi_rmem24___Mmap2Stream_24___mmap_RDATA),
+    .s00_axi_rid(m_axi_rmem24___Mmap2Stream_24___mmap_RID),
+    .s00_axi_rlast(m_axi_rmem24___Mmap2Stream_24___mmap_RLAST),
+    .s00_axi_rready(m_axi_rmem24___Mmap2Stream_24___mmap_RREADY),
+    .s00_axi_rresp(m_axi_rmem24___Mmap2Stream_24___mmap_RRESP),
+    .s00_axi_rvalid(m_axi_rmem24___Mmap2Stream_24___mmap_RVALID),
+    .s00_axi_wdata(m_axi_rmem24___Mmap2Stream_24___mmap_WDATA),
+    .s00_axi_wlast(m_axi_rmem24___Mmap2Stream_24___mmap_WLAST),
+    .s00_axi_wready(m_axi_rmem24___Mmap2Stream_24___mmap_WREADY),
+    .s00_axi_wstrb(m_axi_rmem24___Mmap2Stream_24___mmap_WSTRB),
+    .s00_axi_wvalid(m_axi_rmem24___Mmap2Stream_24___mmap_WVALID),
+    .s01_axi_araddr(m_axi_rmem24___Stream2Mmap_24___mmap_ARADDR),
+    .s01_axi_arburst(m_axi_rmem24___Stream2Mmap_24___mmap_ARBURST),
+    .s01_axi_arcache(m_axi_rmem24___Stream2Mmap_24___mmap_ARCACHE),
+    .s01_axi_arid(m_axi_rmem24___Stream2Mmap_24___mmap_ARID),
+    .s01_axi_arlen(m_axi_rmem24___Stream2Mmap_24___mmap_ARLEN),
+    .s01_axi_arlock(m_axi_rmem24___Stream2Mmap_24___mmap_ARLOCK),
+    .s01_axi_arprot(m_axi_rmem24___Stream2Mmap_24___mmap_ARPROT),
+    .s01_axi_arqos(m_axi_rmem24___Stream2Mmap_24___mmap_ARQOS),
+    .s01_axi_arready(m_axi_rmem24___Stream2Mmap_24___mmap_ARREADY),
+    .s01_axi_arsize(m_axi_rmem24___Stream2Mmap_24___mmap_ARSIZE),
+    .s01_axi_arvalid(m_axi_rmem24___Stream2Mmap_24___mmap_ARVALID),
+    .s01_axi_awaddr(m_axi_rmem24___Stream2Mmap_24___mmap_AWADDR),
+    .s01_axi_awburst(m_axi_rmem24___Stream2Mmap_24___mmap_AWBURST),
+    .s01_axi_awcache(m_axi_rmem24___Stream2Mmap_24___mmap_AWCACHE),
+    .s01_axi_awid(m_axi_rmem24___Stream2Mmap_24___mmap_AWID),
+    .s01_axi_awlen(m_axi_rmem24___Stream2Mmap_24___mmap_AWLEN),
+    .s01_axi_awlock(m_axi_rmem24___Stream2Mmap_24___mmap_AWLOCK),
+    .s01_axi_awprot(m_axi_rmem24___Stream2Mmap_24___mmap_AWPROT),
+    .s01_axi_awqos(m_axi_rmem24___Stream2Mmap_24___mmap_AWQOS),
+    .s01_axi_awready(m_axi_rmem24___Stream2Mmap_24___mmap_AWREADY),
+    .s01_axi_awsize(m_axi_rmem24___Stream2Mmap_24___mmap_AWSIZE),
+    .s01_axi_awvalid(m_axi_rmem24___Stream2Mmap_24___mmap_AWVALID),
+    .s01_axi_bid(m_axi_rmem24___Stream2Mmap_24___mmap_BID),
+    .s01_axi_bready(m_axi_rmem24___Stream2Mmap_24___mmap_BREADY),
+    .s01_axi_bresp(m_axi_rmem24___Stream2Mmap_24___mmap_BRESP),
+    .s01_axi_bvalid(m_axi_rmem24___Stream2Mmap_24___mmap_BVALID),
+    .s01_axi_rdata(m_axi_rmem24___Stream2Mmap_24___mmap_RDATA),
+    .s01_axi_rid(m_axi_rmem24___Stream2Mmap_24___mmap_RID),
+    .s01_axi_rlast(m_axi_rmem24___Stream2Mmap_24___mmap_RLAST),
+    .s01_axi_rready(m_axi_rmem24___Stream2Mmap_24___mmap_RREADY),
+    .s01_axi_rresp(m_axi_rmem24___Stream2Mmap_24___mmap_RRESP),
+    .s01_axi_rvalid(m_axi_rmem24___Stream2Mmap_24___mmap_RVALID),
+    .s01_axi_wdata(m_axi_rmem24___Stream2Mmap_24___mmap_WDATA),
+    .s01_axi_wlast(m_axi_rmem24___Stream2Mmap_24___mmap_WLAST),
+    .s01_axi_wready(m_axi_rmem24___Stream2Mmap_24___mmap_WREADY),
+    .s01_axi_wstrb(m_axi_rmem24___Stream2Mmap_24___mmap_WSTRB),
+    .s01_axi_wvalid(m_axi_rmem24___Stream2Mmap_24___mmap_WVALID)
+  );
+
+
+  (* keep_hierarchy = "yes" *) axi_crossbar_2x1
+  #(
+    .DATA_WIDTH(512),
+    .ADDR_WIDTH(64),
+    .S_ID_WIDTH(1),
+    .M_ID_WIDTH(2),
+    .M00_ADDR_WIDTH(64),
+    .M00_ISSUE(16),
+    .S00_THREADS(1),
+    .S01_THREADS(1)
+  )
+  axi_crossbar_2x1__rmem25
+  (
+    .clk(ap_clk),
+    .rst(ap_rst_n_inv),
+    .m00_axi_araddr(m_axi_rmem25_ARADDR),
+    .m00_axi_arburst(m_axi_rmem25_ARBURST),
+    .m00_axi_arcache(m_axi_rmem25_ARCACHE),
+    .m00_axi_arid(m_axi_rmem25_ARID),
+    .m00_axi_arlen(m_axi_rmem25_ARLEN),
+    .m00_axi_arlock(m_axi_rmem25_ARLOCK),
+    .m00_axi_arprot(m_axi_rmem25_ARPROT),
+    .m00_axi_arqos(m_axi_rmem25_ARQOS),
+    .m00_axi_arready(m_axi_rmem25_ARREADY),
+    .m00_axi_arsize(m_axi_rmem25_ARSIZE),
+    .m00_axi_arvalid(m_axi_rmem25_ARVALID),
+    .m00_axi_awaddr(m_axi_rmem25_AWADDR),
+    .m00_axi_awburst(m_axi_rmem25_AWBURST),
+    .m00_axi_awcache(m_axi_rmem25_AWCACHE),
+    .m00_axi_awid(m_axi_rmem25_AWID),
+    .m00_axi_awlen(m_axi_rmem25_AWLEN),
+    .m00_axi_awlock(m_axi_rmem25_AWLOCK),
+    .m00_axi_awprot(m_axi_rmem25_AWPROT),
+    .m00_axi_awqos(m_axi_rmem25_AWQOS),
+    .m00_axi_awready(m_axi_rmem25_AWREADY),
+    .m00_axi_awsize(m_axi_rmem25_AWSIZE),
+    .m00_axi_awvalid(m_axi_rmem25_AWVALID),
+    .m00_axi_bid(m_axi_rmem25_BID),
+    .m00_axi_bready(m_axi_rmem25_BREADY),
+    .m00_axi_bresp(m_axi_rmem25_BRESP),
+    .m00_axi_bvalid(m_axi_rmem25_BVALID),
+    .m00_axi_rdata(m_axi_rmem25_RDATA),
+    .m00_axi_rid(m_axi_rmem25_RID),
+    .m00_axi_rlast(m_axi_rmem25_RLAST),
+    .m00_axi_rready(m_axi_rmem25_RREADY),
+    .m00_axi_rresp(m_axi_rmem25_RRESP),
+    .m00_axi_rvalid(m_axi_rmem25_RVALID),
+    .m00_axi_wdata(m_axi_rmem25_WDATA),
+    .m00_axi_wlast(m_axi_rmem25_WLAST),
+    .m00_axi_wready(m_axi_rmem25_WREADY),
+    .m00_axi_wstrb(m_axi_rmem25_WSTRB),
+    .m00_axi_wvalid(m_axi_rmem25_WVALID),
+    .s00_axi_araddr(m_axi_rmem25___Mmap2Stream_25___mmap_ARADDR),
+    .s00_axi_arburst(m_axi_rmem25___Mmap2Stream_25___mmap_ARBURST),
+    .s00_axi_arcache(m_axi_rmem25___Mmap2Stream_25___mmap_ARCACHE),
+    .s00_axi_arid(m_axi_rmem25___Mmap2Stream_25___mmap_ARID),
+    .s00_axi_arlen(m_axi_rmem25___Mmap2Stream_25___mmap_ARLEN),
+    .s00_axi_arlock(m_axi_rmem25___Mmap2Stream_25___mmap_ARLOCK),
+    .s00_axi_arprot(m_axi_rmem25___Mmap2Stream_25___mmap_ARPROT),
+    .s00_axi_arqos(m_axi_rmem25___Mmap2Stream_25___mmap_ARQOS),
+    .s00_axi_arready(m_axi_rmem25___Mmap2Stream_25___mmap_ARREADY),
+    .s00_axi_arsize(m_axi_rmem25___Mmap2Stream_25___mmap_ARSIZE),
+    .s00_axi_arvalid(m_axi_rmem25___Mmap2Stream_25___mmap_ARVALID),
+    .s00_axi_awaddr(m_axi_rmem25___Mmap2Stream_25___mmap_AWADDR),
+    .s00_axi_awburst(m_axi_rmem25___Mmap2Stream_25___mmap_AWBURST),
+    .s00_axi_awcache(m_axi_rmem25___Mmap2Stream_25___mmap_AWCACHE),
+    .s00_axi_awid(m_axi_rmem25___Mmap2Stream_25___mmap_AWID),
+    .s00_axi_awlen(m_axi_rmem25___Mmap2Stream_25___mmap_AWLEN),
+    .s00_axi_awlock(m_axi_rmem25___Mmap2Stream_25___mmap_AWLOCK),
+    .s00_axi_awprot(m_axi_rmem25___Mmap2Stream_25___mmap_AWPROT),
+    .s00_axi_awqos(m_axi_rmem25___Mmap2Stream_25___mmap_AWQOS),
+    .s00_axi_awready(m_axi_rmem25___Mmap2Stream_25___mmap_AWREADY),
+    .s00_axi_awsize(m_axi_rmem25___Mmap2Stream_25___mmap_AWSIZE),
+    .s00_axi_awvalid(m_axi_rmem25___Mmap2Stream_25___mmap_AWVALID),
+    .s00_axi_bid(m_axi_rmem25___Mmap2Stream_25___mmap_BID),
+    .s00_axi_bready(m_axi_rmem25___Mmap2Stream_25___mmap_BREADY),
+    .s00_axi_bresp(m_axi_rmem25___Mmap2Stream_25___mmap_BRESP),
+    .s00_axi_bvalid(m_axi_rmem25___Mmap2Stream_25___mmap_BVALID),
+    .s00_axi_rdata(m_axi_rmem25___Mmap2Stream_25___mmap_RDATA),
+    .s00_axi_rid(m_axi_rmem25___Mmap2Stream_25___mmap_RID),
+    .s00_axi_rlast(m_axi_rmem25___Mmap2Stream_25___mmap_RLAST),
+    .s00_axi_rready(m_axi_rmem25___Mmap2Stream_25___mmap_RREADY),
+    .s00_axi_rresp(m_axi_rmem25___Mmap2Stream_25___mmap_RRESP),
+    .s00_axi_rvalid(m_axi_rmem25___Mmap2Stream_25___mmap_RVALID),
+    .s00_axi_wdata(m_axi_rmem25___Mmap2Stream_25___mmap_WDATA),
+    .s00_axi_wlast(m_axi_rmem25___Mmap2Stream_25___mmap_WLAST),
+    .s00_axi_wready(m_axi_rmem25___Mmap2Stream_25___mmap_WREADY),
+    .s00_axi_wstrb(m_axi_rmem25___Mmap2Stream_25___mmap_WSTRB),
+    .s00_axi_wvalid(m_axi_rmem25___Mmap2Stream_25___mmap_WVALID),
+    .s01_axi_araddr(m_axi_rmem25___Stream2Mmap_25___mmap_ARADDR),
+    .s01_axi_arburst(m_axi_rmem25___Stream2Mmap_25___mmap_ARBURST),
+    .s01_axi_arcache(m_axi_rmem25___Stream2Mmap_25___mmap_ARCACHE),
+    .s01_axi_arid(m_axi_rmem25___Stream2Mmap_25___mmap_ARID),
+    .s01_axi_arlen(m_axi_rmem25___Stream2Mmap_25___mmap_ARLEN),
+    .s01_axi_arlock(m_axi_rmem25___Stream2Mmap_25___mmap_ARLOCK),
+    .s01_axi_arprot(m_axi_rmem25___Stream2Mmap_25___mmap_ARPROT),
+    .s01_axi_arqos(m_axi_rmem25___Stream2Mmap_25___mmap_ARQOS),
+    .s01_axi_arready(m_axi_rmem25___Stream2Mmap_25___mmap_ARREADY),
+    .s01_axi_arsize(m_axi_rmem25___Stream2Mmap_25___mmap_ARSIZE),
+    .s01_axi_arvalid(m_axi_rmem25___Stream2Mmap_25___mmap_ARVALID),
+    .s01_axi_awaddr(m_axi_rmem25___Stream2Mmap_25___mmap_AWADDR),
+    .s01_axi_awburst(m_axi_rmem25___Stream2Mmap_25___mmap_AWBURST),
+    .s01_axi_awcache(m_axi_rmem25___Stream2Mmap_25___mmap_AWCACHE),
+    .s01_axi_awid(m_axi_rmem25___Stream2Mmap_25___mmap_AWID),
+    .s01_axi_awlen(m_axi_rmem25___Stream2Mmap_25___mmap_AWLEN),
+    .s01_axi_awlock(m_axi_rmem25___Stream2Mmap_25___mmap_AWLOCK),
+    .s01_axi_awprot(m_axi_rmem25___Stream2Mmap_25___mmap_AWPROT),
+    .s01_axi_awqos(m_axi_rmem25___Stream2Mmap_25___mmap_AWQOS),
+    .s01_axi_awready(m_axi_rmem25___Stream2Mmap_25___mmap_AWREADY),
+    .s01_axi_awsize(m_axi_rmem25___Stream2Mmap_25___mmap_AWSIZE),
+    .s01_axi_awvalid(m_axi_rmem25___Stream2Mmap_25___mmap_AWVALID),
+    .s01_axi_bid(m_axi_rmem25___Stream2Mmap_25___mmap_BID),
+    .s01_axi_bready(m_axi_rmem25___Stream2Mmap_25___mmap_BREADY),
+    .s01_axi_bresp(m_axi_rmem25___Stream2Mmap_25___mmap_BRESP),
+    .s01_axi_bvalid(m_axi_rmem25___Stream2Mmap_25___mmap_BVALID),
+    .s01_axi_rdata(m_axi_rmem25___Stream2Mmap_25___mmap_RDATA),
+    .s01_axi_rid(m_axi_rmem25___Stream2Mmap_25___mmap_RID),
+    .s01_axi_rlast(m_axi_rmem25___Stream2Mmap_25___mmap_RLAST),
+    .s01_axi_rready(m_axi_rmem25___Stream2Mmap_25___mmap_RREADY),
+    .s01_axi_rresp(m_axi_rmem25___Stream2Mmap_25___mmap_RRESP),
+    .s01_axi_rvalid(m_axi_rmem25___Stream2Mmap_25___mmap_RVALID),
+    .s01_axi_wdata(m_axi_rmem25___Stream2Mmap_25___mmap_WDATA),
+    .s01_axi_wlast(m_axi_rmem25___Stream2Mmap_25___mmap_WLAST),
+    .s01_axi_wready(m_axi_rmem25___Stream2Mmap_25___mmap_WREADY),
+    .s01_axi_wstrb(m_axi_rmem25___Stream2Mmap_25___mmap_WSTRB),
+    .s01_axi_wvalid(m_axi_rmem25___Stream2Mmap_25___mmap_WVALID)
+  );
+
+
+  (* keep_hierarchy = "yes" *) axi_crossbar_2x1
+  #(
+    .DATA_WIDTH(512),
+    .ADDR_WIDTH(64),
+    .S_ID_WIDTH(1),
+    .M_ID_WIDTH(2),
+    .M00_ADDR_WIDTH(64),
+    .M00_ISSUE(16),
+    .S00_THREADS(1),
+    .S01_THREADS(1)
+  )
+  axi_crossbar_2x1__rmem26
+  (
+    .clk(ap_clk),
+    .rst(ap_rst_n_inv),
+    .m00_axi_araddr(m_axi_rmem26_ARADDR),
+    .m00_axi_arburst(m_axi_rmem26_ARBURST),
+    .m00_axi_arcache(m_axi_rmem26_ARCACHE),
+    .m00_axi_arid(m_axi_rmem26_ARID),
+    .m00_axi_arlen(m_axi_rmem26_ARLEN),
+    .m00_axi_arlock(m_axi_rmem26_ARLOCK),
+    .m00_axi_arprot(m_axi_rmem26_ARPROT),
+    .m00_axi_arqos(m_axi_rmem26_ARQOS),
+    .m00_axi_arready(m_axi_rmem26_ARREADY),
+    .m00_axi_arsize(m_axi_rmem26_ARSIZE),
+    .m00_axi_arvalid(m_axi_rmem26_ARVALID),
+    .m00_axi_awaddr(m_axi_rmem26_AWADDR),
+    .m00_axi_awburst(m_axi_rmem26_AWBURST),
+    .m00_axi_awcache(m_axi_rmem26_AWCACHE),
+    .m00_axi_awid(m_axi_rmem26_AWID),
+    .m00_axi_awlen(m_axi_rmem26_AWLEN),
+    .m00_axi_awlock(m_axi_rmem26_AWLOCK),
+    .m00_axi_awprot(m_axi_rmem26_AWPROT),
+    .m00_axi_awqos(m_axi_rmem26_AWQOS),
+    .m00_axi_awready(m_axi_rmem26_AWREADY),
+    .m00_axi_awsize(m_axi_rmem26_AWSIZE),
+    .m00_axi_awvalid(m_axi_rmem26_AWVALID),
+    .m00_axi_bid(m_axi_rmem26_BID),
+    .m00_axi_bready(m_axi_rmem26_BREADY),
+    .m00_axi_bresp(m_axi_rmem26_BRESP),
+    .m00_axi_bvalid(m_axi_rmem26_BVALID),
+    .m00_axi_rdata(m_axi_rmem26_RDATA),
+    .m00_axi_rid(m_axi_rmem26_RID),
+    .m00_axi_rlast(m_axi_rmem26_RLAST),
+    .m00_axi_rready(m_axi_rmem26_RREADY),
+    .m00_axi_rresp(m_axi_rmem26_RRESP),
+    .m00_axi_rvalid(m_axi_rmem26_RVALID),
+    .m00_axi_wdata(m_axi_rmem26_WDATA),
+    .m00_axi_wlast(m_axi_rmem26_WLAST),
+    .m00_axi_wready(m_axi_rmem26_WREADY),
+    .m00_axi_wstrb(m_axi_rmem26_WSTRB),
+    .m00_axi_wvalid(m_axi_rmem26_WVALID),
+    .s00_axi_araddr(m_axi_rmem26___Mmap2Stream_26___mmap_ARADDR),
+    .s00_axi_arburst(m_axi_rmem26___Mmap2Stream_26___mmap_ARBURST),
+    .s00_axi_arcache(m_axi_rmem26___Mmap2Stream_26___mmap_ARCACHE),
+    .s00_axi_arid(m_axi_rmem26___Mmap2Stream_26___mmap_ARID),
+    .s00_axi_arlen(m_axi_rmem26___Mmap2Stream_26___mmap_ARLEN),
+    .s00_axi_arlock(m_axi_rmem26___Mmap2Stream_26___mmap_ARLOCK),
+    .s00_axi_arprot(m_axi_rmem26___Mmap2Stream_26___mmap_ARPROT),
+    .s00_axi_arqos(m_axi_rmem26___Mmap2Stream_26___mmap_ARQOS),
+    .s00_axi_arready(m_axi_rmem26___Mmap2Stream_26___mmap_ARREADY),
+    .s00_axi_arsize(m_axi_rmem26___Mmap2Stream_26___mmap_ARSIZE),
+    .s00_axi_arvalid(m_axi_rmem26___Mmap2Stream_26___mmap_ARVALID),
+    .s00_axi_awaddr(m_axi_rmem26___Mmap2Stream_26___mmap_AWADDR),
+    .s00_axi_awburst(m_axi_rmem26___Mmap2Stream_26___mmap_AWBURST),
+    .s00_axi_awcache(m_axi_rmem26___Mmap2Stream_26___mmap_AWCACHE),
+    .s00_axi_awid(m_axi_rmem26___Mmap2Stream_26___mmap_AWID),
+    .s00_axi_awlen(m_axi_rmem26___Mmap2Stream_26___mmap_AWLEN),
+    .s00_axi_awlock(m_axi_rmem26___Mmap2Stream_26___mmap_AWLOCK),
+    .s00_axi_awprot(m_axi_rmem26___Mmap2Stream_26___mmap_AWPROT),
+    .s00_axi_awqos(m_axi_rmem26___Mmap2Stream_26___mmap_AWQOS),
+    .s00_axi_awready(m_axi_rmem26___Mmap2Stream_26___mmap_AWREADY),
+    .s00_axi_awsize(m_axi_rmem26___Mmap2Stream_26___mmap_AWSIZE),
+    .s00_axi_awvalid(m_axi_rmem26___Mmap2Stream_26___mmap_AWVALID),
+    .s00_axi_bid(m_axi_rmem26___Mmap2Stream_26___mmap_BID),
+    .s00_axi_bready(m_axi_rmem26___Mmap2Stream_26___mmap_BREADY),
+    .s00_axi_bresp(m_axi_rmem26___Mmap2Stream_26___mmap_BRESP),
+    .s00_axi_bvalid(m_axi_rmem26___Mmap2Stream_26___mmap_BVALID),
+    .s00_axi_rdata(m_axi_rmem26___Mmap2Stream_26___mmap_RDATA),
+    .s00_axi_rid(m_axi_rmem26___Mmap2Stream_26___mmap_RID),
+    .s00_axi_rlast(m_axi_rmem26___Mmap2Stream_26___mmap_RLAST),
+    .s00_axi_rready(m_axi_rmem26___Mmap2Stream_26___mmap_RREADY),
+    .s00_axi_rresp(m_axi_rmem26___Mmap2Stream_26___mmap_RRESP),
+    .s00_axi_rvalid(m_axi_rmem26___Mmap2Stream_26___mmap_RVALID),
+    .s00_axi_wdata(m_axi_rmem26___Mmap2Stream_26___mmap_WDATA),
+    .s00_axi_wlast(m_axi_rmem26___Mmap2Stream_26___mmap_WLAST),
+    .s00_axi_wready(m_axi_rmem26___Mmap2Stream_26___mmap_WREADY),
+    .s00_axi_wstrb(m_axi_rmem26___Mmap2Stream_26___mmap_WSTRB),
+    .s00_axi_wvalid(m_axi_rmem26___Mmap2Stream_26___mmap_WVALID),
+    .s01_axi_araddr(m_axi_rmem26___Stream2Mmap_26___mmap_ARADDR),
+    .s01_axi_arburst(m_axi_rmem26___Stream2Mmap_26___mmap_ARBURST),
+    .s01_axi_arcache(m_axi_rmem26___Stream2Mmap_26___mmap_ARCACHE),
+    .s01_axi_arid(m_axi_rmem26___Stream2Mmap_26___mmap_ARID),
+    .s01_axi_arlen(m_axi_rmem26___Stream2Mmap_26___mmap_ARLEN),
+    .s01_axi_arlock(m_axi_rmem26___Stream2Mmap_26___mmap_ARLOCK),
+    .s01_axi_arprot(m_axi_rmem26___Stream2Mmap_26___mmap_ARPROT),
+    .s01_axi_arqos(m_axi_rmem26___Stream2Mmap_26___mmap_ARQOS),
+    .s01_axi_arready(m_axi_rmem26___Stream2Mmap_26___mmap_ARREADY),
+    .s01_axi_arsize(m_axi_rmem26___Stream2Mmap_26___mmap_ARSIZE),
+    .s01_axi_arvalid(m_axi_rmem26___Stream2Mmap_26___mmap_ARVALID),
+    .s01_axi_awaddr(m_axi_rmem26___Stream2Mmap_26___mmap_AWADDR),
+    .s01_axi_awburst(m_axi_rmem26___Stream2Mmap_26___mmap_AWBURST),
+    .s01_axi_awcache(m_axi_rmem26___Stream2Mmap_26___mmap_AWCACHE),
+    .s01_axi_awid(m_axi_rmem26___Stream2Mmap_26___mmap_AWID),
+    .s01_axi_awlen(m_axi_rmem26___Stream2Mmap_26___mmap_AWLEN),
+    .s01_axi_awlock(m_axi_rmem26___Stream2Mmap_26___mmap_AWLOCK),
+    .s01_axi_awprot(m_axi_rmem26___Stream2Mmap_26___mmap_AWPROT),
+    .s01_axi_awqos(m_axi_rmem26___Stream2Mmap_26___mmap_AWQOS),
+    .s01_axi_awready(m_axi_rmem26___Stream2Mmap_26___mmap_AWREADY),
+    .s01_axi_awsize(m_axi_rmem26___Stream2Mmap_26___mmap_AWSIZE),
+    .s01_axi_awvalid(m_axi_rmem26___Stream2Mmap_26___mmap_AWVALID),
+    .s01_axi_bid(m_axi_rmem26___Stream2Mmap_26___mmap_BID),
+    .s01_axi_bready(m_axi_rmem26___Stream2Mmap_26___mmap_BREADY),
+    .s01_axi_bresp(m_axi_rmem26___Stream2Mmap_26___mmap_BRESP),
+    .s01_axi_bvalid(m_axi_rmem26___Stream2Mmap_26___mmap_BVALID),
+    .s01_axi_rdata(m_axi_rmem26___Stream2Mmap_26___mmap_RDATA),
+    .s01_axi_rid(m_axi_rmem26___Stream2Mmap_26___mmap_RID),
+    .s01_axi_rlast(m_axi_rmem26___Stream2Mmap_26___mmap_RLAST),
+    .s01_axi_rready(m_axi_rmem26___Stream2Mmap_26___mmap_RREADY),
+    .s01_axi_rresp(m_axi_rmem26___Stream2Mmap_26___mmap_RRESP),
+    .s01_axi_rvalid(m_axi_rmem26___Stream2Mmap_26___mmap_RVALID),
+    .s01_axi_wdata(m_axi_rmem26___Stream2Mmap_26___mmap_WDATA),
+    .s01_axi_wlast(m_axi_rmem26___Stream2Mmap_26___mmap_WLAST),
+    .s01_axi_wready(m_axi_rmem26___Stream2Mmap_26___mmap_WREADY),
+    .s01_axi_wstrb(m_axi_rmem26___Stream2Mmap_26___mmap_WSTRB),
+    .s01_axi_wvalid(m_axi_rmem26___Stream2Mmap_26___mmap_WVALID)
+  );
+
+
+  (* keep_hierarchy = "yes" *) axi_crossbar_2x1
+  #(
+    .DATA_WIDTH(512),
+    .ADDR_WIDTH(64),
+    .S_ID_WIDTH(1),
+    .M_ID_WIDTH(2),
+    .M00_ADDR_WIDTH(64),
+    .M00_ISSUE(16),
+    .S00_THREADS(1),
+    .S01_THREADS(1)
+  )
+  axi_crossbar_2x1__rmem27
+  (
+    .clk(ap_clk),
+    .rst(ap_rst_n_inv),
+    .m00_axi_araddr(m_axi_rmem27_ARADDR),
+    .m00_axi_arburst(m_axi_rmem27_ARBURST),
+    .m00_axi_arcache(m_axi_rmem27_ARCACHE),
+    .m00_axi_arid(m_axi_rmem27_ARID),
+    .m00_axi_arlen(m_axi_rmem27_ARLEN),
+    .m00_axi_arlock(m_axi_rmem27_ARLOCK),
+    .m00_axi_arprot(m_axi_rmem27_ARPROT),
+    .m00_axi_arqos(m_axi_rmem27_ARQOS),
+    .m00_axi_arready(m_axi_rmem27_ARREADY),
+    .m00_axi_arsize(m_axi_rmem27_ARSIZE),
+    .m00_axi_arvalid(m_axi_rmem27_ARVALID),
+    .m00_axi_awaddr(m_axi_rmem27_AWADDR),
+    .m00_axi_awburst(m_axi_rmem27_AWBURST),
+    .m00_axi_awcache(m_axi_rmem27_AWCACHE),
+    .m00_axi_awid(m_axi_rmem27_AWID),
+    .m00_axi_awlen(m_axi_rmem27_AWLEN),
+    .m00_axi_awlock(m_axi_rmem27_AWLOCK),
+    .m00_axi_awprot(m_axi_rmem27_AWPROT),
+    .m00_axi_awqos(m_axi_rmem27_AWQOS),
+    .m00_axi_awready(m_axi_rmem27_AWREADY),
+    .m00_axi_awsize(m_axi_rmem27_AWSIZE),
+    .m00_axi_awvalid(m_axi_rmem27_AWVALID),
+    .m00_axi_bid(m_axi_rmem27_BID),
+    .m00_axi_bready(m_axi_rmem27_BREADY),
+    .m00_axi_bresp(m_axi_rmem27_BRESP),
+    .m00_axi_bvalid(m_axi_rmem27_BVALID),
+    .m00_axi_rdata(m_axi_rmem27_RDATA),
+    .m00_axi_rid(m_axi_rmem27_RID),
+    .m00_axi_rlast(m_axi_rmem27_RLAST),
+    .m00_axi_rready(m_axi_rmem27_RREADY),
+    .m00_axi_rresp(m_axi_rmem27_RRESP),
+    .m00_axi_rvalid(m_axi_rmem27_RVALID),
+    .m00_axi_wdata(m_axi_rmem27_WDATA),
+    .m00_axi_wlast(m_axi_rmem27_WLAST),
+    .m00_axi_wready(m_axi_rmem27_WREADY),
+    .m00_axi_wstrb(m_axi_rmem27_WSTRB),
+    .m00_axi_wvalid(m_axi_rmem27_WVALID),
+    .s00_axi_araddr(m_axi_rmem27___Mmap2Stream_27___mmap_ARADDR),
+    .s00_axi_arburst(m_axi_rmem27___Mmap2Stream_27___mmap_ARBURST),
+    .s00_axi_arcache(m_axi_rmem27___Mmap2Stream_27___mmap_ARCACHE),
+    .s00_axi_arid(m_axi_rmem27___Mmap2Stream_27___mmap_ARID),
+    .s00_axi_arlen(m_axi_rmem27___Mmap2Stream_27___mmap_ARLEN),
+    .s00_axi_arlock(m_axi_rmem27___Mmap2Stream_27___mmap_ARLOCK),
+    .s00_axi_arprot(m_axi_rmem27___Mmap2Stream_27___mmap_ARPROT),
+    .s00_axi_arqos(m_axi_rmem27___Mmap2Stream_27___mmap_ARQOS),
+    .s00_axi_arready(m_axi_rmem27___Mmap2Stream_27___mmap_ARREADY),
+    .s00_axi_arsize(m_axi_rmem27___Mmap2Stream_27___mmap_ARSIZE),
+    .s00_axi_arvalid(m_axi_rmem27___Mmap2Stream_27___mmap_ARVALID),
+    .s00_axi_awaddr(m_axi_rmem27___Mmap2Stream_27___mmap_AWADDR),
+    .s00_axi_awburst(m_axi_rmem27___Mmap2Stream_27___mmap_AWBURST),
+    .s00_axi_awcache(m_axi_rmem27___Mmap2Stream_27___mmap_AWCACHE),
+    .s00_axi_awid(m_axi_rmem27___Mmap2Stream_27___mmap_AWID),
+    .s00_axi_awlen(m_axi_rmem27___Mmap2Stream_27___mmap_AWLEN),
+    .s00_axi_awlock(m_axi_rmem27___Mmap2Stream_27___mmap_AWLOCK),
+    .s00_axi_awprot(m_axi_rmem27___Mmap2Stream_27___mmap_AWPROT),
+    .s00_axi_awqos(m_axi_rmem27___Mmap2Stream_27___mmap_AWQOS),
+    .s00_axi_awready(m_axi_rmem27___Mmap2Stream_27___mmap_AWREADY),
+    .s00_axi_awsize(m_axi_rmem27___Mmap2Stream_27___mmap_AWSIZE),
+    .s00_axi_awvalid(m_axi_rmem27___Mmap2Stream_27___mmap_AWVALID),
+    .s00_axi_bid(m_axi_rmem27___Mmap2Stream_27___mmap_BID),
+    .s00_axi_bready(m_axi_rmem27___Mmap2Stream_27___mmap_BREADY),
+    .s00_axi_bresp(m_axi_rmem27___Mmap2Stream_27___mmap_BRESP),
+    .s00_axi_bvalid(m_axi_rmem27___Mmap2Stream_27___mmap_BVALID),
+    .s00_axi_rdata(m_axi_rmem27___Mmap2Stream_27___mmap_RDATA),
+    .s00_axi_rid(m_axi_rmem27___Mmap2Stream_27___mmap_RID),
+    .s00_axi_rlast(m_axi_rmem27___Mmap2Stream_27___mmap_RLAST),
+    .s00_axi_rready(m_axi_rmem27___Mmap2Stream_27___mmap_RREADY),
+    .s00_axi_rresp(m_axi_rmem27___Mmap2Stream_27___mmap_RRESP),
+    .s00_axi_rvalid(m_axi_rmem27___Mmap2Stream_27___mmap_RVALID),
+    .s00_axi_wdata(m_axi_rmem27___Mmap2Stream_27___mmap_WDATA),
+    .s00_axi_wlast(m_axi_rmem27___Mmap2Stream_27___mmap_WLAST),
+    .s00_axi_wready(m_axi_rmem27___Mmap2Stream_27___mmap_WREADY),
+    .s00_axi_wstrb(m_axi_rmem27___Mmap2Stream_27___mmap_WSTRB),
+    .s00_axi_wvalid(m_axi_rmem27___Mmap2Stream_27___mmap_WVALID),
+    .s01_axi_araddr(m_axi_rmem27___Stream2Mmap_27___mmap_ARADDR),
+    .s01_axi_arburst(m_axi_rmem27___Stream2Mmap_27___mmap_ARBURST),
+    .s01_axi_arcache(m_axi_rmem27___Stream2Mmap_27___mmap_ARCACHE),
+    .s01_axi_arid(m_axi_rmem27___Stream2Mmap_27___mmap_ARID),
+    .s01_axi_arlen(m_axi_rmem27___Stream2Mmap_27___mmap_ARLEN),
+    .s01_axi_arlock(m_axi_rmem27___Stream2Mmap_27___mmap_ARLOCK),
+    .s01_axi_arprot(m_axi_rmem27___Stream2Mmap_27___mmap_ARPROT),
+    .s01_axi_arqos(m_axi_rmem27___Stream2Mmap_27___mmap_ARQOS),
+    .s01_axi_arready(m_axi_rmem27___Stream2Mmap_27___mmap_ARREADY),
+    .s01_axi_arsize(m_axi_rmem27___Stream2Mmap_27___mmap_ARSIZE),
+    .s01_axi_arvalid(m_axi_rmem27___Stream2Mmap_27___mmap_ARVALID),
+    .s01_axi_awaddr(m_axi_rmem27___Stream2Mmap_27___mmap_AWADDR),
+    .s01_axi_awburst(m_axi_rmem27___Stream2Mmap_27___mmap_AWBURST),
+    .s01_axi_awcache(m_axi_rmem27___Stream2Mmap_27___mmap_AWCACHE),
+    .s01_axi_awid(m_axi_rmem27___Stream2Mmap_27___mmap_AWID),
+    .s01_axi_awlen(m_axi_rmem27___Stream2Mmap_27___mmap_AWLEN),
+    .s01_axi_awlock(m_axi_rmem27___Stream2Mmap_27___mmap_AWLOCK),
+    .s01_axi_awprot(m_axi_rmem27___Stream2Mmap_27___mmap_AWPROT),
+    .s01_axi_awqos(m_axi_rmem27___Stream2Mmap_27___mmap_AWQOS),
+    .s01_axi_awready(m_axi_rmem27___Stream2Mmap_27___mmap_AWREADY),
+    .s01_axi_awsize(m_axi_rmem27___Stream2Mmap_27___mmap_AWSIZE),
+    .s01_axi_awvalid(m_axi_rmem27___Stream2Mmap_27___mmap_AWVALID),
+    .s01_axi_bid(m_axi_rmem27___Stream2Mmap_27___mmap_BID),
+    .s01_axi_bready(m_axi_rmem27___Stream2Mmap_27___mmap_BREADY),
+    .s01_axi_bresp(m_axi_rmem27___Stream2Mmap_27___mmap_BRESP),
+    .s01_axi_bvalid(m_axi_rmem27___Stream2Mmap_27___mmap_BVALID),
+    .s01_axi_rdata(m_axi_rmem27___Stream2Mmap_27___mmap_RDATA),
+    .s01_axi_rid(m_axi_rmem27___Stream2Mmap_27___mmap_RID),
+    .s01_axi_rlast(m_axi_rmem27___Stream2Mmap_27___mmap_RLAST),
+    .s01_axi_rready(m_axi_rmem27___Stream2Mmap_27___mmap_RREADY),
+    .s01_axi_rresp(m_axi_rmem27___Stream2Mmap_27___mmap_RRESP),
+    .s01_axi_rvalid(m_axi_rmem27___Stream2Mmap_27___mmap_RVALID),
+    .s01_axi_wdata(m_axi_rmem27___Stream2Mmap_27___mmap_WDATA),
+    .s01_axi_wlast(m_axi_rmem27___Stream2Mmap_27___mmap_WLAST),
+    .s01_axi_wready(m_axi_rmem27___Stream2Mmap_27___mmap_WREADY),
+    .s01_axi_wstrb(m_axi_rmem27___Stream2Mmap_27___mmap_WSTRB),
+    .s01_axi_wvalid(m_axi_rmem27___Stream2Mmap_27___mmap_WVALID)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Mmap2Stream
+  Mmap2Stream_0
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Mmap2Stream_0__ap_start),
+    .ap_done(Mmap2Stream_0__ap_done),
+    .ap_idle(Mmap2Stream_0__ap_idle),
+    .ap_ready(Mmap2Stream_0__ap_ready),
+    .n(Mmap2Stream_0___n__q0),
+    .stream_din(qr0_vadd_bw__din),
+    .stream_full_n(qr0_vadd_bw__full_n),
+    .stream_write(qr0_vadd_bw__write),
+    .m_axi_mmap_ARADDR(m_axi_rmem0___Mmap2Stream_0___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem0___Mmap2Stream_0___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem0___Mmap2Stream_0___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem0___Mmap2Stream_0___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem0___Mmap2Stream_0___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem0___Mmap2Stream_0___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem0___Mmap2Stream_0___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem0___Mmap2Stream_0___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem0___Mmap2Stream_0___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem0___Mmap2Stream_0___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem0___Mmap2Stream_0___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem0___Mmap2Stream_0___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem0___Mmap2Stream_0___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem0___Mmap2Stream_0___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem0___Mmap2Stream_0___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem0___Mmap2Stream_0___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem0___Mmap2Stream_0___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem0___Mmap2Stream_0___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem0___Mmap2Stream_0___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem0___Mmap2Stream_0___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem0___Mmap2Stream_0___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem0___Mmap2Stream_0___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem0___Mmap2Stream_0___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem0___Mmap2Stream_0___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem0___Mmap2Stream_0___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem0___Mmap2Stream_0___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem0___Mmap2Stream_0___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem0___Mmap2Stream_0___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem0___Mmap2Stream_0___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem0___Mmap2Stream_0___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem0___Mmap2Stream_0___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem0___Mmap2Stream_0___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem0___Mmap2Stream_0___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem0___Mmap2Stream_0___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem0___Mmap2Stream_0___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem0___Mmap2Stream_0___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem0___Mmap2Stream_0___mmap_AWQOS),
+    .mmap_offset(Mmap2Stream_0___rmem0__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Mmap2Stream
+  Mmap2Stream_1
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Mmap2Stream_1__ap_start),
+    .ap_done(Mmap2Stream_1__ap_done),
+    .ap_idle(Mmap2Stream_1__ap_idle),
+    .ap_ready(Mmap2Stream_1__ap_ready),
+    .n(Mmap2Stream_1___n__q0),
+    .stream_din(qr1_vadd_bw__din),
+    .stream_full_n(qr1_vadd_bw__full_n),
+    .stream_write(qr1_vadd_bw__write),
+    .m_axi_mmap_ARADDR(m_axi_rmem1___Mmap2Stream_1___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem1___Mmap2Stream_1___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem1___Mmap2Stream_1___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem1___Mmap2Stream_1___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem1___Mmap2Stream_1___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem1___Mmap2Stream_1___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem1___Mmap2Stream_1___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem1___Mmap2Stream_1___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem1___Mmap2Stream_1___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem1___Mmap2Stream_1___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem1___Mmap2Stream_1___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem1___Mmap2Stream_1___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem1___Mmap2Stream_1___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem1___Mmap2Stream_1___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem1___Mmap2Stream_1___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem1___Mmap2Stream_1___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem1___Mmap2Stream_1___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem1___Mmap2Stream_1___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem1___Mmap2Stream_1___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem1___Mmap2Stream_1___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem1___Mmap2Stream_1___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem1___Mmap2Stream_1___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem1___Mmap2Stream_1___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem1___Mmap2Stream_1___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem1___Mmap2Stream_1___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem1___Mmap2Stream_1___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem1___Mmap2Stream_1___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem1___Mmap2Stream_1___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem1___Mmap2Stream_1___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem1___Mmap2Stream_1___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem1___Mmap2Stream_1___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem1___Mmap2Stream_1___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem1___Mmap2Stream_1___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem1___Mmap2Stream_1___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem1___Mmap2Stream_1___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem1___Mmap2Stream_1___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem1___Mmap2Stream_1___mmap_AWQOS),
+    .mmap_offset(Mmap2Stream_1___rmem1__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Mmap2Stream
+  Mmap2Stream_2
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Mmap2Stream_2__ap_start),
+    .ap_done(Mmap2Stream_2__ap_done),
+    .ap_idle(Mmap2Stream_2__ap_idle),
+    .ap_ready(Mmap2Stream_2__ap_ready),
+    .n(Mmap2Stream_2___n__q0),
+    .stream_din(qr2_vadd_bw__din),
+    .stream_full_n(qr2_vadd_bw__full_n),
+    .stream_write(qr2_vadd_bw__write),
+    .m_axi_mmap_ARADDR(m_axi_rmem2___Mmap2Stream_2___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem2___Mmap2Stream_2___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem2___Mmap2Stream_2___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem2___Mmap2Stream_2___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem2___Mmap2Stream_2___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem2___Mmap2Stream_2___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem2___Mmap2Stream_2___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem2___Mmap2Stream_2___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem2___Mmap2Stream_2___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem2___Mmap2Stream_2___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem2___Mmap2Stream_2___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem2___Mmap2Stream_2___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem2___Mmap2Stream_2___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem2___Mmap2Stream_2___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem2___Mmap2Stream_2___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem2___Mmap2Stream_2___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem2___Mmap2Stream_2___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem2___Mmap2Stream_2___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem2___Mmap2Stream_2___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem2___Mmap2Stream_2___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem2___Mmap2Stream_2___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem2___Mmap2Stream_2___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem2___Mmap2Stream_2___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem2___Mmap2Stream_2___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem2___Mmap2Stream_2___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem2___Mmap2Stream_2___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem2___Mmap2Stream_2___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem2___Mmap2Stream_2___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem2___Mmap2Stream_2___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem2___Mmap2Stream_2___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem2___Mmap2Stream_2___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem2___Mmap2Stream_2___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem2___Mmap2Stream_2___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem2___Mmap2Stream_2___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem2___Mmap2Stream_2___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem2___Mmap2Stream_2___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem2___Mmap2Stream_2___mmap_AWQOS),
+    .mmap_offset(Mmap2Stream_2___rmem2__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Mmap2Stream
+  Mmap2Stream_3
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Mmap2Stream_3__ap_start),
+    .ap_done(Mmap2Stream_3__ap_done),
+    .ap_idle(Mmap2Stream_3__ap_idle),
+    .ap_ready(Mmap2Stream_3__ap_ready),
+    .n(Mmap2Stream_3___n__q0),
+    .stream_din(qr3_vadd_bw__din),
+    .stream_full_n(qr3_vadd_bw__full_n),
+    .stream_write(qr3_vadd_bw__write),
+    .m_axi_mmap_ARADDR(m_axi_rmem3___Mmap2Stream_3___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem3___Mmap2Stream_3___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem3___Mmap2Stream_3___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem3___Mmap2Stream_3___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem3___Mmap2Stream_3___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem3___Mmap2Stream_3___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem3___Mmap2Stream_3___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem3___Mmap2Stream_3___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem3___Mmap2Stream_3___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem3___Mmap2Stream_3___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem3___Mmap2Stream_3___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem3___Mmap2Stream_3___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem3___Mmap2Stream_3___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem3___Mmap2Stream_3___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem3___Mmap2Stream_3___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem3___Mmap2Stream_3___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem3___Mmap2Stream_3___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem3___Mmap2Stream_3___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem3___Mmap2Stream_3___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem3___Mmap2Stream_3___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem3___Mmap2Stream_3___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem3___Mmap2Stream_3___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem3___Mmap2Stream_3___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem3___Mmap2Stream_3___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem3___Mmap2Stream_3___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem3___Mmap2Stream_3___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem3___Mmap2Stream_3___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem3___Mmap2Stream_3___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem3___Mmap2Stream_3___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem3___Mmap2Stream_3___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem3___Mmap2Stream_3___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem3___Mmap2Stream_3___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem3___Mmap2Stream_3___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem3___Mmap2Stream_3___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem3___Mmap2Stream_3___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem3___Mmap2Stream_3___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem3___Mmap2Stream_3___mmap_AWQOS),
+    .mmap_offset(Mmap2Stream_3___rmem3__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Mmap2Stream
+  Mmap2Stream_4
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Mmap2Stream_4__ap_start),
+    .ap_done(Mmap2Stream_4__ap_done),
+    .ap_idle(Mmap2Stream_4__ap_idle),
+    .ap_ready(Mmap2Stream_4__ap_ready),
+    .n(Mmap2Stream_4___n__q0),
+    .stream_din(qr4_vadd_bw__din),
+    .stream_full_n(qr4_vadd_bw__full_n),
+    .stream_write(qr4_vadd_bw__write),
+    .m_axi_mmap_ARADDR(m_axi_rmem4___Mmap2Stream_4___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem4___Mmap2Stream_4___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem4___Mmap2Stream_4___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem4___Mmap2Stream_4___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem4___Mmap2Stream_4___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem4___Mmap2Stream_4___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem4___Mmap2Stream_4___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem4___Mmap2Stream_4___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem4___Mmap2Stream_4___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem4___Mmap2Stream_4___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem4___Mmap2Stream_4___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem4___Mmap2Stream_4___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem4___Mmap2Stream_4___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem4___Mmap2Stream_4___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem4___Mmap2Stream_4___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem4___Mmap2Stream_4___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem4___Mmap2Stream_4___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem4___Mmap2Stream_4___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem4___Mmap2Stream_4___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem4___Mmap2Stream_4___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem4___Mmap2Stream_4___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem4___Mmap2Stream_4___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem4___Mmap2Stream_4___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem4___Mmap2Stream_4___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem4___Mmap2Stream_4___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem4___Mmap2Stream_4___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem4___Mmap2Stream_4___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem4___Mmap2Stream_4___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem4___Mmap2Stream_4___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem4___Mmap2Stream_4___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem4___Mmap2Stream_4___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem4___Mmap2Stream_4___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem4___Mmap2Stream_4___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem4___Mmap2Stream_4___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem4___Mmap2Stream_4___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem4___Mmap2Stream_4___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem4___Mmap2Stream_4___mmap_AWQOS),
+    .mmap_offset(Mmap2Stream_4___rmem4__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Mmap2Stream
+  Mmap2Stream_5
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Mmap2Stream_5__ap_start),
+    .ap_done(Mmap2Stream_5__ap_done),
+    .ap_idle(Mmap2Stream_5__ap_idle),
+    .ap_ready(Mmap2Stream_5__ap_ready),
+    .n(Mmap2Stream_5___n__q0),
+    .stream_din(qr5_vadd_bw__din),
+    .stream_full_n(qr5_vadd_bw__full_n),
+    .stream_write(qr5_vadd_bw__write),
+    .m_axi_mmap_ARADDR(m_axi_rmem5___Mmap2Stream_5___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem5___Mmap2Stream_5___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem5___Mmap2Stream_5___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem5___Mmap2Stream_5___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem5___Mmap2Stream_5___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem5___Mmap2Stream_5___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem5___Mmap2Stream_5___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem5___Mmap2Stream_5___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem5___Mmap2Stream_5___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem5___Mmap2Stream_5___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem5___Mmap2Stream_5___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem5___Mmap2Stream_5___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem5___Mmap2Stream_5___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem5___Mmap2Stream_5___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem5___Mmap2Stream_5___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem5___Mmap2Stream_5___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem5___Mmap2Stream_5___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem5___Mmap2Stream_5___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem5___Mmap2Stream_5___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem5___Mmap2Stream_5___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem5___Mmap2Stream_5___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem5___Mmap2Stream_5___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem5___Mmap2Stream_5___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem5___Mmap2Stream_5___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem5___Mmap2Stream_5___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem5___Mmap2Stream_5___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem5___Mmap2Stream_5___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem5___Mmap2Stream_5___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem5___Mmap2Stream_5___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem5___Mmap2Stream_5___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem5___Mmap2Stream_5___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem5___Mmap2Stream_5___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem5___Mmap2Stream_5___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem5___Mmap2Stream_5___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem5___Mmap2Stream_5___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem5___Mmap2Stream_5___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem5___Mmap2Stream_5___mmap_AWQOS),
+    .mmap_offset(Mmap2Stream_5___rmem5__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Mmap2Stream
+  Mmap2Stream_6
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Mmap2Stream_6__ap_start),
+    .ap_done(Mmap2Stream_6__ap_done),
+    .ap_idle(Mmap2Stream_6__ap_idle),
+    .ap_ready(Mmap2Stream_6__ap_ready),
+    .n(Mmap2Stream_6___n__q0),
+    .stream_din(qr6_vadd_bw__din),
+    .stream_full_n(qr6_vadd_bw__full_n),
+    .stream_write(qr6_vadd_bw__write),
+    .m_axi_mmap_ARADDR(m_axi_rmem6___Mmap2Stream_6___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem6___Mmap2Stream_6___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem6___Mmap2Stream_6___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem6___Mmap2Stream_6___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem6___Mmap2Stream_6___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem6___Mmap2Stream_6___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem6___Mmap2Stream_6___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem6___Mmap2Stream_6___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem6___Mmap2Stream_6___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem6___Mmap2Stream_6___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem6___Mmap2Stream_6___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem6___Mmap2Stream_6___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem6___Mmap2Stream_6___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem6___Mmap2Stream_6___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem6___Mmap2Stream_6___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem6___Mmap2Stream_6___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem6___Mmap2Stream_6___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem6___Mmap2Stream_6___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem6___Mmap2Stream_6___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem6___Mmap2Stream_6___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem6___Mmap2Stream_6___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem6___Mmap2Stream_6___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem6___Mmap2Stream_6___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem6___Mmap2Stream_6___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem6___Mmap2Stream_6___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem6___Mmap2Stream_6___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem6___Mmap2Stream_6___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem6___Mmap2Stream_6___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem6___Mmap2Stream_6___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem6___Mmap2Stream_6___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem6___Mmap2Stream_6___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem6___Mmap2Stream_6___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem6___Mmap2Stream_6___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem6___Mmap2Stream_6___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem6___Mmap2Stream_6___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem6___Mmap2Stream_6___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem6___Mmap2Stream_6___mmap_AWQOS),
+    .mmap_offset(Mmap2Stream_6___rmem6__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Mmap2Stream
+  Mmap2Stream_7
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Mmap2Stream_7__ap_start),
+    .ap_done(Mmap2Stream_7__ap_done),
+    .ap_idle(Mmap2Stream_7__ap_idle),
+    .ap_ready(Mmap2Stream_7__ap_ready),
+    .n(Mmap2Stream_7___n__q0),
+    .stream_din(qr7_vadd_bw__din),
+    .stream_full_n(qr7_vadd_bw__full_n),
+    .stream_write(qr7_vadd_bw__write),
+    .m_axi_mmap_ARADDR(m_axi_rmem7___Mmap2Stream_7___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem7___Mmap2Stream_7___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem7___Mmap2Stream_7___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem7___Mmap2Stream_7___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem7___Mmap2Stream_7___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem7___Mmap2Stream_7___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem7___Mmap2Stream_7___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem7___Mmap2Stream_7___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem7___Mmap2Stream_7___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem7___Mmap2Stream_7___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem7___Mmap2Stream_7___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem7___Mmap2Stream_7___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem7___Mmap2Stream_7___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem7___Mmap2Stream_7___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem7___Mmap2Stream_7___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem7___Mmap2Stream_7___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem7___Mmap2Stream_7___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem7___Mmap2Stream_7___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem7___Mmap2Stream_7___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem7___Mmap2Stream_7___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem7___Mmap2Stream_7___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem7___Mmap2Stream_7___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem7___Mmap2Stream_7___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem7___Mmap2Stream_7___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem7___Mmap2Stream_7___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem7___Mmap2Stream_7___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem7___Mmap2Stream_7___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem7___Mmap2Stream_7___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem7___Mmap2Stream_7___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem7___Mmap2Stream_7___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem7___Mmap2Stream_7___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem7___Mmap2Stream_7___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem7___Mmap2Stream_7___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem7___Mmap2Stream_7___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem7___Mmap2Stream_7___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem7___Mmap2Stream_7___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem7___Mmap2Stream_7___mmap_AWQOS),
+    .mmap_offset(Mmap2Stream_7___rmem7__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Mmap2Stream
+  Mmap2Stream_8
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Mmap2Stream_8__ap_start),
+    .ap_done(Mmap2Stream_8__ap_done),
+    .ap_idle(Mmap2Stream_8__ap_idle),
+    .ap_ready(Mmap2Stream_8__ap_ready),
+    .n(Mmap2Stream_8___n__q0),
+    .stream_din(qr8_vadd_bw__din),
+    .stream_full_n(qr8_vadd_bw__full_n),
+    .stream_write(qr8_vadd_bw__write),
+    .m_axi_mmap_ARADDR(m_axi_rmem8___Mmap2Stream_8___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem8___Mmap2Stream_8___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem8___Mmap2Stream_8___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem8___Mmap2Stream_8___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem8___Mmap2Stream_8___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem8___Mmap2Stream_8___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem8___Mmap2Stream_8___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem8___Mmap2Stream_8___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem8___Mmap2Stream_8___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem8___Mmap2Stream_8___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem8___Mmap2Stream_8___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem8___Mmap2Stream_8___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem8___Mmap2Stream_8___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem8___Mmap2Stream_8___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem8___Mmap2Stream_8___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem8___Mmap2Stream_8___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem8___Mmap2Stream_8___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem8___Mmap2Stream_8___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem8___Mmap2Stream_8___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem8___Mmap2Stream_8___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem8___Mmap2Stream_8___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem8___Mmap2Stream_8___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem8___Mmap2Stream_8___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem8___Mmap2Stream_8___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem8___Mmap2Stream_8___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem8___Mmap2Stream_8___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem8___Mmap2Stream_8___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem8___Mmap2Stream_8___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem8___Mmap2Stream_8___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem8___Mmap2Stream_8___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem8___Mmap2Stream_8___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem8___Mmap2Stream_8___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem8___Mmap2Stream_8___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem8___Mmap2Stream_8___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem8___Mmap2Stream_8___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem8___Mmap2Stream_8___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem8___Mmap2Stream_8___mmap_AWQOS),
+    .mmap_offset(Mmap2Stream_8___rmem8__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Mmap2Stream
+  Mmap2Stream_9
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Mmap2Stream_9__ap_start),
+    .ap_done(Mmap2Stream_9__ap_done),
+    .ap_idle(Mmap2Stream_9__ap_idle),
+    .ap_ready(Mmap2Stream_9__ap_ready),
+    .n(Mmap2Stream_9___n__q0),
+    .stream_din(qr9_vadd_bw__din),
+    .stream_full_n(qr9_vadd_bw__full_n),
+    .stream_write(qr9_vadd_bw__write),
+    .m_axi_mmap_ARADDR(m_axi_rmem9___Mmap2Stream_9___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem9___Mmap2Stream_9___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem9___Mmap2Stream_9___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem9___Mmap2Stream_9___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem9___Mmap2Stream_9___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem9___Mmap2Stream_9___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem9___Mmap2Stream_9___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem9___Mmap2Stream_9___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem9___Mmap2Stream_9___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem9___Mmap2Stream_9___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem9___Mmap2Stream_9___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem9___Mmap2Stream_9___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem9___Mmap2Stream_9___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem9___Mmap2Stream_9___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem9___Mmap2Stream_9___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem9___Mmap2Stream_9___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem9___Mmap2Stream_9___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem9___Mmap2Stream_9___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem9___Mmap2Stream_9___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem9___Mmap2Stream_9___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem9___Mmap2Stream_9___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem9___Mmap2Stream_9___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem9___Mmap2Stream_9___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem9___Mmap2Stream_9___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem9___Mmap2Stream_9___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem9___Mmap2Stream_9___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem9___Mmap2Stream_9___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem9___Mmap2Stream_9___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem9___Mmap2Stream_9___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem9___Mmap2Stream_9___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem9___Mmap2Stream_9___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem9___Mmap2Stream_9___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem9___Mmap2Stream_9___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem9___Mmap2Stream_9___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem9___Mmap2Stream_9___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem9___Mmap2Stream_9___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem9___Mmap2Stream_9___mmap_AWQOS),
+    .mmap_offset(Mmap2Stream_9___rmem9__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Mmap2Stream
+  Mmap2Stream_10
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Mmap2Stream_10__ap_start),
+    .ap_done(Mmap2Stream_10__ap_done),
+    .ap_idle(Mmap2Stream_10__ap_idle),
+    .ap_ready(Mmap2Stream_10__ap_ready),
+    .n(Mmap2Stream_10___n__q0),
+    .stream_din(qr10_vadd_bw__din),
+    .stream_full_n(qr10_vadd_bw__full_n),
+    .stream_write(qr10_vadd_bw__write),
+    .m_axi_mmap_ARADDR(m_axi_rmem10___Mmap2Stream_10___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem10___Mmap2Stream_10___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem10___Mmap2Stream_10___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem10___Mmap2Stream_10___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem10___Mmap2Stream_10___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem10___Mmap2Stream_10___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem10___Mmap2Stream_10___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem10___Mmap2Stream_10___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem10___Mmap2Stream_10___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem10___Mmap2Stream_10___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem10___Mmap2Stream_10___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem10___Mmap2Stream_10___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem10___Mmap2Stream_10___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem10___Mmap2Stream_10___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem10___Mmap2Stream_10___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem10___Mmap2Stream_10___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem10___Mmap2Stream_10___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem10___Mmap2Stream_10___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem10___Mmap2Stream_10___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem10___Mmap2Stream_10___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem10___Mmap2Stream_10___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem10___Mmap2Stream_10___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem10___Mmap2Stream_10___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem10___Mmap2Stream_10___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem10___Mmap2Stream_10___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem10___Mmap2Stream_10___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem10___Mmap2Stream_10___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem10___Mmap2Stream_10___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem10___Mmap2Stream_10___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem10___Mmap2Stream_10___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem10___Mmap2Stream_10___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem10___Mmap2Stream_10___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem10___Mmap2Stream_10___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem10___Mmap2Stream_10___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem10___Mmap2Stream_10___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem10___Mmap2Stream_10___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem10___Mmap2Stream_10___mmap_AWQOS),
+    .mmap_offset(Mmap2Stream_10___rmem10__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Mmap2Stream
+  Mmap2Stream_11
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Mmap2Stream_11__ap_start),
+    .ap_done(Mmap2Stream_11__ap_done),
+    .ap_idle(Mmap2Stream_11__ap_idle),
+    .ap_ready(Mmap2Stream_11__ap_ready),
+    .n(Mmap2Stream_11___n__q0),
+    .stream_din(qr11_vadd_bw__din),
+    .stream_full_n(qr11_vadd_bw__full_n),
+    .stream_write(qr11_vadd_bw__write),
+    .m_axi_mmap_ARADDR(m_axi_rmem11___Mmap2Stream_11___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem11___Mmap2Stream_11___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem11___Mmap2Stream_11___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem11___Mmap2Stream_11___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem11___Mmap2Stream_11___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem11___Mmap2Stream_11___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem11___Mmap2Stream_11___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem11___Mmap2Stream_11___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem11___Mmap2Stream_11___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem11___Mmap2Stream_11___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem11___Mmap2Stream_11___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem11___Mmap2Stream_11___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem11___Mmap2Stream_11___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem11___Mmap2Stream_11___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem11___Mmap2Stream_11___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem11___Mmap2Stream_11___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem11___Mmap2Stream_11___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem11___Mmap2Stream_11___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem11___Mmap2Stream_11___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem11___Mmap2Stream_11___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem11___Mmap2Stream_11___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem11___Mmap2Stream_11___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem11___Mmap2Stream_11___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem11___Mmap2Stream_11___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem11___Mmap2Stream_11___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem11___Mmap2Stream_11___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem11___Mmap2Stream_11___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem11___Mmap2Stream_11___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem11___Mmap2Stream_11___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem11___Mmap2Stream_11___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem11___Mmap2Stream_11___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem11___Mmap2Stream_11___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem11___Mmap2Stream_11___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem11___Mmap2Stream_11___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem11___Mmap2Stream_11___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem11___Mmap2Stream_11___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem11___Mmap2Stream_11___mmap_AWQOS),
+    .mmap_offset(Mmap2Stream_11___rmem11__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Mmap2Stream
+  Mmap2Stream_12
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Mmap2Stream_12__ap_start),
+    .ap_done(Mmap2Stream_12__ap_done),
+    .ap_idle(Mmap2Stream_12__ap_idle),
+    .ap_ready(Mmap2Stream_12__ap_ready),
+    .n(Mmap2Stream_12___n__q0),
+    .stream_din(qr12_vadd_bw__din),
+    .stream_full_n(qr12_vadd_bw__full_n),
+    .stream_write(qr12_vadd_bw__write),
+    .m_axi_mmap_ARADDR(m_axi_rmem12___Mmap2Stream_12___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem12___Mmap2Stream_12___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem12___Mmap2Stream_12___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem12___Mmap2Stream_12___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem12___Mmap2Stream_12___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem12___Mmap2Stream_12___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem12___Mmap2Stream_12___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem12___Mmap2Stream_12___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem12___Mmap2Stream_12___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem12___Mmap2Stream_12___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem12___Mmap2Stream_12___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem12___Mmap2Stream_12___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem12___Mmap2Stream_12___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem12___Mmap2Stream_12___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem12___Mmap2Stream_12___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem12___Mmap2Stream_12___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem12___Mmap2Stream_12___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem12___Mmap2Stream_12___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem12___Mmap2Stream_12___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem12___Mmap2Stream_12___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem12___Mmap2Stream_12___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem12___Mmap2Stream_12___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem12___Mmap2Stream_12___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem12___Mmap2Stream_12___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem12___Mmap2Stream_12___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem12___Mmap2Stream_12___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem12___Mmap2Stream_12___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem12___Mmap2Stream_12___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem12___Mmap2Stream_12___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem12___Mmap2Stream_12___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem12___Mmap2Stream_12___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem12___Mmap2Stream_12___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem12___Mmap2Stream_12___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem12___Mmap2Stream_12___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem12___Mmap2Stream_12___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem12___Mmap2Stream_12___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem12___Mmap2Stream_12___mmap_AWQOS),
+    .mmap_offset(Mmap2Stream_12___rmem12__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Mmap2Stream
+  Mmap2Stream_13
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Mmap2Stream_13__ap_start),
+    .ap_done(Mmap2Stream_13__ap_done),
+    .ap_idle(Mmap2Stream_13__ap_idle),
+    .ap_ready(Mmap2Stream_13__ap_ready),
+    .n(Mmap2Stream_13___n__q0),
+    .stream_din(qr13_vadd_bw__din),
+    .stream_full_n(qr13_vadd_bw__full_n),
+    .stream_write(qr13_vadd_bw__write),
+    .m_axi_mmap_ARADDR(m_axi_rmem13___Mmap2Stream_13___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem13___Mmap2Stream_13___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem13___Mmap2Stream_13___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem13___Mmap2Stream_13___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem13___Mmap2Stream_13___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem13___Mmap2Stream_13___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem13___Mmap2Stream_13___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem13___Mmap2Stream_13___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem13___Mmap2Stream_13___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem13___Mmap2Stream_13___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem13___Mmap2Stream_13___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem13___Mmap2Stream_13___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem13___Mmap2Stream_13___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem13___Mmap2Stream_13___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem13___Mmap2Stream_13___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem13___Mmap2Stream_13___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem13___Mmap2Stream_13___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem13___Mmap2Stream_13___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem13___Mmap2Stream_13___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem13___Mmap2Stream_13___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem13___Mmap2Stream_13___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem13___Mmap2Stream_13___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem13___Mmap2Stream_13___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem13___Mmap2Stream_13___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem13___Mmap2Stream_13___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem13___Mmap2Stream_13___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem13___Mmap2Stream_13___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem13___Mmap2Stream_13___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem13___Mmap2Stream_13___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem13___Mmap2Stream_13___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem13___Mmap2Stream_13___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem13___Mmap2Stream_13___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem13___Mmap2Stream_13___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem13___Mmap2Stream_13___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem13___Mmap2Stream_13___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem13___Mmap2Stream_13___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem13___Mmap2Stream_13___mmap_AWQOS),
+    .mmap_offset(Mmap2Stream_13___rmem13__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Mmap2Stream
+  Mmap2Stream_14
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Mmap2Stream_14__ap_start),
+    .ap_done(Mmap2Stream_14__ap_done),
+    .ap_idle(Mmap2Stream_14__ap_idle),
+    .ap_ready(Mmap2Stream_14__ap_ready),
+    .n(Mmap2Stream_14___n__q0),
+    .stream_din(qr14_vadd_bw__din),
+    .stream_full_n(qr14_vadd_bw__full_n),
+    .stream_write(qr14_vadd_bw__write),
+    .m_axi_mmap_ARADDR(m_axi_rmem14___Mmap2Stream_14___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem14___Mmap2Stream_14___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem14___Mmap2Stream_14___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem14___Mmap2Stream_14___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem14___Mmap2Stream_14___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem14___Mmap2Stream_14___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem14___Mmap2Stream_14___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem14___Mmap2Stream_14___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem14___Mmap2Stream_14___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem14___Mmap2Stream_14___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem14___Mmap2Stream_14___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem14___Mmap2Stream_14___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem14___Mmap2Stream_14___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem14___Mmap2Stream_14___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem14___Mmap2Stream_14___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem14___Mmap2Stream_14___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem14___Mmap2Stream_14___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem14___Mmap2Stream_14___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem14___Mmap2Stream_14___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem14___Mmap2Stream_14___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem14___Mmap2Stream_14___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem14___Mmap2Stream_14___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem14___Mmap2Stream_14___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem14___Mmap2Stream_14___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem14___Mmap2Stream_14___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem14___Mmap2Stream_14___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem14___Mmap2Stream_14___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem14___Mmap2Stream_14___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem14___Mmap2Stream_14___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem14___Mmap2Stream_14___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem14___Mmap2Stream_14___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem14___Mmap2Stream_14___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem14___Mmap2Stream_14___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem14___Mmap2Stream_14___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem14___Mmap2Stream_14___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem14___Mmap2Stream_14___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem14___Mmap2Stream_14___mmap_AWQOS),
+    .mmap_offset(Mmap2Stream_14___rmem14__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Mmap2Stream
+  Mmap2Stream_15
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Mmap2Stream_15__ap_start),
+    .ap_done(Mmap2Stream_15__ap_done),
+    .ap_idle(Mmap2Stream_15__ap_idle),
+    .ap_ready(Mmap2Stream_15__ap_ready),
+    .n(Mmap2Stream_15___n__q0),
+    .stream_din(qr15_vadd_bw__din),
+    .stream_full_n(qr15_vadd_bw__full_n),
+    .stream_write(qr15_vadd_bw__write),
+    .m_axi_mmap_ARADDR(m_axi_rmem15___Mmap2Stream_15___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem15___Mmap2Stream_15___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem15___Mmap2Stream_15___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem15___Mmap2Stream_15___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem15___Mmap2Stream_15___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem15___Mmap2Stream_15___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem15___Mmap2Stream_15___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem15___Mmap2Stream_15___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem15___Mmap2Stream_15___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem15___Mmap2Stream_15___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem15___Mmap2Stream_15___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem15___Mmap2Stream_15___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem15___Mmap2Stream_15___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem15___Mmap2Stream_15___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem15___Mmap2Stream_15___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem15___Mmap2Stream_15___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem15___Mmap2Stream_15___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem15___Mmap2Stream_15___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem15___Mmap2Stream_15___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem15___Mmap2Stream_15___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem15___Mmap2Stream_15___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem15___Mmap2Stream_15___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem15___Mmap2Stream_15___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem15___Mmap2Stream_15___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem15___Mmap2Stream_15___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem15___Mmap2Stream_15___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem15___Mmap2Stream_15___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem15___Mmap2Stream_15___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem15___Mmap2Stream_15___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem15___Mmap2Stream_15___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem15___Mmap2Stream_15___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem15___Mmap2Stream_15___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem15___Mmap2Stream_15___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem15___Mmap2Stream_15___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem15___Mmap2Stream_15___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem15___Mmap2Stream_15___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem15___Mmap2Stream_15___mmap_AWQOS),
+    .mmap_offset(Mmap2Stream_15___rmem15__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Mmap2Stream
+  Mmap2Stream_16
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Mmap2Stream_16__ap_start),
+    .ap_done(Mmap2Stream_16__ap_done),
+    .ap_idle(Mmap2Stream_16__ap_idle),
+    .ap_ready(Mmap2Stream_16__ap_ready),
+    .n(Mmap2Stream_16___n__q0),
+    .stream_din(qr16_vadd_bw__din),
+    .stream_full_n(qr16_vadd_bw__full_n),
+    .stream_write(qr16_vadd_bw__write),
+    .m_axi_mmap_ARADDR(m_axi_rmem16___Mmap2Stream_16___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem16___Mmap2Stream_16___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem16___Mmap2Stream_16___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem16___Mmap2Stream_16___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem16___Mmap2Stream_16___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem16___Mmap2Stream_16___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem16___Mmap2Stream_16___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem16___Mmap2Stream_16___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem16___Mmap2Stream_16___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem16___Mmap2Stream_16___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem16___Mmap2Stream_16___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem16___Mmap2Stream_16___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem16___Mmap2Stream_16___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem16___Mmap2Stream_16___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem16___Mmap2Stream_16___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem16___Mmap2Stream_16___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem16___Mmap2Stream_16___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem16___Mmap2Stream_16___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem16___Mmap2Stream_16___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem16___Mmap2Stream_16___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem16___Mmap2Stream_16___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem16___Mmap2Stream_16___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem16___Mmap2Stream_16___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem16___Mmap2Stream_16___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem16___Mmap2Stream_16___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem16___Mmap2Stream_16___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem16___Mmap2Stream_16___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem16___Mmap2Stream_16___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem16___Mmap2Stream_16___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem16___Mmap2Stream_16___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem16___Mmap2Stream_16___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem16___Mmap2Stream_16___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem16___Mmap2Stream_16___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem16___Mmap2Stream_16___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem16___Mmap2Stream_16___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem16___Mmap2Stream_16___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem16___Mmap2Stream_16___mmap_AWQOS),
+    .mmap_offset(Mmap2Stream_16___rmem16__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Mmap2Stream
+  Mmap2Stream_17
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Mmap2Stream_17__ap_start),
+    .ap_done(Mmap2Stream_17__ap_done),
+    .ap_idle(Mmap2Stream_17__ap_idle),
+    .ap_ready(Mmap2Stream_17__ap_ready),
+    .n(Mmap2Stream_17___n__q0),
+    .stream_din(qr17_vadd_bw__din),
+    .stream_full_n(qr17_vadd_bw__full_n),
+    .stream_write(qr17_vadd_bw__write),
+    .m_axi_mmap_ARADDR(m_axi_rmem17___Mmap2Stream_17___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem17___Mmap2Stream_17___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem17___Mmap2Stream_17___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem17___Mmap2Stream_17___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem17___Mmap2Stream_17___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem17___Mmap2Stream_17___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem17___Mmap2Stream_17___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem17___Mmap2Stream_17___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem17___Mmap2Stream_17___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem17___Mmap2Stream_17___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem17___Mmap2Stream_17___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem17___Mmap2Stream_17___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem17___Mmap2Stream_17___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem17___Mmap2Stream_17___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem17___Mmap2Stream_17___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem17___Mmap2Stream_17___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem17___Mmap2Stream_17___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem17___Mmap2Stream_17___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem17___Mmap2Stream_17___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem17___Mmap2Stream_17___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem17___Mmap2Stream_17___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem17___Mmap2Stream_17___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem17___Mmap2Stream_17___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem17___Mmap2Stream_17___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem17___Mmap2Stream_17___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem17___Mmap2Stream_17___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem17___Mmap2Stream_17___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem17___Mmap2Stream_17___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem17___Mmap2Stream_17___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem17___Mmap2Stream_17___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem17___Mmap2Stream_17___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem17___Mmap2Stream_17___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem17___Mmap2Stream_17___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem17___Mmap2Stream_17___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem17___Mmap2Stream_17___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem17___Mmap2Stream_17___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem17___Mmap2Stream_17___mmap_AWQOS),
+    .mmap_offset(Mmap2Stream_17___rmem17__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Mmap2Stream
+  Mmap2Stream_18
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Mmap2Stream_18__ap_start),
+    .ap_done(Mmap2Stream_18__ap_done),
+    .ap_idle(Mmap2Stream_18__ap_idle),
+    .ap_ready(Mmap2Stream_18__ap_ready),
+    .n(Mmap2Stream_18___n__q0),
+    .stream_din(qr18_vadd_bw__din),
+    .stream_full_n(qr18_vadd_bw__full_n),
+    .stream_write(qr18_vadd_bw__write),
+    .m_axi_mmap_ARADDR(m_axi_rmem18___Mmap2Stream_18___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem18___Mmap2Stream_18___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem18___Mmap2Stream_18___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem18___Mmap2Stream_18___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem18___Mmap2Stream_18___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem18___Mmap2Stream_18___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem18___Mmap2Stream_18___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem18___Mmap2Stream_18___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem18___Mmap2Stream_18___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem18___Mmap2Stream_18___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem18___Mmap2Stream_18___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem18___Mmap2Stream_18___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem18___Mmap2Stream_18___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem18___Mmap2Stream_18___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem18___Mmap2Stream_18___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem18___Mmap2Stream_18___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem18___Mmap2Stream_18___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem18___Mmap2Stream_18___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem18___Mmap2Stream_18___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem18___Mmap2Stream_18___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem18___Mmap2Stream_18___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem18___Mmap2Stream_18___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem18___Mmap2Stream_18___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem18___Mmap2Stream_18___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem18___Mmap2Stream_18___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem18___Mmap2Stream_18___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem18___Mmap2Stream_18___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem18___Mmap2Stream_18___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem18___Mmap2Stream_18___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem18___Mmap2Stream_18___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem18___Mmap2Stream_18___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem18___Mmap2Stream_18___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem18___Mmap2Stream_18___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem18___Mmap2Stream_18___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem18___Mmap2Stream_18___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem18___Mmap2Stream_18___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem18___Mmap2Stream_18___mmap_AWQOS),
+    .mmap_offset(Mmap2Stream_18___rmem18__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Mmap2Stream
+  Mmap2Stream_19
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Mmap2Stream_19__ap_start),
+    .ap_done(Mmap2Stream_19__ap_done),
+    .ap_idle(Mmap2Stream_19__ap_idle),
+    .ap_ready(Mmap2Stream_19__ap_ready),
+    .n(Mmap2Stream_19___n__q0),
+    .stream_din(qr19_vadd_bw__din),
+    .stream_full_n(qr19_vadd_bw__full_n),
+    .stream_write(qr19_vadd_bw__write),
+    .m_axi_mmap_ARADDR(m_axi_rmem19___Mmap2Stream_19___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem19___Mmap2Stream_19___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem19___Mmap2Stream_19___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem19___Mmap2Stream_19___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem19___Mmap2Stream_19___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem19___Mmap2Stream_19___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem19___Mmap2Stream_19___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem19___Mmap2Stream_19___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem19___Mmap2Stream_19___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem19___Mmap2Stream_19___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem19___Mmap2Stream_19___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem19___Mmap2Stream_19___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem19___Mmap2Stream_19___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem19___Mmap2Stream_19___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem19___Mmap2Stream_19___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem19___Mmap2Stream_19___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem19___Mmap2Stream_19___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem19___Mmap2Stream_19___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem19___Mmap2Stream_19___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem19___Mmap2Stream_19___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem19___Mmap2Stream_19___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem19___Mmap2Stream_19___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem19___Mmap2Stream_19___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem19___Mmap2Stream_19___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem19___Mmap2Stream_19___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem19___Mmap2Stream_19___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem19___Mmap2Stream_19___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem19___Mmap2Stream_19___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem19___Mmap2Stream_19___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem19___Mmap2Stream_19___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem19___Mmap2Stream_19___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem19___Mmap2Stream_19___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem19___Mmap2Stream_19___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem19___Mmap2Stream_19___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem19___Mmap2Stream_19___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem19___Mmap2Stream_19___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem19___Mmap2Stream_19___mmap_AWQOS),
+    .mmap_offset(Mmap2Stream_19___rmem19__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Mmap2Stream
+  Mmap2Stream_20
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Mmap2Stream_20__ap_start),
+    .ap_done(Mmap2Stream_20__ap_done),
+    .ap_idle(Mmap2Stream_20__ap_idle),
+    .ap_ready(Mmap2Stream_20__ap_ready),
+    .n(Mmap2Stream_20___n__q0),
+    .stream_din(qr20_vadd_bw__din),
+    .stream_full_n(qr20_vadd_bw__full_n),
+    .stream_write(qr20_vadd_bw__write),
+    .m_axi_mmap_ARADDR(m_axi_rmem20___Mmap2Stream_20___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem20___Mmap2Stream_20___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem20___Mmap2Stream_20___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem20___Mmap2Stream_20___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem20___Mmap2Stream_20___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem20___Mmap2Stream_20___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem20___Mmap2Stream_20___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem20___Mmap2Stream_20___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem20___Mmap2Stream_20___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem20___Mmap2Stream_20___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem20___Mmap2Stream_20___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem20___Mmap2Stream_20___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem20___Mmap2Stream_20___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem20___Mmap2Stream_20___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem20___Mmap2Stream_20___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem20___Mmap2Stream_20___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem20___Mmap2Stream_20___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem20___Mmap2Stream_20___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem20___Mmap2Stream_20___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem20___Mmap2Stream_20___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem20___Mmap2Stream_20___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem20___Mmap2Stream_20___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem20___Mmap2Stream_20___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem20___Mmap2Stream_20___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem20___Mmap2Stream_20___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem20___Mmap2Stream_20___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem20___Mmap2Stream_20___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem20___Mmap2Stream_20___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem20___Mmap2Stream_20___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem20___Mmap2Stream_20___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem20___Mmap2Stream_20___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem20___Mmap2Stream_20___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem20___Mmap2Stream_20___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem20___Mmap2Stream_20___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem20___Mmap2Stream_20___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem20___Mmap2Stream_20___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem20___Mmap2Stream_20___mmap_AWQOS),
+    .mmap_offset(Mmap2Stream_20___rmem20__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Mmap2Stream
+  Mmap2Stream_21
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Mmap2Stream_21__ap_start),
+    .ap_done(Mmap2Stream_21__ap_done),
+    .ap_idle(Mmap2Stream_21__ap_idle),
+    .ap_ready(Mmap2Stream_21__ap_ready),
+    .n(Mmap2Stream_21___n__q0),
+    .stream_din(qr21_vadd_bw__din),
+    .stream_full_n(qr21_vadd_bw__full_n),
+    .stream_write(qr21_vadd_bw__write),
+    .m_axi_mmap_ARADDR(m_axi_rmem21___Mmap2Stream_21___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem21___Mmap2Stream_21___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem21___Mmap2Stream_21___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem21___Mmap2Stream_21___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem21___Mmap2Stream_21___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem21___Mmap2Stream_21___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem21___Mmap2Stream_21___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem21___Mmap2Stream_21___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem21___Mmap2Stream_21___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem21___Mmap2Stream_21___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem21___Mmap2Stream_21___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem21___Mmap2Stream_21___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem21___Mmap2Stream_21___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem21___Mmap2Stream_21___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem21___Mmap2Stream_21___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem21___Mmap2Stream_21___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem21___Mmap2Stream_21___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem21___Mmap2Stream_21___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem21___Mmap2Stream_21___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem21___Mmap2Stream_21___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem21___Mmap2Stream_21___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem21___Mmap2Stream_21___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem21___Mmap2Stream_21___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem21___Mmap2Stream_21___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem21___Mmap2Stream_21___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem21___Mmap2Stream_21___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem21___Mmap2Stream_21___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem21___Mmap2Stream_21___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem21___Mmap2Stream_21___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem21___Mmap2Stream_21___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem21___Mmap2Stream_21___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem21___Mmap2Stream_21___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem21___Mmap2Stream_21___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem21___Mmap2Stream_21___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem21___Mmap2Stream_21___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem21___Mmap2Stream_21___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem21___Mmap2Stream_21___mmap_AWQOS),
+    .mmap_offset(Mmap2Stream_21___rmem21__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Mmap2Stream
+  Mmap2Stream_22
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Mmap2Stream_22__ap_start),
+    .ap_done(Mmap2Stream_22__ap_done),
+    .ap_idle(Mmap2Stream_22__ap_idle),
+    .ap_ready(Mmap2Stream_22__ap_ready),
+    .n(Mmap2Stream_22___n__q0),
+    .stream_din(qr22_vadd_bw__din),
+    .stream_full_n(qr22_vadd_bw__full_n),
+    .stream_write(qr22_vadd_bw__write),
+    .m_axi_mmap_ARADDR(m_axi_rmem22___Mmap2Stream_22___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem22___Mmap2Stream_22___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem22___Mmap2Stream_22___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem22___Mmap2Stream_22___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem22___Mmap2Stream_22___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem22___Mmap2Stream_22___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem22___Mmap2Stream_22___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem22___Mmap2Stream_22___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem22___Mmap2Stream_22___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem22___Mmap2Stream_22___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem22___Mmap2Stream_22___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem22___Mmap2Stream_22___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem22___Mmap2Stream_22___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem22___Mmap2Stream_22___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem22___Mmap2Stream_22___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem22___Mmap2Stream_22___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem22___Mmap2Stream_22___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem22___Mmap2Stream_22___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem22___Mmap2Stream_22___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem22___Mmap2Stream_22___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem22___Mmap2Stream_22___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem22___Mmap2Stream_22___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem22___Mmap2Stream_22___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem22___Mmap2Stream_22___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem22___Mmap2Stream_22___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem22___Mmap2Stream_22___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem22___Mmap2Stream_22___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem22___Mmap2Stream_22___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem22___Mmap2Stream_22___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem22___Mmap2Stream_22___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem22___Mmap2Stream_22___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem22___Mmap2Stream_22___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem22___Mmap2Stream_22___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem22___Mmap2Stream_22___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem22___Mmap2Stream_22___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem22___Mmap2Stream_22___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem22___Mmap2Stream_22___mmap_AWQOS),
+    .mmap_offset(Mmap2Stream_22___rmem22__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Mmap2Stream
+  Mmap2Stream_23
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Mmap2Stream_23__ap_start),
+    .ap_done(Mmap2Stream_23__ap_done),
+    .ap_idle(Mmap2Stream_23__ap_idle),
+    .ap_ready(Mmap2Stream_23__ap_ready),
+    .n(Mmap2Stream_23___n__q0),
+    .stream_din(qr23_vadd_bw__din),
+    .stream_full_n(qr23_vadd_bw__full_n),
+    .stream_write(qr23_vadd_bw__write),
+    .m_axi_mmap_ARADDR(m_axi_rmem23___Mmap2Stream_23___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem23___Mmap2Stream_23___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem23___Mmap2Stream_23___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem23___Mmap2Stream_23___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem23___Mmap2Stream_23___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem23___Mmap2Stream_23___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem23___Mmap2Stream_23___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem23___Mmap2Stream_23___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem23___Mmap2Stream_23___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem23___Mmap2Stream_23___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem23___Mmap2Stream_23___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem23___Mmap2Stream_23___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem23___Mmap2Stream_23___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem23___Mmap2Stream_23___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem23___Mmap2Stream_23___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem23___Mmap2Stream_23___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem23___Mmap2Stream_23___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem23___Mmap2Stream_23___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem23___Mmap2Stream_23___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem23___Mmap2Stream_23___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem23___Mmap2Stream_23___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem23___Mmap2Stream_23___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem23___Mmap2Stream_23___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem23___Mmap2Stream_23___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem23___Mmap2Stream_23___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem23___Mmap2Stream_23___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem23___Mmap2Stream_23___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem23___Mmap2Stream_23___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem23___Mmap2Stream_23___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem23___Mmap2Stream_23___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem23___Mmap2Stream_23___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem23___Mmap2Stream_23___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem23___Mmap2Stream_23___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem23___Mmap2Stream_23___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem23___Mmap2Stream_23___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem23___Mmap2Stream_23___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem23___Mmap2Stream_23___mmap_AWQOS),
+    .mmap_offset(Mmap2Stream_23___rmem23__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Mmap2Stream
+  Mmap2Stream_24
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Mmap2Stream_24__ap_start),
+    .ap_done(Mmap2Stream_24__ap_done),
+    .ap_idle(Mmap2Stream_24__ap_idle),
+    .ap_ready(Mmap2Stream_24__ap_ready),
+    .n(Mmap2Stream_24___n__q0),
+    .stream_din(qr24_vadd_bw__din),
+    .stream_full_n(qr24_vadd_bw__full_n),
+    .stream_write(qr24_vadd_bw__write),
+    .m_axi_mmap_ARADDR(m_axi_rmem24___Mmap2Stream_24___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem24___Mmap2Stream_24___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem24___Mmap2Stream_24___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem24___Mmap2Stream_24___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem24___Mmap2Stream_24___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem24___Mmap2Stream_24___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem24___Mmap2Stream_24___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem24___Mmap2Stream_24___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem24___Mmap2Stream_24___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem24___Mmap2Stream_24___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem24___Mmap2Stream_24___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem24___Mmap2Stream_24___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem24___Mmap2Stream_24___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem24___Mmap2Stream_24___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem24___Mmap2Stream_24___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem24___Mmap2Stream_24___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem24___Mmap2Stream_24___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem24___Mmap2Stream_24___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem24___Mmap2Stream_24___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem24___Mmap2Stream_24___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem24___Mmap2Stream_24___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem24___Mmap2Stream_24___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem24___Mmap2Stream_24___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem24___Mmap2Stream_24___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem24___Mmap2Stream_24___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem24___Mmap2Stream_24___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem24___Mmap2Stream_24___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem24___Mmap2Stream_24___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem24___Mmap2Stream_24___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem24___Mmap2Stream_24___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem24___Mmap2Stream_24___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem24___Mmap2Stream_24___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem24___Mmap2Stream_24___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem24___Mmap2Stream_24___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem24___Mmap2Stream_24___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem24___Mmap2Stream_24___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem24___Mmap2Stream_24___mmap_AWQOS),
+    .mmap_offset(Mmap2Stream_24___rmem24__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Mmap2Stream
+  Mmap2Stream_25
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Mmap2Stream_25__ap_start),
+    .ap_done(Mmap2Stream_25__ap_done),
+    .ap_idle(Mmap2Stream_25__ap_idle),
+    .ap_ready(Mmap2Stream_25__ap_ready),
+    .n(Mmap2Stream_25___n__q0),
+    .stream_din(qr25_vadd_bw__din),
+    .stream_full_n(qr25_vadd_bw__full_n),
+    .stream_write(qr25_vadd_bw__write),
+    .m_axi_mmap_ARADDR(m_axi_rmem25___Mmap2Stream_25___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem25___Mmap2Stream_25___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem25___Mmap2Stream_25___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem25___Mmap2Stream_25___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem25___Mmap2Stream_25___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem25___Mmap2Stream_25___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem25___Mmap2Stream_25___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem25___Mmap2Stream_25___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem25___Mmap2Stream_25___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem25___Mmap2Stream_25___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem25___Mmap2Stream_25___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem25___Mmap2Stream_25___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem25___Mmap2Stream_25___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem25___Mmap2Stream_25___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem25___Mmap2Stream_25___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem25___Mmap2Stream_25___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem25___Mmap2Stream_25___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem25___Mmap2Stream_25___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem25___Mmap2Stream_25___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem25___Mmap2Stream_25___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem25___Mmap2Stream_25___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem25___Mmap2Stream_25___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem25___Mmap2Stream_25___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem25___Mmap2Stream_25___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem25___Mmap2Stream_25___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem25___Mmap2Stream_25___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem25___Mmap2Stream_25___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem25___Mmap2Stream_25___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem25___Mmap2Stream_25___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem25___Mmap2Stream_25___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem25___Mmap2Stream_25___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem25___Mmap2Stream_25___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem25___Mmap2Stream_25___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem25___Mmap2Stream_25___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem25___Mmap2Stream_25___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem25___Mmap2Stream_25___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem25___Mmap2Stream_25___mmap_AWQOS),
+    .mmap_offset(Mmap2Stream_25___rmem25__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Mmap2Stream
+  Mmap2Stream_26
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Mmap2Stream_26__ap_start),
+    .ap_done(Mmap2Stream_26__ap_done),
+    .ap_idle(Mmap2Stream_26__ap_idle),
+    .ap_ready(Mmap2Stream_26__ap_ready),
+    .n(Mmap2Stream_26___n__q0),
+    .stream_din(qr26_vadd_bw__din),
+    .stream_full_n(qr26_vadd_bw__full_n),
+    .stream_write(qr26_vadd_bw__write),
+    .m_axi_mmap_ARADDR(m_axi_rmem26___Mmap2Stream_26___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem26___Mmap2Stream_26___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem26___Mmap2Stream_26___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem26___Mmap2Stream_26___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem26___Mmap2Stream_26___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem26___Mmap2Stream_26___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem26___Mmap2Stream_26___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem26___Mmap2Stream_26___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem26___Mmap2Stream_26___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem26___Mmap2Stream_26___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem26___Mmap2Stream_26___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem26___Mmap2Stream_26___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem26___Mmap2Stream_26___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem26___Mmap2Stream_26___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem26___Mmap2Stream_26___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem26___Mmap2Stream_26___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem26___Mmap2Stream_26___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem26___Mmap2Stream_26___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem26___Mmap2Stream_26___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem26___Mmap2Stream_26___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem26___Mmap2Stream_26___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem26___Mmap2Stream_26___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem26___Mmap2Stream_26___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem26___Mmap2Stream_26___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem26___Mmap2Stream_26___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem26___Mmap2Stream_26___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem26___Mmap2Stream_26___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem26___Mmap2Stream_26___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem26___Mmap2Stream_26___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem26___Mmap2Stream_26___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem26___Mmap2Stream_26___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem26___Mmap2Stream_26___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem26___Mmap2Stream_26___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem26___Mmap2Stream_26___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem26___Mmap2Stream_26___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem26___Mmap2Stream_26___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem26___Mmap2Stream_26___mmap_AWQOS),
+    .mmap_offset(Mmap2Stream_26___rmem26__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Mmap2Stream
+  Mmap2Stream_27
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Mmap2Stream_27__ap_start),
+    .ap_done(Mmap2Stream_27__ap_done),
+    .ap_idle(Mmap2Stream_27__ap_idle),
+    .ap_ready(Mmap2Stream_27__ap_ready),
+    .n(Mmap2Stream_27___n__q0),
+    .stream_din(qr27_vadd_bw__din),
+    .stream_full_n(qr27_vadd_bw__full_n),
+    .stream_write(qr27_vadd_bw__write),
+    .m_axi_mmap_ARADDR(m_axi_rmem27___Mmap2Stream_27___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem27___Mmap2Stream_27___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem27___Mmap2Stream_27___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem27___Mmap2Stream_27___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem27___Mmap2Stream_27___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem27___Mmap2Stream_27___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem27___Mmap2Stream_27___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem27___Mmap2Stream_27___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem27___Mmap2Stream_27___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem27___Mmap2Stream_27___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem27___Mmap2Stream_27___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem27___Mmap2Stream_27___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem27___Mmap2Stream_27___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem27___Mmap2Stream_27___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem27___Mmap2Stream_27___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem27___Mmap2Stream_27___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem27___Mmap2Stream_27___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem27___Mmap2Stream_27___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem27___Mmap2Stream_27___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem27___Mmap2Stream_27___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem27___Mmap2Stream_27___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem27___Mmap2Stream_27___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem27___Mmap2Stream_27___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem27___Mmap2Stream_27___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem27___Mmap2Stream_27___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem27___Mmap2Stream_27___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem27___Mmap2Stream_27___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem27___Mmap2Stream_27___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem27___Mmap2Stream_27___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem27___Mmap2Stream_27___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem27___Mmap2Stream_27___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem27___Mmap2Stream_27___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem27___Mmap2Stream_27___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem27___Mmap2Stream_27___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem27___Mmap2Stream_27___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem27___Mmap2Stream_27___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem27___Mmap2Stream_27___mmap_AWQOS),
+    .mmap_offset(Mmap2Stream_27___rmem27__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Stream2Mmap
+  Stream2Mmap_0
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Stream2Mmap_0__ap_start),
+    .ap_done(Stream2Mmap_0__ap_done),
+    .ap_idle(Stream2Mmap_0__ap_idle),
+    .ap_ready(Stream2Mmap_0__ap_ready),
+    .n(Stream2Mmap_0___n__q0),
+    .stream_s_dout(qw0_vadd_bw__dout),
+    .stream_peek_dout(qw0_vadd_bw__dout),
+    .stream_s_empty_n(qw0_vadd_bw__empty_n),
+    .stream_peek_empty_n(qw0_vadd_bw__empty_n),
+    .stream_s_read(qw0_vadd_bw__read),
+    .stream_peek_read(),
+    .m_axi_mmap_ARADDR(m_axi_rmem0___Stream2Mmap_0___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem0___Stream2Mmap_0___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem0___Stream2Mmap_0___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem0___Stream2Mmap_0___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem0___Stream2Mmap_0___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem0___Stream2Mmap_0___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem0___Stream2Mmap_0___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem0___Stream2Mmap_0___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem0___Stream2Mmap_0___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem0___Stream2Mmap_0___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem0___Stream2Mmap_0___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem0___Stream2Mmap_0___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem0___Stream2Mmap_0___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem0___Stream2Mmap_0___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem0___Stream2Mmap_0___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem0___Stream2Mmap_0___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem0___Stream2Mmap_0___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem0___Stream2Mmap_0___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem0___Stream2Mmap_0___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem0___Stream2Mmap_0___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem0___Stream2Mmap_0___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem0___Stream2Mmap_0___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem0___Stream2Mmap_0___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem0___Stream2Mmap_0___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem0___Stream2Mmap_0___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem0___Stream2Mmap_0___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem0___Stream2Mmap_0___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem0___Stream2Mmap_0___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem0___Stream2Mmap_0___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem0___Stream2Mmap_0___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem0___Stream2Mmap_0___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem0___Stream2Mmap_0___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem0___Stream2Mmap_0___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem0___Stream2Mmap_0___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem0___Stream2Mmap_0___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem0___Stream2Mmap_0___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem0___Stream2Mmap_0___mmap_AWQOS),
+    .mmap_offset(Stream2Mmap_0___rmem0__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Stream2Mmap
+  Stream2Mmap_1
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Stream2Mmap_1__ap_start),
+    .ap_done(Stream2Mmap_1__ap_done),
+    .ap_idle(Stream2Mmap_1__ap_idle),
+    .ap_ready(Stream2Mmap_1__ap_ready),
+    .n(Stream2Mmap_1___n__q0),
+    .stream_s_dout(qw1_vadd_bw__dout),
+    .stream_peek_dout(qw1_vadd_bw__dout),
+    .stream_s_empty_n(qw1_vadd_bw__empty_n),
+    .stream_peek_empty_n(qw1_vadd_bw__empty_n),
+    .stream_s_read(qw1_vadd_bw__read),
+    .stream_peek_read(),
+    .m_axi_mmap_ARADDR(m_axi_rmem1___Stream2Mmap_1___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem1___Stream2Mmap_1___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem1___Stream2Mmap_1___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem1___Stream2Mmap_1___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem1___Stream2Mmap_1___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem1___Stream2Mmap_1___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem1___Stream2Mmap_1___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem1___Stream2Mmap_1___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem1___Stream2Mmap_1___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem1___Stream2Mmap_1___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem1___Stream2Mmap_1___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem1___Stream2Mmap_1___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem1___Stream2Mmap_1___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem1___Stream2Mmap_1___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem1___Stream2Mmap_1___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem1___Stream2Mmap_1___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem1___Stream2Mmap_1___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem1___Stream2Mmap_1___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem1___Stream2Mmap_1___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem1___Stream2Mmap_1___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem1___Stream2Mmap_1___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem1___Stream2Mmap_1___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem1___Stream2Mmap_1___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem1___Stream2Mmap_1___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem1___Stream2Mmap_1___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem1___Stream2Mmap_1___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem1___Stream2Mmap_1___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem1___Stream2Mmap_1___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem1___Stream2Mmap_1___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem1___Stream2Mmap_1___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem1___Stream2Mmap_1___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem1___Stream2Mmap_1___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem1___Stream2Mmap_1___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem1___Stream2Mmap_1___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem1___Stream2Mmap_1___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem1___Stream2Mmap_1___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem1___Stream2Mmap_1___mmap_AWQOS),
+    .mmap_offset(Stream2Mmap_1___rmem1__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Stream2Mmap
+  Stream2Mmap_2
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Stream2Mmap_2__ap_start),
+    .ap_done(Stream2Mmap_2__ap_done),
+    .ap_idle(Stream2Mmap_2__ap_idle),
+    .ap_ready(Stream2Mmap_2__ap_ready),
+    .n(Stream2Mmap_2___n__q0),
+    .stream_s_dout(qw2_vadd_bw__dout),
+    .stream_peek_dout(qw2_vadd_bw__dout),
+    .stream_s_empty_n(qw2_vadd_bw__empty_n),
+    .stream_peek_empty_n(qw2_vadd_bw__empty_n),
+    .stream_s_read(qw2_vadd_bw__read),
+    .stream_peek_read(),
+    .m_axi_mmap_ARADDR(m_axi_rmem2___Stream2Mmap_2___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem2___Stream2Mmap_2___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem2___Stream2Mmap_2___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem2___Stream2Mmap_2___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem2___Stream2Mmap_2___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem2___Stream2Mmap_2___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem2___Stream2Mmap_2___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem2___Stream2Mmap_2___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem2___Stream2Mmap_2___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem2___Stream2Mmap_2___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem2___Stream2Mmap_2___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem2___Stream2Mmap_2___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem2___Stream2Mmap_2___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem2___Stream2Mmap_2___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem2___Stream2Mmap_2___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem2___Stream2Mmap_2___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem2___Stream2Mmap_2___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem2___Stream2Mmap_2___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem2___Stream2Mmap_2___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem2___Stream2Mmap_2___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem2___Stream2Mmap_2___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem2___Stream2Mmap_2___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem2___Stream2Mmap_2___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem2___Stream2Mmap_2___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem2___Stream2Mmap_2___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem2___Stream2Mmap_2___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem2___Stream2Mmap_2___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem2___Stream2Mmap_2___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem2___Stream2Mmap_2___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem2___Stream2Mmap_2___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem2___Stream2Mmap_2___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem2___Stream2Mmap_2___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem2___Stream2Mmap_2___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem2___Stream2Mmap_2___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem2___Stream2Mmap_2___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem2___Stream2Mmap_2___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem2___Stream2Mmap_2___mmap_AWQOS),
+    .mmap_offset(Stream2Mmap_2___rmem2__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Stream2Mmap
+  Stream2Mmap_3
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Stream2Mmap_3__ap_start),
+    .ap_done(Stream2Mmap_3__ap_done),
+    .ap_idle(Stream2Mmap_3__ap_idle),
+    .ap_ready(Stream2Mmap_3__ap_ready),
+    .n(Stream2Mmap_3___n__q0),
+    .stream_s_dout(qw3_vadd_bw__dout),
+    .stream_peek_dout(qw3_vadd_bw__dout),
+    .stream_s_empty_n(qw3_vadd_bw__empty_n),
+    .stream_peek_empty_n(qw3_vadd_bw__empty_n),
+    .stream_s_read(qw3_vadd_bw__read),
+    .stream_peek_read(),
+    .m_axi_mmap_ARADDR(m_axi_rmem3___Stream2Mmap_3___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem3___Stream2Mmap_3___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem3___Stream2Mmap_3___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem3___Stream2Mmap_3___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem3___Stream2Mmap_3___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem3___Stream2Mmap_3___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem3___Stream2Mmap_3___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem3___Stream2Mmap_3___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem3___Stream2Mmap_3___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem3___Stream2Mmap_3___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem3___Stream2Mmap_3___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem3___Stream2Mmap_3___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem3___Stream2Mmap_3___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem3___Stream2Mmap_3___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem3___Stream2Mmap_3___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem3___Stream2Mmap_3___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem3___Stream2Mmap_3___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem3___Stream2Mmap_3___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem3___Stream2Mmap_3___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem3___Stream2Mmap_3___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem3___Stream2Mmap_3___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem3___Stream2Mmap_3___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem3___Stream2Mmap_3___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem3___Stream2Mmap_3___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem3___Stream2Mmap_3___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem3___Stream2Mmap_3___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem3___Stream2Mmap_3___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem3___Stream2Mmap_3___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem3___Stream2Mmap_3___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem3___Stream2Mmap_3___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem3___Stream2Mmap_3___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem3___Stream2Mmap_3___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem3___Stream2Mmap_3___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem3___Stream2Mmap_3___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem3___Stream2Mmap_3___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem3___Stream2Mmap_3___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem3___Stream2Mmap_3___mmap_AWQOS),
+    .mmap_offset(Stream2Mmap_3___rmem3__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Stream2Mmap
+  Stream2Mmap_4
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Stream2Mmap_4__ap_start),
+    .ap_done(Stream2Mmap_4__ap_done),
+    .ap_idle(Stream2Mmap_4__ap_idle),
+    .ap_ready(Stream2Mmap_4__ap_ready),
+    .n(Stream2Mmap_4___n__q0),
+    .stream_s_dout(qw4_vadd_bw__dout),
+    .stream_peek_dout(qw4_vadd_bw__dout),
+    .stream_s_empty_n(qw4_vadd_bw__empty_n),
+    .stream_peek_empty_n(qw4_vadd_bw__empty_n),
+    .stream_s_read(qw4_vadd_bw__read),
+    .stream_peek_read(),
+    .m_axi_mmap_ARADDR(m_axi_rmem4___Stream2Mmap_4___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem4___Stream2Mmap_4___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem4___Stream2Mmap_4___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem4___Stream2Mmap_4___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem4___Stream2Mmap_4___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem4___Stream2Mmap_4___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem4___Stream2Mmap_4___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem4___Stream2Mmap_4___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem4___Stream2Mmap_4___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem4___Stream2Mmap_4___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem4___Stream2Mmap_4___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem4___Stream2Mmap_4___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem4___Stream2Mmap_4___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem4___Stream2Mmap_4___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem4___Stream2Mmap_4___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem4___Stream2Mmap_4___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem4___Stream2Mmap_4___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem4___Stream2Mmap_4___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem4___Stream2Mmap_4___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem4___Stream2Mmap_4___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem4___Stream2Mmap_4___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem4___Stream2Mmap_4___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem4___Stream2Mmap_4___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem4___Stream2Mmap_4___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem4___Stream2Mmap_4___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem4___Stream2Mmap_4___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem4___Stream2Mmap_4___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem4___Stream2Mmap_4___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem4___Stream2Mmap_4___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem4___Stream2Mmap_4___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem4___Stream2Mmap_4___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem4___Stream2Mmap_4___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem4___Stream2Mmap_4___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem4___Stream2Mmap_4___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem4___Stream2Mmap_4___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem4___Stream2Mmap_4___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem4___Stream2Mmap_4___mmap_AWQOS),
+    .mmap_offset(Stream2Mmap_4___rmem4__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Stream2Mmap
+  Stream2Mmap_5
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Stream2Mmap_5__ap_start),
+    .ap_done(Stream2Mmap_5__ap_done),
+    .ap_idle(Stream2Mmap_5__ap_idle),
+    .ap_ready(Stream2Mmap_5__ap_ready),
+    .n(Stream2Mmap_5___n__q0),
+    .stream_s_dout(qw5_vadd_bw__dout),
+    .stream_peek_dout(qw5_vadd_bw__dout),
+    .stream_s_empty_n(qw5_vadd_bw__empty_n),
+    .stream_peek_empty_n(qw5_vadd_bw__empty_n),
+    .stream_s_read(qw5_vadd_bw__read),
+    .stream_peek_read(),
+    .m_axi_mmap_ARADDR(m_axi_rmem5___Stream2Mmap_5___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem5___Stream2Mmap_5___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem5___Stream2Mmap_5___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem5___Stream2Mmap_5___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem5___Stream2Mmap_5___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem5___Stream2Mmap_5___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem5___Stream2Mmap_5___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem5___Stream2Mmap_5___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem5___Stream2Mmap_5___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem5___Stream2Mmap_5___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem5___Stream2Mmap_5___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem5___Stream2Mmap_5___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem5___Stream2Mmap_5___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem5___Stream2Mmap_5___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem5___Stream2Mmap_5___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem5___Stream2Mmap_5___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem5___Stream2Mmap_5___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem5___Stream2Mmap_5___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem5___Stream2Mmap_5___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem5___Stream2Mmap_5___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem5___Stream2Mmap_5___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem5___Stream2Mmap_5___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem5___Stream2Mmap_5___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem5___Stream2Mmap_5___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem5___Stream2Mmap_5___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem5___Stream2Mmap_5___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem5___Stream2Mmap_5___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem5___Stream2Mmap_5___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem5___Stream2Mmap_5___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem5___Stream2Mmap_5___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem5___Stream2Mmap_5___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem5___Stream2Mmap_5___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem5___Stream2Mmap_5___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem5___Stream2Mmap_5___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem5___Stream2Mmap_5___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem5___Stream2Mmap_5___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem5___Stream2Mmap_5___mmap_AWQOS),
+    .mmap_offset(Stream2Mmap_5___rmem5__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Stream2Mmap
+  Stream2Mmap_6
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Stream2Mmap_6__ap_start),
+    .ap_done(Stream2Mmap_6__ap_done),
+    .ap_idle(Stream2Mmap_6__ap_idle),
+    .ap_ready(Stream2Mmap_6__ap_ready),
+    .n(Stream2Mmap_6___n__q0),
+    .stream_s_dout(qw6_vadd_bw__dout),
+    .stream_peek_dout(qw6_vadd_bw__dout),
+    .stream_s_empty_n(qw6_vadd_bw__empty_n),
+    .stream_peek_empty_n(qw6_vadd_bw__empty_n),
+    .stream_s_read(qw6_vadd_bw__read),
+    .stream_peek_read(),
+    .m_axi_mmap_ARADDR(m_axi_rmem6___Stream2Mmap_6___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem6___Stream2Mmap_6___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem6___Stream2Mmap_6___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem6___Stream2Mmap_6___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem6___Stream2Mmap_6___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem6___Stream2Mmap_6___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem6___Stream2Mmap_6___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem6___Stream2Mmap_6___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem6___Stream2Mmap_6___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem6___Stream2Mmap_6___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem6___Stream2Mmap_6___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem6___Stream2Mmap_6___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem6___Stream2Mmap_6___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem6___Stream2Mmap_6___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem6___Stream2Mmap_6___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem6___Stream2Mmap_6___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem6___Stream2Mmap_6___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem6___Stream2Mmap_6___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem6___Stream2Mmap_6___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem6___Stream2Mmap_6___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem6___Stream2Mmap_6___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem6___Stream2Mmap_6___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem6___Stream2Mmap_6___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem6___Stream2Mmap_6___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem6___Stream2Mmap_6___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem6___Stream2Mmap_6___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem6___Stream2Mmap_6___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem6___Stream2Mmap_6___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem6___Stream2Mmap_6___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem6___Stream2Mmap_6___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem6___Stream2Mmap_6___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem6___Stream2Mmap_6___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem6___Stream2Mmap_6___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem6___Stream2Mmap_6___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem6___Stream2Mmap_6___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem6___Stream2Mmap_6___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem6___Stream2Mmap_6___mmap_AWQOS),
+    .mmap_offset(Stream2Mmap_6___rmem6__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Stream2Mmap
+  Stream2Mmap_7
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Stream2Mmap_7__ap_start),
+    .ap_done(Stream2Mmap_7__ap_done),
+    .ap_idle(Stream2Mmap_7__ap_idle),
+    .ap_ready(Stream2Mmap_7__ap_ready),
+    .n(Stream2Mmap_7___n__q0),
+    .stream_s_dout(qw7_vadd_bw__dout),
+    .stream_peek_dout(qw7_vadd_bw__dout),
+    .stream_s_empty_n(qw7_vadd_bw__empty_n),
+    .stream_peek_empty_n(qw7_vadd_bw__empty_n),
+    .stream_s_read(qw7_vadd_bw__read),
+    .stream_peek_read(),
+    .m_axi_mmap_ARADDR(m_axi_rmem7___Stream2Mmap_7___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem7___Stream2Mmap_7___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem7___Stream2Mmap_7___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem7___Stream2Mmap_7___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem7___Stream2Mmap_7___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem7___Stream2Mmap_7___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem7___Stream2Mmap_7___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem7___Stream2Mmap_7___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem7___Stream2Mmap_7___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem7___Stream2Mmap_7___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem7___Stream2Mmap_7___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem7___Stream2Mmap_7___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem7___Stream2Mmap_7___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem7___Stream2Mmap_7___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem7___Stream2Mmap_7___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem7___Stream2Mmap_7___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem7___Stream2Mmap_7___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem7___Stream2Mmap_7___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem7___Stream2Mmap_7___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem7___Stream2Mmap_7___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem7___Stream2Mmap_7___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem7___Stream2Mmap_7___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem7___Stream2Mmap_7___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem7___Stream2Mmap_7___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem7___Stream2Mmap_7___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem7___Stream2Mmap_7___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem7___Stream2Mmap_7___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem7___Stream2Mmap_7___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem7___Stream2Mmap_7___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem7___Stream2Mmap_7___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem7___Stream2Mmap_7___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem7___Stream2Mmap_7___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem7___Stream2Mmap_7___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem7___Stream2Mmap_7___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem7___Stream2Mmap_7___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem7___Stream2Mmap_7___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem7___Stream2Mmap_7___mmap_AWQOS),
+    .mmap_offset(Stream2Mmap_7___rmem7__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Stream2Mmap
+  Stream2Mmap_8
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Stream2Mmap_8__ap_start),
+    .ap_done(Stream2Mmap_8__ap_done),
+    .ap_idle(Stream2Mmap_8__ap_idle),
+    .ap_ready(Stream2Mmap_8__ap_ready),
+    .n(Stream2Mmap_8___n__q0),
+    .stream_s_dout(qw8_vadd_bw__dout),
+    .stream_peek_dout(qw8_vadd_bw__dout),
+    .stream_s_empty_n(qw8_vadd_bw__empty_n),
+    .stream_peek_empty_n(qw8_vadd_bw__empty_n),
+    .stream_s_read(qw8_vadd_bw__read),
+    .stream_peek_read(),
+    .m_axi_mmap_ARADDR(m_axi_rmem8___Stream2Mmap_8___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem8___Stream2Mmap_8___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem8___Stream2Mmap_8___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem8___Stream2Mmap_8___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem8___Stream2Mmap_8___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem8___Stream2Mmap_8___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem8___Stream2Mmap_8___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem8___Stream2Mmap_8___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem8___Stream2Mmap_8___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem8___Stream2Mmap_8___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem8___Stream2Mmap_8___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem8___Stream2Mmap_8___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem8___Stream2Mmap_8___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem8___Stream2Mmap_8___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem8___Stream2Mmap_8___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem8___Stream2Mmap_8___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem8___Stream2Mmap_8___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem8___Stream2Mmap_8___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem8___Stream2Mmap_8___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem8___Stream2Mmap_8___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem8___Stream2Mmap_8___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem8___Stream2Mmap_8___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem8___Stream2Mmap_8___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem8___Stream2Mmap_8___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem8___Stream2Mmap_8___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem8___Stream2Mmap_8___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem8___Stream2Mmap_8___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem8___Stream2Mmap_8___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem8___Stream2Mmap_8___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem8___Stream2Mmap_8___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem8___Stream2Mmap_8___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem8___Stream2Mmap_8___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem8___Stream2Mmap_8___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem8___Stream2Mmap_8___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem8___Stream2Mmap_8___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem8___Stream2Mmap_8___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem8___Stream2Mmap_8___mmap_AWQOS),
+    .mmap_offset(Stream2Mmap_8___rmem8__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Stream2Mmap
+  Stream2Mmap_9
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Stream2Mmap_9__ap_start),
+    .ap_done(Stream2Mmap_9__ap_done),
+    .ap_idle(Stream2Mmap_9__ap_idle),
+    .ap_ready(Stream2Mmap_9__ap_ready),
+    .n(Stream2Mmap_9___n__q0),
+    .stream_s_dout(qw9_vadd_bw__dout),
+    .stream_peek_dout(qw9_vadd_bw__dout),
+    .stream_s_empty_n(qw9_vadd_bw__empty_n),
+    .stream_peek_empty_n(qw9_vadd_bw__empty_n),
+    .stream_s_read(qw9_vadd_bw__read),
+    .stream_peek_read(),
+    .m_axi_mmap_ARADDR(m_axi_rmem9___Stream2Mmap_9___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem9___Stream2Mmap_9___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem9___Stream2Mmap_9___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem9___Stream2Mmap_9___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem9___Stream2Mmap_9___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem9___Stream2Mmap_9___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem9___Stream2Mmap_9___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem9___Stream2Mmap_9___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem9___Stream2Mmap_9___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem9___Stream2Mmap_9___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem9___Stream2Mmap_9___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem9___Stream2Mmap_9___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem9___Stream2Mmap_9___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem9___Stream2Mmap_9___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem9___Stream2Mmap_9___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem9___Stream2Mmap_9___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem9___Stream2Mmap_9___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem9___Stream2Mmap_9___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem9___Stream2Mmap_9___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem9___Stream2Mmap_9___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem9___Stream2Mmap_9___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem9___Stream2Mmap_9___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem9___Stream2Mmap_9___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem9___Stream2Mmap_9___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem9___Stream2Mmap_9___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem9___Stream2Mmap_9___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem9___Stream2Mmap_9___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem9___Stream2Mmap_9___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem9___Stream2Mmap_9___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem9___Stream2Mmap_9___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem9___Stream2Mmap_9___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem9___Stream2Mmap_9___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem9___Stream2Mmap_9___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem9___Stream2Mmap_9___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem9___Stream2Mmap_9___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem9___Stream2Mmap_9___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem9___Stream2Mmap_9___mmap_AWQOS),
+    .mmap_offset(Stream2Mmap_9___rmem9__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Stream2Mmap
+  Stream2Mmap_10
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Stream2Mmap_10__ap_start),
+    .ap_done(Stream2Mmap_10__ap_done),
+    .ap_idle(Stream2Mmap_10__ap_idle),
+    .ap_ready(Stream2Mmap_10__ap_ready),
+    .n(Stream2Mmap_10___n__q0),
+    .stream_s_dout(qw10_vadd_bw__dout),
+    .stream_peek_dout(qw10_vadd_bw__dout),
+    .stream_s_empty_n(qw10_vadd_bw__empty_n),
+    .stream_peek_empty_n(qw10_vadd_bw__empty_n),
+    .stream_s_read(qw10_vadd_bw__read),
+    .stream_peek_read(),
+    .m_axi_mmap_ARADDR(m_axi_rmem10___Stream2Mmap_10___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem10___Stream2Mmap_10___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem10___Stream2Mmap_10___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem10___Stream2Mmap_10___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem10___Stream2Mmap_10___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem10___Stream2Mmap_10___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem10___Stream2Mmap_10___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem10___Stream2Mmap_10___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem10___Stream2Mmap_10___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem10___Stream2Mmap_10___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem10___Stream2Mmap_10___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem10___Stream2Mmap_10___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem10___Stream2Mmap_10___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem10___Stream2Mmap_10___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem10___Stream2Mmap_10___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem10___Stream2Mmap_10___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem10___Stream2Mmap_10___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem10___Stream2Mmap_10___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem10___Stream2Mmap_10___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem10___Stream2Mmap_10___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem10___Stream2Mmap_10___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem10___Stream2Mmap_10___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem10___Stream2Mmap_10___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem10___Stream2Mmap_10___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem10___Stream2Mmap_10___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem10___Stream2Mmap_10___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem10___Stream2Mmap_10___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem10___Stream2Mmap_10___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem10___Stream2Mmap_10___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem10___Stream2Mmap_10___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem10___Stream2Mmap_10___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem10___Stream2Mmap_10___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem10___Stream2Mmap_10___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem10___Stream2Mmap_10___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem10___Stream2Mmap_10___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem10___Stream2Mmap_10___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem10___Stream2Mmap_10___mmap_AWQOS),
+    .mmap_offset(Stream2Mmap_10___rmem10__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Stream2Mmap
+  Stream2Mmap_11
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Stream2Mmap_11__ap_start),
+    .ap_done(Stream2Mmap_11__ap_done),
+    .ap_idle(Stream2Mmap_11__ap_idle),
+    .ap_ready(Stream2Mmap_11__ap_ready),
+    .n(Stream2Mmap_11___n__q0),
+    .stream_s_dout(qw11_vadd_bw__dout),
+    .stream_peek_dout(qw11_vadd_bw__dout),
+    .stream_s_empty_n(qw11_vadd_bw__empty_n),
+    .stream_peek_empty_n(qw11_vadd_bw__empty_n),
+    .stream_s_read(qw11_vadd_bw__read),
+    .stream_peek_read(),
+    .m_axi_mmap_ARADDR(m_axi_rmem11___Stream2Mmap_11___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem11___Stream2Mmap_11___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem11___Stream2Mmap_11___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem11___Stream2Mmap_11___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem11___Stream2Mmap_11___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem11___Stream2Mmap_11___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem11___Stream2Mmap_11___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem11___Stream2Mmap_11___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem11___Stream2Mmap_11___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem11___Stream2Mmap_11___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem11___Stream2Mmap_11___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem11___Stream2Mmap_11___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem11___Stream2Mmap_11___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem11___Stream2Mmap_11___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem11___Stream2Mmap_11___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem11___Stream2Mmap_11___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem11___Stream2Mmap_11___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem11___Stream2Mmap_11___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem11___Stream2Mmap_11___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem11___Stream2Mmap_11___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem11___Stream2Mmap_11___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem11___Stream2Mmap_11___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem11___Stream2Mmap_11___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem11___Stream2Mmap_11___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem11___Stream2Mmap_11___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem11___Stream2Mmap_11___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem11___Stream2Mmap_11___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem11___Stream2Mmap_11___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem11___Stream2Mmap_11___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem11___Stream2Mmap_11___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem11___Stream2Mmap_11___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem11___Stream2Mmap_11___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem11___Stream2Mmap_11___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem11___Stream2Mmap_11___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem11___Stream2Mmap_11___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem11___Stream2Mmap_11___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem11___Stream2Mmap_11___mmap_AWQOS),
+    .mmap_offset(Stream2Mmap_11___rmem11__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Stream2Mmap
+  Stream2Mmap_12
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Stream2Mmap_12__ap_start),
+    .ap_done(Stream2Mmap_12__ap_done),
+    .ap_idle(Stream2Mmap_12__ap_idle),
+    .ap_ready(Stream2Mmap_12__ap_ready),
+    .n(Stream2Mmap_12___n__q0),
+    .stream_s_dout(qw12_vadd_bw__dout),
+    .stream_peek_dout(qw12_vadd_bw__dout),
+    .stream_s_empty_n(qw12_vadd_bw__empty_n),
+    .stream_peek_empty_n(qw12_vadd_bw__empty_n),
+    .stream_s_read(qw12_vadd_bw__read),
+    .stream_peek_read(),
+    .m_axi_mmap_ARADDR(m_axi_rmem12___Stream2Mmap_12___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem12___Stream2Mmap_12___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem12___Stream2Mmap_12___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem12___Stream2Mmap_12___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem12___Stream2Mmap_12___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem12___Stream2Mmap_12___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem12___Stream2Mmap_12___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem12___Stream2Mmap_12___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem12___Stream2Mmap_12___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem12___Stream2Mmap_12___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem12___Stream2Mmap_12___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem12___Stream2Mmap_12___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem12___Stream2Mmap_12___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem12___Stream2Mmap_12___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem12___Stream2Mmap_12___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem12___Stream2Mmap_12___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem12___Stream2Mmap_12___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem12___Stream2Mmap_12___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem12___Stream2Mmap_12___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem12___Stream2Mmap_12___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem12___Stream2Mmap_12___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem12___Stream2Mmap_12___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem12___Stream2Mmap_12___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem12___Stream2Mmap_12___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem12___Stream2Mmap_12___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem12___Stream2Mmap_12___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem12___Stream2Mmap_12___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem12___Stream2Mmap_12___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem12___Stream2Mmap_12___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem12___Stream2Mmap_12___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem12___Stream2Mmap_12___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem12___Stream2Mmap_12___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem12___Stream2Mmap_12___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem12___Stream2Mmap_12___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem12___Stream2Mmap_12___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem12___Stream2Mmap_12___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem12___Stream2Mmap_12___mmap_AWQOS),
+    .mmap_offset(Stream2Mmap_12___rmem12__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Stream2Mmap
+  Stream2Mmap_13
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Stream2Mmap_13__ap_start),
+    .ap_done(Stream2Mmap_13__ap_done),
+    .ap_idle(Stream2Mmap_13__ap_idle),
+    .ap_ready(Stream2Mmap_13__ap_ready),
+    .n(Stream2Mmap_13___n__q0),
+    .stream_s_dout(qw13_vadd_bw__dout),
+    .stream_peek_dout(qw13_vadd_bw__dout),
+    .stream_s_empty_n(qw13_vadd_bw__empty_n),
+    .stream_peek_empty_n(qw13_vadd_bw__empty_n),
+    .stream_s_read(qw13_vadd_bw__read),
+    .stream_peek_read(),
+    .m_axi_mmap_ARADDR(m_axi_rmem13___Stream2Mmap_13___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem13___Stream2Mmap_13___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem13___Stream2Mmap_13___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem13___Stream2Mmap_13___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem13___Stream2Mmap_13___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem13___Stream2Mmap_13___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem13___Stream2Mmap_13___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem13___Stream2Mmap_13___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem13___Stream2Mmap_13___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem13___Stream2Mmap_13___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem13___Stream2Mmap_13___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem13___Stream2Mmap_13___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem13___Stream2Mmap_13___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem13___Stream2Mmap_13___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem13___Stream2Mmap_13___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem13___Stream2Mmap_13___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem13___Stream2Mmap_13___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem13___Stream2Mmap_13___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem13___Stream2Mmap_13___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem13___Stream2Mmap_13___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem13___Stream2Mmap_13___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem13___Stream2Mmap_13___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem13___Stream2Mmap_13___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem13___Stream2Mmap_13___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem13___Stream2Mmap_13___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem13___Stream2Mmap_13___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem13___Stream2Mmap_13___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem13___Stream2Mmap_13___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem13___Stream2Mmap_13___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem13___Stream2Mmap_13___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem13___Stream2Mmap_13___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem13___Stream2Mmap_13___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem13___Stream2Mmap_13___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem13___Stream2Mmap_13___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem13___Stream2Mmap_13___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem13___Stream2Mmap_13___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem13___Stream2Mmap_13___mmap_AWQOS),
+    .mmap_offset(Stream2Mmap_13___rmem13__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Stream2Mmap
+  Stream2Mmap_14
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Stream2Mmap_14__ap_start),
+    .ap_done(Stream2Mmap_14__ap_done),
+    .ap_idle(Stream2Mmap_14__ap_idle),
+    .ap_ready(Stream2Mmap_14__ap_ready),
+    .n(Stream2Mmap_14___n__q0),
+    .stream_s_dout(qw14_vadd_bw__dout),
+    .stream_peek_dout(qw14_vadd_bw__dout),
+    .stream_s_empty_n(qw14_vadd_bw__empty_n),
+    .stream_peek_empty_n(qw14_vadd_bw__empty_n),
+    .stream_s_read(qw14_vadd_bw__read),
+    .stream_peek_read(),
+    .m_axi_mmap_ARADDR(m_axi_rmem14___Stream2Mmap_14___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem14___Stream2Mmap_14___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem14___Stream2Mmap_14___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem14___Stream2Mmap_14___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem14___Stream2Mmap_14___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem14___Stream2Mmap_14___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem14___Stream2Mmap_14___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem14___Stream2Mmap_14___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem14___Stream2Mmap_14___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem14___Stream2Mmap_14___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem14___Stream2Mmap_14___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem14___Stream2Mmap_14___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem14___Stream2Mmap_14___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem14___Stream2Mmap_14___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem14___Stream2Mmap_14___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem14___Stream2Mmap_14___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem14___Stream2Mmap_14___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem14___Stream2Mmap_14___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem14___Stream2Mmap_14___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem14___Stream2Mmap_14___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem14___Stream2Mmap_14___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem14___Stream2Mmap_14___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem14___Stream2Mmap_14___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem14___Stream2Mmap_14___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem14___Stream2Mmap_14___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem14___Stream2Mmap_14___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem14___Stream2Mmap_14___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem14___Stream2Mmap_14___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem14___Stream2Mmap_14___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem14___Stream2Mmap_14___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem14___Stream2Mmap_14___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem14___Stream2Mmap_14___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem14___Stream2Mmap_14___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem14___Stream2Mmap_14___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem14___Stream2Mmap_14___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem14___Stream2Mmap_14___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem14___Stream2Mmap_14___mmap_AWQOS),
+    .mmap_offset(Stream2Mmap_14___rmem14__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Stream2Mmap
+  Stream2Mmap_15
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Stream2Mmap_15__ap_start),
+    .ap_done(Stream2Mmap_15__ap_done),
+    .ap_idle(Stream2Mmap_15__ap_idle),
+    .ap_ready(Stream2Mmap_15__ap_ready),
+    .n(Stream2Mmap_15___n__q0),
+    .stream_s_dout(qw15_vadd_bw__dout),
+    .stream_peek_dout(qw15_vadd_bw__dout),
+    .stream_s_empty_n(qw15_vadd_bw__empty_n),
+    .stream_peek_empty_n(qw15_vadd_bw__empty_n),
+    .stream_s_read(qw15_vadd_bw__read),
+    .stream_peek_read(),
+    .m_axi_mmap_ARADDR(m_axi_rmem15___Stream2Mmap_15___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem15___Stream2Mmap_15___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem15___Stream2Mmap_15___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem15___Stream2Mmap_15___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem15___Stream2Mmap_15___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem15___Stream2Mmap_15___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem15___Stream2Mmap_15___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem15___Stream2Mmap_15___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem15___Stream2Mmap_15___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem15___Stream2Mmap_15___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem15___Stream2Mmap_15___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem15___Stream2Mmap_15___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem15___Stream2Mmap_15___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem15___Stream2Mmap_15___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem15___Stream2Mmap_15___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem15___Stream2Mmap_15___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem15___Stream2Mmap_15___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem15___Stream2Mmap_15___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem15___Stream2Mmap_15___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem15___Stream2Mmap_15___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem15___Stream2Mmap_15___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem15___Stream2Mmap_15___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem15___Stream2Mmap_15___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem15___Stream2Mmap_15___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem15___Stream2Mmap_15___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem15___Stream2Mmap_15___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem15___Stream2Mmap_15___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem15___Stream2Mmap_15___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem15___Stream2Mmap_15___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem15___Stream2Mmap_15___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem15___Stream2Mmap_15___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem15___Stream2Mmap_15___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem15___Stream2Mmap_15___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem15___Stream2Mmap_15___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem15___Stream2Mmap_15___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem15___Stream2Mmap_15___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem15___Stream2Mmap_15___mmap_AWQOS),
+    .mmap_offset(Stream2Mmap_15___rmem15__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Stream2Mmap
+  Stream2Mmap_16
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Stream2Mmap_16__ap_start),
+    .ap_done(Stream2Mmap_16__ap_done),
+    .ap_idle(Stream2Mmap_16__ap_idle),
+    .ap_ready(Stream2Mmap_16__ap_ready),
+    .n(Stream2Mmap_16___n__q0),
+    .stream_s_dout(qw16_vadd_bw__dout),
+    .stream_peek_dout(qw16_vadd_bw__dout),
+    .stream_s_empty_n(qw16_vadd_bw__empty_n),
+    .stream_peek_empty_n(qw16_vadd_bw__empty_n),
+    .stream_s_read(qw16_vadd_bw__read),
+    .stream_peek_read(),
+    .m_axi_mmap_ARADDR(m_axi_rmem16___Stream2Mmap_16___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem16___Stream2Mmap_16___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem16___Stream2Mmap_16___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem16___Stream2Mmap_16___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem16___Stream2Mmap_16___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem16___Stream2Mmap_16___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem16___Stream2Mmap_16___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem16___Stream2Mmap_16___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem16___Stream2Mmap_16___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem16___Stream2Mmap_16___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem16___Stream2Mmap_16___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem16___Stream2Mmap_16___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem16___Stream2Mmap_16___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem16___Stream2Mmap_16___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem16___Stream2Mmap_16___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem16___Stream2Mmap_16___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem16___Stream2Mmap_16___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem16___Stream2Mmap_16___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem16___Stream2Mmap_16___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem16___Stream2Mmap_16___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem16___Stream2Mmap_16___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem16___Stream2Mmap_16___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem16___Stream2Mmap_16___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem16___Stream2Mmap_16___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem16___Stream2Mmap_16___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem16___Stream2Mmap_16___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem16___Stream2Mmap_16___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem16___Stream2Mmap_16___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem16___Stream2Mmap_16___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem16___Stream2Mmap_16___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem16___Stream2Mmap_16___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem16___Stream2Mmap_16___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem16___Stream2Mmap_16___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem16___Stream2Mmap_16___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem16___Stream2Mmap_16___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem16___Stream2Mmap_16___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem16___Stream2Mmap_16___mmap_AWQOS),
+    .mmap_offset(Stream2Mmap_16___rmem16__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Stream2Mmap
+  Stream2Mmap_17
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Stream2Mmap_17__ap_start),
+    .ap_done(Stream2Mmap_17__ap_done),
+    .ap_idle(Stream2Mmap_17__ap_idle),
+    .ap_ready(Stream2Mmap_17__ap_ready),
+    .n(Stream2Mmap_17___n__q0),
+    .stream_s_dout(qw17_vadd_bw__dout),
+    .stream_peek_dout(qw17_vadd_bw__dout),
+    .stream_s_empty_n(qw17_vadd_bw__empty_n),
+    .stream_peek_empty_n(qw17_vadd_bw__empty_n),
+    .stream_s_read(qw17_vadd_bw__read),
+    .stream_peek_read(),
+    .m_axi_mmap_ARADDR(m_axi_rmem17___Stream2Mmap_17___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem17___Stream2Mmap_17___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem17___Stream2Mmap_17___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem17___Stream2Mmap_17___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem17___Stream2Mmap_17___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem17___Stream2Mmap_17___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem17___Stream2Mmap_17___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem17___Stream2Mmap_17___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem17___Stream2Mmap_17___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem17___Stream2Mmap_17___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem17___Stream2Mmap_17___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem17___Stream2Mmap_17___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem17___Stream2Mmap_17___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem17___Stream2Mmap_17___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem17___Stream2Mmap_17___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem17___Stream2Mmap_17___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem17___Stream2Mmap_17___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem17___Stream2Mmap_17___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem17___Stream2Mmap_17___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem17___Stream2Mmap_17___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem17___Stream2Mmap_17___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem17___Stream2Mmap_17___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem17___Stream2Mmap_17___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem17___Stream2Mmap_17___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem17___Stream2Mmap_17___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem17___Stream2Mmap_17___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem17___Stream2Mmap_17___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem17___Stream2Mmap_17___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem17___Stream2Mmap_17___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem17___Stream2Mmap_17___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem17___Stream2Mmap_17___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem17___Stream2Mmap_17___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem17___Stream2Mmap_17___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem17___Stream2Mmap_17___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem17___Stream2Mmap_17___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem17___Stream2Mmap_17___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem17___Stream2Mmap_17___mmap_AWQOS),
+    .mmap_offset(Stream2Mmap_17___rmem17__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Stream2Mmap
+  Stream2Mmap_18
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Stream2Mmap_18__ap_start),
+    .ap_done(Stream2Mmap_18__ap_done),
+    .ap_idle(Stream2Mmap_18__ap_idle),
+    .ap_ready(Stream2Mmap_18__ap_ready),
+    .n(Stream2Mmap_18___n__q0),
+    .stream_s_dout(qw18_vadd_bw__dout),
+    .stream_peek_dout(qw18_vadd_bw__dout),
+    .stream_s_empty_n(qw18_vadd_bw__empty_n),
+    .stream_peek_empty_n(qw18_vadd_bw__empty_n),
+    .stream_s_read(qw18_vadd_bw__read),
+    .stream_peek_read(),
+    .m_axi_mmap_ARADDR(m_axi_rmem18___Stream2Mmap_18___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem18___Stream2Mmap_18___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem18___Stream2Mmap_18___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem18___Stream2Mmap_18___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem18___Stream2Mmap_18___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem18___Stream2Mmap_18___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem18___Stream2Mmap_18___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem18___Stream2Mmap_18___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem18___Stream2Mmap_18___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem18___Stream2Mmap_18___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem18___Stream2Mmap_18___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem18___Stream2Mmap_18___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem18___Stream2Mmap_18___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem18___Stream2Mmap_18___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem18___Stream2Mmap_18___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem18___Stream2Mmap_18___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem18___Stream2Mmap_18___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem18___Stream2Mmap_18___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem18___Stream2Mmap_18___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem18___Stream2Mmap_18___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem18___Stream2Mmap_18___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem18___Stream2Mmap_18___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem18___Stream2Mmap_18___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem18___Stream2Mmap_18___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem18___Stream2Mmap_18___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem18___Stream2Mmap_18___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem18___Stream2Mmap_18___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem18___Stream2Mmap_18___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem18___Stream2Mmap_18___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem18___Stream2Mmap_18___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem18___Stream2Mmap_18___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem18___Stream2Mmap_18___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem18___Stream2Mmap_18___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem18___Stream2Mmap_18___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem18___Stream2Mmap_18___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem18___Stream2Mmap_18___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem18___Stream2Mmap_18___mmap_AWQOS),
+    .mmap_offset(Stream2Mmap_18___rmem18__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Stream2Mmap
+  Stream2Mmap_19
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Stream2Mmap_19__ap_start),
+    .ap_done(Stream2Mmap_19__ap_done),
+    .ap_idle(Stream2Mmap_19__ap_idle),
+    .ap_ready(Stream2Mmap_19__ap_ready),
+    .n(Stream2Mmap_19___n__q0),
+    .stream_s_dout(qw19_vadd_bw__dout),
+    .stream_peek_dout(qw19_vadd_bw__dout),
+    .stream_s_empty_n(qw19_vadd_bw__empty_n),
+    .stream_peek_empty_n(qw19_vadd_bw__empty_n),
+    .stream_s_read(qw19_vadd_bw__read),
+    .stream_peek_read(),
+    .m_axi_mmap_ARADDR(m_axi_rmem19___Stream2Mmap_19___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem19___Stream2Mmap_19___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem19___Stream2Mmap_19___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem19___Stream2Mmap_19___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem19___Stream2Mmap_19___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem19___Stream2Mmap_19___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem19___Stream2Mmap_19___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem19___Stream2Mmap_19___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem19___Stream2Mmap_19___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem19___Stream2Mmap_19___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem19___Stream2Mmap_19___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem19___Stream2Mmap_19___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem19___Stream2Mmap_19___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem19___Stream2Mmap_19___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem19___Stream2Mmap_19___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem19___Stream2Mmap_19___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem19___Stream2Mmap_19___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem19___Stream2Mmap_19___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem19___Stream2Mmap_19___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem19___Stream2Mmap_19___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem19___Stream2Mmap_19___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem19___Stream2Mmap_19___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem19___Stream2Mmap_19___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem19___Stream2Mmap_19___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem19___Stream2Mmap_19___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem19___Stream2Mmap_19___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem19___Stream2Mmap_19___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem19___Stream2Mmap_19___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem19___Stream2Mmap_19___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem19___Stream2Mmap_19___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem19___Stream2Mmap_19___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem19___Stream2Mmap_19___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem19___Stream2Mmap_19___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem19___Stream2Mmap_19___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem19___Stream2Mmap_19___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem19___Stream2Mmap_19___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem19___Stream2Mmap_19___mmap_AWQOS),
+    .mmap_offset(Stream2Mmap_19___rmem19__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Stream2Mmap
+  Stream2Mmap_20
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Stream2Mmap_20__ap_start),
+    .ap_done(Stream2Mmap_20__ap_done),
+    .ap_idle(Stream2Mmap_20__ap_idle),
+    .ap_ready(Stream2Mmap_20__ap_ready),
+    .n(Stream2Mmap_20___n__q0),
+    .stream_s_dout(qw20_vadd_bw__dout),
+    .stream_peek_dout(qw20_vadd_bw__dout),
+    .stream_s_empty_n(qw20_vadd_bw__empty_n),
+    .stream_peek_empty_n(qw20_vadd_bw__empty_n),
+    .stream_s_read(qw20_vadd_bw__read),
+    .stream_peek_read(),
+    .m_axi_mmap_ARADDR(m_axi_rmem20___Stream2Mmap_20___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem20___Stream2Mmap_20___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem20___Stream2Mmap_20___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem20___Stream2Mmap_20___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem20___Stream2Mmap_20___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem20___Stream2Mmap_20___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem20___Stream2Mmap_20___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem20___Stream2Mmap_20___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem20___Stream2Mmap_20___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem20___Stream2Mmap_20___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem20___Stream2Mmap_20___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem20___Stream2Mmap_20___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem20___Stream2Mmap_20___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem20___Stream2Mmap_20___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem20___Stream2Mmap_20___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem20___Stream2Mmap_20___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem20___Stream2Mmap_20___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem20___Stream2Mmap_20___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem20___Stream2Mmap_20___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem20___Stream2Mmap_20___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem20___Stream2Mmap_20___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem20___Stream2Mmap_20___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem20___Stream2Mmap_20___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem20___Stream2Mmap_20___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem20___Stream2Mmap_20___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem20___Stream2Mmap_20___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem20___Stream2Mmap_20___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem20___Stream2Mmap_20___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem20___Stream2Mmap_20___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem20___Stream2Mmap_20___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem20___Stream2Mmap_20___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem20___Stream2Mmap_20___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem20___Stream2Mmap_20___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem20___Stream2Mmap_20___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem20___Stream2Mmap_20___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem20___Stream2Mmap_20___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem20___Stream2Mmap_20___mmap_AWQOS),
+    .mmap_offset(Stream2Mmap_20___rmem20__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Stream2Mmap
+  Stream2Mmap_21
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Stream2Mmap_21__ap_start),
+    .ap_done(Stream2Mmap_21__ap_done),
+    .ap_idle(Stream2Mmap_21__ap_idle),
+    .ap_ready(Stream2Mmap_21__ap_ready),
+    .n(Stream2Mmap_21___n__q0),
+    .stream_s_dout(qw21_vadd_bw__dout),
+    .stream_peek_dout(qw21_vadd_bw__dout),
+    .stream_s_empty_n(qw21_vadd_bw__empty_n),
+    .stream_peek_empty_n(qw21_vadd_bw__empty_n),
+    .stream_s_read(qw21_vadd_bw__read),
+    .stream_peek_read(),
+    .m_axi_mmap_ARADDR(m_axi_rmem21___Stream2Mmap_21___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem21___Stream2Mmap_21___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem21___Stream2Mmap_21___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem21___Stream2Mmap_21___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem21___Stream2Mmap_21___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem21___Stream2Mmap_21___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem21___Stream2Mmap_21___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem21___Stream2Mmap_21___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem21___Stream2Mmap_21___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem21___Stream2Mmap_21___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem21___Stream2Mmap_21___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem21___Stream2Mmap_21___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem21___Stream2Mmap_21___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem21___Stream2Mmap_21___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem21___Stream2Mmap_21___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem21___Stream2Mmap_21___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem21___Stream2Mmap_21___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem21___Stream2Mmap_21___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem21___Stream2Mmap_21___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem21___Stream2Mmap_21___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem21___Stream2Mmap_21___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem21___Stream2Mmap_21___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem21___Stream2Mmap_21___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem21___Stream2Mmap_21___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem21___Stream2Mmap_21___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem21___Stream2Mmap_21___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem21___Stream2Mmap_21___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem21___Stream2Mmap_21___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem21___Stream2Mmap_21___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem21___Stream2Mmap_21___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem21___Stream2Mmap_21___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem21___Stream2Mmap_21___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem21___Stream2Mmap_21___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem21___Stream2Mmap_21___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem21___Stream2Mmap_21___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem21___Stream2Mmap_21___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem21___Stream2Mmap_21___mmap_AWQOS),
+    .mmap_offset(Stream2Mmap_21___rmem21__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Stream2Mmap
+  Stream2Mmap_22
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Stream2Mmap_22__ap_start),
+    .ap_done(Stream2Mmap_22__ap_done),
+    .ap_idle(Stream2Mmap_22__ap_idle),
+    .ap_ready(Stream2Mmap_22__ap_ready),
+    .n(Stream2Mmap_22___n__q0),
+    .stream_s_dout(qw22_vadd_bw__dout),
+    .stream_peek_dout(qw22_vadd_bw__dout),
+    .stream_s_empty_n(qw22_vadd_bw__empty_n),
+    .stream_peek_empty_n(qw22_vadd_bw__empty_n),
+    .stream_s_read(qw22_vadd_bw__read),
+    .stream_peek_read(),
+    .m_axi_mmap_ARADDR(m_axi_rmem22___Stream2Mmap_22___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem22___Stream2Mmap_22___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem22___Stream2Mmap_22___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem22___Stream2Mmap_22___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem22___Stream2Mmap_22___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem22___Stream2Mmap_22___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem22___Stream2Mmap_22___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem22___Stream2Mmap_22___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem22___Stream2Mmap_22___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem22___Stream2Mmap_22___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem22___Stream2Mmap_22___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem22___Stream2Mmap_22___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem22___Stream2Mmap_22___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem22___Stream2Mmap_22___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem22___Stream2Mmap_22___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem22___Stream2Mmap_22___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem22___Stream2Mmap_22___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem22___Stream2Mmap_22___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem22___Stream2Mmap_22___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem22___Stream2Mmap_22___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem22___Stream2Mmap_22___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem22___Stream2Mmap_22___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem22___Stream2Mmap_22___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem22___Stream2Mmap_22___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem22___Stream2Mmap_22___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem22___Stream2Mmap_22___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem22___Stream2Mmap_22___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem22___Stream2Mmap_22___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem22___Stream2Mmap_22___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem22___Stream2Mmap_22___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem22___Stream2Mmap_22___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem22___Stream2Mmap_22___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem22___Stream2Mmap_22___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem22___Stream2Mmap_22___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem22___Stream2Mmap_22___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem22___Stream2Mmap_22___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem22___Stream2Mmap_22___mmap_AWQOS),
+    .mmap_offset(Stream2Mmap_22___rmem22__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Stream2Mmap
+  Stream2Mmap_23
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Stream2Mmap_23__ap_start),
+    .ap_done(Stream2Mmap_23__ap_done),
+    .ap_idle(Stream2Mmap_23__ap_idle),
+    .ap_ready(Stream2Mmap_23__ap_ready),
+    .n(Stream2Mmap_23___n__q0),
+    .stream_s_dout(qw23_vadd_bw__dout),
+    .stream_peek_dout(qw23_vadd_bw__dout),
+    .stream_s_empty_n(qw23_vadd_bw__empty_n),
+    .stream_peek_empty_n(qw23_vadd_bw__empty_n),
+    .stream_s_read(qw23_vadd_bw__read),
+    .stream_peek_read(),
+    .m_axi_mmap_ARADDR(m_axi_rmem23___Stream2Mmap_23___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem23___Stream2Mmap_23___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem23___Stream2Mmap_23___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem23___Stream2Mmap_23___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem23___Stream2Mmap_23___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem23___Stream2Mmap_23___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem23___Stream2Mmap_23___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem23___Stream2Mmap_23___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem23___Stream2Mmap_23___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem23___Stream2Mmap_23___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem23___Stream2Mmap_23___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem23___Stream2Mmap_23___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem23___Stream2Mmap_23___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem23___Stream2Mmap_23___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem23___Stream2Mmap_23___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem23___Stream2Mmap_23___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem23___Stream2Mmap_23___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem23___Stream2Mmap_23___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem23___Stream2Mmap_23___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem23___Stream2Mmap_23___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem23___Stream2Mmap_23___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem23___Stream2Mmap_23___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem23___Stream2Mmap_23___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem23___Stream2Mmap_23___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem23___Stream2Mmap_23___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem23___Stream2Mmap_23___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem23___Stream2Mmap_23___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem23___Stream2Mmap_23___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem23___Stream2Mmap_23___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem23___Stream2Mmap_23___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem23___Stream2Mmap_23___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem23___Stream2Mmap_23___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem23___Stream2Mmap_23___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem23___Stream2Mmap_23___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem23___Stream2Mmap_23___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem23___Stream2Mmap_23___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem23___Stream2Mmap_23___mmap_AWQOS),
+    .mmap_offset(Stream2Mmap_23___rmem23__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Stream2Mmap
+  Stream2Mmap_24
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Stream2Mmap_24__ap_start),
+    .ap_done(Stream2Mmap_24__ap_done),
+    .ap_idle(Stream2Mmap_24__ap_idle),
+    .ap_ready(Stream2Mmap_24__ap_ready),
+    .n(Stream2Mmap_24___n__q0),
+    .stream_s_dout(qw24_vadd_bw__dout),
+    .stream_peek_dout(qw24_vadd_bw__dout),
+    .stream_s_empty_n(qw24_vadd_bw__empty_n),
+    .stream_peek_empty_n(qw24_vadd_bw__empty_n),
+    .stream_s_read(qw24_vadd_bw__read),
+    .stream_peek_read(),
+    .m_axi_mmap_ARADDR(m_axi_rmem24___Stream2Mmap_24___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem24___Stream2Mmap_24___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem24___Stream2Mmap_24___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem24___Stream2Mmap_24___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem24___Stream2Mmap_24___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem24___Stream2Mmap_24___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem24___Stream2Mmap_24___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem24___Stream2Mmap_24___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem24___Stream2Mmap_24___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem24___Stream2Mmap_24___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem24___Stream2Mmap_24___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem24___Stream2Mmap_24___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem24___Stream2Mmap_24___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem24___Stream2Mmap_24___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem24___Stream2Mmap_24___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem24___Stream2Mmap_24___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem24___Stream2Mmap_24___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem24___Stream2Mmap_24___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem24___Stream2Mmap_24___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem24___Stream2Mmap_24___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem24___Stream2Mmap_24___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem24___Stream2Mmap_24___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem24___Stream2Mmap_24___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem24___Stream2Mmap_24___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem24___Stream2Mmap_24___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem24___Stream2Mmap_24___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem24___Stream2Mmap_24___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem24___Stream2Mmap_24___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem24___Stream2Mmap_24___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem24___Stream2Mmap_24___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem24___Stream2Mmap_24___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem24___Stream2Mmap_24___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem24___Stream2Mmap_24___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem24___Stream2Mmap_24___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem24___Stream2Mmap_24___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem24___Stream2Mmap_24___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem24___Stream2Mmap_24___mmap_AWQOS),
+    .mmap_offset(Stream2Mmap_24___rmem24__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Stream2Mmap
+  Stream2Mmap_25
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Stream2Mmap_25__ap_start),
+    .ap_done(Stream2Mmap_25__ap_done),
+    .ap_idle(Stream2Mmap_25__ap_idle),
+    .ap_ready(Stream2Mmap_25__ap_ready),
+    .n(Stream2Mmap_25___n__q0),
+    .stream_s_dout(qw25_vadd_bw__dout),
+    .stream_peek_dout(qw25_vadd_bw__dout),
+    .stream_s_empty_n(qw25_vadd_bw__empty_n),
+    .stream_peek_empty_n(qw25_vadd_bw__empty_n),
+    .stream_s_read(qw25_vadd_bw__read),
+    .stream_peek_read(),
+    .m_axi_mmap_ARADDR(m_axi_rmem25___Stream2Mmap_25___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem25___Stream2Mmap_25___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem25___Stream2Mmap_25___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem25___Stream2Mmap_25___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem25___Stream2Mmap_25___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem25___Stream2Mmap_25___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem25___Stream2Mmap_25___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem25___Stream2Mmap_25___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem25___Stream2Mmap_25___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem25___Stream2Mmap_25___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem25___Stream2Mmap_25___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem25___Stream2Mmap_25___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem25___Stream2Mmap_25___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem25___Stream2Mmap_25___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem25___Stream2Mmap_25___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem25___Stream2Mmap_25___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem25___Stream2Mmap_25___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem25___Stream2Mmap_25___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem25___Stream2Mmap_25___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem25___Stream2Mmap_25___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem25___Stream2Mmap_25___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem25___Stream2Mmap_25___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem25___Stream2Mmap_25___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem25___Stream2Mmap_25___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem25___Stream2Mmap_25___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem25___Stream2Mmap_25___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem25___Stream2Mmap_25___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem25___Stream2Mmap_25___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem25___Stream2Mmap_25___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem25___Stream2Mmap_25___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem25___Stream2Mmap_25___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem25___Stream2Mmap_25___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem25___Stream2Mmap_25___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem25___Stream2Mmap_25___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem25___Stream2Mmap_25___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem25___Stream2Mmap_25___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem25___Stream2Mmap_25___mmap_AWQOS),
+    .mmap_offset(Stream2Mmap_25___rmem25__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Stream2Mmap
+  Stream2Mmap_26
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Stream2Mmap_26__ap_start),
+    .ap_done(Stream2Mmap_26__ap_done),
+    .ap_idle(Stream2Mmap_26__ap_idle),
+    .ap_ready(Stream2Mmap_26__ap_ready),
+    .n(Stream2Mmap_26___n__q0),
+    .stream_s_dout(qw26_vadd_bw__dout),
+    .stream_peek_dout(qw26_vadd_bw__dout),
+    .stream_s_empty_n(qw26_vadd_bw__empty_n),
+    .stream_peek_empty_n(qw26_vadd_bw__empty_n),
+    .stream_s_read(qw26_vadd_bw__read),
+    .stream_peek_read(),
+    .m_axi_mmap_ARADDR(m_axi_rmem26___Stream2Mmap_26___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem26___Stream2Mmap_26___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem26___Stream2Mmap_26___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem26___Stream2Mmap_26___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem26___Stream2Mmap_26___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem26___Stream2Mmap_26___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem26___Stream2Mmap_26___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem26___Stream2Mmap_26___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem26___Stream2Mmap_26___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem26___Stream2Mmap_26___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem26___Stream2Mmap_26___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem26___Stream2Mmap_26___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem26___Stream2Mmap_26___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem26___Stream2Mmap_26___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem26___Stream2Mmap_26___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem26___Stream2Mmap_26___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem26___Stream2Mmap_26___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem26___Stream2Mmap_26___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem26___Stream2Mmap_26___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem26___Stream2Mmap_26___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem26___Stream2Mmap_26___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem26___Stream2Mmap_26___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem26___Stream2Mmap_26___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem26___Stream2Mmap_26___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem26___Stream2Mmap_26___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem26___Stream2Mmap_26___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem26___Stream2Mmap_26___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem26___Stream2Mmap_26___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem26___Stream2Mmap_26___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem26___Stream2Mmap_26___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem26___Stream2Mmap_26___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem26___Stream2Mmap_26___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem26___Stream2Mmap_26___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem26___Stream2Mmap_26___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem26___Stream2Mmap_26___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem26___Stream2Mmap_26___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem26___Stream2Mmap_26___mmap_AWQOS),
+    .mmap_offset(Stream2Mmap_26___rmem26__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) Stream2Mmap
+  Stream2Mmap_27
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(Stream2Mmap_27__ap_start),
+    .ap_done(Stream2Mmap_27__ap_done),
+    .ap_idle(Stream2Mmap_27__ap_idle),
+    .ap_ready(Stream2Mmap_27__ap_ready),
+    .n(Stream2Mmap_27___n__q0),
+    .stream_s_dout(qw27_vadd_bw__dout),
+    .stream_peek_dout(qw27_vadd_bw__dout),
+    .stream_s_empty_n(qw27_vadd_bw__empty_n),
+    .stream_peek_empty_n(qw27_vadd_bw__empty_n),
+    .stream_s_read(qw27_vadd_bw__read),
+    .stream_peek_read(),
+    .m_axi_mmap_ARADDR(m_axi_rmem27___Stream2Mmap_27___mmap_ARADDR),
+    .m_axi_mmap_ARBURST(m_axi_rmem27___Stream2Mmap_27___mmap_ARBURST),
+    .m_axi_mmap_ARID(m_axi_rmem27___Stream2Mmap_27___mmap_ARID),
+    .m_axi_mmap_ARLEN(m_axi_rmem27___Stream2Mmap_27___mmap_ARLEN),
+    .m_axi_mmap_ARREADY(m_axi_rmem27___Stream2Mmap_27___mmap_ARREADY),
+    .m_axi_mmap_ARSIZE(m_axi_rmem27___Stream2Mmap_27___mmap_ARSIZE),
+    .m_axi_mmap_ARVALID(m_axi_rmem27___Stream2Mmap_27___mmap_ARVALID),
+    .m_axi_mmap_AWADDR(m_axi_rmem27___Stream2Mmap_27___mmap_AWADDR),
+    .m_axi_mmap_AWBURST(m_axi_rmem27___Stream2Mmap_27___mmap_AWBURST),
+    .m_axi_mmap_AWID(m_axi_rmem27___Stream2Mmap_27___mmap_AWID),
+    .m_axi_mmap_AWLEN(m_axi_rmem27___Stream2Mmap_27___mmap_AWLEN),
+    .m_axi_mmap_AWREADY(m_axi_rmem27___Stream2Mmap_27___mmap_AWREADY),
+    .m_axi_mmap_AWSIZE(m_axi_rmem27___Stream2Mmap_27___mmap_AWSIZE),
+    .m_axi_mmap_AWVALID(m_axi_rmem27___Stream2Mmap_27___mmap_AWVALID),
+    .m_axi_mmap_BID(m_axi_rmem27___Stream2Mmap_27___mmap_BID),
+    .m_axi_mmap_BREADY(m_axi_rmem27___Stream2Mmap_27___mmap_BREADY),
+    .m_axi_mmap_BRESP(m_axi_rmem27___Stream2Mmap_27___mmap_BRESP),
+    .m_axi_mmap_BVALID(m_axi_rmem27___Stream2Mmap_27___mmap_BVALID),
+    .m_axi_mmap_RDATA(m_axi_rmem27___Stream2Mmap_27___mmap_RDATA),
+    .m_axi_mmap_RID(m_axi_rmem27___Stream2Mmap_27___mmap_RID),
+    .m_axi_mmap_RLAST(m_axi_rmem27___Stream2Mmap_27___mmap_RLAST),
+    .m_axi_mmap_RREADY(m_axi_rmem27___Stream2Mmap_27___mmap_RREADY),
+    .m_axi_mmap_RRESP(m_axi_rmem27___Stream2Mmap_27___mmap_RRESP),
+    .m_axi_mmap_RVALID(m_axi_rmem27___Stream2Mmap_27___mmap_RVALID),
+    .m_axi_mmap_WDATA(m_axi_rmem27___Stream2Mmap_27___mmap_WDATA),
+    .m_axi_mmap_WLAST(m_axi_rmem27___Stream2Mmap_27___mmap_WLAST),
+    .m_axi_mmap_WREADY(m_axi_rmem27___Stream2Mmap_27___mmap_WREADY),
+    .m_axi_mmap_WSTRB(m_axi_rmem27___Stream2Mmap_27___mmap_WSTRB),
+    .m_axi_mmap_WVALID(m_axi_rmem27___Stream2Mmap_27___mmap_WVALID),
+    .m_axi_mmap_ARLOCK(m_axi_rmem27___Stream2Mmap_27___mmap_ARLOCK),
+    .m_axi_mmap_ARPROT(m_axi_rmem27___Stream2Mmap_27___mmap_ARPROT),
+    .m_axi_mmap_ARQOS(m_axi_rmem27___Stream2Mmap_27___mmap_ARQOS),
+    .m_axi_mmap_ARCACHE(m_axi_rmem27___Stream2Mmap_27___mmap_ARCACHE),
+    .m_axi_mmap_AWCACHE(m_axi_rmem27___Stream2Mmap_27___mmap_AWCACHE),
+    .m_axi_mmap_AWLOCK(m_axi_rmem27___Stream2Mmap_27___mmap_AWLOCK),
+    .m_axi_mmap_AWPROT(m_axi_rmem27___Stream2Mmap_27___mmap_AWPROT),
+    .m_axi_mmap_AWQOS(m_axi_rmem27___Stream2Mmap_27___mmap_AWQOS),
+    .mmap_offset(Stream2Mmap_27___rmem27__q0)
+  );
+
+
+  (* keep_hierarchy = "yes" *) yshift
+  yshift_0
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(yshift_0__ap_start),
+    .ap_done(yshift_0__ap_done),
+    .ap_idle(yshift_0__ap_idle),
+    .ap_ready(yshift_0__ap_ready),
+    .n(yshift_0___n__q0),
+    .a_s_dout(qr0_vadd_bw__dout),
+    .a_peek_dout(qr0_vadd_bw__dout),
+    .a_s_empty_n(qr0_vadd_bw__empty_n),
+    .a_peek_empty_n(qr0_vadd_bw__empty_n),
+    .a_s_read(qr0_vadd_bw__read),
+    .a_peek_read(),
+    .b_din(qw0_vadd_bw__din),
+    .b_full_n(qw0_vadd_bw__full_n),
+    .b_write(qw0_vadd_bw__write)
+  );
+
+
+  (* keep_hierarchy = "yes" *) yshift
+  yshift_1
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(yshift_1__ap_start),
+    .ap_done(yshift_1__ap_done),
+    .ap_idle(yshift_1__ap_idle),
+    .ap_ready(yshift_1__ap_ready),
+    .n(yshift_1___n__q0),
+    .a_s_dout(qr1_vadd_bw__dout),
+    .a_peek_dout(qr1_vadd_bw__dout),
+    .a_s_empty_n(qr1_vadd_bw__empty_n),
+    .a_peek_empty_n(qr1_vadd_bw__empty_n),
+    .a_s_read(qr1_vadd_bw__read),
+    .a_peek_read(),
+    .b_din(qw1_vadd_bw__din),
+    .b_full_n(qw1_vadd_bw__full_n),
+    .b_write(qw1_vadd_bw__write)
+  );
+
+
+  (* keep_hierarchy = "yes" *) yshift
+  yshift_2
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(yshift_2__ap_start),
+    .ap_done(yshift_2__ap_done),
+    .ap_idle(yshift_2__ap_idle),
+    .ap_ready(yshift_2__ap_ready),
+    .n(yshift_2___n__q0),
+    .a_s_dout(qr2_vadd_bw__dout),
+    .a_peek_dout(qr2_vadd_bw__dout),
+    .a_s_empty_n(qr2_vadd_bw__empty_n),
+    .a_peek_empty_n(qr2_vadd_bw__empty_n),
+    .a_s_read(qr2_vadd_bw__read),
+    .a_peek_read(),
+    .b_din(qw2_vadd_bw__din),
+    .b_full_n(qw2_vadd_bw__full_n),
+    .b_write(qw2_vadd_bw__write)
+  );
+
+
+  (* keep_hierarchy = "yes" *) yshift
+  yshift_3
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(yshift_3__ap_start),
+    .ap_done(yshift_3__ap_done),
+    .ap_idle(yshift_3__ap_idle),
+    .ap_ready(yshift_3__ap_ready),
+    .n(yshift_3___n__q0),
+    .a_s_dout(qr3_vadd_bw__dout),
+    .a_peek_dout(qr3_vadd_bw__dout),
+    .a_s_empty_n(qr3_vadd_bw__empty_n),
+    .a_peek_empty_n(qr3_vadd_bw__empty_n),
+    .a_s_read(qr3_vadd_bw__read),
+    .a_peek_read(),
+    .b_din(qw3_vadd_bw__din),
+    .b_full_n(qw3_vadd_bw__full_n),
+    .b_write(qw3_vadd_bw__write)
+  );
+
+
+  (* keep_hierarchy = "yes" *) yshift
+  yshift_4
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(yshift_4__ap_start),
+    .ap_done(yshift_4__ap_done),
+    .ap_idle(yshift_4__ap_idle),
+    .ap_ready(yshift_4__ap_ready),
+    .n(yshift_4___n__q0),
+    .a_s_dout(qr4_vadd_bw__dout),
+    .a_peek_dout(qr4_vadd_bw__dout),
+    .a_s_empty_n(qr4_vadd_bw__empty_n),
+    .a_peek_empty_n(qr4_vadd_bw__empty_n),
+    .a_s_read(qr4_vadd_bw__read),
+    .a_peek_read(),
+    .b_din(qw4_vadd_bw__din),
+    .b_full_n(qw4_vadd_bw__full_n),
+    .b_write(qw4_vadd_bw__write)
+  );
+
+
+  (* keep_hierarchy = "yes" *) yshift
+  yshift_5
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(yshift_5__ap_start),
+    .ap_done(yshift_5__ap_done),
+    .ap_idle(yshift_5__ap_idle),
+    .ap_ready(yshift_5__ap_ready),
+    .n(yshift_5___n__q0),
+    .a_s_dout(qr5_vadd_bw__dout),
+    .a_peek_dout(qr5_vadd_bw__dout),
+    .a_s_empty_n(qr5_vadd_bw__empty_n),
+    .a_peek_empty_n(qr5_vadd_bw__empty_n),
+    .a_s_read(qr5_vadd_bw__read),
+    .a_peek_read(),
+    .b_din(qw5_vadd_bw__din),
+    .b_full_n(qw5_vadd_bw__full_n),
+    .b_write(qw5_vadd_bw__write)
+  );
+
+
+  (* keep_hierarchy = "yes" *) yshift
+  yshift_6
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(yshift_6__ap_start),
+    .ap_done(yshift_6__ap_done),
+    .ap_idle(yshift_6__ap_idle),
+    .ap_ready(yshift_6__ap_ready),
+    .n(yshift_6___n__q0),
+    .a_s_dout(qr6_vadd_bw__dout),
+    .a_peek_dout(qr6_vadd_bw__dout),
+    .a_s_empty_n(qr6_vadd_bw__empty_n),
+    .a_peek_empty_n(qr6_vadd_bw__empty_n),
+    .a_s_read(qr6_vadd_bw__read),
+    .a_peek_read(),
+    .b_din(qw6_vadd_bw__din),
+    .b_full_n(qw6_vadd_bw__full_n),
+    .b_write(qw6_vadd_bw__write)
+  );
+
+
+  (* keep_hierarchy = "yes" *) yshift
+  yshift_7
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(yshift_7__ap_start),
+    .ap_done(yshift_7__ap_done),
+    .ap_idle(yshift_7__ap_idle),
+    .ap_ready(yshift_7__ap_ready),
+    .n(yshift_7___n__q0),
+    .a_s_dout(qr7_vadd_bw__dout),
+    .a_peek_dout(qr7_vadd_bw__dout),
+    .a_s_empty_n(qr7_vadd_bw__empty_n),
+    .a_peek_empty_n(qr7_vadd_bw__empty_n),
+    .a_s_read(qr7_vadd_bw__read),
+    .a_peek_read(),
+    .b_din(qw7_vadd_bw__din),
+    .b_full_n(qw7_vadd_bw__full_n),
+    .b_write(qw7_vadd_bw__write)
+  );
+
+
+  (* keep_hierarchy = "yes" *) yshift
+  yshift_8
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(yshift_8__ap_start),
+    .ap_done(yshift_8__ap_done),
+    .ap_idle(yshift_8__ap_idle),
+    .ap_ready(yshift_8__ap_ready),
+    .n(yshift_8___n__q0),
+    .a_s_dout(qr8_vadd_bw__dout),
+    .a_peek_dout(qr8_vadd_bw__dout),
+    .a_s_empty_n(qr8_vadd_bw__empty_n),
+    .a_peek_empty_n(qr8_vadd_bw__empty_n),
+    .a_s_read(qr8_vadd_bw__read),
+    .a_peek_read(),
+    .b_din(qw8_vadd_bw__din),
+    .b_full_n(qw8_vadd_bw__full_n),
+    .b_write(qw8_vadd_bw__write)
+  );
+
+
+  (* keep_hierarchy = "yes" *) yshift
+  yshift_9
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(yshift_9__ap_start),
+    .ap_done(yshift_9__ap_done),
+    .ap_idle(yshift_9__ap_idle),
+    .ap_ready(yshift_9__ap_ready),
+    .n(yshift_9___n__q0),
+    .a_s_dout(qr9_vadd_bw__dout),
+    .a_peek_dout(qr9_vadd_bw__dout),
+    .a_s_empty_n(qr9_vadd_bw__empty_n),
+    .a_peek_empty_n(qr9_vadd_bw__empty_n),
+    .a_s_read(qr9_vadd_bw__read),
+    .a_peek_read(),
+    .b_din(qw9_vadd_bw__din),
+    .b_full_n(qw9_vadd_bw__full_n),
+    .b_write(qw9_vadd_bw__write)
+  );
+
+
+  (* keep_hierarchy = "yes" *) yshift
+  yshift_10
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(yshift_10__ap_start),
+    .ap_done(yshift_10__ap_done),
+    .ap_idle(yshift_10__ap_idle),
+    .ap_ready(yshift_10__ap_ready),
+    .n(yshift_10___n__q0),
+    .a_s_dout(qr10_vadd_bw__dout),
+    .a_peek_dout(qr10_vadd_bw__dout),
+    .a_s_empty_n(qr10_vadd_bw__empty_n),
+    .a_peek_empty_n(qr10_vadd_bw__empty_n),
+    .a_s_read(qr10_vadd_bw__read),
+    .a_peek_read(),
+    .b_din(qw10_vadd_bw__din),
+    .b_full_n(qw10_vadd_bw__full_n),
+    .b_write(qw10_vadd_bw__write)
+  );
+
+
+  (* keep_hierarchy = "yes" *) yshift
+  yshift_11
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(yshift_11__ap_start),
+    .ap_done(yshift_11__ap_done),
+    .ap_idle(yshift_11__ap_idle),
+    .ap_ready(yshift_11__ap_ready),
+    .n(yshift_11___n__q0),
+    .a_s_dout(qr11_vadd_bw__dout),
+    .a_peek_dout(qr11_vadd_bw__dout),
+    .a_s_empty_n(qr11_vadd_bw__empty_n),
+    .a_peek_empty_n(qr11_vadd_bw__empty_n),
+    .a_s_read(qr11_vadd_bw__read),
+    .a_peek_read(),
+    .b_din(qw11_vadd_bw__din),
+    .b_full_n(qw11_vadd_bw__full_n),
+    .b_write(qw11_vadd_bw__write)
+  );
+
+
+  (* keep_hierarchy = "yes" *) yshift
+  yshift_12
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(yshift_12__ap_start),
+    .ap_done(yshift_12__ap_done),
+    .ap_idle(yshift_12__ap_idle),
+    .ap_ready(yshift_12__ap_ready),
+    .n(yshift_12___n__q0),
+    .a_s_dout(qr12_vadd_bw__dout),
+    .a_peek_dout(qr12_vadd_bw__dout),
+    .a_s_empty_n(qr12_vadd_bw__empty_n),
+    .a_peek_empty_n(qr12_vadd_bw__empty_n),
+    .a_s_read(qr12_vadd_bw__read),
+    .a_peek_read(),
+    .b_din(qw12_vadd_bw__din),
+    .b_full_n(qw12_vadd_bw__full_n),
+    .b_write(qw12_vadd_bw__write)
+  );
+
+
+  (* keep_hierarchy = "yes" *) yshift
+  yshift_13
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(yshift_13__ap_start),
+    .ap_done(yshift_13__ap_done),
+    .ap_idle(yshift_13__ap_idle),
+    .ap_ready(yshift_13__ap_ready),
+    .n(yshift_13___n__q0),
+    .a_s_dout(qr13_vadd_bw__dout),
+    .a_peek_dout(qr13_vadd_bw__dout),
+    .a_s_empty_n(qr13_vadd_bw__empty_n),
+    .a_peek_empty_n(qr13_vadd_bw__empty_n),
+    .a_s_read(qr13_vadd_bw__read),
+    .a_peek_read(),
+    .b_din(qw13_vadd_bw__din),
+    .b_full_n(qw13_vadd_bw__full_n),
+    .b_write(qw13_vadd_bw__write)
+  );
+
+
+  (* keep_hierarchy = "yes" *) yshift
+  yshift_14
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(yshift_14__ap_start),
+    .ap_done(yshift_14__ap_done),
+    .ap_idle(yshift_14__ap_idle),
+    .ap_ready(yshift_14__ap_ready),
+    .n(yshift_14___n__q0),
+    .a_s_dout(qr14_vadd_bw__dout),
+    .a_peek_dout(qr14_vadd_bw__dout),
+    .a_s_empty_n(qr14_vadd_bw__empty_n),
+    .a_peek_empty_n(qr14_vadd_bw__empty_n),
+    .a_s_read(qr14_vadd_bw__read),
+    .a_peek_read(),
+    .b_din(qw14_vadd_bw__din),
+    .b_full_n(qw14_vadd_bw__full_n),
+    .b_write(qw14_vadd_bw__write)
+  );
+
+
+  (* keep_hierarchy = "yes" *) yshift
+  yshift_15
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(yshift_15__ap_start),
+    .ap_done(yshift_15__ap_done),
+    .ap_idle(yshift_15__ap_idle),
+    .ap_ready(yshift_15__ap_ready),
+    .n(yshift_15___n__q0),
+    .a_s_dout(qr15_vadd_bw__dout),
+    .a_peek_dout(qr15_vadd_bw__dout),
+    .a_s_empty_n(qr15_vadd_bw__empty_n),
+    .a_peek_empty_n(qr15_vadd_bw__empty_n),
+    .a_s_read(qr15_vadd_bw__read),
+    .a_peek_read(),
+    .b_din(qw15_vadd_bw__din),
+    .b_full_n(qw15_vadd_bw__full_n),
+    .b_write(qw15_vadd_bw__write)
+  );
+
+
+  (* keep_hierarchy = "yes" *) yshift
+  yshift_16
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(yshift_16__ap_start),
+    .ap_done(yshift_16__ap_done),
+    .ap_idle(yshift_16__ap_idle),
+    .ap_ready(yshift_16__ap_ready),
+    .n(yshift_16___n__q0),
+    .a_s_dout(qr16_vadd_bw__dout),
+    .a_peek_dout(qr16_vadd_bw__dout),
+    .a_s_empty_n(qr16_vadd_bw__empty_n),
+    .a_peek_empty_n(qr16_vadd_bw__empty_n),
+    .a_s_read(qr16_vadd_bw__read),
+    .a_peek_read(),
+    .b_din(qw16_vadd_bw__din),
+    .b_full_n(qw16_vadd_bw__full_n),
+    .b_write(qw16_vadd_bw__write)
+  );
+
+
+  (* keep_hierarchy = "yes" *) yshift
+  yshift_17
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(yshift_17__ap_start),
+    .ap_done(yshift_17__ap_done),
+    .ap_idle(yshift_17__ap_idle),
+    .ap_ready(yshift_17__ap_ready),
+    .n(yshift_17___n__q0),
+    .a_s_dout(qr17_vadd_bw__dout),
+    .a_peek_dout(qr17_vadd_bw__dout),
+    .a_s_empty_n(qr17_vadd_bw__empty_n),
+    .a_peek_empty_n(qr17_vadd_bw__empty_n),
+    .a_s_read(qr17_vadd_bw__read),
+    .a_peek_read(),
+    .b_din(qw17_vadd_bw__din),
+    .b_full_n(qw17_vadd_bw__full_n),
+    .b_write(qw17_vadd_bw__write)
+  );
+
+
+  (* keep_hierarchy = "yes" *) yshift
+  yshift_18
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(yshift_18__ap_start),
+    .ap_done(yshift_18__ap_done),
+    .ap_idle(yshift_18__ap_idle),
+    .ap_ready(yshift_18__ap_ready),
+    .n(yshift_18___n__q0),
+    .a_s_dout(qr18_vadd_bw__dout),
+    .a_peek_dout(qr18_vadd_bw__dout),
+    .a_s_empty_n(qr18_vadd_bw__empty_n),
+    .a_peek_empty_n(qr18_vadd_bw__empty_n),
+    .a_s_read(qr18_vadd_bw__read),
+    .a_peek_read(),
+    .b_din(qw18_vadd_bw__din),
+    .b_full_n(qw18_vadd_bw__full_n),
+    .b_write(qw18_vadd_bw__write)
+  );
+
+
+  (* keep_hierarchy = "yes" *) yshift
+  yshift_19
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(yshift_19__ap_start),
+    .ap_done(yshift_19__ap_done),
+    .ap_idle(yshift_19__ap_idle),
+    .ap_ready(yshift_19__ap_ready),
+    .n(yshift_19___n__q0),
+    .a_s_dout(qr19_vadd_bw__dout),
+    .a_peek_dout(qr19_vadd_bw__dout),
+    .a_s_empty_n(qr19_vadd_bw__empty_n),
+    .a_peek_empty_n(qr19_vadd_bw__empty_n),
+    .a_s_read(qr19_vadd_bw__read),
+    .a_peek_read(),
+    .b_din(qw19_vadd_bw__din),
+    .b_full_n(qw19_vadd_bw__full_n),
+    .b_write(qw19_vadd_bw__write)
+  );
+
+
+  (* keep_hierarchy = "yes" *) yshift
+  yshift_20
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(yshift_20__ap_start),
+    .ap_done(yshift_20__ap_done),
+    .ap_idle(yshift_20__ap_idle),
+    .ap_ready(yshift_20__ap_ready),
+    .n(yshift_20___n__q0),
+    .a_s_dout(qr20_vadd_bw__dout),
+    .a_peek_dout(qr20_vadd_bw__dout),
+    .a_s_empty_n(qr20_vadd_bw__empty_n),
+    .a_peek_empty_n(qr20_vadd_bw__empty_n),
+    .a_s_read(qr20_vadd_bw__read),
+    .a_peek_read(),
+    .b_din(qw20_vadd_bw__din),
+    .b_full_n(qw20_vadd_bw__full_n),
+    .b_write(qw20_vadd_bw__write)
+  );
+
+
+  (* keep_hierarchy = "yes" *) yshift
+  yshift_21
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(yshift_21__ap_start),
+    .ap_done(yshift_21__ap_done),
+    .ap_idle(yshift_21__ap_idle),
+    .ap_ready(yshift_21__ap_ready),
+    .n(yshift_21___n__q0),
+    .a_s_dout(qr21_vadd_bw__dout),
+    .a_peek_dout(qr21_vadd_bw__dout),
+    .a_s_empty_n(qr21_vadd_bw__empty_n),
+    .a_peek_empty_n(qr21_vadd_bw__empty_n),
+    .a_s_read(qr21_vadd_bw__read),
+    .a_peek_read(),
+    .b_din(qw21_vadd_bw__din),
+    .b_full_n(qw21_vadd_bw__full_n),
+    .b_write(qw21_vadd_bw__write)
+  );
+
+
+  (* keep_hierarchy = "yes" *) yshift
+  yshift_22
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(yshift_22__ap_start),
+    .ap_done(yshift_22__ap_done),
+    .ap_idle(yshift_22__ap_idle),
+    .ap_ready(yshift_22__ap_ready),
+    .n(yshift_22___n__q0),
+    .a_s_dout(qr22_vadd_bw__dout),
+    .a_peek_dout(qr22_vadd_bw__dout),
+    .a_s_empty_n(qr22_vadd_bw__empty_n),
+    .a_peek_empty_n(qr22_vadd_bw__empty_n),
+    .a_s_read(qr22_vadd_bw__read),
+    .a_peek_read(),
+    .b_din(qw22_vadd_bw__din),
+    .b_full_n(qw22_vadd_bw__full_n),
+    .b_write(qw22_vadd_bw__write)
+  );
+
+
+  (* keep_hierarchy = "yes" *) yshift
+  yshift_23
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(yshift_23__ap_start),
+    .ap_done(yshift_23__ap_done),
+    .ap_idle(yshift_23__ap_idle),
+    .ap_ready(yshift_23__ap_ready),
+    .n(yshift_23___n__q0),
+    .a_s_dout(qr23_vadd_bw__dout),
+    .a_peek_dout(qr23_vadd_bw__dout),
+    .a_s_empty_n(qr23_vadd_bw__empty_n),
+    .a_peek_empty_n(qr23_vadd_bw__empty_n),
+    .a_s_read(qr23_vadd_bw__read),
+    .a_peek_read(),
+    .b_din(qw23_vadd_bw__din),
+    .b_full_n(qw23_vadd_bw__full_n),
+    .b_write(qw23_vadd_bw__write)
+  );
+
+
+  (* keep_hierarchy = "yes" *) yshift
+  yshift_24
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(yshift_24__ap_start),
+    .ap_done(yshift_24__ap_done),
+    .ap_idle(yshift_24__ap_idle),
+    .ap_ready(yshift_24__ap_ready),
+    .n(yshift_24___n__q0),
+    .a_s_dout(qr24_vadd_bw__dout),
+    .a_peek_dout(qr24_vadd_bw__dout),
+    .a_s_empty_n(qr24_vadd_bw__empty_n),
+    .a_peek_empty_n(qr24_vadd_bw__empty_n),
+    .a_s_read(qr24_vadd_bw__read),
+    .a_peek_read(),
+    .b_din(qw24_vadd_bw__din),
+    .b_full_n(qw24_vadd_bw__full_n),
+    .b_write(qw24_vadd_bw__write)
+  );
+
+
+  (* keep_hierarchy = "yes" *) yshift
+  yshift_25
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(yshift_25__ap_start),
+    .ap_done(yshift_25__ap_done),
+    .ap_idle(yshift_25__ap_idle),
+    .ap_ready(yshift_25__ap_ready),
+    .n(yshift_25___n__q0),
+    .a_s_dout(qr25_vadd_bw__dout),
+    .a_peek_dout(qr25_vadd_bw__dout),
+    .a_s_empty_n(qr25_vadd_bw__empty_n),
+    .a_peek_empty_n(qr25_vadd_bw__empty_n),
+    .a_s_read(qr25_vadd_bw__read),
+    .a_peek_read(),
+    .b_din(qw25_vadd_bw__din),
+    .b_full_n(qw25_vadd_bw__full_n),
+    .b_write(qw25_vadd_bw__write)
+  );
+
+
+  (* keep_hierarchy = "yes" *) yshift
+  yshift_26
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(yshift_26__ap_start),
+    .ap_done(yshift_26__ap_done),
+    .ap_idle(yshift_26__ap_idle),
+    .ap_ready(yshift_26__ap_ready),
+    .n(yshift_26___n__q0),
+    .a_s_dout(qr26_vadd_bw__dout),
+    .a_peek_dout(qr26_vadd_bw__dout),
+    .a_s_empty_n(qr26_vadd_bw__empty_n),
+    .a_peek_empty_n(qr26_vadd_bw__empty_n),
+    .a_s_read(qr26_vadd_bw__read),
+    .a_peek_read(),
+    .b_din(qw26_vadd_bw__din),
+    .b_full_n(qw26_vadd_bw__full_n),
+    .b_write(qw26_vadd_bw__write)
+  );
+
+
+  (* keep_hierarchy = "yes" *) yshift
+  yshift_27
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(yshift_27__ap_start),
+    .ap_done(yshift_27__ap_done),
+    .ap_idle(yshift_27__ap_idle),
+    .ap_ready(yshift_27__ap_ready),
+    .n(yshift_27___n__q0),
+    .a_s_dout(qr27_vadd_bw__dout),
+    .a_peek_dout(qr27_vadd_bw__dout),
+    .a_s_empty_n(qr27_vadd_bw__empty_n),
+    .a_peek_empty_n(qr27_vadd_bw__empty_n),
+    .a_s_read(qr27_vadd_bw__read),
+    .a_peek_read(),
+    .b_din(qw27_vadd_bw__din),
+    .b_full_n(qw27_vadd_bw__full_n),
+    .b_write(qw27_vadd_bw__write)
+  );
+
+
+  (* keep_hierarchy = "yes" *) vadd_bw_fsm
+  __tapa_fsm_unit
+  (
+    .ap_clk(ap_clk),
+    .ap_rst_n(ap_rst_n),
+    .ap_start(ap_start),
+    .ap_done(ap_done),
+    .ap_idle(ap_idle),
+    .ap_ready(ap_ready),
+    .n(n),
+    .rmem0(rmem0),
+    .rmem1(rmem1),
+    .rmem2(rmem2),
+    .rmem3(rmem3),
+    .rmem4(rmem4),
+    .rmem5(rmem5),
+    .rmem6(rmem6),
+    .rmem7(rmem7),
+    .rmem8(rmem8),
+    .rmem9(rmem9),
+    .rmem10(rmem10),
+    .rmem11(rmem11),
+    .rmem12(rmem12),
+    .rmem13(rmem13),
+    .rmem14(rmem14),
+    .rmem15(rmem15),
+    .rmem16(rmem16),
+    .rmem17(rmem17),
+    .rmem18(rmem18),
+    .rmem19(rmem19),
+    .rmem20(rmem20),
+    .rmem21(rmem21),
+    .rmem22(rmem22),
+    .rmem23(rmem23),
+    .rmem24(rmem24),
+    .rmem25(rmem25),
+    .rmem26(rmem26),
+    .rmem27(rmem27),
+    .Mmap2Stream_0___n__q0(Mmap2Stream_0___n__q0),
+    .Mmap2Stream_0___rmem0__q0(Mmap2Stream_0___rmem0__q0),
+    .Mmap2Stream_0__ap_start(Mmap2Stream_0__ap_start),
+    .Mmap2Stream_0__ap_ready(Mmap2Stream_0__ap_ready),
+    .Mmap2Stream_0__ap_done(Mmap2Stream_0__ap_done),
+    .Mmap2Stream_0__ap_idle(Mmap2Stream_0__ap_idle),
+    .Mmap2Stream_1___n__q0(Mmap2Stream_1___n__q0),
+    .Mmap2Stream_1___rmem1__q0(Mmap2Stream_1___rmem1__q0),
+    .Mmap2Stream_1__ap_start(Mmap2Stream_1__ap_start),
+    .Mmap2Stream_1__ap_ready(Mmap2Stream_1__ap_ready),
+    .Mmap2Stream_1__ap_done(Mmap2Stream_1__ap_done),
+    .Mmap2Stream_1__ap_idle(Mmap2Stream_1__ap_idle),
+    .Mmap2Stream_2___n__q0(Mmap2Stream_2___n__q0),
+    .Mmap2Stream_2___rmem2__q0(Mmap2Stream_2___rmem2__q0),
+    .Mmap2Stream_2__ap_start(Mmap2Stream_2__ap_start),
+    .Mmap2Stream_2__ap_ready(Mmap2Stream_2__ap_ready),
+    .Mmap2Stream_2__ap_done(Mmap2Stream_2__ap_done),
+    .Mmap2Stream_2__ap_idle(Mmap2Stream_2__ap_idle),
+    .Mmap2Stream_3___n__q0(Mmap2Stream_3___n__q0),
+    .Mmap2Stream_3___rmem3__q0(Mmap2Stream_3___rmem3__q0),
+    .Mmap2Stream_3__ap_start(Mmap2Stream_3__ap_start),
+    .Mmap2Stream_3__ap_ready(Mmap2Stream_3__ap_ready),
+    .Mmap2Stream_3__ap_done(Mmap2Stream_3__ap_done),
+    .Mmap2Stream_3__ap_idle(Mmap2Stream_3__ap_idle),
+    .Mmap2Stream_4___n__q0(Mmap2Stream_4___n__q0),
+    .Mmap2Stream_4___rmem4__q0(Mmap2Stream_4___rmem4__q0),
+    .Mmap2Stream_4__ap_start(Mmap2Stream_4__ap_start),
+    .Mmap2Stream_4__ap_ready(Mmap2Stream_4__ap_ready),
+    .Mmap2Stream_4__ap_done(Mmap2Stream_4__ap_done),
+    .Mmap2Stream_4__ap_idle(Mmap2Stream_4__ap_idle),
+    .Mmap2Stream_5___n__q0(Mmap2Stream_5___n__q0),
+    .Mmap2Stream_5___rmem5__q0(Mmap2Stream_5___rmem5__q0),
+    .Mmap2Stream_5__ap_start(Mmap2Stream_5__ap_start),
+    .Mmap2Stream_5__ap_ready(Mmap2Stream_5__ap_ready),
+    .Mmap2Stream_5__ap_done(Mmap2Stream_5__ap_done),
+    .Mmap2Stream_5__ap_idle(Mmap2Stream_5__ap_idle),
+    .Mmap2Stream_6___n__q0(Mmap2Stream_6___n__q0),
+    .Mmap2Stream_6___rmem6__q0(Mmap2Stream_6___rmem6__q0),
+    .Mmap2Stream_6__ap_start(Mmap2Stream_6__ap_start),
+    .Mmap2Stream_6__ap_ready(Mmap2Stream_6__ap_ready),
+    .Mmap2Stream_6__ap_done(Mmap2Stream_6__ap_done),
+    .Mmap2Stream_6__ap_idle(Mmap2Stream_6__ap_idle),
+    .Mmap2Stream_7___n__q0(Mmap2Stream_7___n__q0),
+    .Mmap2Stream_7___rmem7__q0(Mmap2Stream_7___rmem7__q0),
+    .Mmap2Stream_7__ap_start(Mmap2Stream_7__ap_start),
+    .Mmap2Stream_7__ap_ready(Mmap2Stream_7__ap_ready),
+    .Mmap2Stream_7__ap_done(Mmap2Stream_7__ap_done),
+    .Mmap2Stream_7__ap_idle(Mmap2Stream_7__ap_idle),
+    .Mmap2Stream_8___n__q0(Mmap2Stream_8___n__q0),
+    .Mmap2Stream_8___rmem8__q0(Mmap2Stream_8___rmem8__q0),
+    .Mmap2Stream_8__ap_start(Mmap2Stream_8__ap_start),
+    .Mmap2Stream_8__ap_ready(Mmap2Stream_8__ap_ready),
+    .Mmap2Stream_8__ap_done(Mmap2Stream_8__ap_done),
+    .Mmap2Stream_8__ap_idle(Mmap2Stream_8__ap_idle),
+    .Mmap2Stream_9___n__q0(Mmap2Stream_9___n__q0),
+    .Mmap2Stream_9___rmem9__q0(Mmap2Stream_9___rmem9__q0),
+    .Mmap2Stream_9__ap_start(Mmap2Stream_9__ap_start),
+    .Mmap2Stream_9__ap_ready(Mmap2Stream_9__ap_ready),
+    .Mmap2Stream_9__ap_done(Mmap2Stream_9__ap_done),
+    .Mmap2Stream_9__ap_idle(Mmap2Stream_9__ap_idle),
+    .Mmap2Stream_10___n__q0(Mmap2Stream_10___n__q0),
+    .Mmap2Stream_10___rmem10__q0(Mmap2Stream_10___rmem10__q0),
+    .Mmap2Stream_10__ap_start(Mmap2Stream_10__ap_start),
+    .Mmap2Stream_10__ap_ready(Mmap2Stream_10__ap_ready),
+    .Mmap2Stream_10__ap_done(Mmap2Stream_10__ap_done),
+    .Mmap2Stream_10__ap_idle(Mmap2Stream_10__ap_idle),
+    .Mmap2Stream_11___n__q0(Mmap2Stream_11___n__q0),
+    .Mmap2Stream_11___rmem11__q0(Mmap2Stream_11___rmem11__q0),
+    .Mmap2Stream_11__ap_start(Mmap2Stream_11__ap_start),
+    .Mmap2Stream_11__ap_ready(Mmap2Stream_11__ap_ready),
+    .Mmap2Stream_11__ap_done(Mmap2Stream_11__ap_done),
+    .Mmap2Stream_11__ap_idle(Mmap2Stream_11__ap_idle),
+    .Mmap2Stream_12___n__q0(Mmap2Stream_12___n__q0),
+    .Mmap2Stream_12___rmem12__q0(Mmap2Stream_12___rmem12__q0),
+    .Mmap2Stream_12__ap_start(Mmap2Stream_12__ap_start),
+    .Mmap2Stream_12__ap_ready(Mmap2Stream_12__ap_ready),
+    .Mmap2Stream_12__ap_done(Mmap2Stream_12__ap_done),
+    .Mmap2Stream_12__ap_idle(Mmap2Stream_12__ap_idle),
+    .Mmap2Stream_13___n__q0(Mmap2Stream_13___n__q0),
+    .Mmap2Stream_13___rmem13__q0(Mmap2Stream_13___rmem13__q0),
+    .Mmap2Stream_13__ap_start(Mmap2Stream_13__ap_start),
+    .Mmap2Stream_13__ap_ready(Mmap2Stream_13__ap_ready),
+    .Mmap2Stream_13__ap_done(Mmap2Stream_13__ap_done),
+    .Mmap2Stream_13__ap_idle(Mmap2Stream_13__ap_idle),
+    .Mmap2Stream_14___n__q0(Mmap2Stream_14___n__q0),
+    .Mmap2Stream_14___rmem14__q0(Mmap2Stream_14___rmem14__q0),
+    .Mmap2Stream_14__ap_start(Mmap2Stream_14__ap_start),
+    .Mmap2Stream_14__ap_ready(Mmap2Stream_14__ap_ready),
+    .Mmap2Stream_14__ap_done(Mmap2Stream_14__ap_done),
+    .Mmap2Stream_14__ap_idle(Mmap2Stream_14__ap_idle),
+    .Mmap2Stream_15___n__q0(Mmap2Stream_15___n__q0),
+    .Mmap2Stream_15___rmem15__q0(Mmap2Stream_15___rmem15__q0),
+    .Mmap2Stream_15__ap_start(Mmap2Stream_15__ap_start),
+    .Mmap2Stream_15__ap_ready(Mmap2Stream_15__ap_ready),
+    .Mmap2Stream_15__ap_done(Mmap2Stream_15__ap_done),
+    .Mmap2Stream_15__ap_idle(Mmap2Stream_15__ap_idle),
+    .Mmap2Stream_16___n__q0(Mmap2Stream_16___n__q0),
+    .Mmap2Stream_16___rmem16__q0(Mmap2Stream_16___rmem16__q0),
+    .Mmap2Stream_16__ap_start(Mmap2Stream_16__ap_start),
+    .Mmap2Stream_16__ap_ready(Mmap2Stream_16__ap_ready),
+    .Mmap2Stream_16__ap_done(Mmap2Stream_16__ap_done),
+    .Mmap2Stream_16__ap_idle(Mmap2Stream_16__ap_idle),
+    .Mmap2Stream_17___n__q0(Mmap2Stream_17___n__q0),
+    .Mmap2Stream_17___rmem17__q0(Mmap2Stream_17___rmem17__q0),
+    .Mmap2Stream_17__ap_start(Mmap2Stream_17__ap_start),
+    .Mmap2Stream_17__ap_ready(Mmap2Stream_17__ap_ready),
+    .Mmap2Stream_17__ap_done(Mmap2Stream_17__ap_done),
+    .Mmap2Stream_17__ap_idle(Mmap2Stream_17__ap_idle),
+    .Mmap2Stream_18___n__q0(Mmap2Stream_18___n__q0),
+    .Mmap2Stream_18___rmem18__q0(Mmap2Stream_18___rmem18__q0),
+    .Mmap2Stream_18__ap_start(Mmap2Stream_18__ap_start),
+    .Mmap2Stream_18__ap_ready(Mmap2Stream_18__ap_ready),
+    .Mmap2Stream_18__ap_done(Mmap2Stream_18__ap_done),
+    .Mmap2Stream_18__ap_idle(Mmap2Stream_18__ap_idle),
+    .Mmap2Stream_19___n__q0(Mmap2Stream_19___n__q0),
+    .Mmap2Stream_19___rmem19__q0(Mmap2Stream_19___rmem19__q0),
+    .Mmap2Stream_19__ap_start(Mmap2Stream_19__ap_start),
+    .Mmap2Stream_19__ap_ready(Mmap2Stream_19__ap_ready),
+    .Mmap2Stream_19__ap_done(Mmap2Stream_19__ap_done),
+    .Mmap2Stream_19__ap_idle(Mmap2Stream_19__ap_idle),
+    .Mmap2Stream_20___n__q0(Mmap2Stream_20___n__q0),
+    .Mmap2Stream_20___rmem20__q0(Mmap2Stream_20___rmem20__q0),
+    .Mmap2Stream_20__ap_start(Mmap2Stream_20__ap_start),
+    .Mmap2Stream_20__ap_ready(Mmap2Stream_20__ap_ready),
+    .Mmap2Stream_20__ap_done(Mmap2Stream_20__ap_done),
+    .Mmap2Stream_20__ap_idle(Mmap2Stream_20__ap_idle),
+    .Mmap2Stream_21___n__q0(Mmap2Stream_21___n__q0),
+    .Mmap2Stream_21___rmem21__q0(Mmap2Stream_21___rmem21__q0),
+    .Mmap2Stream_21__ap_start(Mmap2Stream_21__ap_start),
+    .Mmap2Stream_21__ap_ready(Mmap2Stream_21__ap_ready),
+    .Mmap2Stream_21__ap_done(Mmap2Stream_21__ap_done),
+    .Mmap2Stream_21__ap_idle(Mmap2Stream_21__ap_idle),
+    .Mmap2Stream_22___n__q0(Mmap2Stream_22___n__q0),
+    .Mmap2Stream_22___rmem22__q0(Mmap2Stream_22___rmem22__q0),
+    .Mmap2Stream_22__ap_start(Mmap2Stream_22__ap_start),
+    .Mmap2Stream_22__ap_ready(Mmap2Stream_22__ap_ready),
+    .Mmap2Stream_22__ap_done(Mmap2Stream_22__ap_done),
+    .Mmap2Stream_22__ap_idle(Mmap2Stream_22__ap_idle),
+    .Mmap2Stream_23___n__q0(Mmap2Stream_23___n__q0),
+    .Mmap2Stream_23___rmem23__q0(Mmap2Stream_23___rmem23__q0),
+    .Mmap2Stream_23__ap_start(Mmap2Stream_23__ap_start),
+    .Mmap2Stream_23__ap_ready(Mmap2Stream_23__ap_ready),
+    .Mmap2Stream_23__ap_done(Mmap2Stream_23__ap_done),
+    .Mmap2Stream_23__ap_idle(Mmap2Stream_23__ap_idle),
+    .Mmap2Stream_24___n__q0(Mmap2Stream_24___n__q0),
+    .Mmap2Stream_24___rmem24__q0(Mmap2Stream_24___rmem24__q0),
+    .Mmap2Stream_24__ap_start(Mmap2Stream_24__ap_start),
+    .Mmap2Stream_24__ap_ready(Mmap2Stream_24__ap_ready),
+    .Mmap2Stream_24__ap_done(Mmap2Stream_24__ap_done),
+    .Mmap2Stream_24__ap_idle(Mmap2Stream_24__ap_idle),
+    .Mmap2Stream_25___n__q0(Mmap2Stream_25___n__q0),
+    .Mmap2Stream_25___rmem25__q0(Mmap2Stream_25___rmem25__q0),
+    .Mmap2Stream_25__ap_start(Mmap2Stream_25__ap_start),
+    .Mmap2Stream_25__ap_ready(Mmap2Stream_25__ap_ready),
+    .Mmap2Stream_25__ap_done(Mmap2Stream_25__ap_done),
+    .Mmap2Stream_25__ap_idle(Mmap2Stream_25__ap_idle),
+    .Mmap2Stream_26___n__q0(Mmap2Stream_26___n__q0),
+    .Mmap2Stream_26___rmem26__q0(Mmap2Stream_26___rmem26__q0),
+    .Mmap2Stream_26__ap_start(Mmap2Stream_26__ap_start),
+    .Mmap2Stream_26__ap_ready(Mmap2Stream_26__ap_ready),
+    .Mmap2Stream_26__ap_done(Mmap2Stream_26__ap_done),
+    .Mmap2Stream_26__ap_idle(Mmap2Stream_26__ap_idle),
+    .Mmap2Stream_27___n__q0(Mmap2Stream_27___n__q0),
+    .Mmap2Stream_27___rmem27__q0(Mmap2Stream_27___rmem27__q0),
+    .Mmap2Stream_27__ap_start(Mmap2Stream_27__ap_start),
+    .Mmap2Stream_27__ap_ready(Mmap2Stream_27__ap_ready),
+    .Mmap2Stream_27__ap_done(Mmap2Stream_27__ap_done),
+    .Mmap2Stream_27__ap_idle(Mmap2Stream_27__ap_idle),
+    .Stream2Mmap_0___n__q0(Stream2Mmap_0___n__q0),
+    .Stream2Mmap_0___rmem0__q0(Stream2Mmap_0___rmem0__q0),
+    .Stream2Mmap_0__ap_start(Stream2Mmap_0__ap_start),
+    .Stream2Mmap_0__ap_ready(Stream2Mmap_0__ap_ready),
+    .Stream2Mmap_0__ap_done(Stream2Mmap_0__ap_done),
+    .Stream2Mmap_0__ap_idle(Stream2Mmap_0__ap_idle),
+    .Stream2Mmap_1___n__q0(Stream2Mmap_1___n__q0),
+    .Stream2Mmap_1___rmem1__q0(Stream2Mmap_1___rmem1__q0),
+    .Stream2Mmap_1__ap_start(Stream2Mmap_1__ap_start),
+    .Stream2Mmap_1__ap_ready(Stream2Mmap_1__ap_ready),
+    .Stream2Mmap_1__ap_done(Stream2Mmap_1__ap_done),
+    .Stream2Mmap_1__ap_idle(Stream2Mmap_1__ap_idle),
+    .Stream2Mmap_2___n__q0(Stream2Mmap_2___n__q0),
+    .Stream2Mmap_2___rmem2__q0(Stream2Mmap_2___rmem2__q0),
+    .Stream2Mmap_2__ap_start(Stream2Mmap_2__ap_start),
+    .Stream2Mmap_2__ap_ready(Stream2Mmap_2__ap_ready),
+    .Stream2Mmap_2__ap_done(Stream2Mmap_2__ap_done),
+    .Stream2Mmap_2__ap_idle(Stream2Mmap_2__ap_idle),
+    .Stream2Mmap_3___n__q0(Stream2Mmap_3___n__q0),
+    .Stream2Mmap_3___rmem3__q0(Stream2Mmap_3___rmem3__q0),
+    .Stream2Mmap_3__ap_start(Stream2Mmap_3__ap_start),
+    .Stream2Mmap_3__ap_ready(Stream2Mmap_3__ap_ready),
+    .Stream2Mmap_3__ap_done(Stream2Mmap_3__ap_done),
+    .Stream2Mmap_3__ap_idle(Stream2Mmap_3__ap_idle),
+    .Stream2Mmap_4___n__q0(Stream2Mmap_4___n__q0),
+    .Stream2Mmap_4___rmem4__q0(Stream2Mmap_4___rmem4__q0),
+    .Stream2Mmap_4__ap_start(Stream2Mmap_4__ap_start),
+    .Stream2Mmap_4__ap_ready(Stream2Mmap_4__ap_ready),
+    .Stream2Mmap_4__ap_done(Stream2Mmap_4__ap_done),
+    .Stream2Mmap_4__ap_idle(Stream2Mmap_4__ap_idle),
+    .Stream2Mmap_5___n__q0(Stream2Mmap_5___n__q0),
+    .Stream2Mmap_5___rmem5__q0(Stream2Mmap_5___rmem5__q0),
+    .Stream2Mmap_5__ap_start(Stream2Mmap_5__ap_start),
+    .Stream2Mmap_5__ap_ready(Stream2Mmap_5__ap_ready),
+    .Stream2Mmap_5__ap_done(Stream2Mmap_5__ap_done),
+    .Stream2Mmap_5__ap_idle(Stream2Mmap_5__ap_idle),
+    .Stream2Mmap_6___n__q0(Stream2Mmap_6___n__q0),
+    .Stream2Mmap_6___rmem6__q0(Stream2Mmap_6___rmem6__q0),
+    .Stream2Mmap_6__ap_start(Stream2Mmap_6__ap_start),
+    .Stream2Mmap_6__ap_ready(Stream2Mmap_6__ap_ready),
+    .Stream2Mmap_6__ap_done(Stream2Mmap_6__ap_done),
+    .Stream2Mmap_6__ap_idle(Stream2Mmap_6__ap_idle),
+    .Stream2Mmap_7___n__q0(Stream2Mmap_7___n__q0),
+    .Stream2Mmap_7___rmem7__q0(Stream2Mmap_7___rmem7__q0),
+    .Stream2Mmap_7__ap_start(Stream2Mmap_7__ap_start),
+    .Stream2Mmap_7__ap_ready(Stream2Mmap_7__ap_ready),
+    .Stream2Mmap_7__ap_done(Stream2Mmap_7__ap_done),
+    .Stream2Mmap_7__ap_idle(Stream2Mmap_7__ap_idle),
+    .Stream2Mmap_8___n__q0(Stream2Mmap_8___n__q0),
+    .Stream2Mmap_8___rmem8__q0(Stream2Mmap_8___rmem8__q0),
+    .Stream2Mmap_8__ap_start(Stream2Mmap_8__ap_start),
+    .Stream2Mmap_8__ap_ready(Stream2Mmap_8__ap_ready),
+    .Stream2Mmap_8__ap_done(Stream2Mmap_8__ap_done),
+    .Stream2Mmap_8__ap_idle(Stream2Mmap_8__ap_idle),
+    .Stream2Mmap_9___n__q0(Stream2Mmap_9___n__q0),
+    .Stream2Mmap_9___rmem9__q0(Stream2Mmap_9___rmem9__q0),
+    .Stream2Mmap_9__ap_start(Stream2Mmap_9__ap_start),
+    .Stream2Mmap_9__ap_ready(Stream2Mmap_9__ap_ready),
+    .Stream2Mmap_9__ap_done(Stream2Mmap_9__ap_done),
+    .Stream2Mmap_9__ap_idle(Stream2Mmap_9__ap_idle),
+    .Stream2Mmap_10___n__q0(Stream2Mmap_10___n__q0),
+    .Stream2Mmap_10___rmem10__q0(Stream2Mmap_10___rmem10__q0),
+    .Stream2Mmap_10__ap_start(Stream2Mmap_10__ap_start),
+    .Stream2Mmap_10__ap_ready(Stream2Mmap_10__ap_ready),
+    .Stream2Mmap_10__ap_done(Stream2Mmap_10__ap_done),
+    .Stream2Mmap_10__ap_idle(Stream2Mmap_10__ap_idle),
+    .Stream2Mmap_11___n__q0(Stream2Mmap_11___n__q0),
+    .Stream2Mmap_11___rmem11__q0(Stream2Mmap_11___rmem11__q0),
+    .Stream2Mmap_11__ap_start(Stream2Mmap_11__ap_start),
+    .Stream2Mmap_11__ap_ready(Stream2Mmap_11__ap_ready),
+    .Stream2Mmap_11__ap_done(Stream2Mmap_11__ap_done),
+    .Stream2Mmap_11__ap_idle(Stream2Mmap_11__ap_idle),
+    .Stream2Mmap_12___n__q0(Stream2Mmap_12___n__q0),
+    .Stream2Mmap_12___rmem12__q0(Stream2Mmap_12___rmem12__q0),
+    .Stream2Mmap_12__ap_start(Stream2Mmap_12__ap_start),
+    .Stream2Mmap_12__ap_ready(Stream2Mmap_12__ap_ready),
+    .Stream2Mmap_12__ap_done(Stream2Mmap_12__ap_done),
+    .Stream2Mmap_12__ap_idle(Stream2Mmap_12__ap_idle),
+    .Stream2Mmap_13___n__q0(Stream2Mmap_13___n__q0),
+    .Stream2Mmap_13___rmem13__q0(Stream2Mmap_13___rmem13__q0),
+    .Stream2Mmap_13__ap_start(Stream2Mmap_13__ap_start),
+    .Stream2Mmap_13__ap_ready(Stream2Mmap_13__ap_ready),
+    .Stream2Mmap_13__ap_done(Stream2Mmap_13__ap_done),
+    .Stream2Mmap_13__ap_idle(Stream2Mmap_13__ap_idle),
+    .Stream2Mmap_14___n__q0(Stream2Mmap_14___n__q0),
+    .Stream2Mmap_14___rmem14__q0(Stream2Mmap_14___rmem14__q0),
+    .Stream2Mmap_14__ap_start(Stream2Mmap_14__ap_start),
+    .Stream2Mmap_14__ap_ready(Stream2Mmap_14__ap_ready),
+    .Stream2Mmap_14__ap_done(Stream2Mmap_14__ap_done),
+    .Stream2Mmap_14__ap_idle(Stream2Mmap_14__ap_idle),
+    .Stream2Mmap_15___n__q0(Stream2Mmap_15___n__q0),
+    .Stream2Mmap_15___rmem15__q0(Stream2Mmap_15___rmem15__q0),
+    .Stream2Mmap_15__ap_start(Stream2Mmap_15__ap_start),
+    .Stream2Mmap_15__ap_ready(Stream2Mmap_15__ap_ready),
+    .Stream2Mmap_15__ap_done(Stream2Mmap_15__ap_done),
+    .Stream2Mmap_15__ap_idle(Stream2Mmap_15__ap_idle),
+    .Stream2Mmap_16___n__q0(Stream2Mmap_16___n__q0),
+    .Stream2Mmap_16___rmem16__q0(Stream2Mmap_16___rmem16__q0),
+    .Stream2Mmap_16__ap_start(Stream2Mmap_16__ap_start),
+    .Stream2Mmap_16__ap_ready(Stream2Mmap_16__ap_ready),
+    .Stream2Mmap_16__ap_done(Stream2Mmap_16__ap_done),
+    .Stream2Mmap_16__ap_idle(Stream2Mmap_16__ap_idle),
+    .Stream2Mmap_17___n__q0(Stream2Mmap_17___n__q0),
+    .Stream2Mmap_17___rmem17__q0(Stream2Mmap_17___rmem17__q0),
+    .Stream2Mmap_17__ap_start(Stream2Mmap_17__ap_start),
+    .Stream2Mmap_17__ap_ready(Stream2Mmap_17__ap_ready),
+    .Stream2Mmap_17__ap_done(Stream2Mmap_17__ap_done),
+    .Stream2Mmap_17__ap_idle(Stream2Mmap_17__ap_idle),
+    .Stream2Mmap_18___n__q0(Stream2Mmap_18___n__q0),
+    .Stream2Mmap_18___rmem18__q0(Stream2Mmap_18___rmem18__q0),
+    .Stream2Mmap_18__ap_start(Stream2Mmap_18__ap_start),
+    .Stream2Mmap_18__ap_ready(Stream2Mmap_18__ap_ready),
+    .Stream2Mmap_18__ap_done(Stream2Mmap_18__ap_done),
+    .Stream2Mmap_18__ap_idle(Stream2Mmap_18__ap_idle),
+    .Stream2Mmap_19___n__q0(Stream2Mmap_19___n__q0),
+    .Stream2Mmap_19___rmem19__q0(Stream2Mmap_19___rmem19__q0),
+    .Stream2Mmap_19__ap_start(Stream2Mmap_19__ap_start),
+    .Stream2Mmap_19__ap_ready(Stream2Mmap_19__ap_ready),
+    .Stream2Mmap_19__ap_done(Stream2Mmap_19__ap_done),
+    .Stream2Mmap_19__ap_idle(Stream2Mmap_19__ap_idle),
+    .Stream2Mmap_20___n__q0(Stream2Mmap_20___n__q0),
+    .Stream2Mmap_20___rmem20__q0(Stream2Mmap_20___rmem20__q0),
+    .Stream2Mmap_20__ap_start(Stream2Mmap_20__ap_start),
+    .Stream2Mmap_20__ap_ready(Stream2Mmap_20__ap_ready),
+    .Stream2Mmap_20__ap_done(Stream2Mmap_20__ap_done),
+    .Stream2Mmap_20__ap_idle(Stream2Mmap_20__ap_idle),
+    .Stream2Mmap_21___n__q0(Stream2Mmap_21___n__q0),
+    .Stream2Mmap_21___rmem21__q0(Stream2Mmap_21___rmem21__q0),
+    .Stream2Mmap_21__ap_start(Stream2Mmap_21__ap_start),
+    .Stream2Mmap_21__ap_ready(Stream2Mmap_21__ap_ready),
+    .Stream2Mmap_21__ap_done(Stream2Mmap_21__ap_done),
+    .Stream2Mmap_21__ap_idle(Stream2Mmap_21__ap_idle),
+    .Stream2Mmap_22___n__q0(Stream2Mmap_22___n__q0),
+    .Stream2Mmap_22___rmem22__q0(Stream2Mmap_22___rmem22__q0),
+    .Stream2Mmap_22__ap_start(Stream2Mmap_22__ap_start),
+    .Stream2Mmap_22__ap_ready(Stream2Mmap_22__ap_ready),
+    .Stream2Mmap_22__ap_done(Stream2Mmap_22__ap_done),
+    .Stream2Mmap_22__ap_idle(Stream2Mmap_22__ap_idle),
+    .Stream2Mmap_23___n__q0(Stream2Mmap_23___n__q0),
+    .Stream2Mmap_23___rmem23__q0(Stream2Mmap_23___rmem23__q0),
+    .Stream2Mmap_23__ap_start(Stream2Mmap_23__ap_start),
+    .Stream2Mmap_23__ap_ready(Stream2Mmap_23__ap_ready),
+    .Stream2Mmap_23__ap_done(Stream2Mmap_23__ap_done),
+    .Stream2Mmap_23__ap_idle(Stream2Mmap_23__ap_idle),
+    .Stream2Mmap_24___n__q0(Stream2Mmap_24___n__q0),
+    .Stream2Mmap_24___rmem24__q0(Stream2Mmap_24___rmem24__q0),
+    .Stream2Mmap_24__ap_start(Stream2Mmap_24__ap_start),
+    .Stream2Mmap_24__ap_ready(Stream2Mmap_24__ap_ready),
+    .Stream2Mmap_24__ap_done(Stream2Mmap_24__ap_done),
+    .Stream2Mmap_24__ap_idle(Stream2Mmap_24__ap_idle),
+    .Stream2Mmap_25___n__q0(Stream2Mmap_25___n__q0),
+    .Stream2Mmap_25___rmem25__q0(Stream2Mmap_25___rmem25__q0),
+    .Stream2Mmap_25__ap_start(Stream2Mmap_25__ap_start),
+    .Stream2Mmap_25__ap_ready(Stream2Mmap_25__ap_ready),
+    .Stream2Mmap_25__ap_done(Stream2Mmap_25__ap_done),
+    .Stream2Mmap_25__ap_idle(Stream2Mmap_25__ap_idle),
+    .Stream2Mmap_26___n__q0(Stream2Mmap_26___n__q0),
+    .Stream2Mmap_26___rmem26__q0(Stream2Mmap_26___rmem26__q0),
+    .Stream2Mmap_26__ap_start(Stream2Mmap_26__ap_start),
+    .Stream2Mmap_26__ap_ready(Stream2Mmap_26__ap_ready),
+    .Stream2Mmap_26__ap_done(Stream2Mmap_26__ap_done),
+    .Stream2Mmap_26__ap_idle(Stream2Mmap_26__ap_idle),
+    .Stream2Mmap_27___n__q0(Stream2Mmap_27___n__q0),
+    .Stream2Mmap_27___rmem27__q0(Stream2Mmap_27___rmem27__q0),
+    .Stream2Mmap_27__ap_start(Stream2Mmap_27__ap_start),
+    .Stream2Mmap_27__ap_ready(Stream2Mmap_27__ap_ready),
+    .Stream2Mmap_27__ap_done(Stream2Mmap_27__ap_done),
+    .Stream2Mmap_27__ap_idle(Stream2Mmap_27__ap_idle),
+    .yshift_0___n__q0(yshift_0___n__q0),
+    .yshift_0__ap_start(yshift_0__ap_start),
+    .yshift_0__ap_ready(yshift_0__ap_ready),
+    .yshift_0__ap_done(yshift_0__ap_done),
+    .yshift_0__ap_idle(yshift_0__ap_idle),
+    .yshift_1___n__q0(yshift_1___n__q0),
+    .yshift_1__ap_start(yshift_1__ap_start),
+    .yshift_1__ap_ready(yshift_1__ap_ready),
+    .yshift_1__ap_done(yshift_1__ap_done),
+    .yshift_1__ap_idle(yshift_1__ap_idle),
+    .yshift_2___n__q0(yshift_2___n__q0),
+    .yshift_2__ap_start(yshift_2__ap_start),
+    .yshift_2__ap_ready(yshift_2__ap_ready),
+    .yshift_2__ap_done(yshift_2__ap_done),
+    .yshift_2__ap_idle(yshift_2__ap_idle),
+    .yshift_3___n__q0(yshift_3___n__q0),
+    .yshift_3__ap_start(yshift_3__ap_start),
+    .yshift_3__ap_ready(yshift_3__ap_ready),
+    .yshift_3__ap_done(yshift_3__ap_done),
+    .yshift_3__ap_idle(yshift_3__ap_idle),
+    .yshift_4___n__q0(yshift_4___n__q0),
+    .yshift_4__ap_start(yshift_4__ap_start),
+    .yshift_4__ap_ready(yshift_4__ap_ready),
+    .yshift_4__ap_done(yshift_4__ap_done),
+    .yshift_4__ap_idle(yshift_4__ap_idle),
+    .yshift_5___n__q0(yshift_5___n__q0),
+    .yshift_5__ap_start(yshift_5__ap_start),
+    .yshift_5__ap_ready(yshift_5__ap_ready),
+    .yshift_5__ap_done(yshift_5__ap_done),
+    .yshift_5__ap_idle(yshift_5__ap_idle),
+    .yshift_6___n__q0(yshift_6___n__q0),
+    .yshift_6__ap_start(yshift_6__ap_start),
+    .yshift_6__ap_ready(yshift_6__ap_ready),
+    .yshift_6__ap_done(yshift_6__ap_done),
+    .yshift_6__ap_idle(yshift_6__ap_idle),
+    .yshift_7___n__q0(yshift_7___n__q0),
+    .yshift_7__ap_start(yshift_7__ap_start),
+    .yshift_7__ap_ready(yshift_7__ap_ready),
+    .yshift_7__ap_done(yshift_7__ap_done),
+    .yshift_7__ap_idle(yshift_7__ap_idle),
+    .yshift_8___n__q0(yshift_8___n__q0),
+    .yshift_8__ap_start(yshift_8__ap_start),
+    .yshift_8__ap_ready(yshift_8__ap_ready),
+    .yshift_8__ap_done(yshift_8__ap_done),
+    .yshift_8__ap_idle(yshift_8__ap_idle),
+    .yshift_9___n__q0(yshift_9___n__q0),
+    .yshift_9__ap_start(yshift_9__ap_start),
+    .yshift_9__ap_ready(yshift_9__ap_ready),
+    .yshift_9__ap_done(yshift_9__ap_done),
+    .yshift_9__ap_idle(yshift_9__ap_idle),
+    .yshift_10___n__q0(yshift_10___n__q0),
+    .yshift_10__ap_start(yshift_10__ap_start),
+    .yshift_10__ap_ready(yshift_10__ap_ready),
+    .yshift_10__ap_done(yshift_10__ap_done),
+    .yshift_10__ap_idle(yshift_10__ap_idle),
+    .yshift_11___n__q0(yshift_11___n__q0),
+    .yshift_11__ap_start(yshift_11__ap_start),
+    .yshift_11__ap_ready(yshift_11__ap_ready),
+    .yshift_11__ap_done(yshift_11__ap_done),
+    .yshift_11__ap_idle(yshift_11__ap_idle),
+    .yshift_12___n__q0(yshift_12___n__q0),
+    .yshift_12__ap_start(yshift_12__ap_start),
+    .yshift_12__ap_ready(yshift_12__ap_ready),
+    .yshift_12__ap_done(yshift_12__ap_done),
+    .yshift_12__ap_idle(yshift_12__ap_idle),
+    .yshift_13___n__q0(yshift_13___n__q0),
+    .yshift_13__ap_start(yshift_13__ap_start),
+    .yshift_13__ap_ready(yshift_13__ap_ready),
+    .yshift_13__ap_done(yshift_13__ap_done),
+    .yshift_13__ap_idle(yshift_13__ap_idle),
+    .yshift_14___n__q0(yshift_14___n__q0),
+    .yshift_14__ap_start(yshift_14__ap_start),
+    .yshift_14__ap_ready(yshift_14__ap_ready),
+    .yshift_14__ap_done(yshift_14__ap_done),
+    .yshift_14__ap_idle(yshift_14__ap_idle),
+    .yshift_15___n__q0(yshift_15___n__q0),
+    .yshift_15__ap_start(yshift_15__ap_start),
+    .yshift_15__ap_ready(yshift_15__ap_ready),
+    .yshift_15__ap_done(yshift_15__ap_done),
+    .yshift_15__ap_idle(yshift_15__ap_idle),
+    .yshift_16___n__q0(yshift_16___n__q0),
+    .yshift_16__ap_start(yshift_16__ap_start),
+    .yshift_16__ap_ready(yshift_16__ap_ready),
+    .yshift_16__ap_done(yshift_16__ap_done),
+    .yshift_16__ap_idle(yshift_16__ap_idle),
+    .yshift_17___n__q0(yshift_17___n__q0),
+    .yshift_17__ap_start(yshift_17__ap_start),
+    .yshift_17__ap_ready(yshift_17__ap_ready),
+    .yshift_17__ap_done(yshift_17__ap_done),
+    .yshift_17__ap_idle(yshift_17__ap_idle),
+    .yshift_18___n__q0(yshift_18___n__q0),
+    .yshift_18__ap_start(yshift_18__ap_start),
+    .yshift_18__ap_ready(yshift_18__ap_ready),
+    .yshift_18__ap_done(yshift_18__ap_done),
+    .yshift_18__ap_idle(yshift_18__ap_idle),
+    .yshift_19___n__q0(yshift_19___n__q0),
+    .yshift_19__ap_start(yshift_19__ap_start),
+    .yshift_19__ap_ready(yshift_19__ap_ready),
+    .yshift_19__ap_done(yshift_19__ap_done),
+    .yshift_19__ap_idle(yshift_19__ap_idle),
+    .yshift_20___n__q0(yshift_20___n__q0),
+    .yshift_20__ap_start(yshift_20__ap_start),
+    .yshift_20__ap_ready(yshift_20__ap_ready),
+    .yshift_20__ap_done(yshift_20__ap_done),
+    .yshift_20__ap_idle(yshift_20__ap_idle),
+    .yshift_21___n__q0(yshift_21___n__q0),
+    .yshift_21__ap_start(yshift_21__ap_start),
+    .yshift_21__ap_ready(yshift_21__ap_ready),
+    .yshift_21__ap_done(yshift_21__ap_done),
+    .yshift_21__ap_idle(yshift_21__ap_idle),
+    .yshift_22___n__q0(yshift_22___n__q0),
+    .yshift_22__ap_start(yshift_22__ap_start),
+    .yshift_22__ap_ready(yshift_22__ap_ready),
+    .yshift_22__ap_done(yshift_22__ap_done),
+    .yshift_22__ap_idle(yshift_22__ap_idle),
+    .yshift_23___n__q0(yshift_23___n__q0),
+    .yshift_23__ap_start(yshift_23__ap_start),
+    .yshift_23__ap_ready(yshift_23__ap_ready),
+    .yshift_23__ap_done(yshift_23__ap_done),
+    .yshift_23__ap_idle(yshift_23__ap_idle),
+    .yshift_24___n__q0(yshift_24___n__q0),
+    .yshift_24__ap_start(yshift_24__ap_start),
+    .yshift_24__ap_ready(yshift_24__ap_ready),
+    .yshift_24__ap_done(yshift_24__ap_done),
+    .yshift_24__ap_idle(yshift_24__ap_idle),
+    .yshift_25___n__q0(yshift_25___n__q0),
+    .yshift_25__ap_start(yshift_25__ap_start),
+    .yshift_25__ap_ready(yshift_25__ap_ready),
+    .yshift_25__ap_done(yshift_25__ap_done),
+    .yshift_25__ap_idle(yshift_25__ap_idle),
+    .yshift_26___n__q0(yshift_26___n__q0),
+    .yshift_26__ap_start(yshift_26__ap_start),
+    .yshift_26__ap_ready(yshift_26__ap_ready),
+    .yshift_26__ap_done(yshift_26__ap_done),
+    .yshift_26__ap_idle(yshift_26__ap_idle),
+    .yshift_27___n__q0(yshift_27___n__q0),
+    .yshift_27__ap_start(yshift_27__ap_start),
+    .yshift_27__ap_ready(yshift_27__ap_ready),
+    .yshift_27__ap_done(yshift_27__ap_done),
+    .yshift_27__ap_idle(yshift_27__ap_idle)
+  );
+
+  assign ap_rst_n_inv = (~ap_rst_n);
+
+endmodule
diff --git a/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/vadd_bw_control_s_axi.v b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/vadd_bw_control_s_axi.v
new file mode 100644
index 00000000..c1820499
--- /dev/null
+++ b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/vadd_bw_control_s_axi.v
@@ -0,0 +1,1427 @@
+// ==============================================================
+// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit)
+// Tool Version Limit: 2019.12
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1ns/1ps
+module vadd_bw_control_s_axi
+#(parameter
+    C_S_AXI_ADDR_WIDTH = 9,
+    C_S_AXI_DATA_WIDTH = 32
+)(
+    input  wire                          ACLK,
+    input  wire                          ARESET,
+    input  wire                          ACLK_EN,
+    input  wire [C_S_AXI_ADDR_WIDTH-1:0] AWADDR,
+    input  wire                          AWVALID,
+    output wire                          AWREADY,
+    input  wire [C_S_AXI_DATA_WIDTH-1:0] WDATA,
+    input  wire [C_S_AXI_DATA_WIDTH/8-1:0] WSTRB,
+    input  wire                          WVALID,
+    output wire                          WREADY,
+    output wire [1:0]                    BRESP,
+    output wire                          BVALID,
+    input  wire                          BREADY,
+    input  wire [C_S_AXI_ADDR_WIDTH-1:0] ARADDR,
+    input  wire                          ARVALID,
+    output wire                          ARREADY,
+    output wire [C_S_AXI_DATA_WIDTH-1:0] RDATA,
+    output wire [1:0]                    RRESP,
+    output wire                          RVALID,
+    input  wire                          RREADY,
+    output wire                          interrupt,
+    output wire [63:0]                   rmem0,
+    output wire [63:0]                   rmem1,
+    output wire [63:0]                   rmem2,
+    output wire [63:0]                   rmem3,
+    output wire [63:0]                   rmem4,
+    output wire [63:0]                   rmem5,
+    output wire [63:0]                   rmem6,
+    output wire [63:0]                   rmem7,
+    output wire [63:0]                   rmem8,
+    output wire [63:0]                   rmem9,
+    output wire [63:0]                   rmem10,
+    output wire [63:0]                   rmem11,
+    output wire [63:0]                   rmem12,
+    output wire [63:0]                   rmem13,
+    output wire [63:0]                   rmem14,
+    output wire [63:0]                   rmem15,
+    output wire [63:0]                   rmem16,
+    output wire [63:0]                   rmem17,
+    output wire [63:0]                   rmem18,
+    output wire [63:0]                   rmem19,
+    output wire [63:0]                   rmem20,
+    output wire [63:0]                   rmem21,
+    output wire [63:0]                   rmem22,
+    output wire [63:0]                   rmem23,
+    output wire [63:0]                   rmem24,
+    output wire [63:0]                   rmem25,
+    output wire [63:0]                   rmem26,
+    output wire [63:0]                   rmem27,
+    output wire [63:0]                   n,
+    output wire                          ap_start,
+    input  wire                          ap_done,
+    input  wire                          ap_ready,
+    input  wire                          ap_idle
+);
+//------------------------Address Info-------------------
+// 0x000 : Control signals
+//         bit 0  - ap_start (Read/Write/SC)
+//         bit 1  - ap_done (Read/COR)
+//         bit 2  - ap_idle (Read)
+//         bit 3  - ap_ready (Read/COR)
+//         bit 7  - auto_restart (Read/Write)
+//         bit 9  - interrupt (Read)
+//         others - reserved
+// 0x004 : Global Interrupt Enable Register
+//         bit 0  - Global Interrupt Enable (Read/Write)
+//         others - reserved
+// 0x008 : IP Interrupt Enable Register (Read/Write)
+//         bit 0 - enable ap_done interrupt (Read/Write)
+//         others - reserved
+// 0x00c : IP Interrupt Status Register (Read/TOW)
+//         bit 0 - ap_done (Read/TOW)
+//         others - reserved
+// 0x010 : Data signal of rmem0
+//         bit 31~0 - rmem0[31:0] (Read/Write)
+// 0x014 : Data signal of rmem0
+//         bit 31~0 - rmem0[63:32] (Read/Write)
+// 0x018 : reserved
+// 0x01c : Data signal of rmem1
+//         bit 31~0 - rmem1[31:0] (Read/Write)
+// 0x020 : Data signal of rmem1
+//         bit 31~0 - rmem1[63:32] (Read/Write)
+// 0x024 : reserved
+// 0x028 : Data signal of rmem2
+//         bit 31~0 - rmem2[31:0] (Read/Write)
+// 0x02c : Data signal of rmem2
+//         bit 31~0 - rmem2[63:32] (Read/Write)
+// 0x030 : reserved
+// 0x034 : Data signal of rmem3
+//         bit 31~0 - rmem3[31:0] (Read/Write)
+// 0x038 : Data signal of rmem3
+//         bit 31~0 - rmem3[63:32] (Read/Write)
+// 0x03c : reserved
+// 0x040 : Data signal of rmem4
+//         bit 31~0 - rmem4[31:0] (Read/Write)
+// 0x044 : Data signal of rmem4
+//         bit 31~0 - rmem4[63:32] (Read/Write)
+// 0x048 : reserved
+// 0x04c : Data signal of rmem5
+//         bit 31~0 - rmem5[31:0] (Read/Write)
+// 0x050 : Data signal of rmem5
+//         bit 31~0 - rmem5[63:32] (Read/Write)
+// 0x054 : reserved
+// 0x058 : Data signal of rmem6
+//         bit 31~0 - rmem6[31:0] (Read/Write)
+// 0x05c : Data signal of rmem6
+//         bit 31~0 - rmem6[63:32] (Read/Write)
+// 0x060 : reserved
+// 0x064 : Data signal of rmem7
+//         bit 31~0 - rmem7[31:0] (Read/Write)
+// 0x068 : Data signal of rmem7
+//         bit 31~0 - rmem7[63:32] (Read/Write)
+// 0x06c : reserved
+// 0x070 : Data signal of rmem8
+//         bit 31~0 - rmem8[31:0] (Read/Write)
+// 0x074 : Data signal of rmem8
+//         bit 31~0 - rmem8[63:32] (Read/Write)
+// 0x078 : reserved
+// 0x07c : Data signal of rmem9
+//         bit 31~0 - rmem9[31:0] (Read/Write)
+// 0x080 : Data signal of rmem9
+//         bit 31~0 - rmem9[63:32] (Read/Write)
+// 0x084 : reserved
+// 0x088 : Data signal of rmem10
+//         bit 31~0 - rmem10[31:0] (Read/Write)
+// 0x08c : Data signal of rmem10
+//         bit 31~0 - rmem10[63:32] (Read/Write)
+// 0x090 : reserved
+// 0x094 : Data signal of rmem11
+//         bit 31~0 - rmem11[31:0] (Read/Write)
+// 0x098 : Data signal of rmem11
+//         bit 31~0 - rmem11[63:32] (Read/Write)
+// 0x09c : reserved
+// 0x0a0 : Data signal of rmem12
+//         bit 31~0 - rmem12[31:0] (Read/Write)
+// 0x0a4 : Data signal of rmem12
+//         bit 31~0 - rmem12[63:32] (Read/Write)
+// 0x0a8 : reserved
+// 0x0ac : Data signal of rmem13
+//         bit 31~0 - rmem13[31:0] (Read/Write)
+// 0x0b0 : Data signal of rmem13
+//         bit 31~0 - rmem13[63:32] (Read/Write)
+// 0x0b4 : reserved
+// 0x0b8 : Data signal of rmem14
+//         bit 31~0 - rmem14[31:0] (Read/Write)
+// 0x0bc : Data signal of rmem14
+//         bit 31~0 - rmem14[63:32] (Read/Write)
+// 0x0c0 : reserved
+// 0x0c4 : Data signal of rmem15
+//         bit 31~0 - rmem15[31:0] (Read/Write)
+// 0x0c8 : Data signal of rmem15
+//         bit 31~0 - rmem15[63:32] (Read/Write)
+// 0x0cc : reserved
+// 0x0d0 : Data signal of rmem16
+//         bit 31~0 - rmem16[31:0] (Read/Write)
+// 0x0d4 : Data signal of rmem16
+//         bit 31~0 - rmem16[63:32] (Read/Write)
+// 0x0d8 : reserved
+// 0x0dc : Data signal of rmem17
+//         bit 31~0 - rmem17[31:0] (Read/Write)
+// 0x0e0 : Data signal of rmem17
+//         bit 31~0 - rmem17[63:32] (Read/Write)
+// 0x0e4 : reserved
+// 0x0e8 : Data signal of rmem18
+//         bit 31~0 - rmem18[31:0] (Read/Write)
+// 0x0ec : Data signal of rmem18
+//         bit 31~0 - rmem18[63:32] (Read/Write)
+// 0x0f0 : reserved
+// 0x0f4 : Data signal of rmem19
+//         bit 31~0 - rmem19[31:0] (Read/Write)
+// 0x0f8 : Data signal of rmem19
+//         bit 31~0 - rmem19[63:32] (Read/Write)
+// 0x0fc : reserved
+// 0x100 : Data signal of rmem20
+//         bit 31~0 - rmem20[31:0] (Read/Write)
+// 0x104 : Data signal of rmem20
+//         bit 31~0 - rmem20[63:32] (Read/Write)
+// 0x108 : reserved
+// 0x10c : Data signal of rmem21
+//         bit 31~0 - rmem21[31:0] (Read/Write)
+// 0x110 : Data signal of rmem21
+//         bit 31~0 - rmem21[63:32] (Read/Write)
+// 0x114 : reserved
+// 0x118 : Data signal of rmem22
+//         bit 31~0 - rmem22[31:0] (Read/Write)
+// 0x11c : Data signal of rmem22
+//         bit 31~0 - rmem22[63:32] (Read/Write)
+// 0x120 : reserved
+// 0x124 : Data signal of rmem23
+//         bit 31~0 - rmem23[31:0] (Read/Write)
+// 0x128 : Data signal of rmem23
+//         bit 31~0 - rmem23[63:32] (Read/Write)
+// 0x12c : reserved
+// 0x130 : Data signal of rmem24
+//         bit 31~0 - rmem24[31:0] (Read/Write)
+// 0x134 : Data signal of rmem24
+//         bit 31~0 - rmem24[63:32] (Read/Write)
+// 0x138 : reserved
+// 0x13c : Data signal of rmem25
+//         bit 31~0 - rmem25[31:0] (Read/Write)
+// 0x140 : Data signal of rmem25
+//         bit 31~0 - rmem25[63:32] (Read/Write)
+// 0x144 : reserved
+// 0x148 : Data signal of rmem26
+//         bit 31~0 - rmem26[31:0] (Read/Write)
+// 0x14c : Data signal of rmem26
+//         bit 31~0 - rmem26[63:32] (Read/Write)
+// 0x150 : reserved
+// 0x154 : Data signal of rmem27
+//         bit 31~0 - rmem27[31:0] (Read/Write)
+// 0x158 : Data signal of rmem27
+//         bit 31~0 - rmem27[63:32] (Read/Write)
+// 0x15c : reserved
+// 0x160 : Data signal of n
+//         bit 31~0 - n[31:0] (Read/Write)
+// 0x164 : Data signal of n
+//         bit 31~0 - n[63:32] (Read/Write)
+// 0x168 : reserved
+// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
+
+//------------------------Parameter----------------------
+localparam
+    ADDR_AP_CTRL       = 9'h000,
+    ADDR_GIE           = 9'h004,
+    ADDR_IER           = 9'h008,
+    ADDR_ISR           = 9'h00c,
+    ADDR_RMEM0_DATA_0  = 9'h010,
+    ADDR_RMEM0_DATA_1  = 9'h014,
+    ADDR_RMEM0_CTRL    = 9'h018,
+    ADDR_RMEM1_DATA_0  = 9'h01c,
+    ADDR_RMEM1_DATA_1  = 9'h020,
+    ADDR_RMEM1_CTRL    = 9'h024,
+    ADDR_RMEM2_DATA_0  = 9'h028,
+    ADDR_RMEM2_DATA_1  = 9'h02c,
+    ADDR_RMEM2_CTRL    = 9'h030,
+    ADDR_RMEM3_DATA_0  = 9'h034,
+    ADDR_RMEM3_DATA_1  = 9'h038,
+    ADDR_RMEM3_CTRL    = 9'h03c,
+    ADDR_RMEM4_DATA_0  = 9'h040,
+    ADDR_RMEM4_DATA_1  = 9'h044,
+    ADDR_RMEM4_CTRL    = 9'h048,
+    ADDR_RMEM5_DATA_0  = 9'h04c,
+    ADDR_RMEM5_DATA_1  = 9'h050,
+    ADDR_RMEM5_CTRL    = 9'h054,
+    ADDR_RMEM6_DATA_0  = 9'h058,
+    ADDR_RMEM6_DATA_1  = 9'h05c,
+    ADDR_RMEM6_CTRL    = 9'h060,
+    ADDR_RMEM7_DATA_0  = 9'h064,
+    ADDR_RMEM7_DATA_1  = 9'h068,
+    ADDR_RMEM7_CTRL    = 9'h06c,
+    ADDR_RMEM8_DATA_0  = 9'h070,
+    ADDR_RMEM8_DATA_1  = 9'h074,
+    ADDR_RMEM8_CTRL    = 9'h078,
+    ADDR_RMEM9_DATA_0  = 9'h07c,
+    ADDR_RMEM9_DATA_1  = 9'h080,
+    ADDR_RMEM9_CTRL    = 9'h084,
+    ADDR_RMEM10_DATA_0 = 9'h088,
+    ADDR_RMEM10_DATA_1 = 9'h08c,
+    ADDR_RMEM10_CTRL   = 9'h090,
+    ADDR_RMEM11_DATA_0 = 9'h094,
+    ADDR_RMEM11_DATA_1 = 9'h098,
+    ADDR_RMEM11_CTRL   = 9'h09c,
+    ADDR_RMEM12_DATA_0 = 9'h0a0,
+    ADDR_RMEM12_DATA_1 = 9'h0a4,
+    ADDR_RMEM12_CTRL   = 9'h0a8,
+    ADDR_RMEM13_DATA_0 = 9'h0ac,
+    ADDR_RMEM13_DATA_1 = 9'h0b0,
+    ADDR_RMEM13_CTRL   = 9'h0b4,
+    ADDR_RMEM14_DATA_0 = 9'h0b8,
+    ADDR_RMEM14_DATA_1 = 9'h0bc,
+    ADDR_RMEM14_CTRL   = 9'h0c0,
+    ADDR_RMEM15_DATA_0 = 9'h0c4,
+    ADDR_RMEM15_DATA_1 = 9'h0c8,
+    ADDR_RMEM15_CTRL   = 9'h0cc,
+    ADDR_RMEM16_DATA_0 = 9'h0d0,
+    ADDR_RMEM16_DATA_1 = 9'h0d4,
+    ADDR_RMEM16_CTRL   = 9'h0d8,
+    ADDR_RMEM17_DATA_0 = 9'h0dc,
+    ADDR_RMEM17_DATA_1 = 9'h0e0,
+    ADDR_RMEM17_CTRL   = 9'h0e4,
+    ADDR_RMEM18_DATA_0 = 9'h0e8,
+    ADDR_RMEM18_DATA_1 = 9'h0ec,
+    ADDR_RMEM18_CTRL   = 9'h0f0,
+    ADDR_RMEM19_DATA_0 = 9'h0f4,
+    ADDR_RMEM19_DATA_1 = 9'h0f8,
+    ADDR_RMEM19_CTRL   = 9'h0fc,
+    ADDR_RMEM20_DATA_0 = 9'h100,
+    ADDR_RMEM20_DATA_1 = 9'h104,
+    ADDR_RMEM20_CTRL   = 9'h108,
+    ADDR_RMEM21_DATA_0 = 9'h10c,
+    ADDR_RMEM21_DATA_1 = 9'h110,
+    ADDR_RMEM21_CTRL   = 9'h114,
+    ADDR_RMEM22_DATA_0 = 9'h118,
+    ADDR_RMEM22_DATA_1 = 9'h11c,
+    ADDR_RMEM22_CTRL   = 9'h120,
+    ADDR_RMEM23_DATA_0 = 9'h124,
+    ADDR_RMEM23_DATA_1 = 9'h128,
+    ADDR_RMEM23_CTRL   = 9'h12c,
+    ADDR_RMEM24_DATA_0 = 9'h130,
+    ADDR_RMEM24_DATA_1 = 9'h134,
+    ADDR_RMEM24_CTRL   = 9'h138,
+    ADDR_RMEM25_DATA_0 = 9'h13c,
+    ADDR_RMEM25_DATA_1 = 9'h140,
+    ADDR_RMEM25_CTRL   = 9'h144,
+    ADDR_RMEM26_DATA_0 = 9'h148,
+    ADDR_RMEM26_DATA_1 = 9'h14c,
+    ADDR_RMEM26_CTRL   = 9'h150,
+    ADDR_RMEM27_DATA_0 = 9'h154,
+    ADDR_RMEM27_DATA_1 = 9'h158,
+    ADDR_RMEM27_CTRL   = 9'h15c,
+    ADDR_N_DATA_0      = 9'h160,
+    ADDR_N_DATA_1      = 9'h164,
+    ADDR_N_CTRL        = 9'h168,
+    WRIDLE             = 2'd0,
+    WRDATA             = 2'd1,
+    WRRESP             = 2'd2,
+    WRRESET            = 2'd3,
+    RDIDLE             = 2'd0,
+    RDDATA             = 2'd1,
+    RDRESET            = 2'd2,
+    ADDR_BITS                = 9;
+
+//------------------------Local signal-------------------
+    reg  [1:0]                    wstate = WRRESET;
+    reg  [1:0]                    wnext;
+    reg  [ADDR_BITS-1:0]          waddr;
+    wire [C_S_AXI_DATA_WIDTH-1:0] wmask;
+    wire                          aw_hs;
+    wire                          w_hs;
+    reg  [1:0]                    rstate = RDRESET;
+    reg  [1:0]                    rnext;
+    reg  [C_S_AXI_DATA_WIDTH-1:0] rdata;
+    wire                          ar_hs;
+    wire [ADDR_BITS-1:0]          raddr;
+    // internal registers
+    reg                           int_ap_idle;
+    reg                           int_ap_ready = 1'b0;
+    wire                          task_ap_ready;
+    reg                           int_ap_done = 1'b0;
+    wire                          task_ap_done;
+    reg                           int_task_ap_done = 1'b0;
+    reg                           int_ap_start = 1'b0;
+    reg                           int_interrupt = 1'b0;
+    reg                           int_auto_restart = 1'b0;
+    reg                           auto_restart_status = 1'b0;
+    wire                          auto_restart_done;
+    reg                           int_gie = 1'b0;
+    reg                           int_ier = 1'b0;
+    reg                           int_isr = 1'b0;
+    reg  [63:0]                   int_rmem0 = 'b0;
+    reg  [63:0]                   int_rmem1 = 'b0;
+    reg  [63:0]                   int_rmem2 = 'b0;
+    reg  [63:0]                   int_rmem3 = 'b0;
+    reg  [63:0]                   int_rmem4 = 'b0;
+    reg  [63:0]                   int_rmem5 = 'b0;
+    reg  [63:0]                   int_rmem6 = 'b0;
+    reg  [63:0]                   int_rmem7 = 'b0;
+    reg  [63:0]                   int_rmem8 = 'b0;
+    reg  [63:0]                   int_rmem9 = 'b0;
+    reg  [63:0]                   int_rmem10 = 'b0;
+    reg  [63:0]                   int_rmem11 = 'b0;
+    reg  [63:0]                   int_rmem12 = 'b0;
+    reg  [63:0]                   int_rmem13 = 'b0;
+    reg  [63:0]                   int_rmem14 = 'b0;
+    reg  [63:0]                   int_rmem15 = 'b0;
+    reg  [63:0]                   int_rmem16 = 'b0;
+    reg  [63:0]                   int_rmem17 = 'b0;
+    reg  [63:0]                   int_rmem18 = 'b0;
+    reg  [63:0]                   int_rmem19 = 'b0;
+    reg  [63:0]                   int_rmem20 = 'b0;
+    reg  [63:0]                   int_rmem21 = 'b0;
+    reg  [63:0]                   int_rmem22 = 'b0;
+    reg  [63:0]                   int_rmem23 = 'b0;
+    reg  [63:0]                   int_rmem24 = 'b0;
+    reg  [63:0]                   int_rmem25 = 'b0;
+    reg  [63:0]                   int_rmem26 = 'b0;
+    reg  [63:0]                   int_rmem27 = 'b0;
+    reg  [63:0]                   int_n = 'b0;
+
+//------------------------Instantiation------------------
+
+
+//------------------------AXI write fsm------------------
+assign AWREADY = (wstate == WRIDLE);
+assign WREADY  = (wstate == WRDATA);
+assign BRESP   = 2'b00;  // OKAY
+assign BVALID  = (wstate == WRRESP);
+assign wmask   = { {8{WSTRB[3]}}, {8{WSTRB[2]}}, {8{WSTRB[1]}}, {8{WSTRB[0]}} };
+assign aw_hs   = AWVALID & AWREADY;
+assign w_hs    = WVALID & WREADY;
+
+// wstate
+always @(posedge ACLK) begin
+    if (ARESET)
+        wstate <= WRRESET;
+    else if (ACLK_EN)
+        wstate <= wnext;
+end
+
+// wnext
+always @(*) begin
+    case (wstate)
+        WRIDLE:
+            if (AWVALID)
+                wnext = WRDATA;
+            else
+                wnext = WRIDLE;
+        WRDATA:
+            if (WVALID)
+                wnext = WRRESP;
+            else
+                wnext = WRDATA;
+        WRRESP:
+            if (BREADY)
+                wnext = WRIDLE;
+            else
+                wnext = WRRESP;
+        default:
+            wnext = WRIDLE;
+    endcase
+end
+
+// waddr
+always @(posedge ACLK) begin
+    if (ACLK_EN) begin
+        if (aw_hs)
+            waddr <= AWADDR[ADDR_BITS-1:0];
+    end
+end
+
+//------------------------AXI read fsm-------------------
+assign ARREADY = (rstate == RDIDLE);
+assign RDATA   = rdata;
+assign RRESP   = 2'b00;  // OKAY
+assign RVALID  = (rstate == RDDATA);
+assign ar_hs   = ARVALID & ARREADY;
+assign raddr   = ARADDR[ADDR_BITS-1:0];
+
+// rstate
+always @(posedge ACLK) begin
+    if (ARESET)
+        rstate <= RDRESET;
+    else if (ACLK_EN)
+        rstate <= rnext;
+end
+
+// rnext
+always @(*) begin
+    case (rstate)
+        RDIDLE:
+            if (ARVALID)
+                rnext = RDDATA;
+            else
+                rnext = RDIDLE;
+        RDDATA:
+            if (RREADY & RVALID)
+                rnext = RDIDLE;
+            else
+                rnext = RDDATA;
+        default:
+            rnext = RDIDLE;
+    endcase
+end
+
+// rdata
+always @(posedge ACLK) begin
+    if (ACLK_EN) begin
+        if (ar_hs) begin
+            rdata <= 'b0;
+            case (raddr)
+                ADDR_AP_CTRL: begin
+                    rdata[0] <= int_ap_start;
+                    rdata[1] <= int_task_ap_done;
+                    rdata[2] <= int_ap_idle;
+                    rdata[3] <= int_ap_ready;
+                    rdata[7] <= int_auto_restart;
+                    rdata[9] <= int_interrupt;
+                end
+                ADDR_GIE: begin
+                    rdata <= int_gie;
+                end
+                ADDR_IER: begin
+                    rdata <= int_ier;
+                end
+                ADDR_ISR: begin
+                    rdata <= int_isr;
+                end
+                ADDR_RMEM0_DATA_0: begin
+                    rdata <= int_rmem0[31:0];
+                end
+                ADDR_RMEM0_DATA_1: begin
+                    rdata <= int_rmem0[63:32];
+                end
+                ADDR_RMEM1_DATA_0: begin
+                    rdata <= int_rmem1[31:0];
+                end
+                ADDR_RMEM1_DATA_1: begin
+                    rdata <= int_rmem1[63:32];
+                end
+                ADDR_RMEM2_DATA_0: begin
+                    rdata <= int_rmem2[31:0];
+                end
+                ADDR_RMEM2_DATA_1: begin
+                    rdata <= int_rmem2[63:32];
+                end
+                ADDR_RMEM3_DATA_0: begin
+                    rdata <= int_rmem3[31:0];
+                end
+                ADDR_RMEM3_DATA_1: begin
+                    rdata <= int_rmem3[63:32];
+                end
+                ADDR_RMEM4_DATA_0: begin
+                    rdata <= int_rmem4[31:0];
+                end
+                ADDR_RMEM4_DATA_1: begin
+                    rdata <= int_rmem4[63:32];
+                end
+                ADDR_RMEM5_DATA_0: begin
+                    rdata <= int_rmem5[31:0];
+                end
+                ADDR_RMEM5_DATA_1: begin
+                    rdata <= int_rmem5[63:32];
+                end
+                ADDR_RMEM6_DATA_0: begin
+                    rdata <= int_rmem6[31:0];
+                end
+                ADDR_RMEM6_DATA_1: begin
+                    rdata <= int_rmem6[63:32];
+                end
+                ADDR_RMEM7_DATA_0: begin
+                    rdata <= int_rmem7[31:0];
+                end
+                ADDR_RMEM7_DATA_1: begin
+                    rdata <= int_rmem7[63:32];
+                end
+                ADDR_RMEM8_DATA_0: begin
+                    rdata <= int_rmem8[31:0];
+                end
+                ADDR_RMEM8_DATA_1: begin
+                    rdata <= int_rmem8[63:32];
+                end
+                ADDR_RMEM9_DATA_0: begin
+                    rdata <= int_rmem9[31:0];
+                end
+                ADDR_RMEM9_DATA_1: begin
+                    rdata <= int_rmem9[63:32];
+                end
+                ADDR_RMEM10_DATA_0: begin
+                    rdata <= int_rmem10[31:0];
+                end
+                ADDR_RMEM10_DATA_1: begin
+                    rdata <= int_rmem10[63:32];
+                end
+                ADDR_RMEM11_DATA_0: begin
+                    rdata <= int_rmem11[31:0];
+                end
+                ADDR_RMEM11_DATA_1: begin
+                    rdata <= int_rmem11[63:32];
+                end
+                ADDR_RMEM12_DATA_0: begin
+                    rdata <= int_rmem12[31:0];
+                end
+                ADDR_RMEM12_DATA_1: begin
+                    rdata <= int_rmem12[63:32];
+                end
+                ADDR_RMEM13_DATA_0: begin
+                    rdata <= int_rmem13[31:0];
+                end
+                ADDR_RMEM13_DATA_1: begin
+                    rdata <= int_rmem13[63:32];
+                end
+                ADDR_RMEM14_DATA_0: begin
+                    rdata <= int_rmem14[31:0];
+                end
+                ADDR_RMEM14_DATA_1: begin
+                    rdata <= int_rmem14[63:32];
+                end
+                ADDR_RMEM15_DATA_0: begin
+                    rdata <= int_rmem15[31:0];
+                end
+                ADDR_RMEM15_DATA_1: begin
+                    rdata <= int_rmem15[63:32];
+                end
+                ADDR_RMEM16_DATA_0: begin
+                    rdata <= int_rmem16[31:0];
+                end
+                ADDR_RMEM16_DATA_1: begin
+                    rdata <= int_rmem16[63:32];
+                end
+                ADDR_RMEM17_DATA_0: begin
+                    rdata <= int_rmem17[31:0];
+                end
+                ADDR_RMEM17_DATA_1: begin
+                    rdata <= int_rmem17[63:32];
+                end
+                ADDR_RMEM18_DATA_0: begin
+                    rdata <= int_rmem18[31:0];
+                end
+                ADDR_RMEM18_DATA_1: begin
+                    rdata <= int_rmem18[63:32];
+                end
+                ADDR_RMEM19_DATA_0: begin
+                    rdata <= int_rmem19[31:0];
+                end
+                ADDR_RMEM19_DATA_1: begin
+                    rdata <= int_rmem19[63:32];
+                end
+                ADDR_RMEM20_DATA_0: begin
+                    rdata <= int_rmem20[31:0];
+                end
+                ADDR_RMEM20_DATA_1: begin
+                    rdata <= int_rmem20[63:32];
+                end
+                ADDR_RMEM21_DATA_0: begin
+                    rdata <= int_rmem21[31:0];
+                end
+                ADDR_RMEM21_DATA_1: begin
+                    rdata <= int_rmem21[63:32];
+                end
+                ADDR_RMEM22_DATA_0: begin
+                    rdata <= int_rmem22[31:0];
+                end
+                ADDR_RMEM22_DATA_1: begin
+                    rdata <= int_rmem22[63:32];
+                end
+                ADDR_RMEM23_DATA_0: begin
+                    rdata <= int_rmem23[31:0];
+                end
+                ADDR_RMEM23_DATA_1: begin
+                    rdata <= int_rmem23[63:32];
+                end
+                ADDR_RMEM24_DATA_0: begin
+                    rdata <= int_rmem24[31:0];
+                end
+                ADDR_RMEM24_DATA_1: begin
+                    rdata <= int_rmem24[63:32];
+                end
+                ADDR_RMEM25_DATA_0: begin
+                    rdata <= int_rmem25[31:0];
+                end
+                ADDR_RMEM25_DATA_1: begin
+                    rdata <= int_rmem25[63:32];
+                end
+                ADDR_RMEM26_DATA_0: begin
+                    rdata <= int_rmem26[31:0];
+                end
+                ADDR_RMEM26_DATA_1: begin
+                    rdata <= int_rmem26[63:32];
+                end
+                ADDR_RMEM27_DATA_0: begin
+                    rdata <= int_rmem27[31:0];
+                end
+                ADDR_RMEM27_DATA_1: begin
+                    rdata <= int_rmem27[63:32];
+                end
+                ADDR_N_DATA_0: begin
+                    rdata <= int_n[31:0];
+                end
+                ADDR_N_DATA_1: begin
+                    rdata <= int_n[63:32];
+                end
+            endcase
+        end
+    end
+end
+
+
+//------------------------Register logic-----------------
+assign interrupt         = int_interrupt;
+assign ap_start          = int_ap_start;
+assign task_ap_done      = (ap_done && !auto_restart_status) || auto_restart_done;
+assign task_ap_ready     = ap_ready && !int_auto_restart;
+assign auto_restart_done = auto_restart_status && (ap_idle && !int_ap_idle);
+assign rmem0             = int_rmem0;
+assign rmem1             = int_rmem1;
+assign rmem2             = int_rmem2;
+assign rmem3             = int_rmem3;
+assign rmem4             = int_rmem4;
+assign rmem5             = int_rmem5;
+assign rmem6             = int_rmem6;
+assign rmem7             = int_rmem7;
+assign rmem8             = int_rmem8;
+assign rmem9             = int_rmem9;
+assign rmem10            = int_rmem10;
+assign rmem11            = int_rmem11;
+assign rmem12            = int_rmem12;
+assign rmem13            = int_rmem13;
+assign rmem14            = int_rmem14;
+assign rmem15            = int_rmem15;
+assign rmem16            = int_rmem16;
+assign rmem17            = int_rmem17;
+assign rmem18            = int_rmem18;
+assign rmem19            = int_rmem19;
+assign rmem20            = int_rmem20;
+assign rmem21            = int_rmem21;
+assign rmem22            = int_rmem22;
+assign rmem23            = int_rmem23;
+assign rmem24            = int_rmem24;
+assign rmem25            = int_rmem25;
+assign rmem26            = int_rmem26;
+assign rmem27            = int_rmem27;
+assign n                 = int_n;
+// int_interrupt
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_interrupt <= 1'b0;
+    else if (ACLK_EN) begin
+        if (int_gie && (|int_isr))
+            int_interrupt <= 1'b1;
+        else
+            int_interrupt <= 1'b0;
+    end
+end
+
+// int_ap_start
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ap_start <= 1'b0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0] && WDATA[0])
+            int_ap_start <= 1'b1;
+        else if (ap_done & int_auto_restart)
+            int_ap_start <= 1'b1; // auto restart
+        else
+            int_ap_start <= 1'b0; // self clear
+    end
+end
+
+// int_ap_done
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ap_done <= 1'b0;
+    else if (ACLK_EN) begin
+            int_ap_done <= ap_done;
+    end
+end
+
+// int_task_ap_done
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_task_ap_done <= 1'b0;
+    else if (ACLK_EN) begin
+        if (task_ap_done)
+            int_task_ap_done <= 1'b1;
+        else if (ar_hs && raddr == ADDR_AP_CTRL)
+            int_task_ap_done <= 1'b0; // clear on read
+    end
+end
+
+// int_ap_idle
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ap_idle <= 1'b0;
+    else if (ACLK_EN) begin
+            int_ap_idle <= ap_idle;
+    end
+end
+
+// int_ap_ready
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ap_ready <= 1'b0;
+    else if (ACLK_EN) begin
+        if (task_ap_ready)
+            int_ap_ready <= 1'b1;
+        else if (ar_hs && raddr == ADDR_AP_CTRL)
+            int_ap_ready <= 1'b0;
+    end
+end
+
+// int_auto_restart
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_auto_restart <= 1'b0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0])
+            int_auto_restart <=  WDATA[7];
+    end
+end
+
+// auto_restart_status
+always @(posedge ACLK) begin
+    if (ARESET)
+        auto_restart_status <= 1'b0;
+    else if (ACLK_EN) begin
+        if (int_auto_restart)
+            auto_restart_status <= 1'b1;
+        else if (ap_idle)
+            auto_restart_status <= 1'b0;
+    end
+end
+
+// int_gie
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_gie <= 1'b0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_GIE && WSTRB[0])
+            int_gie <= WDATA[0];
+    end
+end
+
+// int_ier
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ier <= 1'b0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_IER && WSTRB[0])
+            int_ier <= WDATA[0];
+    end
+end
+
+// int_isr
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_isr <= 1'b0;
+    else if (ACLK_EN) begin
+        if (int_ier & ap_done)
+            int_isr <= 1'b1;
+        else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
+            int_isr <= int_isr ^ WDATA[0]; // toggle on write
+    end
+end
+
+// int_rmem0[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem0[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM0_DATA_0)
+            int_rmem0[31:0] <= (WDATA[31:0] & wmask) | (int_rmem0[31:0] & ~wmask);
+    end
+end
+
+// int_rmem0[63:32]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem0[63:32] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM0_DATA_1)
+            int_rmem0[63:32] <= (WDATA[31:0] & wmask) | (int_rmem0[63:32] & ~wmask);
+    end
+end
+
+// int_rmem1[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem1[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM1_DATA_0)
+            int_rmem1[31:0] <= (WDATA[31:0] & wmask) | (int_rmem1[31:0] & ~wmask);
+    end
+end
+
+// int_rmem1[63:32]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem1[63:32] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM1_DATA_1)
+            int_rmem1[63:32] <= (WDATA[31:0] & wmask) | (int_rmem1[63:32] & ~wmask);
+    end
+end
+
+// int_rmem2[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem2[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM2_DATA_0)
+            int_rmem2[31:0] <= (WDATA[31:0] & wmask) | (int_rmem2[31:0] & ~wmask);
+    end
+end
+
+// int_rmem2[63:32]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem2[63:32] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM2_DATA_1)
+            int_rmem2[63:32] <= (WDATA[31:0] & wmask) | (int_rmem2[63:32] & ~wmask);
+    end
+end
+
+// int_rmem3[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem3[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM3_DATA_0)
+            int_rmem3[31:0] <= (WDATA[31:0] & wmask) | (int_rmem3[31:0] & ~wmask);
+    end
+end
+
+// int_rmem3[63:32]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem3[63:32] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM3_DATA_1)
+            int_rmem3[63:32] <= (WDATA[31:0] & wmask) | (int_rmem3[63:32] & ~wmask);
+    end
+end
+
+// int_rmem4[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem4[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM4_DATA_0)
+            int_rmem4[31:0] <= (WDATA[31:0] & wmask) | (int_rmem4[31:0] & ~wmask);
+    end
+end
+
+// int_rmem4[63:32]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem4[63:32] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM4_DATA_1)
+            int_rmem4[63:32] <= (WDATA[31:0] & wmask) | (int_rmem4[63:32] & ~wmask);
+    end
+end
+
+// int_rmem5[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem5[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM5_DATA_0)
+            int_rmem5[31:0] <= (WDATA[31:0] & wmask) | (int_rmem5[31:0] & ~wmask);
+    end
+end
+
+// int_rmem5[63:32]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem5[63:32] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM5_DATA_1)
+            int_rmem5[63:32] <= (WDATA[31:0] & wmask) | (int_rmem5[63:32] & ~wmask);
+    end
+end
+
+// int_rmem6[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem6[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM6_DATA_0)
+            int_rmem6[31:0] <= (WDATA[31:0] & wmask) | (int_rmem6[31:0] & ~wmask);
+    end
+end
+
+// int_rmem6[63:32]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem6[63:32] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM6_DATA_1)
+            int_rmem6[63:32] <= (WDATA[31:0] & wmask) | (int_rmem6[63:32] & ~wmask);
+    end
+end
+
+// int_rmem7[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem7[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM7_DATA_0)
+            int_rmem7[31:0] <= (WDATA[31:0] & wmask) | (int_rmem7[31:0] & ~wmask);
+    end
+end
+
+// int_rmem7[63:32]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem7[63:32] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM7_DATA_1)
+            int_rmem7[63:32] <= (WDATA[31:0] & wmask) | (int_rmem7[63:32] & ~wmask);
+    end
+end
+
+// int_rmem8[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem8[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM8_DATA_0)
+            int_rmem8[31:0] <= (WDATA[31:0] & wmask) | (int_rmem8[31:0] & ~wmask);
+    end
+end
+
+// int_rmem8[63:32]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem8[63:32] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM8_DATA_1)
+            int_rmem8[63:32] <= (WDATA[31:0] & wmask) | (int_rmem8[63:32] & ~wmask);
+    end
+end
+
+// int_rmem9[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem9[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM9_DATA_0)
+            int_rmem9[31:0] <= (WDATA[31:0] & wmask) | (int_rmem9[31:0] & ~wmask);
+    end
+end
+
+// int_rmem9[63:32]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem9[63:32] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM9_DATA_1)
+            int_rmem9[63:32] <= (WDATA[31:0] & wmask) | (int_rmem9[63:32] & ~wmask);
+    end
+end
+
+// int_rmem10[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem10[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM10_DATA_0)
+            int_rmem10[31:0] <= (WDATA[31:0] & wmask) | (int_rmem10[31:0] & ~wmask);
+    end
+end
+
+// int_rmem10[63:32]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem10[63:32] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM10_DATA_1)
+            int_rmem10[63:32] <= (WDATA[31:0] & wmask) | (int_rmem10[63:32] & ~wmask);
+    end
+end
+
+// int_rmem11[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem11[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM11_DATA_0)
+            int_rmem11[31:0] <= (WDATA[31:0] & wmask) | (int_rmem11[31:0] & ~wmask);
+    end
+end
+
+// int_rmem11[63:32]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem11[63:32] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM11_DATA_1)
+            int_rmem11[63:32] <= (WDATA[31:0] & wmask) | (int_rmem11[63:32] & ~wmask);
+    end
+end
+
+// int_rmem12[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem12[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM12_DATA_0)
+            int_rmem12[31:0] <= (WDATA[31:0] & wmask) | (int_rmem12[31:0] & ~wmask);
+    end
+end
+
+// int_rmem12[63:32]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem12[63:32] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM12_DATA_1)
+            int_rmem12[63:32] <= (WDATA[31:0] & wmask) | (int_rmem12[63:32] & ~wmask);
+    end
+end
+
+// int_rmem13[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem13[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM13_DATA_0)
+            int_rmem13[31:0] <= (WDATA[31:0] & wmask) | (int_rmem13[31:0] & ~wmask);
+    end
+end
+
+// int_rmem13[63:32]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem13[63:32] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM13_DATA_1)
+            int_rmem13[63:32] <= (WDATA[31:0] & wmask) | (int_rmem13[63:32] & ~wmask);
+    end
+end
+
+// int_rmem14[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem14[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM14_DATA_0)
+            int_rmem14[31:0] <= (WDATA[31:0] & wmask) | (int_rmem14[31:0] & ~wmask);
+    end
+end
+
+// int_rmem14[63:32]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem14[63:32] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM14_DATA_1)
+            int_rmem14[63:32] <= (WDATA[31:0] & wmask) | (int_rmem14[63:32] & ~wmask);
+    end
+end
+
+// int_rmem15[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem15[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM15_DATA_0)
+            int_rmem15[31:0] <= (WDATA[31:0] & wmask) | (int_rmem15[31:0] & ~wmask);
+    end
+end
+
+// int_rmem15[63:32]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem15[63:32] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM15_DATA_1)
+            int_rmem15[63:32] <= (WDATA[31:0] & wmask) | (int_rmem15[63:32] & ~wmask);
+    end
+end
+
+// int_rmem16[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem16[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM16_DATA_0)
+            int_rmem16[31:0] <= (WDATA[31:0] & wmask) | (int_rmem16[31:0] & ~wmask);
+    end
+end
+
+// int_rmem16[63:32]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem16[63:32] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM16_DATA_1)
+            int_rmem16[63:32] <= (WDATA[31:0] & wmask) | (int_rmem16[63:32] & ~wmask);
+    end
+end
+
+// int_rmem17[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem17[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM17_DATA_0)
+            int_rmem17[31:0] <= (WDATA[31:0] & wmask) | (int_rmem17[31:0] & ~wmask);
+    end
+end
+
+// int_rmem17[63:32]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem17[63:32] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM17_DATA_1)
+            int_rmem17[63:32] <= (WDATA[31:0] & wmask) | (int_rmem17[63:32] & ~wmask);
+    end
+end
+
+// int_rmem18[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem18[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM18_DATA_0)
+            int_rmem18[31:0] <= (WDATA[31:0] & wmask) | (int_rmem18[31:0] & ~wmask);
+    end
+end
+
+// int_rmem18[63:32]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem18[63:32] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM18_DATA_1)
+            int_rmem18[63:32] <= (WDATA[31:0] & wmask) | (int_rmem18[63:32] & ~wmask);
+    end
+end
+
+// int_rmem19[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem19[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM19_DATA_0)
+            int_rmem19[31:0] <= (WDATA[31:0] & wmask) | (int_rmem19[31:0] & ~wmask);
+    end
+end
+
+// int_rmem19[63:32]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem19[63:32] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM19_DATA_1)
+            int_rmem19[63:32] <= (WDATA[31:0] & wmask) | (int_rmem19[63:32] & ~wmask);
+    end
+end
+
+// int_rmem20[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem20[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM20_DATA_0)
+            int_rmem20[31:0] <= (WDATA[31:0] & wmask) | (int_rmem20[31:0] & ~wmask);
+    end
+end
+
+// int_rmem20[63:32]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem20[63:32] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM20_DATA_1)
+            int_rmem20[63:32] <= (WDATA[31:0] & wmask) | (int_rmem20[63:32] & ~wmask);
+    end
+end
+
+// int_rmem21[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem21[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM21_DATA_0)
+            int_rmem21[31:0] <= (WDATA[31:0] & wmask) | (int_rmem21[31:0] & ~wmask);
+    end
+end
+
+// int_rmem21[63:32]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem21[63:32] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM21_DATA_1)
+            int_rmem21[63:32] <= (WDATA[31:0] & wmask) | (int_rmem21[63:32] & ~wmask);
+    end
+end
+
+// int_rmem22[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem22[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM22_DATA_0)
+            int_rmem22[31:0] <= (WDATA[31:0] & wmask) | (int_rmem22[31:0] & ~wmask);
+    end
+end
+
+// int_rmem22[63:32]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem22[63:32] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM22_DATA_1)
+            int_rmem22[63:32] <= (WDATA[31:0] & wmask) | (int_rmem22[63:32] & ~wmask);
+    end
+end
+
+// int_rmem23[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem23[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM23_DATA_0)
+            int_rmem23[31:0] <= (WDATA[31:0] & wmask) | (int_rmem23[31:0] & ~wmask);
+    end
+end
+
+// int_rmem23[63:32]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem23[63:32] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM23_DATA_1)
+            int_rmem23[63:32] <= (WDATA[31:0] & wmask) | (int_rmem23[63:32] & ~wmask);
+    end
+end
+
+// int_rmem24[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem24[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM24_DATA_0)
+            int_rmem24[31:0] <= (WDATA[31:0] & wmask) | (int_rmem24[31:0] & ~wmask);
+    end
+end
+
+// int_rmem24[63:32]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem24[63:32] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM24_DATA_1)
+            int_rmem24[63:32] <= (WDATA[31:0] & wmask) | (int_rmem24[63:32] & ~wmask);
+    end
+end
+
+// int_rmem25[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem25[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM25_DATA_0)
+            int_rmem25[31:0] <= (WDATA[31:0] & wmask) | (int_rmem25[31:0] & ~wmask);
+    end
+end
+
+// int_rmem25[63:32]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem25[63:32] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM25_DATA_1)
+            int_rmem25[63:32] <= (WDATA[31:0] & wmask) | (int_rmem25[63:32] & ~wmask);
+    end
+end
+
+// int_rmem26[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem26[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM26_DATA_0)
+            int_rmem26[31:0] <= (WDATA[31:0] & wmask) | (int_rmem26[31:0] & ~wmask);
+    end
+end
+
+// int_rmem26[63:32]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem26[63:32] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM26_DATA_1)
+            int_rmem26[63:32] <= (WDATA[31:0] & wmask) | (int_rmem26[63:32] & ~wmask);
+    end
+end
+
+// int_rmem27[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem27[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM27_DATA_0)
+            int_rmem27[31:0] <= (WDATA[31:0] & wmask) | (int_rmem27[31:0] & ~wmask);
+    end
+end
+
+// int_rmem27[63:32]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_rmem27[63:32] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_RMEM27_DATA_1)
+            int_rmem27[63:32] <= (WDATA[31:0] & wmask) | (int_rmem27[63:32] & ~wmask);
+    end
+end
+
+// int_n[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_n[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_N_DATA_0)
+            int_n[31:0] <= (WDATA[31:0] & wmask) | (int_n[31:0] & ~wmask);
+    end
+end
+
+// int_n[63:32]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_n[63:32] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_N_DATA_1)
+            int_n[63:32] <= (WDATA[31:0] & wmask) | (int_n[63:32] & ~wmask);
+    end
+end
+
+//synthesis translate_off
+always @(posedge ACLK) begin
+    if (ACLK_EN) begin
+        if (int_gie & ~int_isr & int_ier & ap_done)
+            $display ("// Interrupt Monitor : interrupt for ap_done detected @ \"%0t\"", $time);
+    end
+end
+//synthesis translate_on
+
+//------------------------Memory logic-------------------
+
+endmodule
diff --git a/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/vadd_bw_fsm.v b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/vadd_bw_fsm.v
new file mode 100644
index 00000000..c9480e0a
--- /dev/null
+++ b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/vadd_bw_fsm.v
@@ -0,0 +1,5134 @@
+
+
+module vadd_bw_fsm
+(
+  ap_clk,
+  ap_rst_n,
+  ap_start,
+  ap_ready,
+  ap_done,
+  ap_idle,
+  n,
+  rmem0,
+  rmem1,
+  rmem2,
+  rmem3,
+  rmem4,
+  rmem5,
+  rmem6,
+  rmem7,
+  rmem8,
+  rmem9,
+  rmem10,
+  rmem11,
+  rmem12,
+  rmem13,
+  rmem14,
+  rmem15,
+  rmem16,
+  rmem17,
+  rmem18,
+  rmem19,
+  rmem20,
+  rmem21,
+  rmem22,
+  rmem23,
+  rmem24,
+  rmem25,
+  rmem26,
+  rmem27,
+  Mmap2Stream_0___n__q0,
+  Mmap2Stream_0___rmem0__q0,
+  Mmap2Stream_0__ap_start,
+  Mmap2Stream_0__ap_ready,
+  Mmap2Stream_0__ap_done,
+  Mmap2Stream_0__ap_idle,
+  Mmap2Stream_1___n__q0,
+  Mmap2Stream_1___rmem1__q0,
+  Mmap2Stream_1__ap_start,
+  Mmap2Stream_1__ap_ready,
+  Mmap2Stream_1__ap_done,
+  Mmap2Stream_1__ap_idle,
+  Mmap2Stream_2___n__q0,
+  Mmap2Stream_2___rmem2__q0,
+  Mmap2Stream_2__ap_start,
+  Mmap2Stream_2__ap_ready,
+  Mmap2Stream_2__ap_done,
+  Mmap2Stream_2__ap_idle,
+  Mmap2Stream_3___n__q0,
+  Mmap2Stream_3___rmem3__q0,
+  Mmap2Stream_3__ap_start,
+  Mmap2Stream_3__ap_ready,
+  Mmap2Stream_3__ap_done,
+  Mmap2Stream_3__ap_idle,
+  Mmap2Stream_4___n__q0,
+  Mmap2Stream_4___rmem4__q0,
+  Mmap2Stream_4__ap_start,
+  Mmap2Stream_4__ap_ready,
+  Mmap2Stream_4__ap_done,
+  Mmap2Stream_4__ap_idle,
+  Mmap2Stream_5___n__q0,
+  Mmap2Stream_5___rmem5__q0,
+  Mmap2Stream_5__ap_start,
+  Mmap2Stream_5__ap_ready,
+  Mmap2Stream_5__ap_done,
+  Mmap2Stream_5__ap_idle,
+  Mmap2Stream_6___n__q0,
+  Mmap2Stream_6___rmem6__q0,
+  Mmap2Stream_6__ap_start,
+  Mmap2Stream_6__ap_ready,
+  Mmap2Stream_6__ap_done,
+  Mmap2Stream_6__ap_idle,
+  Mmap2Stream_7___n__q0,
+  Mmap2Stream_7___rmem7__q0,
+  Mmap2Stream_7__ap_start,
+  Mmap2Stream_7__ap_ready,
+  Mmap2Stream_7__ap_done,
+  Mmap2Stream_7__ap_idle,
+  Mmap2Stream_8___n__q0,
+  Mmap2Stream_8___rmem8__q0,
+  Mmap2Stream_8__ap_start,
+  Mmap2Stream_8__ap_ready,
+  Mmap2Stream_8__ap_done,
+  Mmap2Stream_8__ap_idle,
+  Mmap2Stream_9___n__q0,
+  Mmap2Stream_9___rmem9__q0,
+  Mmap2Stream_9__ap_start,
+  Mmap2Stream_9__ap_ready,
+  Mmap2Stream_9__ap_done,
+  Mmap2Stream_9__ap_idle,
+  Mmap2Stream_10___n__q0,
+  Mmap2Stream_10___rmem10__q0,
+  Mmap2Stream_10__ap_start,
+  Mmap2Stream_10__ap_ready,
+  Mmap2Stream_10__ap_done,
+  Mmap2Stream_10__ap_idle,
+  Mmap2Stream_11___n__q0,
+  Mmap2Stream_11___rmem11__q0,
+  Mmap2Stream_11__ap_start,
+  Mmap2Stream_11__ap_ready,
+  Mmap2Stream_11__ap_done,
+  Mmap2Stream_11__ap_idle,
+  Mmap2Stream_12___n__q0,
+  Mmap2Stream_12___rmem12__q0,
+  Mmap2Stream_12__ap_start,
+  Mmap2Stream_12__ap_ready,
+  Mmap2Stream_12__ap_done,
+  Mmap2Stream_12__ap_idle,
+  Mmap2Stream_13___n__q0,
+  Mmap2Stream_13___rmem13__q0,
+  Mmap2Stream_13__ap_start,
+  Mmap2Stream_13__ap_ready,
+  Mmap2Stream_13__ap_done,
+  Mmap2Stream_13__ap_idle,
+  Mmap2Stream_14___n__q0,
+  Mmap2Stream_14___rmem14__q0,
+  Mmap2Stream_14__ap_start,
+  Mmap2Stream_14__ap_ready,
+  Mmap2Stream_14__ap_done,
+  Mmap2Stream_14__ap_idle,
+  Mmap2Stream_15___n__q0,
+  Mmap2Stream_15___rmem15__q0,
+  Mmap2Stream_15__ap_start,
+  Mmap2Stream_15__ap_ready,
+  Mmap2Stream_15__ap_done,
+  Mmap2Stream_15__ap_idle,
+  Mmap2Stream_16___n__q0,
+  Mmap2Stream_16___rmem16__q0,
+  Mmap2Stream_16__ap_start,
+  Mmap2Stream_16__ap_ready,
+  Mmap2Stream_16__ap_done,
+  Mmap2Stream_16__ap_idle,
+  Mmap2Stream_17___n__q0,
+  Mmap2Stream_17___rmem17__q0,
+  Mmap2Stream_17__ap_start,
+  Mmap2Stream_17__ap_ready,
+  Mmap2Stream_17__ap_done,
+  Mmap2Stream_17__ap_idle,
+  Mmap2Stream_18___n__q0,
+  Mmap2Stream_18___rmem18__q0,
+  Mmap2Stream_18__ap_start,
+  Mmap2Stream_18__ap_ready,
+  Mmap2Stream_18__ap_done,
+  Mmap2Stream_18__ap_idle,
+  Mmap2Stream_19___n__q0,
+  Mmap2Stream_19___rmem19__q0,
+  Mmap2Stream_19__ap_start,
+  Mmap2Stream_19__ap_ready,
+  Mmap2Stream_19__ap_done,
+  Mmap2Stream_19__ap_idle,
+  Mmap2Stream_20___n__q0,
+  Mmap2Stream_20___rmem20__q0,
+  Mmap2Stream_20__ap_start,
+  Mmap2Stream_20__ap_ready,
+  Mmap2Stream_20__ap_done,
+  Mmap2Stream_20__ap_idle,
+  Mmap2Stream_21___n__q0,
+  Mmap2Stream_21___rmem21__q0,
+  Mmap2Stream_21__ap_start,
+  Mmap2Stream_21__ap_ready,
+  Mmap2Stream_21__ap_done,
+  Mmap2Stream_21__ap_idle,
+  Mmap2Stream_22___n__q0,
+  Mmap2Stream_22___rmem22__q0,
+  Mmap2Stream_22__ap_start,
+  Mmap2Stream_22__ap_ready,
+  Mmap2Stream_22__ap_done,
+  Mmap2Stream_22__ap_idle,
+  Mmap2Stream_23___n__q0,
+  Mmap2Stream_23___rmem23__q0,
+  Mmap2Stream_23__ap_start,
+  Mmap2Stream_23__ap_ready,
+  Mmap2Stream_23__ap_done,
+  Mmap2Stream_23__ap_idle,
+  Mmap2Stream_24___n__q0,
+  Mmap2Stream_24___rmem24__q0,
+  Mmap2Stream_24__ap_start,
+  Mmap2Stream_24__ap_ready,
+  Mmap2Stream_24__ap_done,
+  Mmap2Stream_24__ap_idle,
+  Mmap2Stream_25___n__q0,
+  Mmap2Stream_25___rmem25__q0,
+  Mmap2Stream_25__ap_start,
+  Mmap2Stream_25__ap_ready,
+  Mmap2Stream_25__ap_done,
+  Mmap2Stream_25__ap_idle,
+  Mmap2Stream_26___n__q0,
+  Mmap2Stream_26___rmem26__q0,
+  Mmap2Stream_26__ap_start,
+  Mmap2Stream_26__ap_ready,
+  Mmap2Stream_26__ap_done,
+  Mmap2Stream_26__ap_idle,
+  Mmap2Stream_27___n__q0,
+  Mmap2Stream_27___rmem27__q0,
+  Mmap2Stream_27__ap_start,
+  Mmap2Stream_27__ap_ready,
+  Mmap2Stream_27__ap_done,
+  Mmap2Stream_27__ap_idle,
+  Stream2Mmap_0___n__q0,
+  Stream2Mmap_0___rmem0__q0,
+  Stream2Mmap_0__ap_start,
+  Stream2Mmap_0__ap_ready,
+  Stream2Mmap_0__ap_done,
+  Stream2Mmap_0__ap_idle,
+  Stream2Mmap_1___n__q0,
+  Stream2Mmap_1___rmem1__q0,
+  Stream2Mmap_1__ap_start,
+  Stream2Mmap_1__ap_ready,
+  Stream2Mmap_1__ap_done,
+  Stream2Mmap_1__ap_idle,
+  Stream2Mmap_2___n__q0,
+  Stream2Mmap_2___rmem2__q0,
+  Stream2Mmap_2__ap_start,
+  Stream2Mmap_2__ap_ready,
+  Stream2Mmap_2__ap_done,
+  Stream2Mmap_2__ap_idle,
+  Stream2Mmap_3___n__q0,
+  Stream2Mmap_3___rmem3__q0,
+  Stream2Mmap_3__ap_start,
+  Stream2Mmap_3__ap_ready,
+  Stream2Mmap_3__ap_done,
+  Stream2Mmap_3__ap_idle,
+  Stream2Mmap_4___n__q0,
+  Stream2Mmap_4___rmem4__q0,
+  Stream2Mmap_4__ap_start,
+  Stream2Mmap_4__ap_ready,
+  Stream2Mmap_4__ap_done,
+  Stream2Mmap_4__ap_idle,
+  Stream2Mmap_5___n__q0,
+  Stream2Mmap_5___rmem5__q0,
+  Stream2Mmap_5__ap_start,
+  Stream2Mmap_5__ap_ready,
+  Stream2Mmap_5__ap_done,
+  Stream2Mmap_5__ap_idle,
+  Stream2Mmap_6___n__q0,
+  Stream2Mmap_6___rmem6__q0,
+  Stream2Mmap_6__ap_start,
+  Stream2Mmap_6__ap_ready,
+  Stream2Mmap_6__ap_done,
+  Stream2Mmap_6__ap_idle,
+  Stream2Mmap_7___n__q0,
+  Stream2Mmap_7___rmem7__q0,
+  Stream2Mmap_7__ap_start,
+  Stream2Mmap_7__ap_ready,
+  Stream2Mmap_7__ap_done,
+  Stream2Mmap_7__ap_idle,
+  Stream2Mmap_8___n__q0,
+  Stream2Mmap_8___rmem8__q0,
+  Stream2Mmap_8__ap_start,
+  Stream2Mmap_8__ap_ready,
+  Stream2Mmap_8__ap_done,
+  Stream2Mmap_8__ap_idle,
+  Stream2Mmap_9___n__q0,
+  Stream2Mmap_9___rmem9__q0,
+  Stream2Mmap_9__ap_start,
+  Stream2Mmap_9__ap_ready,
+  Stream2Mmap_9__ap_done,
+  Stream2Mmap_9__ap_idle,
+  Stream2Mmap_10___n__q0,
+  Stream2Mmap_10___rmem10__q0,
+  Stream2Mmap_10__ap_start,
+  Stream2Mmap_10__ap_ready,
+  Stream2Mmap_10__ap_done,
+  Stream2Mmap_10__ap_idle,
+  Stream2Mmap_11___n__q0,
+  Stream2Mmap_11___rmem11__q0,
+  Stream2Mmap_11__ap_start,
+  Stream2Mmap_11__ap_ready,
+  Stream2Mmap_11__ap_done,
+  Stream2Mmap_11__ap_idle,
+  Stream2Mmap_12___n__q0,
+  Stream2Mmap_12___rmem12__q0,
+  Stream2Mmap_12__ap_start,
+  Stream2Mmap_12__ap_ready,
+  Stream2Mmap_12__ap_done,
+  Stream2Mmap_12__ap_idle,
+  Stream2Mmap_13___n__q0,
+  Stream2Mmap_13___rmem13__q0,
+  Stream2Mmap_13__ap_start,
+  Stream2Mmap_13__ap_ready,
+  Stream2Mmap_13__ap_done,
+  Stream2Mmap_13__ap_idle,
+  Stream2Mmap_14___n__q0,
+  Stream2Mmap_14___rmem14__q0,
+  Stream2Mmap_14__ap_start,
+  Stream2Mmap_14__ap_ready,
+  Stream2Mmap_14__ap_done,
+  Stream2Mmap_14__ap_idle,
+  Stream2Mmap_15___n__q0,
+  Stream2Mmap_15___rmem15__q0,
+  Stream2Mmap_15__ap_start,
+  Stream2Mmap_15__ap_ready,
+  Stream2Mmap_15__ap_done,
+  Stream2Mmap_15__ap_idle,
+  Stream2Mmap_16___n__q0,
+  Stream2Mmap_16___rmem16__q0,
+  Stream2Mmap_16__ap_start,
+  Stream2Mmap_16__ap_ready,
+  Stream2Mmap_16__ap_done,
+  Stream2Mmap_16__ap_idle,
+  Stream2Mmap_17___n__q0,
+  Stream2Mmap_17___rmem17__q0,
+  Stream2Mmap_17__ap_start,
+  Stream2Mmap_17__ap_ready,
+  Stream2Mmap_17__ap_done,
+  Stream2Mmap_17__ap_idle,
+  Stream2Mmap_18___n__q0,
+  Stream2Mmap_18___rmem18__q0,
+  Stream2Mmap_18__ap_start,
+  Stream2Mmap_18__ap_ready,
+  Stream2Mmap_18__ap_done,
+  Stream2Mmap_18__ap_idle,
+  Stream2Mmap_19___n__q0,
+  Stream2Mmap_19___rmem19__q0,
+  Stream2Mmap_19__ap_start,
+  Stream2Mmap_19__ap_ready,
+  Stream2Mmap_19__ap_done,
+  Stream2Mmap_19__ap_idle,
+  Stream2Mmap_20___n__q0,
+  Stream2Mmap_20___rmem20__q0,
+  Stream2Mmap_20__ap_start,
+  Stream2Mmap_20__ap_ready,
+  Stream2Mmap_20__ap_done,
+  Stream2Mmap_20__ap_idle,
+  Stream2Mmap_21___n__q0,
+  Stream2Mmap_21___rmem21__q0,
+  Stream2Mmap_21__ap_start,
+  Stream2Mmap_21__ap_ready,
+  Stream2Mmap_21__ap_done,
+  Stream2Mmap_21__ap_idle,
+  Stream2Mmap_22___n__q0,
+  Stream2Mmap_22___rmem22__q0,
+  Stream2Mmap_22__ap_start,
+  Stream2Mmap_22__ap_ready,
+  Stream2Mmap_22__ap_done,
+  Stream2Mmap_22__ap_idle,
+  Stream2Mmap_23___n__q0,
+  Stream2Mmap_23___rmem23__q0,
+  Stream2Mmap_23__ap_start,
+  Stream2Mmap_23__ap_ready,
+  Stream2Mmap_23__ap_done,
+  Stream2Mmap_23__ap_idle,
+  Stream2Mmap_24___n__q0,
+  Stream2Mmap_24___rmem24__q0,
+  Stream2Mmap_24__ap_start,
+  Stream2Mmap_24__ap_ready,
+  Stream2Mmap_24__ap_done,
+  Stream2Mmap_24__ap_idle,
+  Stream2Mmap_25___n__q0,
+  Stream2Mmap_25___rmem25__q0,
+  Stream2Mmap_25__ap_start,
+  Stream2Mmap_25__ap_ready,
+  Stream2Mmap_25__ap_done,
+  Stream2Mmap_25__ap_idle,
+  Stream2Mmap_26___n__q0,
+  Stream2Mmap_26___rmem26__q0,
+  Stream2Mmap_26__ap_start,
+  Stream2Mmap_26__ap_ready,
+  Stream2Mmap_26__ap_done,
+  Stream2Mmap_26__ap_idle,
+  Stream2Mmap_27___n__q0,
+  Stream2Mmap_27___rmem27__q0,
+  Stream2Mmap_27__ap_start,
+  Stream2Mmap_27__ap_ready,
+  Stream2Mmap_27__ap_done,
+  Stream2Mmap_27__ap_idle,
+  yshift_0___n__q0,
+  yshift_0__ap_start,
+  yshift_0__ap_ready,
+  yshift_0__ap_done,
+  yshift_0__ap_idle,
+  yshift_1___n__q0,
+  yshift_1__ap_start,
+  yshift_1__ap_ready,
+  yshift_1__ap_done,
+  yshift_1__ap_idle,
+  yshift_2___n__q0,
+  yshift_2__ap_start,
+  yshift_2__ap_ready,
+  yshift_2__ap_done,
+  yshift_2__ap_idle,
+  yshift_3___n__q0,
+  yshift_3__ap_start,
+  yshift_3__ap_ready,
+  yshift_3__ap_done,
+  yshift_3__ap_idle,
+  yshift_4___n__q0,
+  yshift_4__ap_start,
+  yshift_4__ap_ready,
+  yshift_4__ap_done,
+  yshift_4__ap_idle,
+  yshift_5___n__q0,
+  yshift_5__ap_start,
+  yshift_5__ap_ready,
+  yshift_5__ap_done,
+  yshift_5__ap_idle,
+  yshift_6___n__q0,
+  yshift_6__ap_start,
+  yshift_6__ap_ready,
+  yshift_6__ap_done,
+  yshift_6__ap_idle,
+  yshift_7___n__q0,
+  yshift_7__ap_start,
+  yshift_7__ap_ready,
+  yshift_7__ap_done,
+  yshift_7__ap_idle,
+  yshift_8___n__q0,
+  yshift_8__ap_start,
+  yshift_8__ap_ready,
+  yshift_8__ap_done,
+  yshift_8__ap_idle,
+  yshift_9___n__q0,
+  yshift_9__ap_start,
+  yshift_9__ap_ready,
+  yshift_9__ap_done,
+  yshift_9__ap_idle,
+  yshift_10___n__q0,
+  yshift_10__ap_start,
+  yshift_10__ap_ready,
+  yshift_10__ap_done,
+  yshift_10__ap_idle,
+  yshift_11___n__q0,
+  yshift_11__ap_start,
+  yshift_11__ap_ready,
+  yshift_11__ap_done,
+  yshift_11__ap_idle,
+  yshift_12___n__q0,
+  yshift_12__ap_start,
+  yshift_12__ap_ready,
+  yshift_12__ap_done,
+  yshift_12__ap_idle,
+  yshift_13___n__q0,
+  yshift_13__ap_start,
+  yshift_13__ap_ready,
+  yshift_13__ap_done,
+  yshift_13__ap_idle,
+  yshift_14___n__q0,
+  yshift_14__ap_start,
+  yshift_14__ap_ready,
+  yshift_14__ap_done,
+  yshift_14__ap_idle,
+  yshift_15___n__q0,
+  yshift_15__ap_start,
+  yshift_15__ap_ready,
+  yshift_15__ap_done,
+  yshift_15__ap_idle,
+  yshift_16___n__q0,
+  yshift_16__ap_start,
+  yshift_16__ap_ready,
+  yshift_16__ap_done,
+  yshift_16__ap_idle,
+  yshift_17___n__q0,
+  yshift_17__ap_start,
+  yshift_17__ap_ready,
+  yshift_17__ap_done,
+  yshift_17__ap_idle,
+  yshift_18___n__q0,
+  yshift_18__ap_start,
+  yshift_18__ap_ready,
+  yshift_18__ap_done,
+  yshift_18__ap_idle,
+  yshift_19___n__q0,
+  yshift_19__ap_start,
+  yshift_19__ap_ready,
+  yshift_19__ap_done,
+  yshift_19__ap_idle,
+  yshift_20___n__q0,
+  yshift_20__ap_start,
+  yshift_20__ap_ready,
+  yshift_20__ap_done,
+  yshift_20__ap_idle,
+  yshift_21___n__q0,
+  yshift_21__ap_start,
+  yshift_21__ap_ready,
+  yshift_21__ap_done,
+  yshift_21__ap_idle,
+  yshift_22___n__q0,
+  yshift_22__ap_start,
+  yshift_22__ap_ready,
+  yshift_22__ap_done,
+  yshift_22__ap_idle,
+  yshift_23___n__q0,
+  yshift_23__ap_start,
+  yshift_23__ap_ready,
+  yshift_23__ap_done,
+  yshift_23__ap_idle,
+  yshift_24___n__q0,
+  yshift_24__ap_start,
+  yshift_24__ap_ready,
+  yshift_24__ap_done,
+  yshift_24__ap_idle,
+  yshift_25___n__q0,
+  yshift_25__ap_start,
+  yshift_25__ap_ready,
+  yshift_25__ap_done,
+  yshift_25__ap_idle,
+  yshift_26___n__q0,
+  yshift_26__ap_start,
+  yshift_26__ap_ready,
+  yshift_26__ap_done,
+  yshift_26__ap_idle,
+  yshift_27___n__q0,
+  yshift_27__ap_start,
+  yshift_27__ap_ready,
+  yshift_27__ap_done,
+  yshift_27__ap_idle
+);
+
+  // pragma RS clk port=ap_clk
+  // pragma RS rst port=ap_rst_n active=low
+  // pragma RS ap-ctrl ap_start=ap_start ap_done=ap_done ap_idle=ap_idle ap_ready=ap_ready scalar=(rmem0|rmem1|rmem2|rmem3|rmem4|rmem5|rmem6|rmem7|rmem8|rmem9|rmem10|rmem11|rmem12|rmem13|rmem14|rmem15|rmem16|rmem17|rmem18|rmem19|rmem20|rmem21|rmem22|rmem23|rmem24|rmem25|rmem26|rmem27|n)
+  // pragma RS ap-ctrl ap_start=Mmap2Stream_0__ap_start ap_done=Mmap2Stream_0__ap_done ap_idle=Mmap2Stream_0__ap_idle ap_ready=Mmap2Stream_0__ap_ready scalar=Mmap2Stream_0___.*
+  // pragma RS ap-ctrl ap_start=Mmap2Stream_1__ap_start ap_done=Mmap2Stream_1__ap_done ap_idle=Mmap2Stream_1__ap_idle ap_ready=Mmap2Stream_1__ap_ready scalar=Mmap2Stream_1___.*
+  // pragma RS ap-ctrl ap_start=Mmap2Stream_2__ap_start ap_done=Mmap2Stream_2__ap_done ap_idle=Mmap2Stream_2__ap_idle ap_ready=Mmap2Stream_2__ap_ready scalar=Mmap2Stream_2___.*
+  // pragma RS ap-ctrl ap_start=Mmap2Stream_3__ap_start ap_done=Mmap2Stream_3__ap_done ap_idle=Mmap2Stream_3__ap_idle ap_ready=Mmap2Stream_3__ap_ready scalar=Mmap2Stream_3___.*
+  // pragma RS ap-ctrl ap_start=Mmap2Stream_4__ap_start ap_done=Mmap2Stream_4__ap_done ap_idle=Mmap2Stream_4__ap_idle ap_ready=Mmap2Stream_4__ap_ready scalar=Mmap2Stream_4___.*
+  // pragma RS ap-ctrl ap_start=Mmap2Stream_5__ap_start ap_done=Mmap2Stream_5__ap_done ap_idle=Mmap2Stream_5__ap_idle ap_ready=Mmap2Stream_5__ap_ready scalar=Mmap2Stream_5___.*
+  // pragma RS ap-ctrl ap_start=Mmap2Stream_6__ap_start ap_done=Mmap2Stream_6__ap_done ap_idle=Mmap2Stream_6__ap_idle ap_ready=Mmap2Stream_6__ap_ready scalar=Mmap2Stream_6___.*
+  // pragma RS ap-ctrl ap_start=Mmap2Stream_7__ap_start ap_done=Mmap2Stream_7__ap_done ap_idle=Mmap2Stream_7__ap_idle ap_ready=Mmap2Stream_7__ap_ready scalar=Mmap2Stream_7___.*
+  // pragma RS ap-ctrl ap_start=Mmap2Stream_8__ap_start ap_done=Mmap2Stream_8__ap_done ap_idle=Mmap2Stream_8__ap_idle ap_ready=Mmap2Stream_8__ap_ready scalar=Mmap2Stream_8___.*
+  // pragma RS ap-ctrl ap_start=Mmap2Stream_9__ap_start ap_done=Mmap2Stream_9__ap_done ap_idle=Mmap2Stream_9__ap_idle ap_ready=Mmap2Stream_9__ap_ready scalar=Mmap2Stream_9___.*
+  // pragma RS ap-ctrl ap_start=Mmap2Stream_10__ap_start ap_done=Mmap2Stream_10__ap_done ap_idle=Mmap2Stream_10__ap_idle ap_ready=Mmap2Stream_10__ap_ready scalar=Mmap2Stream_10___.*
+  // pragma RS ap-ctrl ap_start=Mmap2Stream_11__ap_start ap_done=Mmap2Stream_11__ap_done ap_idle=Mmap2Stream_11__ap_idle ap_ready=Mmap2Stream_11__ap_ready scalar=Mmap2Stream_11___.*
+  // pragma RS ap-ctrl ap_start=Mmap2Stream_12__ap_start ap_done=Mmap2Stream_12__ap_done ap_idle=Mmap2Stream_12__ap_idle ap_ready=Mmap2Stream_12__ap_ready scalar=Mmap2Stream_12___.*
+  // pragma RS ap-ctrl ap_start=Mmap2Stream_13__ap_start ap_done=Mmap2Stream_13__ap_done ap_idle=Mmap2Stream_13__ap_idle ap_ready=Mmap2Stream_13__ap_ready scalar=Mmap2Stream_13___.*
+  // pragma RS ap-ctrl ap_start=Mmap2Stream_14__ap_start ap_done=Mmap2Stream_14__ap_done ap_idle=Mmap2Stream_14__ap_idle ap_ready=Mmap2Stream_14__ap_ready scalar=Mmap2Stream_14___.*
+  // pragma RS ap-ctrl ap_start=Mmap2Stream_15__ap_start ap_done=Mmap2Stream_15__ap_done ap_idle=Mmap2Stream_15__ap_idle ap_ready=Mmap2Stream_15__ap_ready scalar=Mmap2Stream_15___.*
+  // pragma RS ap-ctrl ap_start=Mmap2Stream_16__ap_start ap_done=Mmap2Stream_16__ap_done ap_idle=Mmap2Stream_16__ap_idle ap_ready=Mmap2Stream_16__ap_ready scalar=Mmap2Stream_16___.*
+  // pragma RS ap-ctrl ap_start=Mmap2Stream_17__ap_start ap_done=Mmap2Stream_17__ap_done ap_idle=Mmap2Stream_17__ap_idle ap_ready=Mmap2Stream_17__ap_ready scalar=Mmap2Stream_17___.*
+  // pragma RS ap-ctrl ap_start=Mmap2Stream_18__ap_start ap_done=Mmap2Stream_18__ap_done ap_idle=Mmap2Stream_18__ap_idle ap_ready=Mmap2Stream_18__ap_ready scalar=Mmap2Stream_18___.*
+  // pragma RS ap-ctrl ap_start=Mmap2Stream_19__ap_start ap_done=Mmap2Stream_19__ap_done ap_idle=Mmap2Stream_19__ap_idle ap_ready=Mmap2Stream_19__ap_ready scalar=Mmap2Stream_19___.*
+  // pragma RS ap-ctrl ap_start=Mmap2Stream_20__ap_start ap_done=Mmap2Stream_20__ap_done ap_idle=Mmap2Stream_20__ap_idle ap_ready=Mmap2Stream_20__ap_ready scalar=Mmap2Stream_20___.*
+  // pragma RS ap-ctrl ap_start=Mmap2Stream_21__ap_start ap_done=Mmap2Stream_21__ap_done ap_idle=Mmap2Stream_21__ap_idle ap_ready=Mmap2Stream_21__ap_ready scalar=Mmap2Stream_21___.*
+  // pragma RS ap-ctrl ap_start=Mmap2Stream_22__ap_start ap_done=Mmap2Stream_22__ap_done ap_idle=Mmap2Stream_22__ap_idle ap_ready=Mmap2Stream_22__ap_ready scalar=Mmap2Stream_22___.*
+  // pragma RS ap-ctrl ap_start=Mmap2Stream_23__ap_start ap_done=Mmap2Stream_23__ap_done ap_idle=Mmap2Stream_23__ap_idle ap_ready=Mmap2Stream_23__ap_ready scalar=Mmap2Stream_23___.*
+  // pragma RS ap-ctrl ap_start=Mmap2Stream_24__ap_start ap_done=Mmap2Stream_24__ap_done ap_idle=Mmap2Stream_24__ap_idle ap_ready=Mmap2Stream_24__ap_ready scalar=Mmap2Stream_24___.*
+  // pragma RS ap-ctrl ap_start=Mmap2Stream_25__ap_start ap_done=Mmap2Stream_25__ap_done ap_idle=Mmap2Stream_25__ap_idle ap_ready=Mmap2Stream_25__ap_ready scalar=Mmap2Stream_25___.*
+  // pragma RS ap-ctrl ap_start=Mmap2Stream_26__ap_start ap_done=Mmap2Stream_26__ap_done ap_idle=Mmap2Stream_26__ap_idle ap_ready=Mmap2Stream_26__ap_ready scalar=Mmap2Stream_26___.*
+  // pragma RS ap-ctrl ap_start=Mmap2Stream_27__ap_start ap_done=Mmap2Stream_27__ap_done ap_idle=Mmap2Stream_27__ap_idle ap_ready=Mmap2Stream_27__ap_ready scalar=Mmap2Stream_27___.*
+  // pragma RS ap-ctrl ap_start=Stream2Mmap_0__ap_start ap_done=Stream2Mmap_0__ap_done ap_idle=Stream2Mmap_0__ap_idle ap_ready=Stream2Mmap_0__ap_ready scalar=Stream2Mmap_0___.*
+  // pragma RS ap-ctrl ap_start=Stream2Mmap_1__ap_start ap_done=Stream2Mmap_1__ap_done ap_idle=Stream2Mmap_1__ap_idle ap_ready=Stream2Mmap_1__ap_ready scalar=Stream2Mmap_1___.*
+  // pragma RS ap-ctrl ap_start=Stream2Mmap_2__ap_start ap_done=Stream2Mmap_2__ap_done ap_idle=Stream2Mmap_2__ap_idle ap_ready=Stream2Mmap_2__ap_ready scalar=Stream2Mmap_2___.*
+  // pragma RS ap-ctrl ap_start=Stream2Mmap_3__ap_start ap_done=Stream2Mmap_3__ap_done ap_idle=Stream2Mmap_3__ap_idle ap_ready=Stream2Mmap_3__ap_ready scalar=Stream2Mmap_3___.*
+  // pragma RS ap-ctrl ap_start=Stream2Mmap_4__ap_start ap_done=Stream2Mmap_4__ap_done ap_idle=Stream2Mmap_4__ap_idle ap_ready=Stream2Mmap_4__ap_ready scalar=Stream2Mmap_4___.*
+  // pragma RS ap-ctrl ap_start=Stream2Mmap_5__ap_start ap_done=Stream2Mmap_5__ap_done ap_idle=Stream2Mmap_5__ap_idle ap_ready=Stream2Mmap_5__ap_ready scalar=Stream2Mmap_5___.*
+  // pragma RS ap-ctrl ap_start=Stream2Mmap_6__ap_start ap_done=Stream2Mmap_6__ap_done ap_idle=Stream2Mmap_6__ap_idle ap_ready=Stream2Mmap_6__ap_ready scalar=Stream2Mmap_6___.*
+  // pragma RS ap-ctrl ap_start=Stream2Mmap_7__ap_start ap_done=Stream2Mmap_7__ap_done ap_idle=Stream2Mmap_7__ap_idle ap_ready=Stream2Mmap_7__ap_ready scalar=Stream2Mmap_7___.*
+  // pragma RS ap-ctrl ap_start=Stream2Mmap_8__ap_start ap_done=Stream2Mmap_8__ap_done ap_idle=Stream2Mmap_8__ap_idle ap_ready=Stream2Mmap_8__ap_ready scalar=Stream2Mmap_8___.*
+  // pragma RS ap-ctrl ap_start=Stream2Mmap_9__ap_start ap_done=Stream2Mmap_9__ap_done ap_idle=Stream2Mmap_9__ap_idle ap_ready=Stream2Mmap_9__ap_ready scalar=Stream2Mmap_9___.*
+  // pragma RS ap-ctrl ap_start=Stream2Mmap_10__ap_start ap_done=Stream2Mmap_10__ap_done ap_idle=Stream2Mmap_10__ap_idle ap_ready=Stream2Mmap_10__ap_ready scalar=Stream2Mmap_10___.*
+  // pragma RS ap-ctrl ap_start=Stream2Mmap_11__ap_start ap_done=Stream2Mmap_11__ap_done ap_idle=Stream2Mmap_11__ap_idle ap_ready=Stream2Mmap_11__ap_ready scalar=Stream2Mmap_11___.*
+  // pragma RS ap-ctrl ap_start=Stream2Mmap_12__ap_start ap_done=Stream2Mmap_12__ap_done ap_idle=Stream2Mmap_12__ap_idle ap_ready=Stream2Mmap_12__ap_ready scalar=Stream2Mmap_12___.*
+  // pragma RS ap-ctrl ap_start=Stream2Mmap_13__ap_start ap_done=Stream2Mmap_13__ap_done ap_idle=Stream2Mmap_13__ap_idle ap_ready=Stream2Mmap_13__ap_ready scalar=Stream2Mmap_13___.*
+  // pragma RS ap-ctrl ap_start=Stream2Mmap_14__ap_start ap_done=Stream2Mmap_14__ap_done ap_idle=Stream2Mmap_14__ap_idle ap_ready=Stream2Mmap_14__ap_ready scalar=Stream2Mmap_14___.*
+  // pragma RS ap-ctrl ap_start=Stream2Mmap_15__ap_start ap_done=Stream2Mmap_15__ap_done ap_idle=Stream2Mmap_15__ap_idle ap_ready=Stream2Mmap_15__ap_ready scalar=Stream2Mmap_15___.*
+  // pragma RS ap-ctrl ap_start=Stream2Mmap_16__ap_start ap_done=Stream2Mmap_16__ap_done ap_idle=Stream2Mmap_16__ap_idle ap_ready=Stream2Mmap_16__ap_ready scalar=Stream2Mmap_16___.*
+  // pragma RS ap-ctrl ap_start=Stream2Mmap_17__ap_start ap_done=Stream2Mmap_17__ap_done ap_idle=Stream2Mmap_17__ap_idle ap_ready=Stream2Mmap_17__ap_ready scalar=Stream2Mmap_17___.*
+  // pragma RS ap-ctrl ap_start=Stream2Mmap_18__ap_start ap_done=Stream2Mmap_18__ap_done ap_idle=Stream2Mmap_18__ap_idle ap_ready=Stream2Mmap_18__ap_ready scalar=Stream2Mmap_18___.*
+  // pragma RS ap-ctrl ap_start=Stream2Mmap_19__ap_start ap_done=Stream2Mmap_19__ap_done ap_idle=Stream2Mmap_19__ap_idle ap_ready=Stream2Mmap_19__ap_ready scalar=Stream2Mmap_19___.*
+  // pragma RS ap-ctrl ap_start=Stream2Mmap_20__ap_start ap_done=Stream2Mmap_20__ap_done ap_idle=Stream2Mmap_20__ap_idle ap_ready=Stream2Mmap_20__ap_ready scalar=Stream2Mmap_20___.*
+  // pragma RS ap-ctrl ap_start=Stream2Mmap_21__ap_start ap_done=Stream2Mmap_21__ap_done ap_idle=Stream2Mmap_21__ap_idle ap_ready=Stream2Mmap_21__ap_ready scalar=Stream2Mmap_21___.*
+  // pragma RS ap-ctrl ap_start=Stream2Mmap_22__ap_start ap_done=Stream2Mmap_22__ap_done ap_idle=Stream2Mmap_22__ap_idle ap_ready=Stream2Mmap_22__ap_ready scalar=Stream2Mmap_22___.*
+  // pragma RS ap-ctrl ap_start=Stream2Mmap_23__ap_start ap_done=Stream2Mmap_23__ap_done ap_idle=Stream2Mmap_23__ap_idle ap_ready=Stream2Mmap_23__ap_ready scalar=Stream2Mmap_23___.*
+  // pragma RS ap-ctrl ap_start=Stream2Mmap_24__ap_start ap_done=Stream2Mmap_24__ap_done ap_idle=Stream2Mmap_24__ap_idle ap_ready=Stream2Mmap_24__ap_ready scalar=Stream2Mmap_24___.*
+  // pragma RS ap-ctrl ap_start=Stream2Mmap_25__ap_start ap_done=Stream2Mmap_25__ap_done ap_idle=Stream2Mmap_25__ap_idle ap_ready=Stream2Mmap_25__ap_ready scalar=Stream2Mmap_25___.*
+  // pragma RS ap-ctrl ap_start=Stream2Mmap_26__ap_start ap_done=Stream2Mmap_26__ap_done ap_idle=Stream2Mmap_26__ap_idle ap_ready=Stream2Mmap_26__ap_ready scalar=Stream2Mmap_26___.*
+  // pragma RS ap-ctrl ap_start=Stream2Mmap_27__ap_start ap_done=Stream2Mmap_27__ap_done ap_idle=Stream2Mmap_27__ap_idle ap_ready=Stream2Mmap_27__ap_ready scalar=Stream2Mmap_27___.*
+  // pragma RS ap-ctrl ap_start=yshift_0__ap_start ap_done=yshift_0__ap_done ap_idle=yshift_0__ap_idle ap_ready=yshift_0__ap_ready scalar=yshift_0___.*
+  // pragma RS ap-ctrl ap_start=yshift_1__ap_start ap_done=yshift_1__ap_done ap_idle=yshift_1__ap_idle ap_ready=yshift_1__ap_ready scalar=yshift_1___.*
+  // pragma RS ap-ctrl ap_start=yshift_2__ap_start ap_done=yshift_2__ap_done ap_idle=yshift_2__ap_idle ap_ready=yshift_2__ap_ready scalar=yshift_2___.*
+  // pragma RS ap-ctrl ap_start=yshift_3__ap_start ap_done=yshift_3__ap_done ap_idle=yshift_3__ap_idle ap_ready=yshift_3__ap_ready scalar=yshift_3___.*
+  // pragma RS ap-ctrl ap_start=yshift_4__ap_start ap_done=yshift_4__ap_done ap_idle=yshift_4__ap_idle ap_ready=yshift_4__ap_ready scalar=yshift_4___.*
+  // pragma RS ap-ctrl ap_start=yshift_5__ap_start ap_done=yshift_5__ap_done ap_idle=yshift_5__ap_idle ap_ready=yshift_5__ap_ready scalar=yshift_5___.*
+  // pragma RS ap-ctrl ap_start=yshift_6__ap_start ap_done=yshift_6__ap_done ap_idle=yshift_6__ap_idle ap_ready=yshift_6__ap_ready scalar=yshift_6___.*
+  // pragma RS ap-ctrl ap_start=yshift_7__ap_start ap_done=yshift_7__ap_done ap_idle=yshift_7__ap_idle ap_ready=yshift_7__ap_ready scalar=yshift_7___.*
+  // pragma RS ap-ctrl ap_start=yshift_8__ap_start ap_done=yshift_8__ap_done ap_idle=yshift_8__ap_idle ap_ready=yshift_8__ap_ready scalar=yshift_8___.*
+  // pragma RS ap-ctrl ap_start=yshift_9__ap_start ap_done=yshift_9__ap_done ap_idle=yshift_9__ap_idle ap_ready=yshift_9__ap_ready scalar=yshift_9___.*
+  // pragma RS ap-ctrl ap_start=yshift_10__ap_start ap_done=yshift_10__ap_done ap_idle=yshift_10__ap_idle ap_ready=yshift_10__ap_ready scalar=yshift_10___.*
+  // pragma RS ap-ctrl ap_start=yshift_11__ap_start ap_done=yshift_11__ap_done ap_idle=yshift_11__ap_idle ap_ready=yshift_11__ap_ready scalar=yshift_11___.*
+  // pragma RS ap-ctrl ap_start=yshift_12__ap_start ap_done=yshift_12__ap_done ap_idle=yshift_12__ap_idle ap_ready=yshift_12__ap_ready scalar=yshift_12___.*
+  // pragma RS ap-ctrl ap_start=yshift_13__ap_start ap_done=yshift_13__ap_done ap_idle=yshift_13__ap_idle ap_ready=yshift_13__ap_ready scalar=yshift_13___.*
+  // pragma RS ap-ctrl ap_start=yshift_14__ap_start ap_done=yshift_14__ap_done ap_idle=yshift_14__ap_idle ap_ready=yshift_14__ap_ready scalar=yshift_14___.*
+  // pragma RS ap-ctrl ap_start=yshift_15__ap_start ap_done=yshift_15__ap_done ap_idle=yshift_15__ap_idle ap_ready=yshift_15__ap_ready scalar=yshift_15___.*
+  // pragma RS ap-ctrl ap_start=yshift_16__ap_start ap_done=yshift_16__ap_done ap_idle=yshift_16__ap_idle ap_ready=yshift_16__ap_ready scalar=yshift_16___.*
+  // pragma RS ap-ctrl ap_start=yshift_17__ap_start ap_done=yshift_17__ap_done ap_idle=yshift_17__ap_idle ap_ready=yshift_17__ap_ready scalar=yshift_17___.*
+  // pragma RS ap-ctrl ap_start=yshift_18__ap_start ap_done=yshift_18__ap_done ap_idle=yshift_18__ap_idle ap_ready=yshift_18__ap_ready scalar=yshift_18___.*
+  // pragma RS ap-ctrl ap_start=yshift_19__ap_start ap_done=yshift_19__ap_done ap_idle=yshift_19__ap_idle ap_ready=yshift_19__ap_ready scalar=yshift_19___.*
+  // pragma RS ap-ctrl ap_start=yshift_20__ap_start ap_done=yshift_20__ap_done ap_idle=yshift_20__ap_idle ap_ready=yshift_20__ap_ready scalar=yshift_20___.*
+  // pragma RS ap-ctrl ap_start=yshift_21__ap_start ap_done=yshift_21__ap_done ap_idle=yshift_21__ap_idle ap_ready=yshift_21__ap_ready scalar=yshift_21___.*
+  // pragma RS ap-ctrl ap_start=yshift_22__ap_start ap_done=yshift_22__ap_done ap_idle=yshift_22__ap_idle ap_ready=yshift_22__ap_ready scalar=yshift_22___.*
+  // pragma RS ap-ctrl ap_start=yshift_23__ap_start ap_done=yshift_23__ap_done ap_idle=yshift_23__ap_idle ap_ready=yshift_23__ap_ready scalar=yshift_23___.*
+  // pragma RS ap-ctrl ap_start=yshift_24__ap_start ap_done=yshift_24__ap_done ap_idle=yshift_24__ap_idle ap_ready=yshift_24__ap_ready scalar=yshift_24___.*
+  // pragma RS ap-ctrl ap_start=yshift_25__ap_start ap_done=yshift_25__ap_done ap_idle=yshift_25__ap_idle ap_ready=yshift_25__ap_ready scalar=yshift_25___.*
+  // pragma RS ap-ctrl ap_start=yshift_26__ap_start ap_done=yshift_26__ap_done ap_idle=yshift_26__ap_idle ap_ready=yshift_26__ap_ready scalar=yshift_26___.*
+  // pragma RS ap-ctrl ap_start=yshift_27__ap_start ap_done=yshift_27__ap_done ap_idle=yshift_27__ap_idle ap_ready=yshift_27__ap_ready scalar=yshift_27___.*
+
+  input ap_clk;
+  input ap_rst_n;
+  input ap_start;
+  output ap_ready;
+  output ap_done;
+  output ap_idle;
+  input [63:0] n;
+  input [63:0] rmem0;
+  input [63:0] rmem1;
+  input [63:0] rmem2;
+  input [63:0] rmem3;
+  input [63:0] rmem4;
+  input [63:0] rmem5;
+  input [63:0] rmem6;
+  input [63:0] rmem7;
+  input [63:0] rmem8;
+  input [63:0] rmem9;
+  input [63:0] rmem10;
+  input [63:0] rmem11;
+  input [63:0] rmem12;
+  input [63:0] rmem13;
+  input [63:0] rmem14;
+  input [63:0] rmem15;
+  input [63:0] rmem16;
+  input [63:0] rmem17;
+  input [63:0] rmem18;
+  input [63:0] rmem19;
+  input [63:0] rmem20;
+  input [63:0] rmem21;
+  input [63:0] rmem22;
+  input [63:0] rmem23;
+  input [63:0] rmem24;
+  input [63:0] rmem25;
+  input [63:0] rmem26;
+  input [63:0] rmem27;
+  output [63:0] Mmap2Stream_0___n__q0;
+  output [63:0] Mmap2Stream_0___rmem0__q0;
+  output Mmap2Stream_0__ap_start;
+  input Mmap2Stream_0__ap_ready;
+  input Mmap2Stream_0__ap_done;
+  input Mmap2Stream_0__ap_idle;
+  output [63:0] Mmap2Stream_1___n__q0;
+  output [63:0] Mmap2Stream_1___rmem1__q0;
+  output Mmap2Stream_1__ap_start;
+  input Mmap2Stream_1__ap_ready;
+  input Mmap2Stream_1__ap_done;
+  input Mmap2Stream_1__ap_idle;
+  output [63:0] Mmap2Stream_2___n__q0;
+  output [63:0] Mmap2Stream_2___rmem2__q0;
+  output Mmap2Stream_2__ap_start;
+  input Mmap2Stream_2__ap_ready;
+  input Mmap2Stream_2__ap_done;
+  input Mmap2Stream_2__ap_idle;
+  output [63:0] Mmap2Stream_3___n__q0;
+  output [63:0] Mmap2Stream_3___rmem3__q0;
+  output Mmap2Stream_3__ap_start;
+  input Mmap2Stream_3__ap_ready;
+  input Mmap2Stream_3__ap_done;
+  input Mmap2Stream_3__ap_idle;
+  output [63:0] Mmap2Stream_4___n__q0;
+  output [63:0] Mmap2Stream_4___rmem4__q0;
+  output Mmap2Stream_4__ap_start;
+  input Mmap2Stream_4__ap_ready;
+  input Mmap2Stream_4__ap_done;
+  input Mmap2Stream_4__ap_idle;
+  output [63:0] Mmap2Stream_5___n__q0;
+  output [63:0] Mmap2Stream_5___rmem5__q0;
+  output Mmap2Stream_5__ap_start;
+  input Mmap2Stream_5__ap_ready;
+  input Mmap2Stream_5__ap_done;
+  input Mmap2Stream_5__ap_idle;
+  output [63:0] Mmap2Stream_6___n__q0;
+  output [63:0] Mmap2Stream_6___rmem6__q0;
+  output Mmap2Stream_6__ap_start;
+  input Mmap2Stream_6__ap_ready;
+  input Mmap2Stream_6__ap_done;
+  input Mmap2Stream_6__ap_idle;
+  output [63:0] Mmap2Stream_7___n__q0;
+  output [63:0] Mmap2Stream_7___rmem7__q0;
+  output Mmap2Stream_7__ap_start;
+  input Mmap2Stream_7__ap_ready;
+  input Mmap2Stream_7__ap_done;
+  input Mmap2Stream_7__ap_idle;
+  output [63:0] Mmap2Stream_8___n__q0;
+  output [63:0] Mmap2Stream_8___rmem8__q0;
+  output Mmap2Stream_8__ap_start;
+  input Mmap2Stream_8__ap_ready;
+  input Mmap2Stream_8__ap_done;
+  input Mmap2Stream_8__ap_idle;
+  output [63:0] Mmap2Stream_9___n__q0;
+  output [63:0] Mmap2Stream_9___rmem9__q0;
+  output Mmap2Stream_9__ap_start;
+  input Mmap2Stream_9__ap_ready;
+  input Mmap2Stream_9__ap_done;
+  input Mmap2Stream_9__ap_idle;
+  output [63:0] Mmap2Stream_10___n__q0;
+  output [63:0] Mmap2Stream_10___rmem10__q0;
+  output Mmap2Stream_10__ap_start;
+  input Mmap2Stream_10__ap_ready;
+  input Mmap2Stream_10__ap_done;
+  input Mmap2Stream_10__ap_idle;
+  output [63:0] Mmap2Stream_11___n__q0;
+  output [63:0] Mmap2Stream_11___rmem11__q0;
+  output Mmap2Stream_11__ap_start;
+  input Mmap2Stream_11__ap_ready;
+  input Mmap2Stream_11__ap_done;
+  input Mmap2Stream_11__ap_idle;
+  output [63:0] Mmap2Stream_12___n__q0;
+  output [63:0] Mmap2Stream_12___rmem12__q0;
+  output Mmap2Stream_12__ap_start;
+  input Mmap2Stream_12__ap_ready;
+  input Mmap2Stream_12__ap_done;
+  input Mmap2Stream_12__ap_idle;
+  output [63:0] Mmap2Stream_13___n__q0;
+  output [63:0] Mmap2Stream_13___rmem13__q0;
+  output Mmap2Stream_13__ap_start;
+  input Mmap2Stream_13__ap_ready;
+  input Mmap2Stream_13__ap_done;
+  input Mmap2Stream_13__ap_idle;
+  output [63:0] Mmap2Stream_14___n__q0;
+  output [63:0] Mmap2Stream_14___rmem14__q0;
+  output Mmap2Stream_14__ap_start;
+  input Mmap2Stream_14__ap_ready;
+  input Mmap2Stream_14__ap_done;
+  input Mmap2Stream_14__ap_idle;
+  output [63:0] Mmap2Stream_15___n__q0;
+  output [63:0] Mmap2Stream_15___rmem15__q0;
+  output Mmap2Stream_15__ap_start;
+  input Mmap2Stream_15__ap_ready;
+  input Mmap2Stream_15__ap_done;
+  input Mmap2Stream_15__ap_idle;
+  output [63:0] Mmap2Stream_16___n__q0;
+  output [63:0] Mmap2Stream_16___rmem16__q0;
+  output Mmap2Stream_16__ap_start;
+  input Mmap2Stream_16__ap_ready;
+  input Mmap2Stream_16__ap_done;
+  input Mmap2Stream_16__ap_idle;
+  output [63:0] Mmap2Stream_17___n__q0;
+  output [63:0] Mmap2Stream_17___rmem17__q0;
+  output Mmap2Stream_17__ap_start;
+  input Mmap2Stream_17__ap_ready;
+  input Mmap2Stream_17__ap_done;
+  input Mmap2Stream_17__ap_idle;
+  output [63:0] Mmap2Stream_18___n__q0;
+  output [63:0] Mmap2Stream_18___rmem18__q0;
+  output Mmap2Stream_18__ap_start;
+  input Mmap2Stream_18__ap_ready;
+  input Mmap2Stream_18__ap_done;
+  input Mmap2Stream_18__ap_idle;
+  output [63:0] Mmap2Stream_19___n__q0;
+  output [63:0] Mmap2Stream_19___rmem19__q0;
+  output Mmap2Stream_19__ap_start;
+  input Mmap2Stream_19__ap_ready;
+  input Mmap2Stream_19__ap_done;
+  input Mmap2Stream_19__ap_idle;
+  output [63:0] Mmap2Stream_20___n__q0;
+  output [63:0] Mmap2Stream_20___rmem20__q0;
+  output Mmap2Stream_20__ap_start;
+  input Mmap2Stream_20__ap_ready;
+  input Mmap2Stream_20__ap_done;
+  input Mmap2Stream_20__ap_idle;
+  output [63:0] Mmap2Stream_21___n__q0;
+  output [63:0] Mmap2Stream_21___rmem21__q0;
+  output Mmap2Stream_21__ap_start;
+  input Mmap2Stream_21__ap_ready;
+  input Mmap2Stream_21__ap_done;
+  input Mmap2Stream_21__ap_idle;
+  output [63:0] Mmap2Stream_22___n__q0;
+  output [63:0] Mmap2Stream_22___rmem22__q0;
+  output Mmap2Stream_22__ap_start;
+  input Mmap2Stream_22__ap_ready;
+  input Mmap2Stream_22__ap_done;
+  input Mmap2Stream_22__ap_idle;
+  output [63:0] Mmap2Stream_23___n__q0;
+  output [63:0] Mmap2Stream_23___rmem23__q0;
+  output Mmap2Stream_23__ap_start;
+  input Mmap2Stream_23__ap_ready;
+  input Mmap2Stream_23__ap_done;
+  input Mmap2Stream_23__ap_idle;
+  output [63:0] Mmap2Stream_24___n__q0;
+  output [63:0] Mmap2Stream_24___rmem24__q0;
+  output Mmap2Stream_24__ap_start;
+  input Mmap2Stream_24__ap_ready;
+  input Mmap2Stream_24__ap_done;
+  input Mmap2Stream_24__ap_idle;
+  output [63:0] Mmap2Stream_25___n__q0;
+  output [63:0] Mmap2Stream_25___rmem25__q0;
+  output Mmap2Stream_25__ap_start;
+  input Mmap2Stream_25__ap_ready;
+  input Mmap2Stream_25__ap_done;
+  input Mmap2Stream_25__ap_idle;
+  output [63:0] Mmap2Stream_26___n__q0;
+  output [63:0] Mmap2Stream_26___rmem26__q0;
+  output Mmap2Stream_26__ap_start;
+  input Mmap2Stream_26__ap_ready;
+  input Mmap2Stream_26__ap_done;
+  input Mmap2Stream_26__ap_idle;
+  output [63:0] Mmap2Stream_27___n__q0;
+  output [63:0] Mmap2Stream_27___rmem27__q0;
+  output Mmap2Stream_27__ap_start;
+  input Mmap2Stream_27__ap_ready;
+  input Mmap2Stream_27__ap_done;
+  input Mmap2Stream_27__ap_idle;
+  output [63:0] Stream2Mmap_0___n__q0;
+  output [63:0] Stream2Mmap_0___rmem0__q0;
+  output Stream2Mmap_0__ap_start;
+  input Stream2Mmap_0__ap_ready;
+  input Stream2Mmap_0__ap_done;
+  input Stream2Mmap_0__ap_idle;
+  output [63:0] Stream2Mmap_1___n__q0;
+  output [63:0] Stream2Mmap_1___rmem1__q0;
+  output Stream2Mmap_1__ap_start;
+  input Stream2Mmap_1__ap_ready;
+  input Stream2Mmap_1__ap_done;
+  input Stream2Mmap_1__ap_idle;
+  output [63:0] Stream2Mmap_2___n__q0;
+  output [63:0] Stream2Mmap_2___rmem2__q0;
+  output Stream2Mmap_2__ap_start;
+  input Stream2Mmap_2__ap_ready;
+  input Stream2Mmap_2__ap_done;
+  input Stream2Mmap_2__ap_idle;
+  output [63:0] Stream2Mmap_3___n__q0;
+  output [63:0] Stream2Mmap_3___rmem3__q0;
+  output Stream2Mmap_3__ap_start;
+  input Stream2Mmap_3__ap_ready;
+  input Stream2Mmap_3__ap_done;
+  input Stream2Mmap_3__ap_idle;
+  output [63:0] Stream2Mmap_4___n__q0;
+  output [63:0] Stream2Mmap_4___rmem4__q0;
+  output Stream2Mmap_4__ap_start;
+  input Stream2Mmap_4__ap_ready;
+  input Stream2Mmap_4__ap_done;
+  input Stream2Mmap_4__ap_idle;
+  output [63:0] Stream2Mmap_5___n__q0;
+  output [63:0] Stream2Mmap_5___rmem5__q0;
+  output Stream2Mmap_5__ap_start;
+  input Stream2Mmap_5__ap_ready;
+  input Stream2Mmap_5__ap_done;
+  input Stream2Mmap_5__ap_idle;
+  output [63:0] Stream2Mmap_6___n__q0;
+  output [63:0] Stream2Mmap_6___rmem6__q0;
+  output Stream2Mmap_6__ap_start;
+  input Stream2Mmap_6__ap_ready;
+  input Stream2Mmap_6__ap_done;
+  input Stream2Mmap_6__ap_idle;
+  output [63:0] Stream2Mmap_7___n__q0;
+  output [63:0] Stream2Mmap_7___rmem7__q0;
+  output Stream2Mmap_7__ap_start;
+  input Stream2Mmap_7__ap_ready;
+  input Stream2Mmap_7__ap_done;
+  input Stream2Mmap_7__ap_idle;
+  output [63:0] Stream2Mmap_8___n__q0;
+  output [63:0] Stream2Mmap_8___rmem8__q0;
+  output Stream2Mmap_8__ap_start;
+  input Stream2Mmap_8__ap_ready;
+  input Stream2Mmap_8__ap_done;
+  input Stream2Mmap_8__ap_idle;
+  output [63:0] Stream2Mmap_9___n__q0;
+  output [63:0] Stream2Mmap_9___rmem9__q0;
+  output Stream2Mmap_9__ap_start;
+  input Stream2Mmap_9__ap_ready;
+  input Stream2Mmap_9__ap_done;
+  input Stream2Mmap_9__ap_idle;
+  output [63:0] Stream2Mmap_10___n__q0;
+  output [63:0] Stream2Mmap_10___rmem10__q0;
+  output Stream2Mmap_10__ap_start;
+  input Stream2Mmap_10__ap_ready;
+  input Stream2Mmap_10__ap_done;
+  input Stream2Mmap_10__ap_idle;
+  output [63:0] Stream2Mmap_11___n__q0;
+  output [63:0] Stream2Mmap_11___rmem11__q0;
+  output Stream2Mmap_11__ap_start;
+  input Stream2Mmap_11__ap_ready;
+  input Stream2Mmap_11__ap_done;
+  input Stream2Mmap_11__ap_idle;
+  output [63:0] Stream2Mmap_12___n__q0;
+  output [63:0] Stream2Mmap_12___rmem12__q0;
+  output Stream2Mmap_12__ap_start;
+  input Stream2Mmap_12__ap_ready;
+  input Stream2Mmap_12__ap_done;
+  input Stream2Mmap_12__ap_idle;
+  output [63:0] Stream2Mmap_13___n__q0;
+  output [63:0] Stream2Mmap_13___rmem13__q0;
+  output Stream2Mmap_13__ap_start;
+  input Stream2Mmap_13__ap_ready;
+  input Stream2Mmap_13__ap_done;
+  input Stream2Mmap_13__ap_idle;
+  output [63:0] Stream2Mmap_14___n__q0;
+  output [63:0] Stream2Mmap_14___rmem14__q0;
+  output Stream2Mmap_14__ap_start;
+  input Stream2Mmap_14__ap_ready;
+  input Stream2Mmap_14__ap_done;
+  input Stream2Mmap_14__ap_idle;
+  output [63:0] Stream2Mmap_15___n__q0;
+  output [63:0] Stream2Mmap_15___rmem15__q0;
+  output Stream2Mmap_15__ap_start;
+  input Stream2Mmap_15__ap_ready;
+  input Stream2Mmap_15__ap_done;
+  input Stream2Mmap_15__ap_idle;
+  output [63:0] Stream2Mmap_16___n__q0;
+  output [63:0] Stream2Mmap_16___rmem16__q0;
+  output Stream2Mmap_16__ap_start;
+  input Stream2Mmap_16__ap_ready;
+  input Stream2Mmap_16__ap_done;
+  input Stream2Mmap_16__ap_idle;
+  output [63:0] Stream2Mmap_17___n__q0;
+  output [63:0] Stream2Mmap_17___rmem17__q0;
+  output Stream2Mmap_17__ap_start;
+  input Stream2Mmap_17__ap_ready;
+  input Stream2Mmap_17__ap_done;
+  input Stream2Mmap_17__ap_idle;
+  output [63:0] Stream2Mmap_18___n__q0;
+  output [63:0] Stream2Mmap_18___rmem18__q0;
+  output Stream2Mmap_18__ap_start;
+  input Stream2Mmap_18__ap_ready;
+  input Stream2Mmap_18__ap_done;
+  input Stream2Mmap_18__ap_idle;
+  output [63:0] Stream2Mmap_19___n__q0;
+  output [63:0] Stream2Mmap_19___rmem19__q0;
+  output Stream2Mmap_19__ap_start;
+  input Stream2Mmap_19__ap_ready;
+  input Stream2Mmap_19__ap_done;
+  input Stream2Mmap_19__ap_idle;
+  output [63:0] Stream2Mmap_20___n__q0;
+  output [63:0] Stream2Mmap_20___rmem20__q0;
+  output Stream2Mmap_20__ap_start;
+  input Stream2Mmap_20__ap_ready;
+  input Stream2Mmap_20__ap_done;
+  input Stream2Mmap_20__ap_idle;
+  output [63:0] Stream2Mmap_21___n__q0;
+  output [63:0] Stream2Mmap_21___rmem21__q0;
+  output Stream2Mmap_21__ap_start;
+  input Stream2Mmap_21__ap_ready;
+  input Stream2Mmap_21__ap_done;
+  input Stream2Mmap_21__ap_idle;
+  output [63:0] Stream2Mmap_22___n__q0;
+  output [63:0] Stream2Mmap_22___rmem22__q0;
+  output Stream2Mmap_22__ap_start;
+  input Stream2Mmap_22__ap_ready;
+  input Stream2Mmap_22__ap_done;
+  input Stream2Mmap_22__ap_idle;
+  output [63:0] Stream2Mmap_23___n__q0;
+  output [63:0] Stream2Mmap_23___rmem23__q0;
+  output Stream2Mmap_23__ap_start;
+  input Stream2Mmap_23__ap_ready;
+  input Stream2Mmap_23__ap_done;
+  input Stream2Mmap_23__ap_idle;
+  output [63:0] Stream2Mmap_24___n__q0;
+  output [63:0] Stream2Mmap_24___rmem24__q0;
+  output Stream2Mmap_24__ap_start;
+  input Stream2Mmap_24__ap_ready;
+  input Stream2Mmap_24__ap_done;
+  input Stream2Mmap_24__ap_idle;
+  output [63:0] Stream2Mmap_25___n__q0;
+  output [63:0] Stream2Mmap_25___rmem25__q0;
+  output Stream2Mmap_25__ap_start;
+  input Stream2Mmap_25__ap_ready;
+  input Stream2Mmap_25__ap_done;
+  input Stream2Mmap_25__ap_idle;
+  output [63:0] Stream2Mmap_26___n__q0;
+  output [63:0] Stream2Mmap_26___rmem26__q0;
+  output Stream2Mmap_26__ap_start;
+  input Stream2Mmap_26__ap_ready;
+  input Stream2Mmap_26__ap_done;
+  input Stream2Mmap_26__ap_idle;
+  output [63:0] Stream2Mmap_27___n__q0;
+  output [63:0] Stream2Mmap_27___rmem27__q0;
+  output Stream2Mmap_27__ap_start;
+  input Stream2Mmap_27__ap_ready;
+  input Stream2Mmap_27__ap_done;
+  input Stream2Mmap_27__ap_idle;
+  output [63:0] yshift_0___n__q0;
+  output yshift_0__ap_start;
+  input yshift_0__ap_ready;
+  input yshift_0__ap_done;
+  input yshift_0__ap_idle;
+  output [63:0] yshift_1___n__q0;
+  output yshift_1__ap_start;
+  input yshift_1__ap_ready;
+  input yshift_1__ap_done;
+  input yshift_1__ap_idle;
+  output [63:0] yshift_2___n__q0;
+  output yshift_2__ap_start;
+  input yshift_2__ap_ready;
+  input yshift_2__ap_done;
+  input yshift_2__ap_idle;
+  output [63:0] yshift_3___n__q0;
+  output yshift_3__ap_start;
+  input yshift_3__ap_ready;
+  input yshift_3__ap_done;
+  input yshift_3__ap_idle;
+  output [63:0] yshift_4___n__q0;
+  output yshift_4__ap_start;
+  input yshift_4__ap_ready;
+  input yshift_4__ap_done;
+  input yshift_4__ap_idle;
+  output [63:0] yshift_5___n__q0;
+  output yshift_5__ap_start;
+  input yshift_5__ap_ready;
+  input yshift_5__ap_done;
+  input yshift_5__ap_idle;
+  output [63:0] yshift_6___n__q0;
+  output yshift_6__ap_start;
+  input yshift_6__ap_ready;
+  input yshift_6__ap_done;
+  input yshift_6__ap_idle;
+  output [63:0] yshift_7___n__q0;
+  output yshift_7__ap_start;
+  input yshift_7__ap_ready;
+  input yshift_7__ap_done;
+  input yshift_7__ap_idle;
+  output [63:0] yshift_8___n__q0;
+  output yshift_8__ap_start;
+  input yshift_8__ap_ready;
+  input yshift_8__ap_done;
+  input yshift_8__ap_idle;
+  output [63:0] yshift_9___n__q0;
+  output yshift_9__ap_start;
+  input yshift_9__ap_ready;
+  input yshift_9__ap_done;
+  input yshift_9__ap_idle;
+  output [63:0] yshift_10___n__q0;
+  output yshift_10__ap_start;
+  input yshift_10__ap_ready;
+  input yshift_10__ap_done;
+  input yshift_10__ap_idle;
+  output [63:0] yshift_11___n__q0;
+  output yshift_11__ap_start;
+  input yshift_11__ap_ready;
+  input yshift_11__ap_done;
+  input yshift_11__ap_idle;
+  output [63:0] yshift_12___n__q0;
+  output yshift_12__ap_start;
+  input yshift_12__ap_ready;
+  input yshift_12__ap_done;
+  input yshift_12__ap_idle;
+  output [63:0] yshift_13___n__q0;
+  output yshift_13__ap_start;
+  input yshift_13__ap_ready;
+  input yshift_13__ap_done;
+  input yshift_13__ap_idle;
+  output [63:0] yshift_14___n__q0;
+  output yshift_14__ap_start;
+  input yshift_14__ap_ready;
+  input yshift_14__ap_done;
+  input yshift_14__ap_idle;
+  output [63:0] yshift_15___n__q0;
+  output yshift_15__ap_start;
+  input yshift_15__ap_ready;
+  input yshift_15__ap_done;
+  input yshift_15__ap_idle;
+  output [63:0] yshift_16___n__q0;
+  output yshift_16__ap_start;
+  input yshift_16__ap_ready;
+  input yshift_16__ap_done;
+  input yshift_16__ap_idle;
+  output [63:0] yshift_17___n__q0;
+  output yshift_17__ap_start;
+  input yshift_17__ap_ready;
+  input yshift_17__ap_done;
+  input yshift_17__ap_idle;
+  output [63:0] yshift_18___n__q0;
+  output yshift_18__ap_start;
+  input yshift_18__ap_ready;
+  input yshift_18__ap_done;
+  input yshift_18__ap_idle;
+  output [63:0] yshift_19___n__q0;
+  output yshift_19__ap_start;
+  input yshift_19__ap_ready;
+  input yshift_19__ap_done;
+  input yshift_19__ap_idle;
+  output [63:0] yshift_20___n__q0;
+  output yshift_20__ap_start;
+  input yshift_20__ap_ready;
+  input yshift_20__ap_done;
+  input yshift_20__ap_idle;
+  output [63:0] yshift_21___n__q0;
+  output yshift_21__ap_start;
+  input yshift_21__ap_ready;
+  input yshift_21__ap_done;
+  input yshift_21__ap_idle;
+  output [63:0] yshift_22___n__q0;
+  output yshift_22__ap_start;
+  input yshift_22__ap_ready;
+  input yshift_22__ap_done;
+  input yshift_22__ap_idle;
+  output [63:0] yshift_23___n__q0;
+  output yshift_23__ap_start;
+  input yshift_23__ap_ready;
+  input yshift_23__ap_done;
+  input yshift_23__ap_idle;
+  output [63:0] yshift_24___n__q0;
+  output yshift_24__ap_start;
+  input yshift_24__ap_ready;
+  input yshift_24__ap_done;
+  input yshift_24__ap_idle;
+  output [63:0] yshift_25___n__q0;
+  output yshift_25__ap_start;
+  input yshift_25__ap_ready;
+  input yshift_25__ap_done;
+  input yshift_25__ap_idle;
+  output [63:0] yshift_26___n__q0;
+  output yshift_26__ap_start;
+  input yshift_26__ap_ready;
+  input yshift_26__ap_done;
+  input yshift_26__ap_idle;
+  output [63:0] yshift_27___n__q0;
+  output yshift_27__ap_start;
+  input yshift_27__ap_ready;
+  input yshift_27__ap_done;
+  input yshift_27__ap_idle;
+  wire [63:0] Mmap2Stream_0___n__q0;
+  wire [63:0] Mmap2Stream_0___rmem0__q0;
+  wire Mmap2Stream_0__ap_start_global__q0;
+  wire Mmap2Stream_0__is_done__q0;
+  wire Mmap2Stream_0__ap_done_global__q0;
+  wire Mmap2Stream_0__ap_start;
+  wire Mmap2Stream_0__ap_ready;
+  wire Mmap2Stream_0__ap_done;
+  wire Mmap2Stream_0__ap_idle;
+  reg [1:0] Mmap2Stream_0__state;
+  wire [63:0] Mmap2Stream_1___n__q0;
+  wire [63:0] Mmap2Stream_1___rmem1__q0;
+  wire Mmap2Stream_1__ap_start_global__q0;
+  wire Mmap2Stream_1__is_done__q0;
+  wire Mmap2Stream_1__ap_done_global__q0;
+  wire Mmap2Stream_1__ap_start;
+  wire Mmap2Stream_1__ap_ready;
+  wire Mmap2Stream_1__ap_done;
+  wire Mmap2Stream_1__ap_idle;
+  reg [1:0] Mmap2Stream_1__state;
+  wire [63:0] Mmap2Stream_2___n__q0;
+  wire [63:0] Mmap2Stream_2___rmem2__q0;
+  wire Mmap2Stream_2__ap_start_global__q0;
+  wire Mmap2Stream_2__is_done__q0;
+  wire Mmap2Stream_2__ap_done_global__q0;
+  wire Mmap2Stream_2__ap_start;
+  wire Mmap2Stream_2__ap_ready;
+  wire Mmap2Stream_2__ap_done;
+  wire Mmap2Stream_2__ap_idle;
+  reg [1:0] Mmap2Stream_2__state;
+  wire [63:0] Mmap2Stream_3___n__q0;
+  wire [63:0] Mmap2Stream_3___rmem3__q0;
+  wire Mmap2Stream_3__ap_start_global__q0;
+  wire Mmap2Stream_3__is_done__q0;
+  wire Mmap2Stream_3__ap_done_global__q0;
+  wire Mmap2Stream_3__ap_start;
+  wire Mmap2Stream_3__ap_ready;
+  wire Mmap2Stream_3__ap_done;
+  wire Mmap2Stream_3__ap_idle;
+  reg [1:0] Mmap2Stream_3__state;
+  wire [63:0] Mmap2Stream_4___n__q0;
+  wire [63:0] Mmap2Stream_4___rmem4__q0;
+  wire Mmap2Stream_4__ap_start_global__q0;
+  wire Mmap2Stream_4__is_done__q0;
+  wire Mmap2Stream_4__ap_done_global__q0;
+  wire Mmap2Stream_4__ap_start;
+  wire Mmap2Stream_4__ap_ready;
+  wire Mmap2Stream_4__ap_done;
+  wire Mmap2Stream_4__ap_idle;
+  reg [1:0] Mmap2Stream_4__state;
+  wire [63:0] Mmap2Stream_5___n__q0;
+  wire [63:0] Mmap2Stream_5___rmem5__q0;
+  wire Mmap2Stream_5__ap_start_global__q0;
+  wire Mmap2Stream_5__is_done__q0;
+  wire Mmap2Stream_5__ap_done_global__q0;
+  wire Mmap2Stream_5__ap_start;
+  wire Mmap2Stream_5__ap_ready;
+  wire Mmap2Stream_5__ap_done;
+  wire Mmap2Stream_5__ap_idle;
+  reg [1:0] Mmap2Stream_5__state;
+  wire [63:0] Mmap2Stream_6___n__q0;
+  wire [63:0] Mmap2Stream_6___rmem6__q0;
+  wire Mmap2Stream_6__ap_start_global__q0;
+  wire Mmap2Stream_6__is_done__q0;
+  wire Mmap2Stream_6__ap_done_global__q0;
+  wire Mmap2Stream_6__ap_start;
+  wire Mmap2Stream_6__ap_ready;
+  wire Mmap2Stream_6__ap_done;
+  wire Mmap2Stream_6__ap_idle;
+  reg [1:0] Mmap2Stream_6__state;
+  wire [63:0] Mmap2Stream_7___n__q0;
+  wire [63:0] Mmap2Stream_7___rmem7__q0;
+  wire Mmap2Stream_7__ap_start_global__q0;
+  wire Mmap2Stream_7__is_done__q0;
+  wire Mmap2Stream_7__ap_done_global__q0;
+  wire Mmap2Stream_7__ap_start;
+  wire Mmap2Stream_7__ap_ready;
+  wire Mmap2Stream_7__ap_done;
+  wire Mmap2Stream_7__ap_idle;
+  reg [1:0] Mmap2Stream_7__state;
+  wire [63:0] Mmap2Stream_8___n__q0;
+  wire [63:0] Mmap2Stream_8___rmem8__q0;
+  wire Mmap2Stream_8__ap_start_global__q0;
+  wire Mmap2Stream_8__is_done__q0;
+  wire Mmap2Stream_8__ap_done_global__q0;
+  wire Mmap2Stream_8__ap_start;
+  wire Mmap2Stream_8__ap_ready;
+  wire Mmap2Stream_8__ap_done;
+  wire Mmap2Stream_8__ap_idle;
+  reg [1:0] Mmap2Stream_8__state;
+  wire [63:0] Mmap2Stream_9___n__q0;
+  wire [63:0] Mmap2Stream_9___rmem9__q0;
+  wire Mmap2Stream_9__ap_start_global__q0;
+  wire Mmap2Stream_9__is_done__q0;
+  wire Mmap2Stream_9__ap_done_global__q0;
+  wire Mmap2Stream_9__ap_start;
+  wire Mmap2Stream_9__ap_ready;
+  wire Mmap2Stream_9__ap_done;
+  wire Mmap2Stream_9__ap_idle;
+  reg [1:0] Mmap2Stream_9__state;
+  wire [63:0] Mmap2Stream_10___n__q0;
+  wire [63:0] Mmap2Stream_10___rmem10__q0;
+  wire Mmap2Stream_10__ap_start_global__q0;
+  wire Mmap2Stream_10__is_done__q0;
+  wire Mmap2Stream_10__ap_done_global__q0;
+  wire Mmap2Stream_10__ap_start;
+  wire Mmap2Stream_10__ap_ready;
+  wire Mmap2Stream_10__ap_done;
+  wire Mmap2Stream_10__ap_idle;
+  reg [1:0] Mmap2Stream_10__state;
+  wire [63:0] Mmap2Stream_11___n__q0;
+  wire [63:0] Mmap2Stream_11___rmem11__q0;
+  wire Mmap2Stream_11__ap_start_global__q0;
+  wire Mmap2Stream_11__is_done__q0;
+  wire Mmap2Stream_11__ap_done_global__q0;
+  wire Mmap2Stream_11__ap_start;
+  wire Mmap2Stream_11__ap_ready;
+  wire Mmap2Stream_11__ap_done;
+  wire Mmap2Stream_11__ap_idle;
+  reg [1:0] Mmap2Stream_11__state;
+  wire [63:0] Mmap2Stream_12___n__q0;
+  wire [63:0] Mmap2Stream_12___rmem12__q0;
+  wire Mmap2Stream_12__ap_start_global__q0;
+  wire Mmap2Stream_12__is_done__q0;
+  wire Mmap2Stream_12__ap_done_global__q0;
+  wire Mmap2Stream_12__ap_start;
+  wire Mmap2Stream_12__ap_ready;
+  wire Mmap2Stream_12__ap_done;
+  wire Mmap2Stream_12__ap_idle;
+  reg [1:0] Mmap2Stream_12__state;
+  wire [63:0] Mmap2Stream_13___n__q0;
+  wire [63:0] Mmap2Stream_13___rmem13__q0;
+  wire Mmap2Stream_13__ap_start_global__q0;
+  wire Mmap2Stream_13__is_done__q0;
+  wire Mmap2Stream_13__ap_done_global__q0;
+  wire Mmap2Stream_13__ap_start;
+  wire Mmap2Stream_13__ap_ready;
+  wire Mmap2Stream_13__ap_done;
+  wire Mmap2Stream_13__ap_idle;
+  reg [1:0] Mmap2Stream_13__state;
+  wire [63:0] Mmap2Stream_14___n__q0;
+  wire [63:0] Mmap2Stream_14___rmem14__q0;
+  wire Mmap2Stream_14__ap_start_global__q0;
+  wire Mmap2Stream_14__is_done__q0;
+  wire Mmap2Stream_14__ap_done_global__q0;
+  wire Mmap2Stream_14__ap_start;
+  wire Mmap2Stream_14__ap_ready;
+  wire Mmap2Stream_14__ap_done;
+  wire Mmap2Stream_14__ap_idle;
+  reg [1:0] Mmap2Stream_14__state;
+  wire [63:0] Mmap2Stream_15___n__q0;
+  wire [63:0] Mmap2Stream_15___rmem15__q0;
+  wire Mmap2Stream_15__ap_start_global__q0;
+  wire Mmap2Stream_15__is_done__q0;
+  wire Mmap2Stream_15__ap_done_global__q0;
+  wire Mmap2Stream_15__ap_start;
+  wire Mmap2Stream_15__ap_ready;
+  wire Mmap2Stream_15__ap_done;
+  wire Mmap2Stream_15__ap_idle;
+  reg [1:0] Mmap2Stream_15__state;
+  wire [63:0] Mmap2Stream_16___n__q0;
+  wire [63:0] Mmap2Stream_16___rmem16__q0;
+  wire Mmap2Stream_16__ap_start_global__q0;
+  wire Mmap2Stream_16__is_done__q0;
+  wire Mmap2Stream_16__ap_done_global__q0;
+  wire Mmap2Stream_16__ap_start;
+  wire Mmap2Stream_16__ap_ready;
+  wire Mmap2Stream_16__ap_done;
+  wire Mmap2Stream_16__ap_idle;
+  reg [1:0] Mmap2Stream_16__state;
+  wire [63:0] Mmap2Stream_17___n__q0;
+  wire [63:0] Mmap2Stream_17___rmem17__q0;
+  wire Mmap2Stream_17__ap_start_global__q0;
+  wire Mmap2Stream_17__is_done__q0;
+  wire Mmap2Stream_17__ap_done_global__q0;
+  wire Mmap2Stream_17__ap_start;
+  wire Mmap2Stream_17__ap_ready;
+  wire Mmap2Stream_17__ap_done;
+  wire Mmap2Stream_17__ap_idle;
+  reg [1:0] Mmap2Stream_17__state;
+  wire [63:0] Mmap2Stream_18___n__q0;
+  wire [63:0] Mmap2Stream_18___rmem18__q0;
+  wire Mmap2Stream_18__ap_start_global__q0;
+  wire Mmap2Stream_18__is_done__q0;
+  wire Mmap2Stream_18__ap_done_global__q0;
+  wire Mmap2Stream_18__ap_start;
+  wire Mmap2Stream_18__ap_ready;
+  wire Mmap2Stream_18__ap_done;
+  wire Mmap2Stream_18__ap_idle;
+  reg [1:0] Mmap2Stream_18__state;
+  wire [63:0] Mmap2Stream_19___n__q0;
+  wire [63:0] Mmap2Stream_19___rmem19__q0;
+  wire Mmap2Stream_19__ap_start_global__q0;
+  wire Mmap2Stream_19__is_done__q0;
+  wire Mmap2Stream_19__ap_done_global__q0;
+  wire Mmap2Stream_19__ap_start;
+  wire Mmap2Stream_19__ap_ready;
+  wire Mmap2Stream_19__ap_done;
+  wire Mmap2Stream_19__ap_idle;
+  reg [1:0] Mmap2Stream_19__state;
+  wire [63:0] Mmap2Stream_20___n__q0;
+  wire [63:0] Mmap2Stream_20___rmem20__q0;
+  wire Mmap2Stream_20__ap_start_global__q0;
+  wire Mmap2Stream_20__is_done__q0;
+  wire Mmap2Stream_20__ap_done_global__q0;
+  wire Mmap2Stream_20__ap_start;
+  wire Mmap2Stream_20__ap_ready;
+  wire Mmap2Stream_20__ap_done;
+  wire Mmap2Stream_20__ap_idle;
+  reg [1:0] Mmap2Stream_20__state;
+  wire [63:0] Mmap2Stream_21___n__q0;
+  wire [63:0] Mmap2Stream_21___rmem21__q0;
+  wire Mmap2Stream_21__ap_start_global__q0;
+  wire Mmap2Stream_21__is_done__q0;
+  wire Mmap2Stream_21__ap_done_global__q0;
+  wire Mmap2Stream_21__ap_start;
+  wire Mmap2Stream_21__ap_ready;
+  wire Mmap2Stream_21__ap_done;
+  wire Mmap2Stream_21__ap_idle;
+  reg [1:0] Mmap2Stream_21__state;
+  wire [63:0] Mmap2Stream_22___n__q0;
+  wire [63:0] Mmap2Stream_22___rmem22__q0;
+  wire Mmap2Stream_22__ap_start_global__q0;
+  wire Mmap2Stream_22__is_done__q0;
+  wire Mmap2Stream_22__ap_done_global__q0;
+  wire Mmap2Stream_22__ap_start;
+  wire Mmap2Stream_22__ap_ready;
+  wire Mmap2Stream_22__ap_done;
+  wire Mmap2Stream_22__ap_idle;
+  reg [1:0] Mmap2Stream_22__state;
+  wire [63:0] Mmap2Stream_23___n__q0;
+  wire [63:0] Mmap2Stream_23___rmem23__q0;
+  wire Mmap2Stream_23__ap_start_global__q0;
+  wire Mmap2Stream_23__is_done__q0;
+  wire Mmap2Stream_23__ap_done_global__q0;
+  wire Mmap2Stream_23__ap_start;
+  wire Mmap2Stream_23__ap_ready;
+  wire Mmap2Stream_23__ap_done;
+  wire Mmap2Stream_23__ap_idle;
+  reg [1:0] Mmap2Stream_23__state;
+  wire [63:0] Mmap2Stream_24___n__q0;
+  wire [63:0] Mmap2Stream_24___rmem24__q0;
+  wire Mmap2Stream_24__ap_start_global__q0;
+  wire Mmap2Stream_24__is_done__q0;
+  wire Mmap2Stream_24__ap_done_global__q0;
+  wire Mmap2Stream_24__ap_start;
+  wire Mmap2Stream_24__ap_ready;
+  wire Mmap2Stream_24__ap_done;
+  wire Mmap2Stream_24__ap_idle;
+  reg [1:0] Mmap2Stream_24__state;
+  wire [63:0] Mmap2Stream_25___n__q0;
+  wire [63:0] Mmap2Stream_25___rmem25__q0;
+  wire Mmap2Stream_25__ap_start_global__q0;
+  wire Mmap2Stream_25__is_done__q0;
+  wire Mmap2Stream_25__ap_done_global__q0;
+  wire Mmap2Stream_25__ap_start;
+  wire Mmap2Stream_25__ap_ready;
+  wire Mmap2Stream_25__ap_done;
+  wire Mmap2Stream_25__ap_idle;
+  reg [1:0] Mmap2Stream_25__state;
+  wire [63:0] Mmap2Stream_26___n__q0;
+  wire [63:0] Mmap2Stream_26___rmem26__q0;
+  wire Mmap2Stream_26__ap_start_global__q0;
+  wire Mmap2Stream_26__is_done__q0;
+  wire Mmap2Stream_26__ap_done_global__q0;
+  wire Mmap2Stream_26__ap_start;
+  wire Mmap2Stream_26__ap_ready;
+  wire Mmap2Stream_26__ap_done;
+  wire Mmap2Stream_26__ap_idle;
+  reg [1:0] Mmap2Stream_26__state;
+  wire [63:0] Mmap2Stream_27___n__q0;
+  wire [63:0] Mmap2Stream_27___rmem27__q0;
+  wire Mmap2Stream_27__ap_start_global__q0;
+  wire Mmap2Stream_27__is_done__q0;
+  wire Mmap2Stream_27__ap_done_global__q0;
+  wire Mmap2Stream_27__ap_start;
+  wire Mmap2Stream_27__ap_ready;
+  wire Mmap2Stream_27__ap_done;
+  wire Mmap2Stream_27__ap_idle;
+  reg [1:0] Mmap2Stream_27__state;
+  wire [63:0] Stream2Mmap_0___n__q0;
+  wire [63:0] Stream2Mmap_0___rmem0__q0;
+  wire Stream2Mmap_0__ap_start_global__q0;
+  wire Stream2Mmap_0__is_done__q0;
+  wire Stream2Mmap_0__ap_done_global__q0;
+  wire Stream2Mmap_0__ap_start;
+  wire Stream2Mmap_0__ap_ready;
+  wire Stream2Mmap_0__ap_done;
+  wire Stream2Mmap_0__ap_idle;
+  reg [1:0] Stream2Mmap_0__state;
+  wire [63:0] Stream2Mmap_1___n__q0;
+  wire [63:0] Stream2Mmap_1___rmem1__q0;
+  wire Stream2Mmap_1__ap_start_global__q0;
+  wire Stream2Mmap_1__is_done__q0;
+  wire Stream2Mmap_1__ap_done_global__q0;
+  wire Stream2Mmap_1__ap_start;
+  wire Stream2Mmap_1__ap_ready;
+  wire Stream2Mmap_1__ap_done;
+  wire Stream2Mmap_1__ap_idle;
+  reg [1:0] Stream2Mmap_1__state;
+  wire [63:0] Stream2Mmap_2___n__q0;
+  wire [63:0] Stream2Mmap_2___rmem2__q0;
+  wire Stream2Mmap_2__ap_start_global__q0;
+  wire Stream2Mmap_2__is_done__q0;
+  wire Stream2Mmap_2__ap_done_global__q0;
+  wire Stream2Mmap_2__ap_start;
+  wire Stream2Mmap_2__ap_ready;
+  wire Stream2Mmap_2__ap_done;
+  wire Stream2Mmap_2__ap_idle;
+  reg [1:0] Stream2Mmap_2__state;
+  wire [63:0] Stream2Mmap_3___n__q0;
+  wire [63:0] Stream2Mmap_3___rmem3__q0;
+  wire Stream2Mmap_3__ap_start_global__q0;
+  wire Stream2Mmap_3__is_done__q0;
+  wire Stream2Mmap_3__ap_done_global__q0;
+  wire Stream2Mmap_3__ap_start;
+  wire Stream2Mmap_3__ap_ready;
+  wire Stream2Mmap_3__ap_done;
+  wire Stream2Mmap_3__ap_idle;
+  reg [1:0] Stream2Mmap_3__state;
+  wire [63:0] Stream2Mmap_4___n__q0;
+  wire [63:0] Stream2Mmap_4___rmem4__q0;
+  wire Stream2Mmap_4__ap_start_global__q0;
+  wire Stream2Mmap_4__is_done__q0;
+  wire Stream2Mmap_4__ap_done_global__q0;
+  wire Stream2Mmap_4__ap_start;
+  wire Stream2Mmap_4__ap_ready;
+  wire Stream2Mmap_4__ap_done;
+  wire Stream2Mmap_4__ap_idle;
+  reg [1:0] Stream2Mmap_4__state;
+  wire [63:0] Stream2Mmap_5___n__q0;
+  wire [63:0] Stream2Mmap_5___rmem5__q0;
+  wire Stream2Mmap_5__ap_start_global__q0;
+  wire Stream2Mmap_5__is_done__q0;
+  wire Stream2Mmap_5__ap_done_global__q0;
+  wire Stream2Mmap_5__ap_start;
+  wire Stream2Mmap_5__ap_ready;
+  wire Stream2Mmap_5__ap_done;
+  wire Stream2Mmap_5__ap_idle;
+  reg [1:0] Stream2Mmap_5__state;
+  wire [63:0] Stream2Mmap_6___n__q0;
+  wire [63:0] Stream2Mmap_6___rmem6__q0;
+  wire Stream2Mmap_6__ap_start_global__q0;
+  wire Stream2Mmap_6__is_done__q0;
+  wire Stream2Mmap_6__ap_done_global__q0;
+  wire Stream2Mmap_6__ap_start;
+  wire Stream2Mmap_6__ap_ready;
+  wire Stream2Mmap_6__ap_done;
+  wire Stream2Mmap_6__ap_idle;
+  reg [1:0] Stream2Mmap_6__state;
+  wire [63:0] Stream2Mmap_7___n__q0;
+  wire [63:0] Stream2Mmap_7___rmem7__q0;
+  wire Stream2Mmap_7__ap_start_global__q0;
+  wire Stream2Mmap_7__is_done__q0;
+  wire Stream2Mmap_7__ap_done_global__q0;
+  wire Stream2Mmap_7__ap_start;
+  wire Stream2Mmap_7__ap_ready;
+  wire Stream2Mmap_7__ap_done;
+  wire Stream2Mmap_7__ap_idle;
+  reg [1:0] Stream2Mmap_7__state;
+  wire [63:0] Stream2Mmap_8___n__q0;
+  wire [63:0] Stream2Mmap_8___rmem8__q0;
+  wire Stream2Mmap_8__ap_start_global__q0;
+  wire Stream2Mmap_8__is_done__q0;
+  wire Stream2Mmap_8__ap_done_global__q0;
+  wire Stream2Mmap_8__ap_start;
+  wire Stream2Mmap_8__ap_ready;
+  wire Stream2Mmap_8__ap_done;
+  wire Stream2Mmap_8__ap_idle;
+  reg [1:0] Stream2Mmap_8__state;
+  wire [63:0] Stream2Mmap_9___n__q0;
+  wire [63:0] Stream2Mmap_9___rmem9__q0;
+  wire Stream2Mmap_9__ap_start_global__q0;
+  wire Stream2Mmap_9__is_done__q0;
+  wire Stream2Mmap_9__ap_done_global__q0;
+  wire Stream2Mmap_9__ap_start;
+  wire Stream2Mmap_9__ap_ready;
+  wire Stream2Mmap_9__ap_done;
+  wire Stream2Mmap_9__ap_idle;
+  reg [1:0] Stream2Mmap_9__state;
+  wire [63:0] Stream2Mmap_10___n__q0;
+  wire [63:0] Stream2Mmap_10___rmem10__q0;
+  wire Stream2Mmap_10__ap_start_global__q0;
+  wire Stream2Mmap_10__is_done__q0;
+  wire Stream2Mmap_10__ap_done_global__q0;
+  wire Stream2Mmap_10__ap_start;
+  wire Stream2Mmap_10__ap_ready;
+  wire Stream2Mmap_10__ap_done;
+  wire Stream2Mmap_10__ap_idle;
+  reg [1:0] Stream2Mmap_10__state;
+  wire [63:0] Stream2Mmap_11___n__q0;
+  wire [63:0] Stream2Mmap_11___rmem11__q0;
+  wire Stream2Mmap_11__ap_start_global__q0;
+  wire Stream2Mmap_11__is_done__q0;
+  wire Stream2Mmap_11__ap_done_global__q0;
+  wire Stream2Mmap_11__ap_start;
+  wire Stream2Mmap_11__ap_ready;
+  wire Stream2Mmap_11__ap_done;
+  wire Stream2Mmap_11__ap_idle;
+  reg [1:0] Stream2Mmap_11__state;
+  wire [63:0] Stream2Mmap_12___n__q0;
+  wire [63:0] Stream2Mmap_12___rmem12__q0;
+  wire Stream2Mmap_12__ap_start_global__q0;
+  wire Stream2Mmap_12__is_done__q0;
+  wire Stream2Mmap_12__ap_done_global__q0;
+  wire Stream2Mmap_12__ap_start;
+  wire Stream2Mmap_12__ap_ready;
+  wire Stream2Mmap_12__ap_done;
+  wire Stream2Mmap_12__ap_idle;
+  reg [1:0] Stream2Mmap_12__state;
+  wire [63:0] Stream2Mmap_13___n__q0;
+  wire [63:0] Stream2Mmap_13___rmem13__q0;
+  wire Stream2Mmap_13__ap_start_global__q0;
+  wire Stream2Mmap_13__is_done__q0;
+  wire Stream2Mmap_13__ap_done_global__q0;
+  wire Stream2Mmap_13__ap_start;
+  wire Stream2Mmap_13__ap_ready;
+  wire Stream2Mmap_13__ap_done;
+  wire Stream2Mmap_13__ap_idle;
+  reg [1:0] Stream2Mmap_13__state;
+  wire [63:0] Stream2Mmap_14___n__q0;
+  wire [63:0] Stream2Mmap_14___rmem14__q0;
+  wire Stream2Mmap_14__ap_start_global__q0;
+  wire Stream2Mmap_14__is_done__q0;
+  wire Stream2Mmap_14__ap_done_global__q0;
+  wire Stream2Mmap_14__ap_start;
+  wire Stream2Mmap_14__ap_ready;
+  wire Stream2Mmap_14__ap_done;
+  wire Stream2Mmap_14__ap_idle;
+  reg [1:0] Stream2Mmap_14__state;
+  wire [63:0] Stream2Mmap_15___n__q0;
+  wire [63:0] Stream2Mmap_15___rmem15__q0;
+  wire Stream2Mmap_15__ap_start_global__q0;
+  wire Stream2Mmap_15__is_done__q0;
+  wire Stream2Mmap_15__ap_done_global__q0;
+  wire Stream2Mmap_15__ap_start;
+  wire Stream2Mmap_15__ap_ready;
+  wire Stream2Mmap_15__ap_done;
+  wire Stream2Mmap_15__ap_idle;
+  reg [1:0] Stream2Mmap_15__state;
+  wire [63:0] Stream2Mmap_16___n__q0;
+  wire [63:0] Stream2Mmap_16___rmem16__q0;
+  wire Stream2Mmap_16__ap_start_global__q0;
+  wire Stream2Mmap_16__is_done__q0;
+  wire Stream2Mmap_16__ap_done_global__q0;
+  wire Stream2Mmap_16__ap_start;
+  wire Stream2Mmap_16__ap_ready;
+  wire Stream2Mmap_16__ap_done;
+  wire Stream2Mmap_16__ap_idle;
+  reg [1:0] Stream2Mmap_16__state;
+  wire [63:0] Stream2Mmap_17___n__q0;
+  wire [63:0] Stream2Mmap_17___rmem17__q0;
+  wire Stream2Mmap_17__ap_start_global__q0;
+  wire Stream2Mmap_17__is_done__q0;
+  wire Stream2Mmap_17__ap_done_global__q0;
+  wire Stream2Mmap_17__ap_start;
+  wire Stream2Mmap_17__ap_ready;
+  wire Stream2Mmap_17__ap_done;
+  wire Stream2Mmap_17__ap_idle;
+  reg [1:0] Stream2Mmap_17__state;
+  wire [63:0] Stream2Mmap_18___n__q0;
+  wire [63:0] Stream2Mmap_18___rmem18__q0;
+  wire Stream2Mmap_18__ap_start_global__q0;
+  wire Stream2Mmap_18__is_done__q0;
+  wire Stream2Mmap_18__ap_done_global__q0;
+  wire Stream2Mmap_18__ap_start;
+  wire Stream2Mmap_18__ap_ready;
+  wire Stream2Mmap_18__ap_done;
+  wire Stream2Mmap_18__ap_idle;
+  reg [1:0] Stream2Mmap_18__state;
+  wire [63:0] Stream2Mmap_19___n__q0;
+  wire [63:0] Stream2Mmap_19___rmem19__q0;
+  wire Stream2Mmap_19__ap_start_global__q0;
+  wire Stream2Mmap_19__is_done__q0;
+  wire Stream2Mmap_19__ap_done_global__q0;
+  wire Stream2Mmap_19__ap_start;
+  wire Stream2Mmap_19__ap_ready;
+  wire Stream2Mmap_19__ap_done;
+  wire Stream2Mmap_19__ap_idle;
+  reg [1:0] Stream2Mmap_19__state;
+  wire [63:0] Stream2Mmap_20___n__q0;
+  wire [63:0] Stream2Mmap_20___rmem20__q0;
+  wire Stream2Mmap_20__ap_start_global__q0;
+  wire Stream2Mmap_20__is_done__q0;
+  wire Stream2Mmap_20__ap_done_global__q0;
+  wire Stream2Mmap_20__ap_start;
+  wire Stream2Mmap_20__ap_ready;
+  wire Stream2Mmap_20__ap_done;
+  wire Stream2Mmap_20__ap_idle;
+  reg [1:0] Stream2Mmap_20__state;
+  wire [63:0] Stream2Mmap_21___n__q0;
+  wire [63:0] Stream2Mmap_21___rmem21__q0;
+  wire Stream2Mmap_21__ap_start_global__q0;
+  wire Stream2Mmap_21__is_done__q0;
+  wire Stream2Mmap_21__ap_done_global__q0;
+  wire Stream2Mmap_21__ap_start;
+  wire Stream2Mmap_21__ap_ready;
+  wire Stream2Mmap_21__ap_done;
+  wire Stream2Mmap_21__ap_idle;
+  reg [1:0] Stream2Mmap_21__state;
+  wire [63:0] Stream2Mmap_22___n__q0;
+  wire [63:0] Stream2Mmap_22___rmem22__q0;
+  wire Stream2Mmap_22__ap_start_global__q0;
+  wire Stream2Mmap_22__is_done__q0;
+  wire Stream2Mmap_22__ap_done_global__q0;
+  wire Stream2Mmap_22__ap_start;
+  wire Stream2Mmap_22__ap_ready;
+  wire Stream2Mmap_22__ap_done;
+  wire Stream2Mmap_22__ap_idle;
+  reg [1:0] Stream2Mmap_22__state;
+  wire [63:0] Stream2Mmap_23___n__q0;
+  wire [63:0] Stream2Mmap_23___rmem23__q0;
+  wire Stream2Mmap_23__ap_start_global__q0;
+  wire Stream2Mmap_23__is_done__q0;
+  wire Stream2Mmap_23__ap_done_global__q0;
+  wire Stream2Mmap_23__ap_start;
+  wire Stream2Mmap_23__ap_ready;
+  wire Stream2Mmap_23__ap_done;
+  wire Stream2Mmap_23__ap_idle;
+  reg [1:0] Stream2Mmap_23__state;
+  wire [63:0] Stream2Mmap_24___n__q0;
+  wire [63:0] Stream2Mmap_24___rmem24__q0;
+  wire Stream2Mmap_24__ap_start_global__q0;
+  wire Stream2Mmap_24__is_done__q0;
+  wire Stream2Mmap_24__ap_done_global__q0;
+  wire Stream2Mmap_24__ap_start;
+  wire Stream2Mmap_24__ap_ready;
+  wire Stream2Mmap_24__ap_done;
+  wire Stream2Mmap_24__ap_idle;
+  reg [1:0] Stream2Mmap_24__state;
+  wire [63:0] Stream2Mmap_25___n__q0;
+  wire [63:0] Stream2Mmap_25___rmem25__q0;
+  wire Stream2Mmap_25__ap_start_global__q0;
+  wire Stream2Mmap_25__is_done__q0;
+  wire Stream2Mmap_25__ap_done_global__q0;
+  wire Stream2Mmap_25__ap_start;
+  wire Stream2Mmap_25__ap_ready;
+  wire Stream2Mmap_25__ap_done;
+  wire Stream2Mmap_25__ap_idle;
+  reg [1:0] Stream2Mmap_25__state;
+  wire [63:0] Stream2Mmap_26___n__q0;
+  wire [63:0] Stream2Mmap_26___rmem26__q0;
+  wire Stream2Mmap_26__ap_start_global__q0;
+  wire Stream2Mmap_26__is_done__q0;
+  wire Stream2Mmap_26__ap_done_global__q0;
+  wire Stream2Mmap_26__ap_start;
+  wire Stream2Mmap_26__ap_ready;
+  wire Stream2Mmap_26__ap_done;
+  wire Stream2Mmap_26__ap_idle;
+  reg [1:0] Stream2Mmap_26__state;
+  wire [63:0] Stream2Mmap_27___n__q0;
+  wire [63:0] Stream2Mmap_27___rmem27__q0;
+  wire Stream2Mmap_27__ap_start_global__q0;
+  wire Stream2Mmap_27__is_done__q0;
+  wire Stream2Mmap_27__ap_done_global__q0;
+  wire Stream2Mmap_27__ap_start;
+  wire Stream2Mmap_27__ap_ready;
+  wire Stream2Mmap_27__ap_done;
+  wire Stream2Mmap_27__ap_idle;
+  reg [1:0] Stream2Mmap_27__state;
+  wire [63:0] yshift_0___n__q0;
+  wire yshift_0__ap_start_global__q0;
+  wire yshift_0__is_done__q0;
+  wire yshift_0__ap_done_global__q0;
+  wire yshift_0__ap_start;
+  wire yshift_0__ap_ready;
+  wire yshift_0__ap_done;
+  wire yshift_0__ap_idle;
+  reg [1:0] yshift_0__state;
+  wire [63:0] yshift_1___n__q0;
+  wire yshift_1__ap_start_global__q0;
+  wire yshift_1__is_done__q0;
+  wire yshift_1__ap_done_global__q0;
+  wire yshift_1__ap_start;
+  wire yshift_1__ap_ready;
+  wire yshift_1__ap_done;
+  wire yshift_1__ap_idle;
+  reg [1:0] yshift_1__state;
+  wire [63:0] yshift_2___n__q0;
+  wire yshift_2__ap_start_global__q0;
+  wire yshift_2__is_done__q0;
+  wire yshift_2__ap_done_global__q0;
+  wire yshift_2__ap_start;
+  wire yshift_2__ap_ready;
+  wire yshift_2__ap_done;
+  wire yshift_2__ap_idle;
+  reg [1:0] yshift_2__state;
+  wire [63:0] yshift_3___n__q0;
+  wire yshift_3__ap_start_global__q0;
+  wire yshift_3__is_done__q0;
+  wire yshift_3__ap_done_global__q0;
+  wire yshift_3__ap_start;
+  wire yshift_3__ap_ready;
+  wire yshift_3__ap_done;
+  wire yshift_3__ap_idle;
+  reg [1:0] yshift_3__state;
+  wire [63:0] yshift_4___n__q0;
+  wire yshift_4__ap_start_global__q0;
+  wire yshift_4__is_done__q0;
+  wire yshift_4__ap_done_global__q0;
+  wire yshift_4__ap_start;
+  wire yshift_4__ap_ready;
+  wire yshift_4__ap_done;
+  wire yshift_4__ap_idle;
+  reg [1:0] yshift_4__state;
+  wire [63:0] yshift_5___n__q0;
+  wire yshift_5__ap_start_global__q0;
+  wire yshift_5__is_done__q0;
+  wire yshift_5__ap_done_global__q0;
+  wire yshift_5__ap_start;
+  wire yshift_5__ap_ready;
+  wire yshift_5__ap_done;
+  wire yshift_5__ap_idle;
+  reg [1:0] yshift_5__state;
+  wire [63:0] yshift_6___n__q0;
+  wire yshift_6__ap_start_global__q0;
+  wire yshift_6__is_done__q0;
+  wire yshift_6__ap_done_global__q0;
+  wire yshift_6__ap_start;
+  wire yshift_6__ap_ready;
+  wire yshift_6__ap_done;
+  wire yshift_6__ap_idle;
+  reg [1:0] yshift_6__state;
+  wire [63:0] yshift_7___n__q0;
+  wire yshift_7__ap_start_global__q0;
+  wire yshift_7__is_done__q0;
+  wire yshift_7__ap_done_global__q0;
+  wire yshift_7__ap_start;
+  wire yshift_7__ap_ready;
+  wire yshift_7__ap_done;
+  wire yshift_7__ap_idle;
+  reg [1:0] yshift_7__state;
+  wire [63:0] yshift_8___n__q0;
+  wire yshift_8__ap_start_global__q0;
+  wire yshift_8__is_done__q0;
+  wire yshift_8__ap_done_global__q0;
+  wire yshift_8__ap_start;
+  wire yshift_8__ap_ready;
+  wire yshift_8__ap_done;
+  wire yshift_8__ap_idle;
+  reg [1:0] yshift_8__state;
+  wire [63:0] yshift_9___n__q0;
+  wire yshift_9__ap_start_global__q0;
+  wire yshift_9__is_done__q0;
+  wire yshift_9__ap_done_global__q0;
+  wire yshift_9__ap_start;
+  wire yshift_9__ap_ready;
+  wire yshift_9__ap_done;
+  wire yshift_9__ap_idle;
+  reg [1:0] yshift_9__state;
+  wire [63:0] yshift_10___n__q0;
+  wire yshift_10__ap_start_global__q0;
+  wire yshift_10__is_done__q0;
+  wire yshift_10__ap_done_global__q0;
+  wire yshift_10__ap_start;
+  wire yshift_10__ap_ready;
+  wire yshift_10__ap_done;
+  wire yshift_10__ap_idle;
+  reg [1:0] yshift_10__state;
+  wire [63:0] yshift_11___n__q0;
+  wire yshift_11__ap_start_global__q0;
+  wire yshift_11__is_done__q0;
+  wire yshift_11__ap_done_global__q0;
+  wire yshift_11__ap_start;
+  wire yshift_11__ap_ready;
+  wire yshift_11__ap_done;
+  wire yshift_11__ap_idle;
+  reg [1:0] yshift_11__state;
+  wire [63:0] yshift_12___n__q0;
+  wire yshift_12__ap_start_global__q0;
+  wire yshift_12__is_done__q0;
+  wire yshift_12__ap_done_global__q0;
+  wire yshift_12__ap_start;
+  wire yshift_12__ap_ready;
+  wire yshift_12__ap_done;
+  wire yshift_12__ap_idle;
+  reg [1:0] yshift_12__state;
+  wire [63:0] yshift_13___n__q0;
+  wire yshift_13__ap_start_global__q0;
+  wire yshift_13__is_done__q0;
+  wire yshift_13__ap_done_global__q0;
+  wire yshift_13__ap_start;
+  wire yshift_13__ap_ready;
+  wire yshift_13__ap_done;
+  wire yshift_13__ap_idle;
+  reg [1:0] yshift_13__state;
+  wire [63:0] yshift_14___n__q0;
+  wire yshift_14__ap_start_global__q0;
+  wire yshift_14__is_done__q0;
+  wire yshift_14__ap_done_global__q0;
+  wire yshift_14__ap_start;
+  wire yshift_14__ap_ready;
+  wire yshift_14__ap_done;
+  wire yshift_14__ap_idle;
+  reg [1:0] yshift_14__state;
+  wire [63:0] yshift_15___n__q0;
+  wire yshift_15__ap_start_global__q0;
+  wire yshift_15__is_done__q0;
+  wire yshift_15__ap_done_global__q0;
+  wire yshift_15__ap_start;
+  wire yshift_15__ap_ready;
+  wire yshift_15__ap_done;
+  wire yshift_15__ap_idle;
+  reg [1:0] yshift_15__state;
+  wire [63:0] yshift_16___n__q0;
+  wire yshift_16__ap_start_global__q0;
+  wire yshift_16__is_done__q0;
+  wire yshift_16__ap_done_global__q0;
+  wire yshift_16__ap_start;
+  wire yshift_16__ap_ready;
+  wire yshift_16__ap_done;
+  wire yshift_16__ap_idle;
+  reg [1:0] yshift_16__state;
+  wire [63:0] yshift_17___n__q0;
+  wire yshift_17__ap_start_global__q0;
+  wire yshift_17__is_done__q0;
+  wire yshift_17__ap_done_global__q0;
+  wire yshift_17__ap_start;
+  wire yshift_17__ap_ready;
+  wire yshift_17__ap_done;
+  wire yshift_17__ap_idle;
+  reg [1:0] yshift_17__state;
+  wire [63:0] yshift_18___n__q0;
+  wire yshift_18__ap_start_global__q0;
+  wire yshift_18__is_done__q0;
+  wire yshift_18__ap_done_global__q0;
+  wire yshift_18__ap_start;
+  wire yshift_18__ap_ready;
+  wire yshift_18__ap_done;
+  wire yshift_18__ap_idle;
+  reg [1:0] yshift_18__state;
+  wire [63:0] yshift_19___n__q0;
+  wire yshift_19__ap_start_global__q0;
+  wire yshift_19__is_done__q0;
+  wire yshift_19__ap_done_global__q0;
+  wire yshift_19__ap_start;
+  wire yshift_19__ap_ready;
+  wire yshift_19__ap_done;
+  wire yshift_19__ap_idle;
+  reg [1:0] yshift_19__state;
+  wire [63:0] yshift_20___n__q0;
+  wire yshift_20__ap_start_global__q0;
+  wire yshift_20__is_done__q0;
+  wire yshift_20__ap_done_global__q0;
+  wire yshift_20__ap_start;
+  wire yshift_20__ap_ready;
+  wire yshift_20__ap_done;
+  wire yshift_20__ap_idle;
+  reg [1:0] yshift_20__state;
+  wire [63:0] yshift_21___n__q0;
+  wire yshift_21__ap_start_global__q0;
+  wire yshift_21__is_done__q0;
+  wire yshift_21__ap_done_global__q0;
+  wire yshift_21__ap_start;
+  wire yshift_21__ap_ready;
+  wire yshift_21__ap_done;
+  wire yshift_21__ap_idle;
+  reg [1:0] yshift_21__state;
+  wire [63:0] yshift_22___n__q0;
+  wire yshift_22__ap_start_global__q0;
+  wire yshift_22__is_done__q0;
+  wire yshift_22__ap_done_global__q0;
+  wire yshift_22__ap_start;
+  wire yshift_22__ap_ready;
+  wire yshift_22__ap_done;
+  wire yshift_22__ap_idle;
+  reg [1:0] yshift_22__state;
+  wire [63:0] yshift_23___n__q0;
+  wire yshift_23__ap_start_global__q0;
+  wire yshift_23__is_done__q0;
+  wire yshift_23__ap_done_global__q0;
+  wire yshift_23__ap_start;
+  wire yshift_23__ap_ready;
+  wire yshift_23__ap_done;
+  wire yshift_23__ap_idle;
+  reg [1:0] yshift_23__state;
+  wire [63:0] yshift_24___n__q0;
+  wire yshift_24__ap_start_global__q0;
+  wire yshift_24__is_done__q0;
+  wire yshift_24__ap_done_global__q0;
+  wire yshift_24__ap_start;
+  wire yshift_24__ap_ready;
+  wire yshift_24__ap_done;
+  wire yshift_24__ap_idle;
+  reg [1:0] yshift_24__state;
+  wire [63:0] yshift_25___n__q0;
+  wire yshift_25__ap_start_global__q0;
+  wire yshift_25__is_done__q0;
+  wire yshift_25__ap_done_global__q0;
+  wire yshift_25__ap_start;
+  wire yshift_25__ap_ready;
+  wire yshift_25__ap_done;
+  wire yshift_25__ap_idle;
+  reg [1:0] yshift_25__state;
+  wire [63:0] yshift_26___n__q0;
+  wire yshift_26__ap_start_global__q0;
+  wire yshift_26__is_done__q0;
+  wire yshift_26__ap_done_global__q0;
+  wire yshift_26__ap_start;
+  wire yshift_26__ap_ready;
+  wire yshift_26__ap_done;
+  wire yshift_26__ap_idle;
+  reg [1:0] yshift_26__state;
+  wire [63:0] yshift_27___n__q0;
+  wire yshift_27__ap_start_global__q0;
+  wire yshift_27__is_done__q0;
+  wire yshift_27__ap_done_global__q0;
+  wire yshift_27__ap_start;
+  wire yshift_27__ap_ready;
+  wire yshift_27__ap_done;
+  wire yshift_27__ap_idle;
+  reg [1:0] yshift_27__state;
+  reg [1:0] tapa_state;
+  reg [0:0] countdown;
+  wire ap_start__q0;
+  wire ap_done__q0;
+  assign Mmap2Stream_0___n__q0 = n;
+  assign Mmap2Stream_0___rmem0__q0 = rmem0;
+  assign Mmap2Stream_0__ap_start_global__q0 = ap_start__q0;
+  assign Mmap2Stream_0__is_done__q0 = (Mmap2Stream_0__state == 2'b10);
+  assign Mmap2Stream_0__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Mmap2Stream_0__state <= 2'b00;
+    end else begin
+      if(Mmap2Stream_0__state == 2'b00) begin
+        if(Mmap2Stream_0__ap_start_global__q0) begin
+          Mmap2Stream_0__state <= 2'b01;
+        end
+      end
+      if(Mmap2Stream_0__state == 2'b01) begin
+        if(Mmap2Stream_0__ap_ready) begin
+          if(Mmap2Stream_0__ap_done) begin
+            Mmap2Stream_0__state <= 2'b10;
+          end else begin
+            Mmap2Stream_0__state <= 2'b11;
+          end
+        end
+      end
+      if(Mmap2Stream_0__state == 2'b11) begin
+        if(Mmap2Stream_0__ap_done) begin
+          Mmap2Stream_0__state <= 2'b10;
+        end
+      end
+      if(Mmap2Stream_0__state == 2'b10) begin
+        if(Mmap2Stream_0__ap_done_global__q0) begin
+          Mmap2Stream_0__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Mmap2Stream_0__ap_start = (Mmap2Stream_0__state == 2'b01);
+  assign Mmap2Stream_1___n__q0 = n;
+  assign Mmap2Stream_1___rmem1__q0 = rmem1;
+  assign Mmap2Stream_1__ap_start_global__q0 = ap_start__q0;
+  assign Mmap2Stream_1__is_done__q0 = (Mmap2Stream_1__state == 2'b10);
+  assign Mmap2Stream_1__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Mmap2Stream_1__state <= 2'b00;
+    end else begin
+      if(Mmap2Stream_1__state == 2'b00) begin
+        if(Mmap2Stream_1__ap_start_global__q0) begin
+          Mmap2Stream_1__state <= 2'b01;
+        end
+      end
+      if(Mmap2Stream_1__state == 2'b01) begin
+        if(Mmap2Stream_1__ap_ready) begin
+          if(Mmap2Stream_1__ap_done) begin
+            Mmap2Stream_1__state <= 2'b10;
+          end else begin
+            Mmap2Stream_1__state <= 2'b11;
+          end
+        end
+      end
+      if(Mmap2Stream_1__state == 2'b11) begin
+        if(Mmap2Stream_1__ap_done) begin
+          Mmap2Stream_1__state <= 2'b10;
+        end
+      end
+      if(Mmap2Stream_1__state == 2'b10) begin
+        if(Mmap2Stream_1__ap_done_global__q0) begin
+          Mmap2Stream_1__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Mmap2Stream_1__ap_start = (Mmap2Stream_1__state == 2'b01);
+  assign Mmap2Stream_2___n__q0 = n;
+  assign Mmap2Stream_2___rmem2__q0 = rmem2;
+  assign Mmap2Stream_2__ap_start_global__q0 = ap_start__q0;
+  assign Mmap2Stream_2__is_done__q0 = (Mmap2Stream_2__state == 2'b10);
+  assign Mmap2Stream_2__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Mmap2Stream_2__state <= 2'b00;
+    end else begin
+      if(Mmap2Stream_2__state == 2'b00) begin
+        if(Mmap2Stream_2__ap_start_global__q0) begin
+          Mmap2Stream_2__state <= 2'b01;
+        end
+      end
+      if(Mmap2Stream_2__state == 2'b01) begin
+        if(Mmap2Stream_2__ap_ready) begin
+          if(Mmap2Stream_2__ap_done) begin
+            Mmap2Stream_2__state <= 2'b10;
+          end else begin
+            Mmap2Stream_2__state <= 2'b11;
+          end
+        end
+      end
+      if(Mmap2Stream_2__state == 2'b11) begin
+        if(Mmap2Stream_2__ap_done) begin
+          Mmap2Stream_2__state <= 2'b10;
+        end
+      end
+      if(Mmap2Stream_2__state == 2'b10) begin
+        if(Mmap2Stream_2__ap_done_global__q0) begin
+          Mmap2Stream_2__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Mmap2Stream_2__ap_start = (Mmap2Stream_2__state == 2'b01);
+  assign Mmap2Stream_3___n__q0 = n;
+  assign Mmap2Stream_3___rmem3__q0 = rmem3;
+  assign Mmap2Stream_3__ap_start_global__q0 = ap_start__q0;
+  assign Mmap2Stream_3__is_done__q0 = (Mmap2Stream_3__state == 2'b10);
+  assign Mmap2Stream_3__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Mmap2Stream_3__state <= 2'b00;
+    end else begin
+      if(Mmap2Stream_3__state == 2'b00) begin
+        if(Mmap2Stream_3__ap_start_global__q0) begin
+          Mmap2Stream_3__state <= 2'b01;
+        end
+      end
+      if(Mmap2Stream_3__state == 2'b01) begin
+        if(Mmap2Stream_3__ap_ready) begin
+          if(Mmap2Stream_3__ap_done) begin
+            Mmap2Stream_3__state <= 2'b10;
+          end else begin
+            Mmap2Stream_3__state <= 2'b11;
+          end
+        end
+      end
+      if(Mmap2Stream_3__state == 2'b11) begin
+        if(Mmap2Stream_3__ap_done) begin
+          Mmap2Stream_3__state <= 2'b10;
+        end
+      end
+      if(Mmap2Stream_3__state == 2'b10) begin
+        if(Mmap2Stream_3__ap_done_global__q0) begin
+          Mmap2Stream_3__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Mmap2Stream_3__ap_start = (Mmap2Stream_3__state == 2'b01);
+  assign Mmap2Stream_4___n__q0 = n;
+  assign Mmap2Stream_4___rmem4__q0 = rmem4;
+  assign Mmap2Stream_4__ap_start_global__q0 = ap_start__q0;
+  assign Mmap2Stream_4__is_done__q0 = (Mmap2Stream_4__state == 2'b10);
+  assign Mmap2Stream_4__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Mmap2Stream_4__state <= 2'b00;
+    end else begin
+      if(Mmap2Stream_4__state == 2'b00) begin
+        if(Mmap2Stream_4__ap_start_global__q0) begin
+          Mmap2Stream_4__state <= 2'b01;
+        end
+      end
+      if(Mmap2Stream_4__state == 2'b01) begin
+        if(Mmap2Stream_4__ap_ready) begin
+          if(Mmap2Stream_4__ap_done) begin
+            Mmap2Stream_4__state <= 2'b10;
+          end else begin
+            Mmap2Stream_4__state <= 2'b11;
+          end
+        end
+      end
+      if(Mmap2Stream_4__state == 2'b11) begin
+        if(Mmap2Stream_4__ap_done) begin
+          Mmap2Stream_4__state <= 2'b10;
+        end
+      end
+      if(Mmap2Stream_4__state == 2'b10) begin
+        if(Mmap2Stream_4__ap_done_global__q0) begin
+          Mmap2Stream_4__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Mmap2Stream_4__ap_start = (Mmap2Stream_4__state == 2'b01);
+  assign Mmap2Stream_5___n__q0 = n;
+  assign Mmap2Stream_5___rmem5__q0 = rmem5;
+  assign Mmap2Stream_5__ap_start_global__q0 = ap_start__q0;
+  assign Mmap2Stream_5__is_done__q0 = (Mmap2Stream_5__state == 2'b10);
+  assign Mmap2Stream_5__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Mmap2Stream_5__state <= 2'b00;
+    end else begin
+      if(Mmap2Stream_5__state == 2'b00) begin
+        if(Mmap2Stream_5__ap_start_global__q0) begin
+          Mmap2Stream_5__state <= 2'b01;
+        end
+      end
+      if(Mmap2Stream_5__state == 2'b01) begin
+        if(Mmap2Stream_5__ap_ready) begin
+          if(Mmap2Stream_5__ap_done) begin
+            Mmap2Stream_5__state <= 2'b10;
+          end else begin
+            Mmap2Stream_5__state <= 2'b11;
+          end
+        end
+      end
+      if(Mmap2Stream_5__state == 2'b11) begin
+        if(Mmap2Stream_5__ap_done) begin
+          Mmap2Stream_5__state <= 2'b10;
+        end
+      end
+      if(Mmap2Stream_5__state == 2'b10) begin
+        if(Mmap2Stream_5__ap_done_global__q0) begin
+          Mmap2Stream_5__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Mmap2Stream_5__ap_start = (Mmap2Stream_5__state == 2'b01);
+  assign Mmap2Stream_6___n__q0 = n;
+  assign Mmap2Stream_6___rmem6__q0 = rmem6;
+  assign Mmap2Stream_6__ap_start_global__q0 = ap_start__q0;
+  assign Mmap2Stream_6__is_done__q0 = (Mmap2Stream_6__state == 2'b10);
+  assign Mmap2Stream_6__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Mmap2Stream_6__state <= 2'b00;
+    end else begin
+      if(Mmap2Stream_6__state == 2'b00) begin
+        if(Mmap2Stream_6__ap_start_global__q0) begin
+          Mmap2Stream_6__state <= 2'b01;
+        end
+      end
+      if(Mmap2Stream_6__state == 2'b01) begin
+        if(Mmap2Stream_6__ap_ready) begin
+          if(Mmap2Stream_6__ap_done) begin
+            Mmap2Stream_6__state <= 2'b10;
+          end else begin
+            Mmap2Stream_6__state <= 2'b11;
+          end
+        end
+      end
+      if(Mmap2Stream_6__state == 2'b11) begin
+        if(Mmap2Stream_6__ap_done) begin
+          Mmap2Stream_6__state <= 2'b10;
+        end
+      end
+      if(Mmap2Stream_6__state == 2'b10) begin
+        if(Mmap2Stream_6__ap_done_global__q0) begin
+          Mmap2Stream_6__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Mmap2Stream_6__ap_start = (Mmap2Stream_6__state == 2'b01);
+  assign Mmap2Stream_7___n__q0 = n;
+  assign Mmap2Stream_7___rmem7__q0 = rmem7;
+  assign Mmap2Stream_7__ap_start_global__q0 = ap_start__q0;
+  assign Mmap2Stream_7__is_done__q0 = (Mmap2Stream_7__state == 2'b10);
+  assign Mmap2Stream_7__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Mmap2Stream_7__state <= 2'b00;
+    end else begin
+      if(Mmap2Stream_7__state == 2'b00) begin
+        if(Mmap2Stream_7__ap_start_global__q0) begin
+          Mmap2Stream_7__state <= 2'b01;
+        end
+      end
+      if(Mmap2Stream_7__state == 2'b01) begin
+        if(Mmap2Stream_7__ap_ready) begin
+          if(Mmap2Stream_7__ap_done) begin
+            Mmap2Stream_7__state <= 2'b10;
+          end else begin
+            Mmap2Stream_7__state <= 2'b11;
+          end
+        end
+      end
+      if(Mmap2Stream_7__state == 2'b11) begin
+        if(Mmap2Stream_7__ap_done) begin
+          Mmap2Stream_7__state <= 2'b10;
+        end
+      end
+      if(Mmap2Stream_7__state == 2'b10) begin
+        if(Mmap2Stream_7__ap_done_global__q0) begin
+          Mmap2Stream_7__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Mmap2Stream_7__ap_start = (Mmap2Stream_7__state == 2'b01);
+  assign Mmap2Stream_8___n__q0 = n;
+  assign Mmap2Stream_8___rmem8__q0 = rmem8;
+  assign Mmap2Stream_8__ap_start_global__q0 = ap_start__q0;
+  assign Mmap2Stream_8__is_done__q0 = (Mmap2Stream_8__state == 2'b10);
+  assign Mmap2Stream_8__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Mmap2Stream_8__state <= 2'b00;
+    end else begin
+      if(Mmap2Stream_8__state == 2'b00) begin
+        if(Mmap2Stream_8__ap_start_global__q0) begin
+          Mmap2Stream_8__state <= 2'b01;
+        end
+      end
+      if(Mmap2Stream_8__state == 2'b01) begin
+        if(Mmap2Stream_8__ap_ready) begin
+          if(Mmap2Stream_8__ap_done) begin
+            Mmap2Stream_8__state <= 2'b10;
+          end else begin
+            Mmap2Stream_8__state <= 2'b11;
+          end
+        end
+      end
+      if(Mmap2Stream_8__state == 2'b11) begin
+        if(Mmap2Stream_8__ap_done) begin
+          Mmap2Stream_8__state <= 2'b10;
+        end
+      end
+      if(Mmap2Stream_8__state == 2'b10) begin
+        if(Mmap2Stream_8__ap_done_global__q0) begin
+          Mmap2Stream_8__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Mmap2Stream_8__ap_start = (Mmap2Stream_8__state == 2'b01);
+  assign Mmap2Stream_9___n__q0 = n;
+  assign Mmap2Stream_9___rmem9__q0 = rmem9;
+  assign Mmap2Stream_9__ap_start_global__q0 = ap_start__q0;
+  assign Mmap2Stream_9__is_done__q0 = (Mmap2Stream_9__state == 2'b10);
+  assign Mmap2Stream_9__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Mmap2Stream_9__state <= 2'b00;
+    end else begin
+      if(Mmap2Stream_9__state == 2'b00) begin
+        if(Mmap2Stream_9__ap_start_global__q0) begin
+          Mmap2Stream_9__state <= 2'b01;
+        end
+      end
+      if(Mmap2Stream_9__state == 2'b01) begin
+        if(Mmap2Stream_9__ap_ready) begin
+          if(Mmap2Stream_9__ap_done) begin
+            Mmap2Stream_9__state <= 2'b10;
+          end else begin
+            Mmap2Stream_9__state <= 2'b11;
+          end
+        end
+      end
+      if(Mmap2Stream_9__state == 2'b11) begin
+        if(Mmap2Stream_9__ap_done) begin
+          Mmap2Stream_9__state <= 2'b10;
+        end
+      end
+      if(Mmap2Stream_9__state == 2'b10) begin
+        if(Mmap2Stream_9__ap_done_global__q0) begin
+          Mmap2Stream_9__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Mmap2Stream_9__ap_start = (Mmap2Stream_9__state == 2'b01);
+  assign Mmap2Stream_10___n__q0 = n;
+  assign Mmap2Stream_10___rmem10__q0 = rmem10;
+  assign Mmap2Stream_10__ap_start_global__q0 = ap_start__q0;
+  assign Mmap2Stream_10__is_done__q0 = (Mmap2Stream_10__state == 2'b10);
+  assign Mmap2Stream_10__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Mmap2Stream_10__state <= 2'b00;
+    end else begin
+      if(Mmap2Stream_10__state == 2'b00) begin
+        if(Mmap2Stream_10__ap_start_global__q0) begin
+          Mmap2Stream_10__state <= 2'b01;
+        end
+      end
+      if(Mmap2Stream_10__state == 2'b01) begin
+        if(Mmap2Stream_10__ap_ready) begin
+          if(Mmap2Stream_10__ap_done) begin
+            Mmap2Stream_10__state <= 2'b10;
+          end else begin
+            Mmap2Stream_10__state <= 2'b11;
+          end
+        end
+      end
+      if(Mmap2Stream_10__state == 2'b11) begin
+        if(Mmap2Stream_10__ap_done) begin
+          Mmap2Stream_10__state <= 2'b10;
+        end
+      end
+      if(Mmap2Stream_10__state == 2'b10) begin
+        if(Mmap2Stream_10__ap_done_global__q0) begin
+          Mmap2Stream_10__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Mmap2Stream_10__ap_start = (Mmap2Stream_10__state == 2'b01);
+  assign Mmap2Stream_11___n__q0 = n;
+  assign Mmap2Stream_11___rmem11__q0 = rmem11;
+  assign Mmap2Stream_11__ap_start_global__q0 = ap_start__q0;
+  assign Mmap2Stream_11__is_done__q0 = (Mmap2Stream_11__state == 2'b10);
+  assign Mmap2Stream_11__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Mmap2Stream_11__state <= 2'b00;
+    end else begin
+      if(Mmap2Stream_11__state == 2'b00) begin
+        if(Mmap2Stream_11__ap_start_global__q0) begin
+          Mmap2Stream_11__state <= 2'b01;
+        end
+      end
+      if(Mmap2Stream_11__state == 2'b01) begin
+        if(Mmap2Stream_11__ap_ready) begin
+          if(Mmap2Stream_11__ap_done) begin
+            Mmap2Stream_11__state <= 2'b10;
+          end else begin
+            Mmap2Stream_11__state <= 2'b11;
+          end
+        end
+      end
+      if(Mmap2Stream_11__state == 2'b11) begin
+        if(Mmap2Stream_11__ap_done) begin
+          Mmap2Stream_11__state <= 2'b10;
+        end
+      end
+      if(Mmap2Stream_11__state == 2'b10) begin
+        if(Mmap2Stream_11__ap_done_global__q0) begin
+          Mmap2Stream_11__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Mmap2Stream_11__ap_start = (Mmap2Stream_11__state == 2'b01);
+  assign Mmap2Stream_12___n__q0 = n;
+  assign Mmap2Stream_12___rmem12__q0 = rmem12;
+  assign Mmap2Stream_12__ap_start_global__q0 = ap_start__q0;
+  assign Mmap2Stream_12__is_done__q0 = (Mmap2Stream_12__state == 2'b10);
+  assign Mmap2Stream_12__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Mmap2Stream_12__state <= 2'b00;
+    end else begin
+      if(Mmap2Stream_12__state == 2'b00) begin
+        if(Mmap2Stream_12__ap_start_global__q0) begin
+          Mmap2Stream_12__state <= 2'b01;
+        end
+      end
+      if(Mmap2Stream_12__state == 2'b01) begin
+        if(Mmap2Stream_12__ap_ready) begin
+          if(Mmap2Stream_12__ap_done) begin
+            Mmap2Stream_12__state <= 2'b10;
+          end else begin
+            Mmap2Stream_12__state <= 2'b11;
+          end
+        end
+      end
+      if(Mmap2Stream_12__state == 2'b11) begin
+        if(Mmap2Stream_12__ap_done) begin
+          Mmap2Stream_12__state <= 2'b10;
+        end
+      end
+      if(Mmap2Stream_12__state == 2'b10) begin
+        if(Mmap2Stream_12__ap_done_global__q0) begin
+          Mmap2Stream_12__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Mmap2Stream_12__ap_start = (Mmap2Stream_12__state == 2'b01);
+  assign Mmap2Stream_13___n__q0 = n;
+  assign Mmap2Stream_13___rmem13__q0 = rmem13;
+  assign Mmap2Stream_13__ap_start_global__q0 = ap_start__q0;
+  assign Mmap2Stream_13__is_done__q0 = (Mmap2Stream_13__state == 2'b10);
+  assign Mmap2Stream_13__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Mmap2Stream_13__state <= 2'b00;
+    end else begin
+      if(Mmap2Stream_13__state == 2'b00) begin
+        if(Mmap2Stream_13__ap_start_global__q0) begin
+          Mmap2Stream_13__state <= 2'b01;
+        end
+      end
+      if(Mmap2Stream_13__state == 2'b01) begin
+        if(Mmap2Stream_13__ap_ready) begin
+          if(Mmap2Stream_13__ap_done) begin
+            Mmap2Stream_13__state <= 2'b10;
+          end else begin
+            Mmap2Stream_13__state <= 2'b11;
+          end
+        end
+      end
+      if(Mmap2Stream_13__state == 2'b11) begin
+        if(Mmap2Stream_13__ap_done) begin
+          Mmap2Stream_13__state <= 2'b10;
+        end
+      end
+      if(Mmap2Stream_13__state == 2'b10) begin
+        if(Mmap2Stream_13__ap_done_global__q0) begin
+          Mmap2Stream_13__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Mmap2Stream_13__ap_start = (Mmap2Stream_13__state == 2'b01);
+  assign Mmap2Stream_14___n__q0 = n;
+  assign Mmap2Stream_14___rmem14__q0 = rmem14;
+  assign Mmap2Stream_14__ap_start_global__q0 = ap_start__q0;
+  assign Mmap2Stream_14__is_done__q0 = (Mmap2Stream_14__state == 2'b10);
+  assign Mmap2Stream_14__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Mmap2Stream_14__state <= 2'b00;
+    end else begin
+      if(Mmap2Stream_14__state == 2'b00) begin
+        if(Mmap2Stream_14__ap_start_global__q0) begin
+          Mmap2Stream_14__state <= 2'b01;
+        end
+      end
+      if(Mmap2Stream_14__state == 2'b01) begin
+        if(Mmap2Stream_14__ap_ready) begin
+          if(Mmap2Stream_14__ap_done) begin
+            Mmap2Stream_14__state <= 2'b10;
+          end else begin
+            Mmap2Stream_14__state <= 2'b11;
+          end
+        end
+      end
+      if(Mmap2Stream_14__state == 2'b11) begin
+        if(Mmap2Stream_14__ap_done) begin
+          Mmap2Stream_14__state <= 2'b10;
+        end
+      end
+      if(Mmap2Stream_14__state == 2'b10) begin
+        if(Mmap2Stream_14__ap_done_global__q0) begin
+          Mmap2Stream_14__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Mmap2Stream_14__ap_start = (Mmap2Stream_14__state == 2'b01);
+  assign Mmap2Stream_15___n__q0 = n;
+  assign Mmap2Stream_15___rmem15__q0 = rmem15;
+  assign Mmap2Stream_15__ap_start_global__q0 = ap_start__q0;
+  assign Mmap2Stream_15__is_done__q0 = (Mmap2Stream_15__state == 2'b10);
+  assign Mmap2Stream_15__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Mmap2Stream_15__state <= 2'b00;
+    end else begin
+      if(Mmap2Stream_15__state == 2'b00) begin
+        if(Mmap2Stream_15__ap_start_global__q0) begin
+          Mmap2Stream_15__state <= 2'b01;
+        end
+      end
+      if(Mmap2Stream_15__state == 2'b01) begin
+        if(Mmap2Stream_15__ap_ready) begin
+          if(Mmap2Stream_15__ap_done) begin
+            Mmap2Stream_15__state <= 2'b10;
+          end else begin
+            Mmap2Stream_15__state <= 2'b11;
+          end
+        end
+      end
+      if(Mmap2Stream_15__state == 2'b11) begin
+        if(Mmap2Stream_15__ap_done) begin
+          Mmap2Stream_15__state <= 2'b10;
+        end
+      end
+      if(Mmap2Stream_15__state == 2'b10) begin
+        if(Mmap2Stream_15__ap_done_global__q0) begin
+          Mmap2Stream_15__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Mmap2Stream_15__ap_start = (Mmap2Stream_15__state == 2'b01);
+  assign Mmap2Stream_16___n__q0 = n;
+  assign Mmap2Stream_16___rmem16__q0 = rmem16;
+  assign Mmap2Stream_16__ap_start_global__q0 = ap_start__q0;
+  assign Mmap2Stream_16__is_done__q0 = (Mmap2Stream_16__state == 2'b10);
+  assign Mmap2Stream_16__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Mmap2Stream_16__state <= 2'b00;
+    end else begin
+      if(Mmap2Stream_16__state == 2'b00) begin
+        if(Mmap2Stream_16__ap_start_global__q0) begin
+          Mmap2Stream_16__state <= 2'b01;
+        end
+      end
+      if(Mmap2Stream_16__state == 2'b01) begin
+        if(Mmap2Stream_16__ap_ready) begin
+          if(Mmap2Stream_16__ap_done) begin
+            Mmap2Stream_16__state <= 2'b10;
+          end else begin
+            Mmap2Stream_16__state <= 2'b11;
+          end
+        end
+      end
+      if(Mmap2Stream_16__state == 2'b11) begin
+        if(Mmap2Stream_16__ap_done) begin
+          Mmap2Stream_16__state <= 2'b10;
+        end
+      end
+      if(Mmap2Stream_16__state == 2'b10) begin
+        if(Mmap2Stream_16__ap_done_global__q0) begin
+          Mmap2Stream_16__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Mmap2Stream_16__ap_start = (Mmap2Stream_16__state == 2'b01);
+  assign Mmap2Stream_17___n__q0 = n;
+  assign Mmap2Stream_17___rmem17__q0 = rmem17;
+  assign Mmap2Stream_17__ap_start_global__q0 = ap_start__q0;
+  assign Mmap2Stream_17__is_done__q0 = (Mmap2Stream_17__state == 2'b10);
+  assign Mmap2Stream_17__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Mmap2Stream_17__state <= 2'b00;
+    end else begin
+      if(Mmap2Stream_17__state == 2'b00) begin
+        if(Mmap2Stream_17__ap_start_global__q0) begin
+          Mmap2Stream_17__state <= 2'b01;
+        end
+      end
+      if(Mmap2Stream_17__state == 2'b01) begin
+        if(Mmap2Stream_17__ap_ready) begin
+          if(Mmap2Stream_17__ap_done) begin
+            Mmap2Stream_17__state <= 2'b10;
+          end else begin
+            Mmap2Stream_17__state <= 2'b11;
+          end
+        end
+      end
+      if(Mmap2Stream_17__state == 2'b11) begin
+        if(Mmap2Stream_17__ap_done) begin
+          Mmap2Stream_17__state <= 2'b10;
+        end
+      end
+      if(Mmap2Stream_17__state == 2'b10) begin
+        if(Mmap2Stream_17__ap_done_global__q0) begin
+          Mmap2Stream_17__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Mmap2Stream_17__ap_start = (Mmap2Stream_17__state == 2'b01);
+  assign Mmap2Stream_18___n__q0 = n;
+  assign Mmap2Stream_18___rmem18__q0 = rmem18;
+  assign Mmap2Stream_18__ap_start_global__q0 = ap_start__q0;
+  assign Mmap2Stream_18__is_done__q0 = (Mmap2Stream_18__state == 2'b10);
+  assign Mmap2Stream_18__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Mmap2Stream_18__state <= 2'b00;
+    end else begin
+      if(Mmap2Stream_18__state == 2'b00) begin
+        if(Mmap2Stream_18__ap_start_global__q0) begin
+          Mmap2Stream_18__state <= 2'b01;
+        end
+      end
+      if(Mmap2Stream_18__state == 2'b01) begin
+        if(Mmap2Stream_18__ap_ready) begin
+          if(Mmap2Stream_18__ap_done) begin
+            Mmap2Stream_18__state <= 2'b10;
+          end else begin
+            Mmap2Stream_18__state <= 2'b11;
+          end
+        end
+      end
+      if(Mmap2Stream_18__state == 2'b11) begin
+        if(Mmap2Stream_18__ap_done) begin
+          Mmap2Stream_18__state <= 2'b10;
+        end
+      end
+      if(Mmap2Stream_18__state == 2'b10) begin
+        if(Mmap2Stream_18__ap_done_global__q0) begin
+          Mmap2Stream_18__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Mmap2Stream_18__ap_start = (Mmap2Stream_18__state == 2'b01);
+  assign Mmap2Stream_19___n__q0 = n;
+  assign Mmap2Stream_19___rmem19__q0 = rmem19;
+  assign Mmap2Stream_19__ap_start_global__q0 = ap_start__q0;
+  assign Mmap2Stream_19__is_done__q0 = (Mmap2Stream_19__state == 2'b10);
+  assign Mmap2Stream_19__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Mmap2Stream_19__state <= 2'b00;
+    end else begin
+      if(Mmap2Stream_19__state == 2'b00) begin
+        if(Mmap2Stream_19__ap_start_global__q0) begin
+          Mmap2Stream_19__state <= 2'b01;
+        end
+      end
+      if(Mmap2Stream_19__state == 2'b01) begin
+        if(Mmap2Stream_19__ap_ready) begin
+          if(Mmap2Stream_19__ap_done) begin
+            Mmap2Stream_19__state <= 2'b10;
+          end else begin
+            Mmap2Stream_19__state <= 2'b11;
+          end
+        end
+      end
+      if(Mmap2Stream_19__state == 2'b11) begin
+        if(Mmap2Stream_19__ap_done) begin
+          Mmap2Stream_19__state <= 2'b10;
+        end
+      end
+      if(Mmap2Stream_19__state == 2'b10) begin
+        if(Mmap2Stream_19__ap_done_global__q0) begin
+          Mmap2Stream_19__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Mmap2Stream_19__ap_start = (Mmap2Stream_19__state == 2'b01);
+  assign Mmap2Stream_20___n__q0 = n;
+  assign Mmap2Stream_20___rmem20__q0 = rmem20;
+  assign Mmap2Stream_20__ap_start_global__q0 = ap_start__q0;
+  assign Mmap2Stream_20__is_done__q0 = (Mmap2Stream_20__state == 2'b10);
+  assign Mmap2Stream_20__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Mmap2Stream_20__state <= 2'b00;
+    end else begin
+      if(Mmap2Stream_20__state == 2'b00) begin
+        if(Mmap2Stream_20__ap_start_global__q0) begin
+          Mmap2Stream_20__state <= 2'b01;
+        end
+      end
+      if(Mmap2Stream_20__state == 2'b01) begin
+        if(Mmap2Stream_20__ap_ready) begin
+          if(Mmap2Stream_20__ap_done) begin
+            Mmap2Stream_20__state <= 2'b10;
+          end else begin
+            Mmap2Stream_20__state <= 2'b11;
+          end
+        end
+      end
+      if(Mmap2Stream_20__state == 2'b11) begin
+        if(Mmap2Stream_20__ap_done) begin
+          Mmap2Stream_20__state <= 2'b10;
+        end
+      end
+      if(Mmap2Stream_20__state == 2'b10) begin
+        if(Mmap2Stream_20__ap_done_global__q0) begin
+          Mmap2Stream_20__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Mmap2Stream_20__ap_start = (Mmap2Stream_20__state == 2'b01);
+  assign Mmap2Stream_21___n__q0 = n;
+  assign Mmap2Stream_21___rmem21__q0 = rmem21;
+  assign Mmap2Stream_21__ap_start_global__q0 = ap_start__q0;
+  assign Mmap2Stream_21__is_done__q0 = (Mmap2Stream_21__state == 2'b10);
+  assign Mmap2Stream_21__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Mmap2Stream_21__state <= 2'b00;
+    end else begin
+      if(Mmap2Stream_21__state == 2'b00) begin
+        if(Mmap2Stream_21__ap_start_global__q0) begin
+          Mmap2Stream_21__state <= 2'b01;
+        end
+      end
+      if(Mmap2Stream_21__state == 2'b01) begin
+        if(Mmap2Stream_21__ap_ready) begin
+          if(Mmap2Stream_21__ap_done) begin
+            Mmap2Stream_21__state <= 2'b10;
+          end else begin
+            Mmap2Stream_21__state <= 2'b11;
+          end
+        end
+      end
+      if(Mmap2Stream_21__state == 2'b11) begin
+        if(Mmap2Stream_21__ap_done) begin
+          Mmap2Stream_21__state <= 2'b10;
+        end
+      end
+      if(Mmap2Stream_21__state == 2'b10) begin
+        if(Mmap2Stream_21__ap_done_global__q0) begin
+          Mmap2Stream_21__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Mmap2Stream_21__ap_start = (Mmap2Stream_21__state == 2'b01);
+  assign Mmap2Stream_22___n__q0 = n;
+  assign Mmap2Stream_22___rmem22__q0 = rmem22;
+  assign Mmap2Stream_22__ap_start_global__q0 = ap_start__q0;
+  assign Mmap2Stream_22__is_done__q0 = (Mmap2Stream_22__state == 2'b10);
+  assign Mmap2Stream_22__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Mmap2Stream_22__state <= 2'b00;
+    end else begin
+      if(Mmap2Stream_22__state == 2'b00) begin
+        if(Mmap2Stream_22__ap_start_global__q0) begin
+          Mmap2Stream_22__state <= 2'b01;
+        end
+      end
+      if(Mmap2Stream_22__state == 2'b01) begin
+        if(Mmap2Stream_22__ap_ready) begin
+          if(Mmap2Stream_22__ap_done) begin
+            Mmap2Stream_22__state <= 2'b10;
+          end else begin
+            Mmap2Stream_22__state <= 2'b11;
+          end
+        end
+      end
+      if(Mmap2Stream_22__state == 2'b11) begin
+        if(Mmap2Stream_22__ap_done) begin
+          Mmap2Stream_22__state <= 2'b10;
+        end
+      end
+      if(Mmap2Stream_22__state == 2'b10) begin
+        if(Mmap2Stream_22__ap_done_global__q0) begin
+          Mmap2Stream_22__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Mmap2Stream_22__ap_start = (Mmap2Stream_22__state == 2'b01);
+  assign Mmap2Stream_23___n__q0 = n;
+  assign Mmap2Stream_23___rmem23__q0 = rmem23;
+  assign Mmap2Stream_23__ap_start_global__q0 = ap_start__q0;
+  assign Mmap2Stream_23__is_done__q0 = (Mmap2Stream_23__state == 2'b10);
+  assign Mmap2Stream_23__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Mmap2Stream_23__state <= 2'b00;
+    end else begin
+      if(Mmap2Stream_23__state == 2'b00) begin
+        if(Mmap2Stream_23__ap_start_global__q0) begin
+          Mmap2Stream_23__state <= 2'b01;
+        end
+      end
+      if(Mmap2Stream_23__state == 2'b01) begin
+        if(Mmap2Stream_23__ap_ready) begin
+          if(Mmap2Stream_23__ap_done) begin
+            Mmap2Stream_23__state <= 2'b10;
+          end else begin
+            Mmap2Stream_23__state <= 2'b11;
+          end
+        end
+      end
+      if(Mmap2Stream_23__state == 2'b11) begin
+        if(Mmap2Stream_23__ap_done) begin
+          Mmap2Stream_23__state <= 2'b10;
+        end
+      end
+      if(Mmap2Stream_23__state == 2'b10) begin
+        if(Mmap2Stream_23__ap_done_global__q0) begin
+          Mmap2Stream_23__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Mmap2Stream_23__ap_start = (Mmap2Stream_23__state == 2'b01);
+  assign Mmap2Stream_24___n__q0 = n;
+  assign Mmap2Stream_24___rmem24__q0 = rmem24;
+  assign Mmap2Stream_24__ap_start_global__q0 = ap_start__q0;
+  assign Mmap2Stream_24__is_done__q0 = (Mmap2Stream_24__state == 2'b10);
+  assign Mmap2Stream_24__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Mmap2Stream_24__state <= 2'b00;
+    end else begin
+      if(Mmap2Stream_24__state == 2'b00) begin
+        if(Mmap2Stream_24__ap_start_global__q0) begin
+          Mmap2Stream_24__state <= 2'b01;
+        end
+      end
+      if(Mmap2Stream_24__state == 2'b01) begin
+        if(Mmap2Stream_24__ap_ready) begin
+          if(Mmap2Stream_24__ap_done) begin
+            Mmap2Stream_24__state <= 2'b10;
+          end else begin
+            Mmap2Stream_24__state <= 2'b11;
+          end
+        end
+      end
+      if(Mmap2Stream_24__state == 2'b11) begin
+        if(Mmap2Stream_24__ap_done) begin
+          Mmap2Stream_24__state <= 2'b10;
+        end
+      end
+      if(Mmap2Stream_24__state == 2'b10) begin
+        if(Mmap2Stream_24__ap_done_global__q0) begin
+          Mmap2Stream_24__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Mmap2Stream_24__ap_start = (Mmap2Stream_24__state == 2'b01);
+  assign Mmap2Stream_25___n__q0 = n;
+  assign Mmap2Stream_25___rmem25__q0 = rmem25;
+  assign Mmap2Stream_25__ap_start_global__q0 = ap_start__q0;
+  assign Mmap2Stream_25__is_done__q0 = (Mmap2Stream_25__state == 2'b10);
+  assign Mmap2Stream_25__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Mmap2Stream_25__state <= 2'b00;
+    end else begin
+      if(Mmap2Stream_25__state == 2'b00) begin
+        if(Mmap2Stream_25__ap_start_global__q0) begin
+          Mmap2Stream_25__state <= 2'b01;
+        end
+      end
+      if(Mmap2Stream_25__state == 2'b01) begin
+        if(Mmap2Stream_25__ap_ready) begin
+          if(Mmap2Stream_25__ap_done) begin
+            Mmap2Stream_25__state <= 2'b10;
+          end else begin
+            Mmap2Stream_25__state <= 2'b11;
+          end
+        end
+      end
+      if(Mmap2Stream_25__state == 2'b11) begin
+        if(Mmap2Stream_25__ap_done) begin
+          Mmap2Stream_25__state <= 2'b10;
+        end
+      end
+      if(Mmap2Stream_25__state == 2'b10) begin
+        if(Mmap2Stream_25__ap_done_global__q0) begin
+          Mmap2Stream_25__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Mmap2Stream_25__ap_start = (Mmap2Stream_25__state == 2'b01);
+  assign Mmap2Stream_26___n__q0 = n;
+  assign Mmap2Stream_26___rmem26__q0 = rmem26;
+  assign Mmap2Stream_26__ap_start_global__q0 = ap_start__q0;
+  assign Mmap2Stream_26__is_done__q0 = (Mmap2Stream_26__state == 2'b10);
+  assign Mmap2Stream_26__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Mmap2Stream_26__state <= 2'b00;
+    end else begin
+      if(Mmap2Stream_26__state == 2'b00) begin
+        if(Mmap2Stream_26__ap_start_global__q0) begin
+          Mmap2Stream_26__state <= 2'b01;
+        end
+      end
+      if(Mmap2Stream_26__state == 2'b01) begin
+        if(Mmap2Stream_26__ap_ready) begin
+          if(Mmap2Stream_26__ap_done) begin
+            Mmap2Stream_26__state <= 2'b10;
+          end else begin
+            Mmap2Stream_26__state <= 2'b11;
+          end
+        end
+      end
+      if(Mmap2Stream_26__state == 2'b11) begin
+        if(Mmap2Stream_26__ap_done) begin
+          Mmap2Stream_26__state <= 2'b10;
+        end
+      end
+      if(Mmap2Stream_26__state == 2'b10) begin
+        if(Mmap2Stream_26__ap_done_global__q0) begin
+          Mmap2Stream_26__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Mmap2Stream_26__ap_start = (Mmap2Stream_26__state == 2'b01);
+  assign Mmap2Stream_27___n__q0 = n;
+  assign Mmap2Stream_27___rmem27__q0 = rmem27;
+  assign Mmap2Stream_27__ap_start_global__q0 = ap_start__q0;
+  assign Mmap2Stream_27__is_done__q0 = (Mmap2Stream_27__state == 2'b10);
+  assign Mmap2Stream_27__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Mmap2Stream_27__state <= 2'b00;
+    end else begin
+      if(Mmap2Stream_27__state == 2'b00) begin
+        if(Mmap2Stream_27__ap_start_global__q0) begin
+          Mmap2Stream_27__state <= 2'b01;
+        end
+      end
+      if(Mmap2Stream_27__state == 2'b01) begin
+        if(Mmap2Stream_27__ap_ready) begin
+          if(Mmap2Stream_27__ap_done) begin
+            Mmap2Stream_27__state <= 2'b10;
+          end else begin
+            Mmap2Stream_27__state <= 2'b11;
+          end
+        end
+      end
+      if(Mmap2Stream_27__state == 2'b11) begin
+        if(Mmap2Stream_27__ap_done) begin
+          Mmap2Stream_27__state <= 2'b10;
+        end
+      end
+      if(Mmap2Stream_27__state == 2'b10) begin
+        if(Mmap2Stream_27__ap_done_global__q0) begin
+          Mmap2Stream_27__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Mmap2Stream_27__ap_start = (Mmap2Stream_27__state == 2'b01);
+  assign Stream2Mmap_0___n__q0 = n;
+  assign Stream2Mmap_0___rmem0__q0 = rmem0;
+  assign Stream2Mmap_0__ap_start_global__q0 = ap_start__q0;
+  assign Stream2Mmap_0__is_done__q0 = (Stream2Mmap_0__state == 2'b10);
+  assign Stream2Mmap_0__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Stream2Mmap_0__state <= 2'b00;
+    end else begin
+      if(Stream2Mmap_0__state == 2'b00) begin
+        if(Stream2Mmap_0__ap_start_global__q0) begin
+          Stream2Mmap_0__state <= 2'b01;
+        end
+      end
+      if(Stream2Mmap_0__state == 2'b01) begin
+        if(Stream2Mmap_0__ap_ready) begin
+          if(Stream2Mmap_0__ap_done) begin
+            Stream2Mmap_0__state <= 2'b10;
+          end else begin
+            Stream2Mmap_0__state <= 2'b11;
+          end
+        end
+      end
+      if(Stream2Mmap_0__state == 2'b11) begin
+        if(Stream2Mmap_0__ap_done) begin
+          Stream2Mmap_0__state <= 2'b10;
+        end
+      end
+      if(Stream2Mmap_0__state == 2'b10) begin
+        if(Stream2Mmap_0__ap_done_global__q0) begin
+          Stream2Mmap_0__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Stream2Mmap_0__ap_start = (Stream2Mmap_0__state == 2'b01);
+  assign Stream2Mmap_1___n__q0 = n;
+  assign Stream2Mmap_1___rmem1__q0 = rmem1;
+  assign Stream2Mmap_1__ap_start_global__q0 = ap_start__q0;
+  assign Stream2Mmap_1__is_done__q0 = (Stream2Mmap_1__state == 2'b10);
+  assign Stream2Mmap_1__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Stream2Mmap_1__state <= 2'b00;
+    end else begin
+      if(Stream2Mmap_1__state == 2'b00) begin
+        if(Stream2Mmap_1__ap_start_global__q0) begin
+          Stream2Mmap_1__state <= 2'b01;
+        end
+      end
+      if(Stream2Mmap_1__state == 2'b01) begin
+        if(Stream2Mmap_1__ap_ready) begin
+          if(Stream2Mmap_1__ap_done) begin
+            Stream2Mmap_1__state <= 2'b10;
+          end else begin
+            Stream2Mmap_1__state <= 2'b11;
+          end
+        end
+      end
+      if(Stream2Mmap_1__state == 2'b11) begin
+        if(Stream2Mmap_1__ap_done) begin
+          Stream2Mmap_1__state <= 2'b10;
+        end
+      end
+      if(Stream2Mmap_1__state == 2'b10) begin
+        if(Stream2Mmap_1__ap_done_global__q0) begin
+          Stream2Mmap_1__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Stream2Mmap_1__ap_start = (Stream2Mmap_1__state == 2'b01);
+  assign Stream2Mmap_2___n__q0 = n;
+  assign Stream2Mmap_2___rmem2__q0 = rmem2;
+  assign Stream2Mmap_2__ap_start_global__q0 = ap_start__q0;
+  assign Stream2Mmap_2__is_done__q0 = (Stream2Mmap_2__state == 2'b10);
+  assign Stream2Mmap_2__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Stream2Mmap_2__state <= 2'b00;
+    end else begin
+      if(Stream2Mmap_2__state == 2'b00) begin
+        if(Stream2Mmap_2__ap_start_global__q0) begin
+          Stream2Mmap_2__state <= 2'b01;
+        end
+      end
+      if(Stream2Mmap_2__state == 2'b01) begin
+        if(Stream2Mmap_2__ap_ready) begin
+          if(Stream2Mmap_2__ap_done) begin
+            Stream2Mmap_2__state <= 2'b10;
+          end else begin
+            Stream2Mmap_2__state <= 2'b11;
+          end
+        end
+      end
+      if(Stream2Mmap_2__state == 2'b11) begin
+        if(Stream2Mmap_2__ap_done) begin
+          Stream2Mmap_2__state <= 2'b10;
+        end
+      end
+      if(Stream2Mmap_2__state == 2'b10) begin
+        if(Stream2Mmap_2__ap_done_global__q0) begin
+          Stream2Mmap_2__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Stream2Mmap_2__ap_start = (Stream2Mmap_2__state == 2'b01);
+  assign Stream2Mmap_3___n__q0 = n;
+  assign Stream2Mmap_3___rmem3__q0 = rmem3;
+  assign Stream2Mmap_3__ap_start_global__q0 = ap_start__q0;
+  assign Stream2Mmap_3__is_done__q0 = (Stream2Mmap_3__state == 2'b10);
+  assign Stream2Mmap_3__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Stream2Mmap_3__state <= 2'b00;
+    end else begin
+      if(Stream2Mmap_3__state == 2'b00) begin
+        if(Stream2Mmap_3__ap_start_global__q0) begin
+          Stream2Mmap_3__state <= 2'b01;
+        end
+      end
+      if(Stream2Mmap_3__state == 2'b01) begin
+        if(Stream2Mmap_3__ap_ready) begin
+          if(Stream2Mmap_3__ap_done) begin
+            Stream2Mmap_3__state <= 2'b10;
+          end else begin
+            Stream2Mmap_3__state <= 2'b11;
+          end
+        end
+      end
+      if(Stream2Mmap_3__state == 2'b11) begin
+        if(Stream2Mmap_3__ap_done) begin
+          Stream2Mmap_3__state <= 2'b10;
+        end
+      end
+      if(Stream2Mmap_3__state == 2'b10) begin
+        if(Stream2Mmap_3__ap_done_global__q0) begin
+          Stream2Mmap_3__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Stream2Mmap_3__ap_start = (Stream2Mmap_3__state == 2'b01);
+  assign Stream2Mmap_4___n__q0 = n;
+  assign Stream2Mmap_4___rmem4__q0 = rmem4;
+  assign Stream2Mmap_4__ap_start_global__q0 = ap_start__q0;
+  assign Stream2Mmap_4__is_done__q0 = (Stream2Mmap_4__state == 2'b10);
+  assign Stream2Mmap_4__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Stream2Mmap_4__state <= 2'b00;
+    end else begin
+      if(Stream2Mmap_4__state == 2'b00) begin
+        if(Stream2Mmap_4__ap_start_global__q0) begin
+          Stream2Mmap_4__state <= 2'b01;
+        end
+      end
+      if(Stream2Mmap_4__state == 2'b01) begin
+        if(Stream2Mmap_4__ap_ready) begin
+          if(Stream2Mmap_4__ap_done) begin
+            Stream2Mmap_4__state <= 2'b10;
+          end else begin
+            Stream2Mmap_4__state <= 2'b11;
+          end
+        end
+      end
+      if(Stream2Mmap_4__state == 2'b11) begin
+        if(Stream2Mmap_4__ap_done) begin
+          Stream2Mmap_4__state <= 2'b10;
+        end
+      end
+      if(Stream2Mmap_4__state == 2'b10) begin
+        if(Stream2Mmap_4__ap_done_global__q0) begin
+          Stream2Mmap_4__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Stream2Mmap_4__ap_start = (Stream2Mmap_4__state == 2'b01);
+  assign Stream2Mmap_5___n__q0 = n;
+  assign Stream2Mmap_5___rmem5__q0 = rmem5;
+  assign Stream2Mmap_5__ap_start_global__q0 = ap_start__q0;
+  assign Stream2Mmap_5__is_done__q0 = (Stream2Mmap_5__state == 2'b10);
+  assign Stream2Mmap_5__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Stream2Mmap_5__state <= 2'b00;
+    end else begin
+      if(Stream2Mmap_5__state == 2'b00) begin
+        if(Stream2Mmap_5__ap_start_global__q0) begin
+          Stream2Mmap_5__state <= 2'b01;
+        end
+      end
+      if(Stream2Mmap_5__state == 2'b01) begin
+        if(Stream2Mmap_5__ap_ready) begin
+          if(Stream2Mmap_5__ap_done) begin
+            Stream2Mmap_5__state <= 2'b10;
+          end else begin
+            Stream2Mmap_5__state <= 2'b11;
+          end
+        end
+      end
+      if(Stream2Mmap_5__state == 2'b11) begin
+        if(Stream2Mmap_5__ap_done) begin
+          Stream2Mmap_5__state <= 2'b10;
+        end
+      end
+      if(Stream2Mmap_5__state == 2'b10) begin
+        if(Stream2Mmap_5__ap_done_global__q0) begin
+          Stream2Mmap_5__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Stream2Mmap_5__ap_start = (Stream2Mmap_5__state == 2'b01);
+  assign Stream2Mmap_6___n__q0 = n;
+  assign Stream2Mmap_6___rmem6__q0 = rmem6;
+  assign Stream2Mmap_6__ap_start_global__q0 = ap_start__q0;
+  assign Stream2Mmap_6__is_done__q0 = (Stream2Mmap_6__state == 2'b10);
+  assign Stream2Mmap_6__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Stream2Mmap_6__state <= 2'b00;
+    end else begin
+      if(Stream2Mmap_6__state == 2'b00) begin
+        if(Stream2Mmap_6__ap_start_global__q0) begin
+          Stream2Mmap_6__state <= 2'b01;
+        end
+      end
+      if(Stream2Mmap_6__state == 2'b01) begin
+        if(Stream2Mmap_6__ap_ready) begin
+          if(Stream2Mmap_6__ap_done) begin
+            Stream2Mmap_6__state <= 2'b10;
+          end else begin
+            Stream2Mmap_6__state <= 2'b11;
+          end
+        end
+      end
+      if(Stream2Mmap_6__state == 2'b11) begin
+        if(Stream2Mmap_6__ap_done) begin
+          Stream2Mmap_6__state <= 2'b10;
+        end
+      end
+      if(Stream2Mmap_6__state == 2'b10) begin
+        if(Stream2Mmap_6__ap_done_global__q0) begin
+          Stream2Mmap_6__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Stream2Mmap_6__ap_start = (Stream2Mmap_6__state == 2'b01);
+  assign Stream2Mmap_7___n__q0 = n;
+  assign Stream2Mmap_7___rmem7__q0 = rmem7;
+  assign Stream2Mmap_7__ap_start_global__q0 = ap_start__q0;
+  assign Stream2Mmap_7__is_done__q0 = (Stream2Mmap_7__state == 2'b10);
+  assign Stream2Mmap_7__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Stream2Mmap_7__state <= 2'b00;
+    end else begin
+      if(Stream2Mmap_7__state == 2'b00) begin
+        if(Stream2Mmap_7__ap_start_global__q0) begin
+          Stream2Mmap_7__state <= 2'b01;
+        end
+      end
+      if(Stream2Mmap_7__state == 2'b01) begin
+        if(Stream2Mmap_7__ap_ready) begin
+          if(Stream2Mmap_7__ap_done) begin
+            Stream2Mmap_7__state <= 2'b10;
+          end else begin
+            Stream2Mmap_7__state <= 2'b11;
+          end
+        end
+      end
+      if(Stream2Mmap_7__state == 2'b11) begin
+        if(Stream2Mmap_7__ap_done) begin
+          Stream2Mmap_7__state <= 2'b10;
+        end
+      end
+      if(Stream2Mmap_7__state == 2'b10) begin
+        if(Stream2Mmap_7__ap_done_global__q0) begin
+          Stream2Mmap_7__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Stream2Mmap_7__ap_start = (Stream2Mmap_7__state == 2'b01);
+  assign Stream2Mmap_8___n__q0 = n;
+  assign Stream2Mmap_8___rmem8__q0 = rmem8;
+  assign Stream2Mmap_8__ap_start_global__q0 = ap_start__q0;
+  assign Stream2Mmap_8__is_done__q0 = (Stream2Mmap_8__state == 2'b10);
+  assign Stream2Mmap_8__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Stream2Mmap_8__state <= 2'b00;
+    end else begin
+      if(Stream2Mmap_8__state == 2'b00) begin
+        if(Stream2Mmap_8__ap_start_global__q0) begin
+          Stream2Mmap_8__state <= 2'b01;
+        end
+      end
+      if(Stream2Mmap_8__state == 2'b01) begin
+        if(Stream2Mmap_8__ap_ready) begin
+          if(Stream2Mmap_8__ap_done) begin
+            Stream2Mmap_8__state <= 2'b10;
+          end else begin
+            Stream2Mmap_8__state <= 2'b11;
+          end
+        end
+      end
+      if(Stream2Mmap_8__state == 2'b11) begin
+        if(Stream2Mmap_8__ap_done) begin
+          Stream2Mmap_8__state <= 2'b10;
+        end
+      end
+      if(Stream2Mmap_8__state == 2'b10) begin
+        if(Stream2Mmap_8__ap_done_global__q0) begin
+          Stream2Mmap_8__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Stream2Mmap_8__ap_start = (Stream2Mmap_8__state == 2'b01);
+  assign Stream2Mmap_9___n__q0 = n;
+  assign Stream2Mmap_9___rmem9__q0 = rmem9;
+  assign Stream2Mmap_9__ap_start_global__q0 = ap_start__q0;
+  assign Stream2Mmap_9__is_done__q0 = (Stream2Mmap_9__state == 2'b10);
+  assign Stream2Mmap_9__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Stream2Mmap_9__state <= 2'b00;
+    end else begin
+      if(Stream2Mmap_9__state == 2'b00) begin
+        if(Stream2Mmap_9__ap_start_global__q0) begin
+          Stream2Mmap_9__state <= 2'b01;
+        end
+      end
+      if(Stream2Mmap_9__state == 2'b01) begin
+        if(Stream2Mmap_9__ap_ready) begin
+          if(Stream2Mmap_9__ap_done) begin
+            Stream2Mmap_9__state <= 2'b10;
+          end else begin
+            Stream2Mmap_9__state <= 2'b11;
+          end
+        end
+      end
+      if(Stream2Mmap_9__state == 2'b11) begin
+        if(Stream2Mmap_9__ap_done) begin
+          Stream2Mmap_9__state <= 2'b10;
+        end
+      end
+      if(Stream2Mmap_9__state == 2'b10) begin
+        if(Stream2Mmap_9__ap_done_global__q0) begin
+          Stream2Mmap_9__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Stream2Mmap_9__ap_start = (Stream2Mmap_9__state == 2'b01);
+  assign Stream2Mmap_10___n__q0 = n;
+  assign Stream2Mmap_10___rmem10__q0 = rmem10;
+  assign Stream2Mmap_10__ap_start_global__q0 = ap_start__q0;
+  assign Stream2Mmap_10__is_done__q0 = (Stream2Mmap_10__state == 2'b10);
+  assign Stream2Mmap_10__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Stream2Mmap_10__state <= 2'b00;
+    end else begin
+      if(Stream2Mmap_10__state == 2'b00) begin
+        if(Stream2Mmap_10__ap_start_global__q0) begin
+          Stream2Mmap_10__state <= 2'b01;
+        end
+      end
+      if(Stream2Mmap_10__state == 2'b01) begin
+        if(Stream2Mmap_10__ap_ready) begin
+          if(Stream2Mmap_10__ap_done) begin
+            Stream2Mmap_10__state <= 2'b10;
+          end else begin
+            Stream2Mmap_10__state <= 2'b11;
+          end
+        end
+      end
+      if(Stream2Mmap_10__state == 2'b11) begin
+        if(Stream2Mmap_10__ap_done) begin
+          Stream2Mmap_10__state <= 2'b10;
+        end
+      end
+      if(Stream2Mmap_10__state == 2'b10) begin
+        if(Stream2Mmap_10__ap_done_global__q0) begin
+          Stream2Mmap_10__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Stream2Mmap_10__ap_start = (Stream2Mmap_10__state == 2'b01);
+  assign Stream2Mmap_11___n__q0 = n;
+  assign Stream2Mmap_11___rmem11__q0 = rmem11;
+  assign Stream2Mmap_11__ap_start_global__q0 = ap_start__q0;
+  assign Stream2Mmap_11__is_done__q0 = (Stream2Mmap_11__state == 2'b10);
+  assign Stream2Mmap_11__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Stream2Mmap_11__state <= 2'b00;
+    end else begin
+      if(Stream2Mmap_11__state == 2'b00) begin
+        if(Stream2Mmap_11__ap_start_global__q0) begin
+          Stream2Mmap_11__state <= 2'b01;
+        end
+      end
+      if(Stream2Mmap_11__state == 2'b01) begin
+        if(Stream2Mmap_11__ap_ready) begin
+          if(Stream2Mmap_11__ap_done) begin
+            Stream2Mmap_11__state <= 2'b10;
+          end else begin
+            Stream2Mmap_11__state <= 2'b11;
+          end
+        end
+      end
+      if(Stream2Mmap_11__state == 2'b11) begin
+        if(Stream2Mmap_11__ap_done) begin
+          Stream2Mmap_11__state <= 2'b10;
+        end
+      end
+      if(Stream2Mmap_11__state == 2'b10) begin
+        if(Stream2Mmap_11__ap_done_global__q0) begin
+          Stream2Mmap_11__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Stream2Mmap_11__ap_start = (Stream2Mmap_11__state == 2'b01);
+  assign Stream2Mmap_12___n__q0 = n;
+  assign Stream2Mmap_12___rmem12__q0 = rmem12;
+  assign Stream2Mmap_12__ap_start_global__q0 = ap_start__q0;
+  assign Stream2Mmap_12__is_done__q0 = (Stream2Mmap_12__state == 2'b10);
+  assign Stream2Mmap_12__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Stream2Mmap_12__state <= 2'b00;
+    end else begin
+      if(Stream2Mmap_12__state == 2'b00) begin
+        if(Stream2Mmap_12__ap_start_global__q0) begin
+          Stream2Mmap_12__state <= 2'b01;
+        end
+      end
+      if(Stream2Mmap_12__state == 2'b01) begin
+        if(Stream2Mmap_12__ap_ready) begin
+          if(Stream2Mmap_12__ap_done) begin
+            Stream2Mmap_12__state <= 2'b10;
+          end else begin
+            Stream2Mmap_12__state <= 2'b11;
+          end
+        end
+      end
+      if(Stream2Mmap_12__state == 2'b11) begin
+        if(Stream2Mmap_12__ap_done) begin
+          Stream2Mmap_12__state <= 2'b10;
+        end
+      end
+      if(Stream2Mmap_12__state == 2'b10) begin
+        if(Stream2Mmap_12__ap_done_global__q0) begin
+          Stream2Mmap_12__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Stream2Mmap_12__ap_start = (Stream2Mmap_12__state == 2'b01);
+  assign Stream2Mmap_13___n__q0 = n;
+  assign Stream2Mmap_13___rmem13__q0 = rmem13;
+  assign Stream2Mmap_13__ap_start_global__q0 = ap_start__q0;
+  assign Stream2Mmap_13__is_done__q0 = (Stream2Mmap_13__state == 2'b10);
+  assign Stream2Mmap_13__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Stream2Mmap_13__state <= 2'b00;
+    end else begin
+      if(Stream2Mmap_13__state == 2'b00) begin
+        if(Stream2Mmap_13__ap_start_global__q0) begin
+          Stream2Mmap_13__state <= 2'b01;
+        end
+      end
+      if(Stream2Mmap_13__state == 2'b01) begin
+        if(Stream2Mmap_13__ap_ready) begin
+          if(Stream2Mmap_13__ap_done) begin
+            Stream2Mmap_13__state <= 2'b10;
+          end else begin
+            Stream2Mmap_13__state <= 2'b11;
+          end
+        end
+      end
+      if(Stream2Mmap_13__state == 2'b11) begin
+        if(Stream2Mmap_13__ap_done) begin
+          Stream2Mmap_13__state <= 2'b10;
+        end
+      end
+      if(Stream2Mmap_13__state == 2'b10) begin
+        if(Stream2Mmap_13__ap_done_global__q0) begin
+          Stream2Mmap_13__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Stream2Mmap_13__ap_start = (Stream2Mmap_13__state == 2'b01);
+  assign Stream2Mmap_14___n__q0 = n;
+  assign Stream2Mmap_14___rmem14__q0 = rmem14;
+  assign Stream2Mmap_14__ap_start_global__q0 = ap_start__q0;
+  assign Stream2Mmap_14__is_done__q0 = (Stream2Mmap_14__state == 2'b10);
+  assign Stream2Mmap_14__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Stream2Mmap_14__state <= 2'b00;
+    end else begin
+      if(Stream2Mmap_14__state == 2'b00) begin
+        if(Stream2Mmap_14__ap_start_global__q0) begin
+          Stream2Mmap_14__state <= 2'b01;
+        end
+      end
+      if(Stream2Mmap_14__state == 2'b01) begin
+        if(Stream2Mmap_14__ap_ready) begin
+          if(Stream2Mmap_14__ap_done) begin
+            Stream2Mmap_14__state <= 2'b10;
+          end else begin
+            Stream2Mmap_14__state <= 2'b11;
+          end
+        end
+      end
+      if(Stream2Mmap_14__state == 2'b11) begin
+        if(Stream2Mmap_14__ap_done) begin
+          Stream2Mmap_14__state <= 2'b10;
+        end
+      end
+      if(Stream2Mmap_14__state == 2'b10) begin
+        if(Stream2Mmap_14__ap_done_global__q0) begin
+          Stream2Mmap_14__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Stream2Mmap_14__ap_start = (Stream2Mmap_14__state == 2'b01);
+  assign Stream2Mmap_15___n__q0 = n;
+  assign Stream2Mmap_15___rmem15__q0 = rmem15;
+  assign Stream2Mmap_15__ap_start_global__q0 = ap_start__q0;
+  assign Stream2Mmap_15__is_done__q0 = (Stream2Mmap_15__state == 2'b10);
+  assign Stream2Mmap_15__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Stream2Mmap_15__state <= 2'b00;
+    end else begin
+      if(Stream2Mmap_15__state == 2'b00) begin
+        if(Stream2Mmap_15__ap_start_global__q0) begin
+          Stream2Mmap_15__state <= 2'b01;
+        end
+      end
+      if(Stream2Mmap_15__state == 2'b01) begin
+        if(Stream2Mmap_15__ap_ready) begin
+          if(Stream2Mmap_15__ap_done) begin
+            Stream2Mmap_15__state <= 2'b10;
+          end else begin
+            Stream2Mmap_15__state <= 2'b11;
+          end
+        end
+      end
+      if(Stream2Mmap_15__state == 2'b11) begin
+        if(Stream2Mmap_15__ap_done) begin
+          Stream2Mmap_15__state <= 2'b10;
+        end
+      end
+      if(Stream2Mmap_15__state == 2'b10) begin
+        if(Stream2Mmap_15__ap_done_global__q0) begin
+          Stream2Mmap_15__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Stream2Mmap_15__ap_start = (Stream2Mmap_15__state == 2'b01);
+  assign Stream2Mmap_16___n__q0 = n;
+  assign Stream2Mmap_16___rmem16__q0 = rmem16;
+  assign Stream2Mmap_16__ap_start_global__q0 = ap_start__q0;
+  assign Stream2Mmap_16__is_done__q0 = (Stream2Mmap_16__state == 2'b10);
+  assign Stream2Mmap_16__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Stream2Mmap_16__state <= 2'b00;
+    end else begin
+      if(Stream2Mmap_16__state == 2'b00) begin
+        if(Stream2Mmap_16__ap_start_global__q0) begin
+          Stream2Mmap_16__state <= 2'b01;
+        end
+      end
+      if(Stream2Mmap_16__state == 2'b01) begin
+        if(Stream2Mmap_16__ap_ready) begin
+          if(Stream2Mmap_16__ap_done) begin
+            Stream2Mmap_16__state <= 2'b10;
+          end else begin
+            Stream2Mmap_16__state <= 2'b11;
+          end
+        end
+      end
+      if(Stream2Mmap_16__state == 2'b11) begin
+        if(Stream2Mmap_16__ap_done) begin
+          Stream2Mmap_16__state <= 2'b10;
+        end
+      end
+      if(Stream2Mmap_16__state == 2'b10) begin
+        if(Stream2Mmap_16__ap_done_global__q0) begin
+          Stream2Mmap_16__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Stream2Mmap_16__ap_start = (Stream2Mmap_16__state == 2'b01);
+  assign Stream2Mmap_17___n__q0 = n;
+  assign Stream2Mmap_17___rmem17__q0 = rmem17;
+  assign Stream2Mmap_17__ap_start_global__q0 = ap_start__q0;
+  assign Stream2Mmap_17__is_done__q0 = (Stream2Mmap_17__state == 2'b10);
+  assign Stream2Mmap_17__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Stream2Mmap_17__state <= 2'b00;
+    end else begin
+      if(Stream2Mmap_17__state == 2'b00) begin
+        if(Stream2Mmap_17__ap_start_global__q0) begin
+          Stream2Mmap_17__state <= 2'b01;
+        end
+      end
+      if(Stream2Mmap_17__state == 2'b01) begin
+        if(Stream2Mmap_17__ap_ready) begin
+          if(Stream2Mmap_17__ap_done) begin
+            Stream2Mmap_17__state <= 2'b10;
+          end else begin
+            Stream2Mmap_17__state <= 2'b11;
+          end
+        end
+      end
+      if(Stream2Mmap_17__state == 2'b11) begin
+        if(Stream2Mmap_17__ap_done) begin
+          Stream2Mmap_17__state <= 2'b10;
+        end
+      end
+      if(Stream2Mmap_17__state == 2'b10) begin
+        if(Stream2Mmap_17__ap_done_global__q0) begin
+          Stream2Mmap_17__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Stream2Mmap_17__ap_start = (Stream2Mmap_17__state == 2'b01);
+  assign Stream2Mmap_18___n__q0 = n;
+  assign Stream2Mmap_18___rmem18__q0 = rmem18;
+  assign Stream2Mmap_18__ap_start_global__q0 = ap_start__q0;
+  assign Stream2Mmap_18__is_done__q0 = (Stream2Mmap_18__state == 2'b10);
+  assign Stream2Mmap_18__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Stream2Mmap_18__state <= 2'b00;
+    end else begin
+      if(Stream2Mmap_18__state == 2'b00) begin
+        if(Stream2Mmap_18__ap_start_global__q0) begin
+          Stream2Mmap_18__state <= 2'b01;
+        end
+      end
+      if(Stream2Mmap_18__state == 2'b01) begin
+        if(Stream2Mmap_18__ap_ready) begin
+          if(Stream2Mmap_18__ap_done) begin
+            Stream2Mmap_18__state <= 2'b10;
+          end else begin
+            Stream2Mmap_18__state <= 2'b11;
+          end
+        end
+      end
+      if(Stream2Mmap_18__state == 2'b11) begin
+        if(Stream2Mmap_18__ap_done) begin
+          Stream2Mmap_18__state <= 2'b10;
+        end
+      end
+      if(Stream2Mmap_18__state == 2'b10) begin
+        if(Stream2Mmap_18__ap_done_global__q0) begin
+          Stream2Mmap_18__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Stream2Mmap_18__ap_start = (Stream2Mmap_18__state == 2'b01);
+  assign Stream2Mmap_19___n__q0 = n;
+  assign Stream2Mmap_19___rmem19__q0 = rmem19;
+  assign Stream2Mmap_19__ap_start_global__q0 = ap_start__q0;
+  assign Stream2Mmap_19__is_done__q0 = (Stream2Mmap_19__state == 2'b10);
+  assign Stream2Mmap_19__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Stream2Mmap_19__state <= 2'b00;
+    end else begin
+      if(Stream2Mmap_19__state == 2'b00) begin
+        if(Stream2Mmap_19__ap_start_global__q0) begin
+          Stream2Mmap_19__state <= 2'b01;
+        end
+      end
+      if(Stream2Mmap_19__state == 2'b01) begin
+        if(Stream2Mmap_19__ap_ready) begin
+          if(Stream2Mmap_19__ap_done) begin
+            Stream2Mmap_19__state <= 2'b10;
+          end else begin
+            Stream2Mmap_19__state <= 2'b11;
+          end
+        end
+      end
+      if(Stream2Mmap_19__state == 2'b11) begin
+        if(Stream2Mmap_19__ap_done) begin
+          Stream2Mmap_19__state <= 2'b10;
+        end
+      end
+      if(Stream2Mmap_19__state == 2'b10) begin
+        if(Stream2Mmap_19__ap_done_global__q0) begin
+          Stream2Mmap_19__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Stream2Mmap_19__ap_start = (Stream2Mmap_19__state == 2'b01);
+  assign Stream2Mmap_20___n__q0 = n;
+  assign Stream2Mmap_20___rmem20__q0 = rmem20;
+  assign Stream2Mmap_20__ap_start_global__q0 = ap_start__q0;
+  assign Stream2Mmap_20__is_done__q0 = (Stream2Mmap_20__state == 2'b10);
+  assign Stream2Mmap_20__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Stream2Mmap_20__state <= 2'b00;
+    end else begin
+      if(Stream2Mmap_20__state == 2'b00) begin
+        if(Stream2Mmap_20__ap_start_global__q0) begin
+          Stream2Mmap_20__state <= 2'b01;
+        end
+      end
+      if(Stream2Mmap_20__state == 2'b01) begin
+        if(Stream2Mmap_20__ap_ready) begin
+          if(Stream2Mmap_20__ap_done) begin
+            Stream2Mmap_20__state <= 2'b10;
+          end else begin
+            Stream2Mmap_20__state <= 2'b11;
+          end
+        end
+      end
+      if(Stream2Mmap_20__state == 2'b11) begin
+        if(Stream2Mmap_20__ap_done) begin
+          Stream2Mmap_20__state <= 2'b10;
+        end
+      end
+      if(Stream2Mmap_20__state == 2'b10) begin
+        if(Stream2Mmap_20__ap_done_global__q0) begin
+          Stream2Mmap_20__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Stream2Mmap_20__ap_start = (Stream2Mmap_20__state == 2'b01);
+  assign Stream2Mmap_21___n__q0 = n;
+  assign Stream2Mmap_21___rmem21__q0 = rmem21;
+  assign Stream2Mmap_21__ap_start_global__q0 = ap_start__q0;
+  assign Stream2Mmap_21__is_done__q0 = (Stream2Mmap_21__state == 2'b10);
+  assign Stream2Mmap_21__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Stream2Mmap_21__state <= 2'b00;
+    end else begin
+      if(Stream2Mmap_21__state == 2'b00) begin
+        if(Stream2Mmap_21__ap_start_global__q0) begin
+          Stream2Mmap_21__state <= 2'b01;
+        end
+      end
+      if(Stream2Mmap_21__state == 2'b01) begin
+        if(Stream2Mmap_21__ap_ready) begin
+          if(Stream2Mmap_21__ap_done) begin
+            Stream2Mmap_21__state <= 2'b10;
+          end else begin
+            Stream2Mmap_21__state <= 2'b11;
+          end
+        end
+      end
+      if(Stream2Mmap_21__state == 2'b11) begin
+        if(Stream2Mmap_21__ap_done) begin
+          Stream2Mmap_21__state <= 2'b10;
+        end
+      end
+      if(Stream2Mmap_21__state == 2'b10) begin
+        if(Stream2Mmap_21__ap_done_global__q0) begin
+          Stream2Mmap_21__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Stream2Mmap_21__ap_start = (Stream2Mmap_21__state == 2'b01);
+  assign Stream2Mmap_22___n__q0 = n;
+  assign Stream2Mmap_22___rmem22__q0 = rmem22;
+  assign Stream2Mmap_22__ap_start_global__q0 = ap_start__q0;
+  assign Stream2Mmap_22__is_done__q0 = (Stream2Mmap_22__state == 2'b10);
+  assign Stream2Mmap_22__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Stream2Mmap_22__state <= 2'b00;
+    end else begin
+      if(Stream2Mmap_22__state == 2'b00) begin
+        if(Stream2Mmap_22__ap_start_global__q0) begin
+          Stream2Mmap_22__state <= 2'b01;
+        end
+      end
+      if(Stream2Mmap_22__state == 2'b01) begin
+        if(Stream2Mmap_22__ap_ready) begin
+          if(Stream2Mmap_22__ap_done) begin
+            Stream2Mmap_22__state <= 2'b10;
+          end else begin
+            Stream2Mmap_22__state <= 2'b11;
+          end
+        end
+      end
+      if(Stream2Mmap_22__state == 2'b11) begin
+        if(Stream2Mmap_22__ap_done) begin
+          Stream2Mmap_22__state <= 2'b10;
+        end
+      end
+      if(Stream2Mmap_22__state == 2'b10) begin
+        if(Stream2Mmap_22__ap_done_global__q0) begin
+          Stream2Mmap_22__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Stream2Mmap_22__ap_start = (Stream2Mmap_22__state == 2'b01);
+  assign Stream2Mmap_23___n__q0 = n;
+  assign Stream2Mmap_23___rmem23__q0 = rmem23;
+  assign Stream2Mmap_23__ap_start_global__q0 = ap_start__q0;
+  assign Stream2Mmap_23__is_done__q0 = (Stream2Mmap_23__state == 2'b10);
+  assign Stream2Mmap_23__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Stream2Mmap_23__state <= 2'b00;
+    end else begin
+      if(Stream2Mmap_23__state == 2'b00) begin
+        if(Stream2Mmap_23__ap_start_global__q0) begin
+          Stream2Mmap_23__state <= 2'b01;
+        end
+      end
+      if(Stream2Mmap_23__state == 2'b01) begin
+        if(Stream2Mmap_23__ap_ready) begin
+          if(Stream2Mmap_23__ap_done) begin
+            Stream2Mmap_23__state <= 2'b10;
+          end else begin
+            Stream2Mmap_23__state <= 2'b11;
+          end
+        end
+      end
+      if(Stream2Mmap_23__state == 2'b11) begin
+        if(Stream2Mmap_23__ap_done) begin
+          Stream2Mmap_23__state <= 2'b10;
+        end
+      end
+      if(Stream2Mmap_23__state == 2'b10) begin
+        if(Stream2Mmap_23__ap_done_global__q0) begin
+          Stream2Mmap_23__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Stream2Mmap_23__ap_start = (Stream2Mmap_23__state == 2'b01);
+  assign Stream2Mmap_24___n__q0 = n;
+  assign Stream2Mmap_24___rmem24__q0 = rmem24;
+  assign Stream2Mmap_24__ap_start_global__q0 = ap_start__q0;
+  assign Stream2Mmap_24__is_done__q0 = (Stream2Mmap_24__state == 2'b10);
+  assign Stream2Mmap_24__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Stream2Mmap_24__state <= 2'b00;
+    end else begin
+      if(Stream2Mmap_24__state == 2'b00) begin
+        if(Stream2Mmap_24__ap_start_global__q0) begin
+          Stream2Mmap_24__state <= 2'b01;
+        end
+      end
+      if(Stream2Mmap_24__state == 2'b01) begin
+        if(Stream2Mmap_24__ap_ready) begin
+          if(Stream2Mmap_24__ap_done) begin
+            Stream2Mmap_24__state <= 2'b10;
+          end else begin
+            Stream2Mmap_24__state <= 2'b11;
+          end
+        end
+      end
+      if(Stream2Mmap_24__state == 2'b11) begin
+        if(Stream2Mmap_24__ap_done) begin
+          Stream2Mmap_24__state <= 2'b10;
+        end
+      end
+      if(Stream2Mmap_24__state == 2'b10) begin
+        if(Stream2Mmap_24__ap_done_global__q0) begin
+          Stream2Mmap_24__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Stream2Mmap_24__ap_start = (Stream2Mmap_24__state == 2'b01);
+  assign Stream2Mmap_25___n__q0 = n;
+  assign Stream2Mmap_25___rmem25__q0 = rmem25;
+  assign Stream2Mmap_25__ap_start_global__q0 = ap_start__q0;
+  assign Stream2Mmap_25__is_done__q0 = (Stream2Mmap_25__state == 2'b10);
+  assign Stream2Mmap_25__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Stream2Mmap_25__state <= 2'b00;
+    end else begin
+      if(Stream2Mmap_25__state == 2'b00) begin
+        if(Stream2Mmap_25__ap_start_global__q0) begin
+          Stream2Mmap_25__state <= 2'b01;
+        end
+      end
+      if(Stream2Mmap_25__state == 2'b01) begin
+        if(Stream2Mmap_25__ap_ready) begin
+          if(Stream2Mmap_25__ap_done) begin
+            Stream2Mmap_25__state <= 2'b10;
+          end else begin
+            Stream2Mmap_25__state <= 2'b11;
+          end
+        end
+      end
+      if(Stream2Mmap_25__state == 2'b11) begin
+        if(Stream2Mmap_25__ap_done) begin
+          Stream2Mmap_25__state <= 2'b10;
+        end
+      end
+      if(Stream2Mmap_25__state == 2'b10) begin
+        if(Stream2Mmap_25__ap_done_global__q0) begin
+          Stream2Mmap_25__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Stream2Mmap_25__ap_start = (Stream2Mmap_25__state == 2'b01);
+  assign Stream2Mmap_26___n__q0 = n;
+  assign Stream2Mmap_26___rmem26__q0 = rmem26;
+  assign Stream2Mmap_26__ap_start_global__q0 = ap_start__q0;
+  assign Stream2Mmap_26__is_done__q0 = (Stream2Mmap_26__state == 2'b10);
+  assign Stream2Mmap_26__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Stream2Mmap_26__state <= 2'b00;
+    end else begin
+      if(Stream2Mmap_26__state == 2'b00) begin
+        if(Stream2Mmap_26__ap_start_global__q0) begin
+          Stream2Mmap_26__state <= 2'b01;
+        end
+      end
+      if(Stream2Mmap_26__state == 2'b01) begin
+        if(Stream2Mmap_26__ap_ready) begin
+          if(Stream2Mmap_26__ap_done) begin
+            Stream2Mmap_26__state <= 2'b10;
+          end else begin
+            Stream2Mmap_26__state <= 2'b11;
+          end
+        end
+      end
+      if(Stream2Mmap_26__state == 2'b11) begin
+        if(Stream2Mmap_26__ap_done) begin
+          Stream2Mmap_26__state <= 2'b10;
+        end
+      end
+      if(Stream2Mmap_26__state == 2'b10) begin
+        if(Stream2Mmap_26__ap_done_global__q0) begin
+          Stream2Mmap_26__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Stream2Mmap_26__ap_start = (Stream2Mmap_26__state == 2'b01);
+  assign Stream2Mmap_27___n__q0 = n;
+  assign Stream2Mmap_27___rmem27__q0 = rmem27;
+  assign Stream2Mmap_27__ap_start_global__q0 = ap_start__q0;
+  assign Stream2Mmap_27__is_done__q0 = (Stream2Mmap_27__state == 2'b10);
+  assign Stream2Mmap_27__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      Stream2Mmap_27__state <= 2'b00;
+    end else begin
+      if(Stream2Mmap_27__state == 2'b00) begin
+        if(Stream2Mmap_27__ap_start_global__q0) begin
+          Stream2Mmap_27__state <= 2'b01;
+        end
+      end
+      if(Stream2Mmap_27__state == 2'b01) begin
+        if(Stream2Mmap_27__ap_ready) begin
+          if(Stream2Mmap_27__ap_done) begin
+            Stream2Mmap_27__state <= 2'b10;
+          end else begin
+            Stream2Mmap_27__state <= 2'b11;
+          end
+        end
+      end
+      if(Stream2Mmap_27__state == 2'b11) begin
+        if(Stream2Mmap_27__ap_done) begin
+          Stream2Mmap_27__state <= 2'b10;
+        end
+      end
+      if(Stream2Mmap_27__state == 2'b10) begin
+        if(Stream2Mmap_27__ap_done_global__q0) begin
+          Stream2Mmap_27__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign Stream2Mmap_27__ap_start = (Stream2Mmap_27__state == 2'b01);
+  assign yshift_0___n__q0 = n;
+  assign yshift_0__ap_start_global__q0 = ap_start__q0;
+  assign yshift_0__is_done__q0 = (yshift_0__state == 2'b10);
+  assign yshift_0__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      yshift_0__state <= 2'b00;
+    end else begin
+      if(yshift_0__state == 2'b00) begin
+        if(yshift_0__ap_start_global__q0) begin
+          yshift_0__state <= 2'b01;
+        end
+      end
+      if(yshift_0__state == 2'b01) begin
+        if(yshift_0__ap_ready) begin
+          if(yshift_0__ap_done) begin
+            yshift_0__state <= 2'b10;
+          end else begin
+            yshift_0__state <= 2'b11;
+          end
+        end
+      end
+      if(yshift_0__state == 2'b11) begin
+        if(yshift_0__ap_done) begin
+          yshift_0__state <= 2'b10;
+        end
+      end
+      if(yshift_0__state == 2'b10) begin
+        if(yshift_0__ap_done_global__q0) begin
+          yshift_0__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign yshift_0__ap_start = (yshift_0__state == 2'b01);
+  assign yshift_1___n__q0 = n;
+  assign yshift_1__ap_start_global__q0 = ap_start__q0;
+  assign yshift_1__is_done__q0 = (yshift_1__state == 2'b10);
+  assign yshift_1__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      yshift_1__state <= 2'b00;
+    end else begin
+      if(yshift_1__state == 2'b00) begin
+        if(yshift_1__ap_start_global__q0) begin
+          yshift_1__state <= 2'b01;
+        end
+      end
+      if(yshift_1__state == 2'b01) begin
+        if(yshift_1__ap_ready) begin
+          if(yshift_1__ap_done) begin
+            yshift_1__state <= 2'b10;
+          end else begin
+            yshift_1__state <= 2'b11;
+          end
+        end
+      end
+      if(yshift_1__state == 2'b11) begin
+        if(yshift_1__ap_done) begin
+          yshift_1__state <= 2'b10;
+        end
+      end
+      if(yshift_1__state == 2'b10) begin
+        if(yshift_1__ap_done_global__q0) begin
+          yshift_1__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign yshift_1__ap_start = (yshift_1__state == 2'b01);
+  assign yshift_2___n__q0 = n;
+  assign yshift_2__ap_start_global__q0 = ap_start__q0;
+  assign yshift_2__is_done__q0 = (yshift_2__state == 2'b10);
+  assign yshift_2__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      yshift_2__state <= 2'b00;
+    end else begin
+      if(yshift_2__state == 2'b00) begin
+        if(yshift_2__ap_start_global__q0) begin
+          yshift_2__state <= 2'b01;
+        end
+      end
+      if(yshift_2__state == 2'b01) begin
+        if(yshift_2__ap_ready) begin
+          if(yshift_2__ap_done) begin
+            yshift_2__state <= 2'b10;
+          end else begin
+            yshift_2__state <= 2'b11;
+          end
+        end
+      end
+      if(yshift_2__state == 2'b11) begin
+        if(yshift_2__ap_done) begin
+          yshift_2__state <= 2'b10;
+        end
+      end
+      if(yshift_2__state == 2'b10) begin
+        if(yshift_2__ap_done_global__q0) begin
+          yshift_2__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign yshift_2__ap_start = (yshift_2__state == 2'b01);
+  assign yshift_3___n__q0 = n;
+  assign yshift_3__ap_start_global__q0 = ap_start__q0;
+  assign yshift_3__is_done__q0 = (yshift_3__state == 2'b10);
+  assign yshift_3__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      yshift_3__state <= 2'b00;
+    end else begin
+      if(yshift_3__state == 2'b00) begin
+        if(yshift_3__ap_start_global__q0) begin
+          yshift_3__state <= 2'b01;
+        end
+      end
+      if(yshift_3__state == 2'b01) begin
+        if(yshift_3__ap_ready) begin
+          if(yshift_3__ap_done) begin
+            yshift_3__state <= 2'b10;
+          end else begin
+            yshift_3__state <= 2'b11;
+          end
+        end
+      end
+      if(yshift_3__state == 2'b11) begin
+        if(yshift_3__ap_done) begin
+          yshift_3__state <= 2'b10;
+        end
+      end
+      if(yshift_3__state == 2'b10) begin
+        if(yshift_3__ap_done_global__q0) begin
+          yshift_3__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign yshift_3__ap_start = (yshift_3__state == 2'b01);
+  assign yshift_4___n__q0 = n;
+  assign yshift_4__ap_start_global__q0 = ap_start__q0;
+  assign yshift_4__is_done__q0 = (yshift_4__state == 2'b10);
+  assign yshift_4__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      yshift_4__state <= 2'b00;
+    end else begin
+      if(yshift_4__state == 2'b00) begin
+        if(yshift_4__ap_start_global__q0) begin
+          yshift_4__state <= 2'b01;
+        end
+      end
+      if(yshift_4__state == 2'b01) begin
+        if(yshift_4__ap_ready) begin
+          if(yshift_4__ap_done) begin
+            yshift_4__state <= 2'b10;
+          end else begin
+            yshift_4__state <= 2'b11;
+          end
+        end
+      end
+      if(yshift_4__state == 2'b11) begin
+        if(yshift_4__ap_done) begin
+          yshift_4__state <= 2'b10;
+        end
+      end
+      if(yshift_4__state == 2'b10) begin
+        if(yshift_4__ap_done_global__q0) begin
+          yshift_4__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign yshift_4__ap_start = (yshift_4__state == 2'b01);
+  assign yshift_5___n__q0 = n;
+  assign yshift_5__ap_start_global__q0 = ap_start__q0;
+  assign yshift_5__is_done__q0 = (yshift_5__state == 2'b10);
+  assign yshift_5__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      yshift_5__state <= 2'b00;
+    end else begin
+      if(yshift_5__state == 2'b00) begin
+        if(yshift_5__ap_start_global__q0) begin
+          yshift_5__state <= 2'b01;
+        end
+      end
+      if(yshift_5__state == 2'b01) begin
+        if(yshift_5__ap_ready) begin
+          if(yshift_5__ap_done) begin
+            yshift_5__state <= 2'b10;
+          end else begin
+            yshift_5__state <= 2'b11;
+          end
+        end
+      end
+      if(yshift_5__state == 2'b11) begin
+        if(yshift_5__ap_done) begin
+          yshift_5__state <= 2'b10;
+        end
+      end
+      if(yshift_5__state == 2'b10) begin
+        if(yshift_5__ap_done_global__q0) begin
+          yshift_5__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign yshift_5__ap_start = (yshift_5__state == 2'b01);
+  assign yshift_6___n__q0 = n;
+  assign yshift_6__ap_start_global__q0 = ap_start__q0;
+  assign yshift_6__is_done__q0 = (yshift_6__state == 2'b10);
+  assign yshift_6__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      yshift_6__state <= 2'b00;
+    end else begin
+      if(yshift_6__state == 2'b00) begin
+        if(yshift_6__ap_start_global__q0) begin
+          yshift_6__state <= 2'b01;
+        end
+      end
+      if(yshift_6__state == 2'b01) begin
+        if(yshift_6__ap_ready) begin
+          if(yshift_6__ap_done) begin
+            yshift_6__state <= 2'b10;
+          end else begin
+            yshift_6__state <= 2'b11;
+          end
+        end
+      end
+      if(yshift_6__state == 2'b11) begin
+        if(yshift_6__ap_done) begin
+          yshift_6__state <= 2'b10;
+        end
+      end
+      if(yshift_6__state == 2'b10) begin
+        if(yshift_6__ap_done_global__q0) begin
+          yshift_6__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign yshift_6__ap_start = (yshift_6__state == 2'b01);
+  assign yshift_7___n__q0 = n;
+  assign yshift_7__ap_start_global__q0 = ap_start__q0;
+  assign yshift_7__is_done__q0 = (yshift_7__state == 2'b10);
+  assign yshift_7__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      yshift_7__state <= 2'b00;
+    end else begin
+      if(yshift_7__state == 2'b00) begin
+        if(yshift_7__ap_start_global__q0) begin
+          yshift_7__state <= 2'b01;
+        end
+      end
+      if(yshift_7__state == 2'b01) begin
+        if(yshift_7__ap_ready) begin
+          if(yshift_7__ap_done) begin
+            yshift_7__state <= 2'b10;
+          end else begin
+            yshift_7__state <= 2'b11;
+          end
+        end
+      end
+      if(yshift_7__state == 2'b11) begin
+        if(yshift_7__ap_done) begin
+          yshift_7__state <= 2'b10;
+        end
+      end
+      if(yshift_7__state == 2'b10) begin
+        if(yshift_7__ap_done_global__q0) begin
+          yshift_7__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign yshift_7__ap_start = (yshift_7__state == 2'b01);
+  assign yshift_8___n__q0 = n;
+  assign yshift_8__ap_start_global__q0 = ap_start__q0;
+  assign yshift_8__is_done__q0 = (yshift_8__state == 2'b10);
+  assign yshift_8__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      yshift_8__state <= 2'b00;
+    end else begin
+      if(yshift_8__state == 2'b00) begin
+        if(yshift_8__ap_start_global__q0) begin
+          yshift_8__state <= 2'b01;
+        end
+      end
+      if(yshift_8__state == 2'b01) begin
+        if(yshift_8__ap_ready) begin
+          if(yshift_8__ap_done) begin
+            yshift_8__state <= 2'b10;
+          end else begin
+            yshift_8__state <= 2'b11;
+          end
+        end
+      end
+      if(yshift_8__state == 2'b11) begin
+        if(yshift_8__ap_done) begin
+          yshift_8__state <= 2'b10;
+        end
+      end
+      if(yshift_8__state == 2'b10) begin
+        if(yshift_8__ap_done_global__q0) begin
+          yshift_8__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign yshift_8__ap_start = (yshift_8__state == 2'b01);
+  assign yshift_9___n__q0 = n;
+  assign yshift_9__ap_start_global__q0 = ap_start__q0;
+  assign yshift_9__is_done__q0 = (yshift_9__state == 2'b10);
+  assign yshift_9__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      yshift_9__state <= 2'b00;
+    end else begin
+      if(yshift_9__state == 2'b00) begin
+        if(yshift_9__ap_start_global__q0) begin
+          yshift_9__state <= 2'b01;
+        end
+      end
+      if(yshift_9__state == 2'b01) begin
+        if(yshift_9__ap_ready) begin
+          if(yshift_9__ap_done) begin
+            yshift_9__state <= 2'b10;
+          end else begin
+            yshift_9__state <= 2'b11;
+          end
+        end
+      end
+      if(yshift_9__state == 2'b11) begin
+        if(yshift_9__ap_done) begin
+          yshift_9__state <= 2'b10;
+        end
+      end
+      if(yshift_9__state == 2'b10) begin
+        if(yshift_9__ap_done_global__q0) begin
+          yshift_9__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign yshift_9__ap_start = (yshift_9__state == 2'b01);
+  assign yshift_10___n__q0 = n;
+  assign yshift_10__ap_start_global__q0 = ap_start__q0;
+  assign yshift_10__is_done__q0 = (yshift_10__state == 2'b10);
+  assign yshift_10__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      yshift_10__state <= 2'b00;
+    end else begin
+      if(yshift_10__state == 2'b00) begin
+        if(yshift_10__ap_start_global__q0) begin
+          yshift_10__state <= 2'b01;
+        end
+      end
+      if(yshift_10__state == 2'b01) begin
+        if(yshift_10__ap_ready) begin
+          if(yshift_10__ap_done) begin
+            yshift_10__state <= 2'b10;
+          end else begin
+            yshift_10__state <= 2'b11;
+          end
+        end
+      end
+      if(yshift_10__state == 2'b11) begin
+        if(yshift_10__ap_done) begin
+          yshift_10__state <= 2'b10;
+        end
+      end
+      if(yshift_10__state == 2'b10) begin
+        if(yshift_10__ap_done_global__q0) begin
+          yshift_10__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign yshift_10__ap_start = (yshift_10__state == 2'b01);
+  assign yshift_11___n__q0 = n;
+  assign yshift_11__ap_start_global__q0 = ap_start__q0;
+  assign yshift_11__is_done__q0 = (yshift_11__state == 2'b10);
+  assign yshift_11__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      yshift_11__state <= 2'b00;
+    end else begin
+      if(yshift_11__state == 2'b00) begin
+        if(yshift_11__ap_start_global__q0) begin
+          yshift_11__state <= 2'b01;
+        end
+      end
+      if(yshift_11__state == 2'b01) begin
+        if(yshift_11__ap_ready) begin
+          if(yshift_11__ap_done) begin
+            yshift_11__state <= 2'b10;
+          end else begin
+            yshift_11__state <= 2'b11;
+          end
+        end
+      end
+      if(yshift_11__state == 2'b11) begin
+        if(yshift_11__ap_done) begin
+          yshift_11__state <= 2'b10;
+        end
+      end
+      if(yshift_11__state == 2'b10) begin
+        if(yshift_11__ap_done_global__q0) begin
+          yshift_11__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign yshift_11__ap_start = (yshift_11__state == 2'b01);
+  assign yshift_12___n__q0 = n;
+  assign yshift_12__ap_start_global__q0 = ap_start__q0;
+  assign yshift_12__is_done__q0 = (yshift_12__state == 2'b10);
+  assign yshift_12__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      yshift_12__state <= 2'b00;
+    end else begin
+      if(yshift_12__state == 2'b00) begin
+        if(yshift_12__ap_start_global__q0) begin
+          yshift_12__state <= 2'b01;
+        end
+      end
+      if(yshift_12__state == 2'b01) begin
+        if(yshift_12__ap_ready) begin
+          if(yshift_12__ap_done) begin
+            yshift_12__state <= 2'b10;
+          end else begin
+            yshift_12__state <= 2'b11;
+          end
+        end
+      end
+      if(yshift_12__state == 2'b11) begin
+        if(yshift_12__ap_done) begin
+          yshift_12__state <= 2'b10;
+        end
+      end
+      if(yshift_12__state == 2'b10) begin
+        if(yshift_12__ap_done_global__q0) begin
+          yshift_12__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign yshift_12__ap_start = (yshift_12__state == 2'b01);
+  assign yshift_13___n__q0 = n;
+  assign yshift_13__ap_start_global__q0 = ap_start__q0;
+  assign yshift_13__is_done__q0 = (yshift_13__state == 2'b10);
+  assign yshift_13__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      yshift_13__state <= 2'b00;
+    end else begin
+      if(yshift_13__state == 2'b00) begin
+        if(yshift_13__ap_start_global__q0) begin
+          yshift_13__state <= 2'b01;
+        end
+      end
+      if(yshift_13__state == 2'b01) begin
+        if(yshift_13__ap_ready) begin
+          if(yshift_13__ap_done) begin
+            yshift_13__state <= 2'b10;
+          end else begin
+            yshift_13__state <= 2'b11;
+          end
+        end
+      end
+      if(yshift_13__state == 2'b11) begin
+        if(yshift_13__ap_done) begin
+          yshift_13__state <= 2'b10;
+        end
+      end
+      if(yshift_13__state == 2'b10) begin
+        if(yshift_13__ap_done_global__q0) begin
+          yshift_13__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign yshift_13__ap_start = (yshift_13__state == 2'b01);
+  assign yshift_14___n__q0 = n;
+  assign yshift_14__ap_start_global__q0 = ap_start__q0;
+  assign yshift_14__is_done__q0 = (yshift_14__state == 2'b10);
+  assign yshift_14__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      yshift_14__state <= 2'b00;
+    end else begin
+      if(yshift_14__state == 2'b00) begin
+        if(yshift_14__ap_start_global__q0) begin
+          yshift_14__state <= 2'b01;
+        end
+      end
+      if(yshift_14__state == 2'b01) begin
+        if(yshift_14__ap_ready) begin
+          if(yshift_14__ap_done) begin
+            yshift_14__state <= 2'b10;
+          end else begin
+            yshift_14__state <= 2'b11;
+          end
+        end
+      end
+      if(yshift_14__state == 2'b11) begin
+        if(yshift_14__ap_done) begin
+          yshift_14__state <= 2'b10;
+        end
+      end
+      if(yshift_14__state == 2'b10) begin
+        if(yshift_14__ap_done_global__q0) begin
+          yshift_14__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign yshift_14__ap_start = (yshift_14__state == 2'b01);
+  assign yshift_15___n__q0 = n;
+  assign yshift_15__ap_start_global__q0 = ap_start__q0;
+  assign yshift_15__is_done__q0 = (yshift_15__state == 2'b10);
+  assign yshift_15__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      yshift_15__state <= 2'b00;
+    end else begin
+      if(yshift_15__state == 2'b00) begin
+        if(yshift_15__ap_start_global__q0) begin
+          yshift_15__state <= 2'b01;
+        end
+      end
+      if(yshift_15__state == 2'b01) begin
+        if(yshift_15__ap_ready) begin
+          if(yshift_15__ap_done) begin
+            yshift_15__state <= 2'b10;
+          end else begin
+            yshift_15__state <= 2'b11;
+          end
+        end
+      end
+      if(yshift_15__state == 2'b11) begin
+        if(yshift_15__ap_done) begin
+          yshift_15__state <= 2'b10;
+        end
+      end
+      if(yshift_15__state == 2'b10) begin
+        if(yshift_15__ap_done_global__q0) begin
+          yshift_15__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign yshift_15__ap_start = (yshift_15__state == 2'b01);
+  assign yshift_16___n__q0 = n;
+  assign yshift_16__ap_start_global__q0 = ap_start__q0;
+  assign yshift_16__is_done__q0 = (yshift_16__state == 2'b10);
+  assign yshift_16__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      yshift_16__state <= 2'b00;
+    end else begin
+      if(yshift_16__state == 2'b00) begin
+        if(yshift_16__ap_start_global__q0) begin
+          yshift_16__state <= 2'b01;
+        end
+      end
+      if(yshift_16__state == 2'b01) begin
+        if(yshift_16__ap_ready) begin
+          if(yshift_16__ap_done) begin
+            yshift_16__state <= 2'b10;
+          end else begin
+            yshift_16__state <= 2'b11;
+          end
+        end
+      end
+      if(yshift_16__state == 2'b11) begin
+        if(yshift_16__ap_done) begin
+          yshift_16__state <= 2'b10;
+        end
+      end
+      if(yshift_16__state == 2'b10) begin
+        if(yshift_16__ap_done_global__q0) begin
+          yshift_16__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign yshift_16__ap_start = (yshift_16__state == 2'b01);
+  assign yshift_17___n__q0 = n;
+  assign yshift_17__ap_start_global__q0 = ap_start__q0;
+  assign yshift_17__is_done__q0 = (yshift_17__state == 2'b10);
+  assign yshift_17__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      yshift_17__state <= 2'b00;
+    end else begin
+      if(yshift_17__state == 2'b00) begin
+        if(yshift_17__ap_start_global__q0) begin
+          yshift_17__state <= 2'b01;
+        end
+      end
+      if(yshift_17__state == 2'b01) begin
+        if(yshift_17__ap_ready) begin
+          if(yshift_17__ap_done) begin
+            yshift_17__state <= 2'b10;
+          end else begin
+            yshift_17__state <= 2'b11;
+          end
+        end
+      end
+      if(yshift_17__state == 2'b11) begin
+        if(yshift_17__ap_done) begin
+          yshift_17__state <= 2'b10;
+        end
+      end
+      if(yshift_17__state == 2'b10) begin
+        if(yshift_17__ap_done_global__q0) begin
+          yshift_17__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign yshift_17__ap_start = (yshift_17__state == 2'b01);
+  assign yshift_18___n__q0 = n;
+  assign yshift_18__ap_start_global__q0 = ap_start__q0;
+  assign yshift_18__is_done__q0 = (yshift_18__state == 2'b10);
+  assign yshift_18__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      yshift_18__state <= 2'b00;
+    end else begin
+      if(yshift_18__state == 2'b00) begin
+        if(yshift_18__ap_start_global__q0) begin
+          yshift_18__state <= 2'b01;
+        end
+      end
+      if(yshift_18__state == 2'b01) begin
+        if(yshift_18__ap_ready) begin
+          if(yshift_18__ap_done) begin
+            yshift_18__state <= 2'b10;
+          end else begin
+            yshift_18__state <= 2'b11;
+          end
+        end
+      end
+      if(yshift_18__state == 2'b11) begin
+        if(yshift_18__ap_done) begin
+          yshift_18__state <= 2'b10;
+        end
+      end
+      if(yshift_18__state == 2'b10) begin
+        if(yshift_18__ap_done_global__q0) begin
+          yshift_18__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign yshift_18__ap_start = (yshift_18__state == 2'b01);
+  assign yshift_19___n__q0 = n;
+  assign yshift_19__ap_start_global__q0 = ap_start__q0;
+  assign yshift_19__is_done__q0 = (yshift_19__state == 2'b10);
+  assign yshift_19__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      yshift_19__state <= 2'b00;
+    end else begin
+      if(yshift_19__state == 2'b00) begin
+        if(yshift_19__ap_start_global__q0) begin
+          yshift_19__state <= 2'b01;
+        end
+      end
+      if(yshift_19__state == 2'b01) begin
+        if(yshift_19__ap_ready) begin
+          if(yshift_19__ap_done) begin
+            yshift_19__state <= 2'b10;
+          end else begin
+            yshift_19__state <= 2'b11;
+          end
+        end
+      end
+      if(yshift_19__state == 2'b11) begin
+        if(yshift_19__ap_done) begin
+          yshift_19__state <= 2'b10;
+        end
+      end
+      if(yshift_19__state == 2'b10) begin
+        if(yshift_19__ap_done_global__q0) begin
+          yshift_19__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign yshift_19__ap_start = (yshift_19__state == 2'b01);
+  assign yshift_20___n__q0 = n;
+  assign yshift_20__ap_start_global__q0 = ap_start__q0;
+  assign yshift_20__is_done__q0 = (yshift_20__state == 2'b10);
+  assign yshift_20__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      yshift_20__state <= 2'b00;
+    end else begin
+      if(yshift_20__state == 2'b00) begin
+        if(yshift_20__ap_start_global__q0) begin
+          yshift_20__state <= 2'b01;
+        end
+      end
+      if(yshift_20__state == 2'b01) begin
+        if(yshift_20__ap_ready) begin
+          if(yshift_20__ap_done) begin
+            yshift_20__state <= 2'b10;
+          end else begin
+            yshift_20__state <= 2'b11;
+          end
+        end
+      end
+      if(yshift_20__state == 2'b11) begin
+        if(yshift_20__ap_done) begin
+          yshift_20__state <= 2'b10;
+        end
+      end
+      if(yshift_20__state == 2'b10) begin
+        if(yshift_20__ap_done_global__q0) begin
+          yshift_20__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign yshift_20__ap_start = (yshift_20__state == 2'b01);
+  assign yshift_21___n__q0 = n;
+  assign yshift_21__ap_start_global__q0 = ap_start__q0;
+  assign yshift_21__is_done__q0 = (yshift_21__state == 2'b10);
+  assign yshift_21__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      yshift_21__state <= 2'b00;
+    end else begin
+      if(yshift_21__state == 2'b00) begin
+        if(yshift_21__ap_start_global__q0) begin
+          yshift_21__state <= 2'b01;
+        end
+      end
+      if(yshift_21__state == 2'b01) begin
+        if(yshift_21__ap_ready) begin
+          if(yshift_21__ap_done) begin
+            yshift_21__state <= 2'b10;
+          end else begin
+            yshift_21__state <= 2'b11;
+          end
+        end
+      end
+      if(yshift_21__state == 2'b11) begin
+        if(yshift_21__ap_done) begin
+          yshift_21__state <= 2'b10;
+        end
+      end
+      if(yshift_21__state == 2'b10) begin
+        if(yshift_21__ap_done_global__q0) begin
+          yshift_21__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign yshift_21__ap_start = (yshift_21__state == 2'b01);
+  assign yshift_22___n__q0 = n;
+  assign yshift_22__ap_start_global__q0 = ap_start__q0;
+  assign yshift_22__is_done__q0 = (yshift_22__state == 2'b10);
+  assign yshift_22__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      yshift_22__state <= 2'b00;
+    end else begin
+      if(yshift_22__state == 2'b00) begin
+        if(yshift_22__ap_start_global__q0) begin
+          yshift_22__state <= 2'b01;
+        end
+      end
+      if(yshift_22__state == 2'b01) begin
+        if(yshift_22__ap_ready) begin
+          if(yshift_22__ap_done) begin
+            yshift_22__state <= 2'b10;
+          end else begin
+            yshift_22__state <= 2'b11;
+          end
+        end
+      end
+      if(yshift_22__state == 2'b11) begin
+        if(yshift_22__ap_done) begin
+          yshift_22__state <= 2'b10;
+        end
+      end
+      if(yshift_22__state == 2'b10) begin
+        if(yshift_22__ap_done_global__q0) begin
+          yshift_22__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign yshift_22__ap_start = (yshift_22__state == 2'b01);
+  assign yshift_23___n__q0 = n;
+  assign yshift_23__ap_start_global__q0 = ap_start__q0;
+  assign yshift_23__is_done__q0 = (yshift_23__state == 2'b10);
+  assign yshift_23__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      yshift_23__state <= 2'b00;
+    end else begin
+      if(yshift_23__state == 2'b00) begin
+        if(yshift_23__ap_start_global__q0) begin
+          yshift_23__state <= 2'b01;
+        end
+      end
+      if(yshift_23__state == 2'b01) begin
+        if(yshift_23__ap_ready) begin
+          if(yshift_23__ap_done) begin
+            yshift_23__state <= 2'b10;
+          end else begin
+            yshift_23__state <= 2'b11;
+          end
+        end
+      end
+      if(yshift_23__state == 2'b11) begin
+        if(yshift_23__ap_done) begin
+          yshift_23__state <= 2'b10;
+        end
+      end
+      if(yshift_23__state == 2'b10) begin
+        if(yshift_23__ap_done_global__q0) begin
+          yshift_23__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign yshift_23__ap_start = (yshift_23__state == 2'b01);
+  assign yshift_24___n__q0 = n;
+  assign yshift_24__ap_start_global__q0 = ap_start__q0;
+  assign yshift_24__is_done__q0 = (yshift_24__state == 2'b10);
+  assign yshift_24__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      yshift_24__state <= 2'b00;
+    end else begin
+      if(yshift_24__state == 2'b00) begin
+        if(yshift_24__ap_start_global__q0) begin
+          yshift_24__state <= 2'b01;
+        end
+      end
+      if(yshift_24__state == 2'b01) begin
+        if(yshift_24__ap_ready) begin
+          if(yshift_24__ap_done) begin
+            yshift_24__state <= 2'b10;
+          end else begin
+            yshift_24__state <= 2'b11;
+          end
+        end
+      end
+      if(yshift_24__state == 2'b11) begin
+        if(yshift_24__ap_done) begin
+          yshift_24__state <= 2'b10;
+        end
+      end
+      if(yshift_24__state == 2'b10) begin
+        if(yshift_24__ap_done_global__q0) begin
+          yshift_24__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign yshift_24__ap_start = (yshift_24__state == 2'b01);
+  assign yshift_25___n__q0 = n;
+  assign yshift_25__ap_start_global__q0 = ap_start__q0;
+  assign yshift_25__is_done__q0 = (yshift_25__state == 2'b10);
+  assign yshift_25__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      yshift_25__state <= 2'b00;
+    end else begin
+      if(yshift_25__state == 2'b00) begin
+        if(yshift_25__ap_start_global__q0) begin
+          yshift_25__state <= 2'b01;
+        end
+      end
+      if(yshift_25__state == 2'b01) begin
+        if(yshift_25__ap_ready) begin
+          if(yshift_25__ap_done) begin
+            yshift_25__state <= 2'b10;
+          end else begin
+            yshift_25__state <= 2'b11;
+          end
+        end
+      end
+      if(yshift_25__state == 2'b11) begin
+        if(yshift_25__ap_done) begin
+          yshift_25__state <= 2'b10;
+        end
+      end
+      if(yshift_25__state == 2'b10) begin
+        if(yshift_25__ap_done_global__q0) begin
+          yshift_25__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign yshift_25__ap_start = (yshift_25__state == 2'b01);
+  assign yshift_26___n__q0 = n;
+  assign yshift_26__ap_start_global__q0 = ap_start__q0;
+  assign yshift_26__is_done__q0 = (yshift_26__state == 2'b10);
+  assign yshift_26__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      yshift_26__state <= 2'b00;
+    end else begin
+      if(yshift_26__state == 2'b00) begin
+        if(yshift_26__ap_start_global__q0) begin
+          yshift_26__state <= 2'b01;
+        end
+      end
+      if(yshift_26__state == 2'b01) begin
+        if(yshift_26__ap_ready) begin
+          if(yshift_26__ap_done) begin
+            yshift_26__state <= 2'b10;
+          end else begin
+            yshift_26__state <= 2'b11;
+          end
+        end
+      end
+      if(yshift_26__state == 2'b11) begin
+        if(yshift_26__ap_done) begin
+          yshift_26__state <= 2'b10;
+        end
+      end
+      if(yshift_26__state == 2'b10) begin
+        if(yshift_26__ap_done_global__q0) begin
+          yshift_26__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign yshift_26__ap_start = (yshift_26__state == 2'b01);
+  assign yshift_27___n__q0 = n;
+  assign yshift_27__ap_start_global__q0 = ap_start__q0;
+  assign yshift_27__is_done__q0 = (yshift_27__state == 2'b10);
+  assign yshift_27__ap_done_global__q0 = ap_done__q0;
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      yshift_27__state <= 2'b00;
+    end else begin
+      if(yshift_27__state == 2'b00) begin
+        if(yshift_27__ap_start_global__q0) begin
+          yshift_27__state <= 2'b01;
+        end
+      end
+      if(yshift_27__state == 2'b01) begin
+        if(yshift_27__ap_ready) begin
+          if(yshift_27__ap_done) begin
+            yshift_27__state <= 2'b10;
+          end else begin
+            yshift_27__state <= 2'b11;
+          end
+        end
+      end
+      if(yshift_27__state == 2'b11) begin
+        if(yshift_27__ap_done) begin
+          yshift_27__state <= 2'b10;
+        end
+      end
+      if(yshift_27__state == 2'b10) begin
+        if(yshift_27__ap_done_global__q0) begin
+          yshift_27__state <= 2'b00;
+        end
+      end
+    end
+  end
+
+  assign yshift_27__ap_start = (yshift_27__state == 2'b01);
+
+  always @(posedge ap_clk) begin
+    if(~ap_rst_n) begin
+      tapa_state <= 2'b00;
+    end else begin
+      case(tapa_state)
+        2'b00: begin
+          if(ap_start__q0) begin
+            tapa_state <= 2'b01;
+          end
+        end
+        2'b01: begin
+          if(Mmap2Stream_0__is_done__q0 && Mmap2Stream_1__is_done__q0 && Mmap2Stream_2__is_done__q0 && Mmap2Stream_3__is_done__q0 && Mmap2Stream_4__is_done__q0 && Mmap2Stream_5__is_done__q0 && Mmap2Stream_6__is_done__q0 && Mmap2Stream_7__is_done__q0 && Mmap2Stream_8__is_done__q0 && Mmap2Stream_9__is_done__q0 && Mmap2Stream_10__is_done__q0 && Mmap2Stream_11__is_done__q0 && Mmap2Stream_12__is_done__q0 && Mmap2Stream_13__is_done__q0 && Mmap2Stream_14__is_done__q0 && Mmap2Stream_15__is_done__q0 && Mmap2Stream_16__is_done__q0 && Mmap2Stream_17__is_done__q0 && Mmap2Stream_18__is_done__q0 && Mmap2Stream_19__is_done__q0 && Mmap2Stream_20__is_done__q0 && Mmap2Stream_21__is_done__q0 && Mmap2Stream_22__is_done__q0 && Mmap2Stream_23__is_done__q0 && Mmap2Stream_24__is_done__q0 && Mmap2Stream_25__is_done__q0 && Mmap2Stream_26__is_done__q0 && Mmap2Stream_27__is_done__q0 && Stream2Mmap_0__is_done__q0 && Stream2Mmap_1__is_done__q0 && Stream2Mmap_2__is_done__q0 && Stream2Mmap_3__is_done__q0 && Stream2Mmap_4__is_done__q0 && Stream2Mmap_5__is_done__q0 && Stream2Mmap_6__is_done__q0 && Stream2Mmap_7__is_done__q0 && Stream2Mmap_8__is_done__q0 && Stream2Mmap_9__is_done__q0 && Stream2Mmap_10__is_done__q0 && Stream2Mmap_11__is_done__q0 && Stream2Mmap_12__is_done__q0 && Stream2Mmap_13__is_done__q0 && Stream2Mmap_14__is_done__q0 && Stream2Mmap_15__is_done__q0 && Stream2Mmap_16__is_done__q0 && Stream2Mmap_17__is_done__q0 && Stream2Mmap_18__is_done__q0 && Stream2Mmap_19__is_done__q0 && Stream2Mmap_20__is_done__q0 && Stream2Mmap_21__is_done__q0 && Stream2Mmap_22__is_done__q0 && Stream2Mmap_23__is_done__q0 && Stream2Mmap_24__is_done__q0 && Stream2Mmap_25__is_done__q0 && Stream2Mmap_26__is_done__q0 && Stream2Mmap_27__is_done__q0 && yshift_0__is_done__q0 && yshift_1__is_done__q0 && yshift_2__is_done__q0 && yshift_3__is_done__q0 && yshift_4__is_done__q0 && yshift_5__is_done__q0 && yshift_6__is_done__q0 && yshift_7__is_done__q0 && yshift_8__is_done__q0 && yshift_9__is_done__q0 && yshift_10__is_done__q0 && yshift_11__is_done__q0 && yshift_12__is_done__q0 && yshift_13__is_done__q0 && yshift_14__is_done__q0 && yshift_15__is_done__q0 && yshift_16__is_done__q0 && yshift_17__is_done__q0 && yshift_18__is_done__q0 && yshift_19__is_done__q0 && yshift_20__is_done__q0 && yshift_21__is_done__q0 && yshift_22__is_done__q0 && yshift_23__is_done__q0 && yshift_24__is_done__q0 && yshift_25__is_done__q0 && yshift_26__is_done__q0 && yshift_27__is_done__q0) begin
+            tapa_state <= 2'b10;
+          end
+        end
+        2'b10: begin
+          tapa_state <= 2'b00;
+          countdown <= 1'd0;
+        end
+        2'b11: begin
+          if(countdown == 1'd0) begin
+            tapa_state <= 2'b00;
+          end else begin
+            countdown <= (countdown - 1'd1);
+          end
+        end
+      endcase
+    end
+  end
+
+  assign ap_idle = (tapa_state == 2'b00);
+  assign ap_done = ap_done__q0;
+  assign ap_ready = ap_done__q0;
+  assign ap_start__q0 = ap_start;
+  assign ap_done__q0 = (tapa_state == 2'b10);
+
+endmodule
diff --git a/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/yshift.v b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/yshift.v
new file mode 100644
index 00000000..df872e19
--- /dev/null
+++ b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/yshift.v
@@ -0,0 +1,218 @@
+// ==============================================================
+// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit)
+// Version: 2022.2
+// Copyright (C) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+//
+// ===========================================================
+
+`timescale 1 ns / 1 ps
+
+(* CORE_GENERATION_INFO="yshift_yshift,hls_ip_2022_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xcu50-fsvh2104-2-e,HLS_INPUT_CLOCK=3.330000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.430900,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=72,HLS_SYN_LUT=198,HLS_VERSION=2022_2}" *)
+
+module yshift (
+        ap_clk,
+        ap_rst_n,
+        ap_start,
+        ap_done,
+        ap_idle,
+        ap_ready,
+        a_s_dout,
+        a_s_empty_n,
+        a_s_read,
+        a_peek_dout,
+        a_peek_empty_n,
+        a_peek_read,
+        b_din,
+        b_full_n,
+        b_write,
+        n
+);
+
+parameter    ap_ST_fsm_state1 = 3'd1;
+parameter    ap_ST_fsm_state2 = 3'd2;
+parameter    ap_ST_fsm_state3 = 3'd4;
+
+input   ap_clk;
+input   ap_rst_n;
+input   ap_start;
+output   ap_done;
+output   ap_idle;
+output   ap_ready;
+input  [512:0] a_s_dout;
+input   a_s_empty_n;
+output   a_s_read;
+input  [512:0] a_peek_dout;
+input   a_peek_empty_n;
+output   a_peek_read;
+output  [512:0] b_din;
+input   b_full_n;
+output   b_write;
+input  [63:0] n;
+
+reg ap_done;
+reg ap_idle;
+reg ap_ready;
+reg a_s_read;
+reg b_write;
+
+ reg    ap_rst_n_inv;
+(* fsm_encoding = "none" *) reg   [2:0] ap_CS_fsm;
+wire    ap_CS_fsm_state1;
+wire    grp_yshift_Pipeline_VITIS_LOOP_61_1_fu_68_ap_start;
+wire    grp_yshift_Pipeline_VITIS_LOOP_61_1_fu_68_ap_done;
+wire    grp_yshift_Pipeline_VITIS_LOOP_61_1_fu_68_ap_idle;
+wire    grp_yshift_Pipeline_VITIS_LOOP_61_1_fu_68_ap_ready;
+wire    grp_yshift_Pipeline_VITIS_LOOP_61_1_fu_68_a_s_read;
+wire   [512:0] grp_yshift_Pipeline_VITIS_LOOP_61_1_fu_68_b_din;
+wire    grp_yshift_Pipeline_VITIS_LOOP_61_1_fu_68_b_write;
+reg    grp_yshift_Pipeline_VITIS_LOOP_61_1_fu_68_ap_start_reg;
+reg   [2:0] ap_NS_fsm;
+wire    ap_NS_fsm_state2;
+wire    ap_CS_fsm_state3;
+reg    ap_ST_fsm_state1_blk;
+wire    ap_ST_fsm_state2_blk;
+reg    ap_ST_fsm_state3_blk;
+wire    ap_ce_reg;
+
+// power-on initialization
+initial begin
+#0 ap_CS_fsm = 3'd1;
+#0 grp_yshift_Pipeline_VITIS_LOOP_61_1_fu_68_ap_start_reg = 1'b0;
+end
+
+yshift_yshift_Pipeline_VITIS_LOOP_61_1 grp_yshift_Pipeline_VITIS_LOOP_61_1_fu_68(
+    .ap_clk(ap_clk),
+    .ap_rst(ap_rst_n_inv),
+    .ap_start(grp_yshift_Pipeline_VITIS_LOOP_61_1_fu_68_ap_start),
+    .ap_done(grp_yshift_Pipeline_VITIS_LOOP_61_1_fu_68_ap_done),
+    .ap_idle(grp_yshift_Pipeline_VITIS_LOOP_61_1_fu_68_ap_idle),
+    .ap_ready(grp_yshift_Pipeline_VITIS_LOOP_61_1_fu_68_ap_ready),
+    .a_s_dout(a_s_dout),
+    .a_s_empty_n(a_s_empty_n),
+    .a_s_read(grp_yshift_Pipeline_VITIS_LOOP_61_1_fu_68_a_s_read),
+    .b_din(grp_yshift_Pipeline_VITIS_LOOP_61_1_fu_68_b_din),
+    .b_full_n(b_full_n),
+    .b_write(grp_yshift_Pipeline_VITIS_LOOP_61_1_fu_68_b_write),
+    .n(n)
+);
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_CS_fsm <= ap_ST_fsm_state1;
+    end else begin
+        ap_CS_fsm <= ap_NS_fsm;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        grp_yshift_Pipeline_VITIS_LOOP_61_1_fu_68_ap_start_reg <= 1'b0;
+    end else begin
+        if (((1'b1 == ap_NS_fsm_state2) & (1'b1 == ap_CS_fsm_state1))) begin
+            grp_yshift_Pipeline_VITIS_LOOP_61_1_fu_68_ap_start_reg <= 1'b1;
+        end else if ((grp_yshift_Pipeline_VITIS_LOOP_61_1_fu_68_ap_ready == 1'b1)) begin
+            grp_yshift_Pipeline_VITIS_LOOP_61_1_fu_68_ap_start_reg <= 1'b0;
+        end
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state3)) begin
+        a_s_read = grp_yshift_Pipeline_VITIS_LOOP_61_1_fu_68_a_s_read;
+    end else begin
+        a_s_read = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((ap_start == 1'b0)) begin
+        ap_ST_fsm_state1_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state1_blk = 1'b0;
+    end
+end
+
+assign ap_ST_fsm_state2_blk = 1'b0;
+
+always @ (*) begin
+    if ((grp_yshift_Pipeline_VITIS_LOOP_61_1_fu_68_ap_done == 1'b0)) begin
+        ap_ST_fsm_state3_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state3_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((grp_yshift_Pipeline_VITIS_LOOP_61_1_fu_68_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state3))) begin
+        ap_done = 1'b1;
+    end else begin
+        ap_done = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin
+        ap_idle = 1'b1;
+    end else begin
+        ap_idle = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((grp_yshift_Pipeline_VITIS_LOOP_61_1_fu_68_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state3))) begin
+        ap_ready = 1'b1;
+    end else begin
+        ap_ready = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state3)) begin
+        b_write = grp_yshift_Pipeline_VITIS_LOOP_61_1_fu_68_b_write;
+    end else begin
+        b_write = 1'b0;
+    end
+end
+
+always @ (*) begin
+    case (ap_CS_fsm)
+        ap_ST_fsm_state1 : begin
+            if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end
+        end
+        ap_ST_fsm_state2 : begin
+            ap_NS_fsm = ap_ST_fsm_state3;
+        end
+        ap_ST_fsm_state3 : begin
+            if (((grp_yshift_Pipeline_VITIS_LOOP_61_1_fu_68_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state3))) begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state3;
+            end
+        end
+        default : begin
+            ap_NS_fsm = 'bx;
+        end
+    endcase
+end
+
+assign a_peek_read = 1'b0;
+
+assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
+
+assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2];
+
+assign ap_NS_fsm_state2 = ap_NS_fsm[32'd1];
+
+always @ (*) begin
+    ap_rst_n_inv = ~ap_rst_n;
+end
+
+assign b_din = grp_yshift_Pipeline_VITIS_LOOP_61_1_fu_68_b_din;
+
+assign grp_yshift_Pipeline_VITIS_LOOP_61_1_fu_68_ap_start = grp_yshift_Pipeline_VITIS_LOOP_61_1_fu_68_ap_start_reg;
+
+endmodule //yshift
diff --git a/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/yshift_flow_control_loop_pipe_sequential_init.v b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/yshift_flow_control_loop_pipe_sequential_init.v
new file mode 100644
index 00000000..7cc4ded0
--- /dev/null
+++ b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/yshift_flow_control_loop_pipe_sequential_init.v
@@ -0,0 +1,104 @@
+// ==============================================================
+// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit)
+// Tool Version Limit: 2019.12
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+
+`timescale 1 ns / 1 ps
+
+module yshift_flow_control_loop_pipe_sequential_init(
+        ap_clk,
+        ap_rst,
+        ap_start,
+        ap_ready,
+        ap_done,
+        ap_start_int,
+        ap_ready_int,
+        ap_done_int,
+        ap_continue_int,
+        ap_loop_init,
+        ap_loop_exit_ready,
+        ap_loop_exit_done
+);
+
+input   ap_clk;
+input   ap_rst;
+
+//Block level handshake with outside loop
+input   ap_start;
+output  ap_ready;
+output  ap_done;
+
+//Block level handshake with loop body
+output  ap_start_int;
+input   ap_ready_int;
+input   ap_done_int;
+output  ap_continue_int;
+
+//Init live in variables
+output   ap_loop_init;
+wire     ap_loop_init;
+reg ap_loop_init_int;
+reg ap_done;
+reg ap_done_cache;
+
+//Exit signal from loop body
+input   ap_loop_exit_ready;
+input   ap_loop_exit_done;
+
+// power-on initialization
+initial begin
+#0 ap_loop_init_int = 1'b1;
+#0 ap_done_cache = 1'b0;
+end
+
+assign ap_start_int = ap_start;
+
+assign ap_continue_int = 1'b1;
+
+assign ap_ready = ap_loop_exit_ready;
+
+//ap_loop_init is valid for the first II
+//of the first loop run so as to enable
+//the init block ops which are pushed into
+//the first state of the pipeline region
+always @ (posedge ap_clk)
+begin
+    if (ap_rst == 1'b1) begin
+        ap_loop_init_int <= 1'b1;
+    end else if(ap_loop_exit_done == 1'b1) begin
+        ap_loop_init_int <= 1'b1;
+    end else if(ap_ready_int == 1'b1) begin
+        ap_loop_init_int <= 1'b0;
+    end
+end
+
+assign ap_loop_init = ap_loop_init_int & ap_start;
+
+// if no ap_continue port and current module is not top module,
+// ap_done handshakes with ap_start. Internally, flow control sends out
+// ap_conintue_int = 1'b1 so the ap_done_int is asserted high for 1 clock cycle.
+// ap_done_cache is used to record ap_done_int, and de-assert if ap_start_int
+// is asserted, so DUT can start the next run
+always @(posedge ap_clk)
+begin
+    if (ap_rst == 1'b1) begin
+        ap_done_cache <= 1'b0;
+    end else if (ap_done_int == 1'b1) begin
+        ap_done_cache <= 1'b1;
+    end else if (ap_start_int == 1'b1) begin
+        ap_done_cache <= 1'b0;
+    end
+end
+
+// if no ap_continue port and current module is not top module, ap_done handshakes with ap_start
+always @(*)
+begin
+    if ((ap_done_int == 1'b1) || ((ap_done_cache == 1'b1) && (ap_start_int == 1'b0))) begin
+        ap_done = 1'b1;
+    end else begin
+        ap_done = 1'b0;
+    end
+end
+
+endmodule
diff --git a/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/yshift_yshift_Pipeline_VITIS_LOOP_61_1.v b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/yshift_yshift_Pipeline_VITIS_LOOP_61_1.v
new file mode 100644
index 00000000..e8407969
--- /dev/null
+++ b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w/yshift_yshift_Pipeline_VITIS_LOOP_61_1.v
@@ -0,0 +1,275 @@
+// ==============================================================
+// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit)
+// Version: 2022.2
+// Copyright (C) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+//
+// ===========================================================
+
+`timescale 1 ns / 1 ps
+
+module yshift_yshift_Pipeline_VITIS_LOOP_61_1 (
+        ap_clk,
+        ap_rst,
+        ap_start,
+        ap_done,
+        ap_idle,
+        ap_ready,
+        a_s_dout,
+        a_s_empty_n,
+        a_s_read,
+        b_din,
+        b_full_n,
+        b_write,
+        n
+);
+
+parameter    ap_ST_fsm_pp0_stage0 = 1'd1;
+
+input   ap_clk;
+input   ap_rst;
+input   ap_start;
+output   ap_done;
+output   ap_idle;
+output   ap_ready;
+input  [512:0] a_s_dout;
+input   a_s_empty_n;
+output   a_s_read;
+output  [512:0] b_din;
+input   b_full_n;
+output   b_write;
+input  [63:0] n;
+
+reg ap_idle;
+reg a_s_read;
+reg b_write;
+
+(* fsm_encoding = "none" *) reg   [0:0] ap_CS_fsm;
+wire    ap_CS_fsm_pp0_stage0;
+wire    ap_enable_reg_pp0_iter0;
+reg    ap_enable_reg_pp0_iter1;
+reg    ap_enable_reg_pp0_iter2;
+reg    ap_idle_pp0;
+wire    ap_block_state1_pp0_stage0_iter0;
+wire    ap_block_state2_pp0_stage0_iter1;
+reg    ap_block_state3_pp0_stage0_iter2;
+reg    ap_block_pp0_stage0_subdone;
+wire   [0:0] icmp_ln61_fu_71_p2;
+reg    ap_condition_exit_pp0_iter1_stage0;
+wire    ap_loop_exit_ready;
+reg    ap_ready_int;
+reg    a_s_blk_n;
+wire    ap_block_pp0_stage0;
+reg    b_blk_n;
+reg    ap_block_pp0_stage0_11001;
+reg   [63:0] i_fu_40;
+wire   [63:0] i_2_fu_76_p2;
+wire    ap_loop_init;
+reg    ap_block_pp0_stage0_01001;
+wire   [510:0] trunc_ln1669_fu_87_p1;
+reg    ap_done_reg;
+wire    ap_continue_int;
+reg    ap_done_int;
+reg   [0:0] ap_NS_fsm;
+wire    ap_enable_pp0;
+wire    ap_start_int;
+wire    ap_ce_reg;
+
+// power-on initialization
+initial begin
+#0 ap_CS_fsm = 1'd1;
+#0 ap_enable_reg_pp0_iter1 = 1'b0;
+#0 ap_enable_reg_pp0_iter2 = 1'b0;
+#0 ap_done_reg = 1'b0;
+end
+
+yshift_flow_control_loop_pipe_sequential_init flow_control_loop_pipe_sequential_init_U(
+    .ap_clk(ap_clk),
+    .ap_rst(ap_rst),
+    .ap_start(ap_start),
+    .ap_ready(ap_ready),
+    .ap_done(ap_done),
+    .ap_start_int(ap_start_int),
+    .ap_loop_init(ap_loop_init),
+    .ap_ready_int(ap_ready_int),
+    .ap_loop_exit_ready(ap_condition_exit_pp0_iter1_stage0),
+    .ap_loop_exit_done(ap_done_int),
+    .ap_continue_int(ap_continue_int),
+    .ap_done_int(ap_done_int)
+);
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_CS_fsm <= ap_ST_fsm_pp0_stage0;
+    end else begin
+        ap_CS_fsm <= ap_NS_fsm;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_done_reg <= 1'b0;
+    end else begin
+        if ((ap_continue_int == 1'b1)) begin
+            ap_done_reg <= 1'b0;
+        end else if (((ap_loop_exit_ready == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+            ap_done_reg <= 1'b1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_enable_reg_pp0_iter1 <= 1'b0;
+    end else begin
+        if ((1'b1 == ap_condition_exit_pp0_iter1_stage0)) begin
+            ap_enable_reg_pp0_iter1 <= 1'b0;
+        end else if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+            ap_enable_reg_pp0_iter1 <= ap_start_int;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_enable_reg_pp0_iter2 <= 1'b0;
+    end else begin
+        if ((1'b1 == ap_condition_exit_pp0_iter1_stage0)) begin
+            ap_enable_reg_pp0_iter2 <= 1'b0;
+        end else if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
+            ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        if ((ap_loop_init == 1'b1)) begin
+            i_fu_40 <= 64'd0;
+        end else if (((icmp_ln61_fu_71_p2 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin
+            i_fu_40 <= i_2_fu_76_p2;
+        end
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        a_s_blk_n = a_s_empty_n;
+    end else begin
+        a_s_blk_n = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        a_s_read = 1'b1;
+    end else begin
+        a_s_read = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((icmp_ln61_fu_71_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        ap_condition_exit_pp0_iter1_stage0 = 1'b1;
+    end else begin
+        ap_condition_exit_pp0_iter1_stage0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_loop_exit_ready == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        ap_done_int = 1'b1;
+    end else begin
+        ap_done_int = ap_done_reg;
+    end
+end
+
+always @ (*) begin
+    if (((ap_idle_pp0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_start_int == 1'b0))) begin
+        ap_idle = 1'b1;
+    end else begin
+        ap_idle = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin
+        ap_idle_pp0 = 1'b1;
+    end else begin
+        ap_idle_pp0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        ap_ready_int = 1'b1;
+    end else begin
+        ap_ready_int = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        b_blk_n = b_full_n;
+    end else begin
+        b_blk_n = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        b_write = 1'b1;
+    end else begin
+        b_write = 1'b0;
+    end
+end
+
+always @ (*) begin
+    case (ap_CS_fsm)
+        ap_ST_fsm_pp0_stage0 : begin
+            ap_NS_fsm = ap_ST_fsm_pp0_stage0;
+        end
+        default : begin
+            ap_NS_fsm = 'bx;
+        end
+    endcase
+end
+
+assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd0];
+
+assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_block_pp0_stage0_01001 = ((ap_enable_reg_pp0_iter2 == 1'b1) & ((b_full_n == 1'b0) | (1'b0 == a_s_empty_n)));
+end
+
+always @ (*) begin
+    ap_block_pp0_stage0_11001 = ((ap_enable_reg_pp0_iter2 == 1'b1) & ((b_full_n == 1'b0) | (1'b0 == a_s_empty_n)));
+end
+
+always @ (*) begin
+    ap_block_pp0_stage0_subdone = ((ap_enable_reg_pp0_iter2 == 1'b1) & ((b_full_n == 1'b0) | (1'b0 == a_s_empty_n)));
+end
+
+assign ap_block_state1_pp0_stage0_iter0 = ~(1'b1 == 1'b1);
+
+assign ap_block_state2_pp0_stage0_iter1 = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_block_state3_pp0_stage0_iter2 = ((b_full_n == 1'b0) | (1'b0 == a_s_empty_n));
+end
+
+assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1);
+
+assign ap_enable_reg_pp0_iter0 = ap_start_int;
+
+assign ap_loop_exit_ready = ap_condition_exit_pp0_iter1_stage0;
+
+assign b_din = {{{{1'd0}, {trunc_ln1669_fu_87_p1}}}, {1'd0}};
+
+assign i_2_fu_76_p2 = (i_fu_40 + 64'd1);
+
+assign icmp_ln61_fu_71_p2 = ((i_fu_40 == n) ? 1'b1 : 1'b0);
+
+assign trunc_ln1669_fu_87_p1 = a_s_dout[510:0];
+
+endmodule //yshift_yshift_Pipeline_VITIS_LOOP_61_1
diff --git a/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w_placeholder/vadd_bw.v b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w_placeholder/vadd_bw.v
new file mode 100644
index 00000000..dfd6368f
--- /dev/null
+++ b/benchmarks/vivado_flow/vck5000_dfx/v/vadd_bandwidth28r28w_placeholder/vadd_bw.v
@@ -0,0 +1,2128 @@
+`timescale 1 ns / 1 ps
+
+(* CORE_GENERATION_INFO = "vadd_bw_vadd_bw,hls_ip_2022_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xcu50-fsvh2104-2-e,HLS_INPUT_CLOCK=3.330000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=1.000000,HLS_SYN_LAT=0,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=2066,HLS_SYN_LUT=3752,HLS_VERSION=2022_2}" *)
+
+
+module vadd_bw
+(
+  s_axi_control_AWVALID,
+  s_axi_control_AWREADY,
+  s_axi_control_AWADDR,
+  s_axi_control_WVALID,
+  s_axi_control_WREADY,
+  s_axi_control_WDATA,
+  s_axi_control_WSTRB,
+  s_axi_control_ARVALID,
+  s_axi_control_ARREADY,
+  s_axi_control_ARADDR,
+  s_axi_control_RVALID,
+  s_axi_control_RREADY,
+  s_axi_control_RDATA,
+  s_axi_control_RRESP,
+  s_axi_control_BVALID,
+  s_axi_control_BREADY,
+  s_axi_control_BRESP,
+  ap_clk,
+  ap_rst_n,
+  interrupt,
+  m_axi_rmem0_ARADDR,
+  m_axi_rmem0_ARBURST,
+  m_axi_rmem0_ARCACHE,
+  m_axi_rmem0_ARID,
+  m_axi_rmem0_ARLEN,
+  m_axi_rmem0_ARLOCK,
+  m_axi_rmem0_ARPROT,
+  m_axi_rmem0_ARQOS,
+  m_axi_rmem0_ARREADY,
+  m_axi_rmem0_ARSIZE,
+  m_axi_rmem0_ARVALID,
+  m_axi_rmem0_AWADDR,
+  m_axi_rmem0_AWBURST,
+  m_axi_rmem0_AWCACHE,
+  m_axi_rmem0_AWID,
+  m_axi_rmem0_AWLEN,
+  m_axi_rmem0_AWLOCK,
+  m_axi_rmem0_AWPROT,
+  m_axi_rmem0_AWQOS,
+  m_axi_rmem0_AWREADY,
+  m_axi_rmem0_AWSIZE,
+  m_axi_rmem0_AWVALID,
+  m_axi_rmem0_BID,
+  m_axi_rmem0_BREADY,
+  m_axi_rmem0_BRESP,
+  m_axi_rmem0_BVALID,
+  m_axi_rmem0_RDATA,
+  m_axi_rmem0_RID,
+  m_axi_rmem0_RLAST,
+  m_axi_rmem0_RREADY,
+  m_axi_rmem0_RRESP,
+  m_axi_rmem0_RVALID,
+  m_axi_rmem0_WDATA,
+  m_axi_rmem0_WLAST,
+  m_axi_rmem0_WREADY,
+  m_axi_rmem0_WSTRB,
+  m_axi_rmem0_WVALID,
+  m_axi_rmem1_ARADDR,
+  m_axi_rmem1_ARBURST,
+  m_axi_rmem1_ARCACHE,
+  m_axi_rmem1_ARID,
+  m_axi_rmem1_ARLEN,
+  m_axi_rmem1_ARLOCK,
+  m_axi_rmem1_ARPROT,
+  m_axi_rmem1_ARQOS,
+  m_axi_rmem1_ARREADY,
+  m_axi_rmem1_ARSIZE,
+  m_axi_rmem1_ARVALID,
+  m_axi_rmem1_AWADDR,
+  m_axi_rmem1_AWBURST,
+  m_axi_rmem1_AWCACHE,
+  m_axi_rmem1_AWID,
+  m_axi_rmem1_AWLEN,
+  m_axi_rmem1_AWLOCK,
+  m_axi_rmem1_AWPROT,
+  m_axi_rmem1_AWQOS,
+  m_axi_rmem1_AWREADY,
+  m_axi_rmem1_AWSIZE,
+  m_axi_rmem1_AWVALID,
+  m_axi_rmem1_BID,
+  m_axi_rmem1_BREADY,
+  m_axi_rmem1_BRESP,
+  m_axi_rmem1_BVALID,
+  m_axi_rmem1_RDATA,
+  m_axi_rmem1_RID,
+  m_axi_rmem1_RLAST,
+  m_axi_rmem1_RREADY,
+  m_axi_rmem1_RRESP,
+  m_axi_rmem1_RVALID,
+  m_axi_rmem1_WDATA,
+  m_axi_rmem1_WLAST,
+  m_axi_rmem1_WREADY,
+  m_axi_rmem1_WSTRB,
+  m_axi_rmem1_WVALID,
+  m_axi_rmem2_ARADDR,
+  m_axi_rmem2_ARBURST,
+  m_axi_rmem2_ARCACHE,
+  m_axi_rmem2_ARID,
+  m_axi_rmem2_ARLEN,
+  m_axi_rmem2_ARLOCK,
+  m_axi_rmem2_ARPROT,
+  m_axi_rmem2_ARQOS,
+  m_axi_rmem2_ARREADY,
+  m_axi_rmem2_ARSIZE,
+  m_axi_rmem2_ARVALID,
+  m_axi_rmem2_AWADDR,
+  m_axi_rmem2_AWBURST,
+  m_axi_rmem2_AWCACHE,
+  m_axi_rmem2_AWID,
+  m_axi_rmem2_AWLEN,
+  m_axi_rmem2_AWLOCK,
+  m_axi_rmem2_AWPROT,
+  m_axi_rmem2_AWQOS,
+  m_axi_rmem2_AWREADY,
+  m_axi_rmem2_AWSIZE,
+  m_axi_rmem2_AWVALID,
+  m_axi_rmem2_BID,
+  m_axi_rmem2_BREADY,
+  m_axi_rmem2_BRESP,
+  m_axi_rmem2_BVALID,
+  m_axi_rmem2_RDATA,
+  m_axi_rmem2_RID,
+  m_axi_rmem2_RLAST,
+  m_axi_rmem2_RREADY,
+  m_axi_rmem2_RRESP,
+  m_axi_rmem2_RVALID,
+  m_axi_rmem2_WDATA,
+  m_axi_rmem2_WLAST,
+  m_axi_rmem2_WREADY,
+  m_axi_rmem2_WSTRB,
+  m_axi_rmem2_WVALID,
+  m_axi_rmem3_ARADDR,
+  m_axi_rmem3_ARBURST,
+  m_axi_rmem3_ARCACHE,
+  m_axi_rmem3_ARID,
+  m_axi_rmem3_ARLEN,
+  m_axi_rmem3_ARLOCK,
+  m_axi_rmem3_ARPROT,
+  m_axi_rmem3_ARQOS,
+  m_axi_rmem3_ARREADY,
+  m_axi_rmem3_ARSIZE,
+  m_axi_rmem3_ARVALID,
+  m_axi_rmem3_AWADDR,
+  m_axi_rmem3_AWBURST,
+  m_axi_rmem3_AWCACHE,
+  m_axi_rmem3_AWID,
+  m_axi_rmem3_AWLEN,
+  m_axi_rmem3_AWLOCK,
+  m_axi_rmem3_AWPROT,
+  m_axi_rmem3_AWQOS,
+  m_axi_rmem3_AWREADY,
+  m_axi_rmem3_AWSIZE,
+  m_axi_rmem3_AWVALID,
+  m_axi_rmem3_BID,
+  m_axi_rmem3_BREADY,
+  m_axi_rmem3_BRESP,
+  m_axi_rmem3_BVALID,
+  m_axi_rmem3_RDATA,
+  m_axi_rmem3_RID,
+  m_axi_rmem3_RLAST,
+  m_axi_rmem3_RREADY,
+  m_axi_rmem3_RRESP,
+  m_axi_rmem3_RVALID,
+  m_axi_rmem3_WDATA,
+  m_axi_rmem3_WLAST,
+  m_axi_rmem3_WREADY,
+  m_axi_rmem3_WSTRB,
+  m_axi_rmem3_WVALID,
+  m_axi_rmem4_ARADDR,
+  m_axi_rmem4_ARBURST,
+  m_axi_rmem4_ARCACHE,
+  m_axi_rmem4_ARID,
+  m_axi_rmem4_ARLEN,
+  m_axi_rmem4_ARLOCK,
+  m_axi_rmem4_ARPROT,
+  m_axi_rmem4_ARQOS,
+  m_axi_rmem4_ARREADY,
+  m_axi_rmem4_ARSIZE,
+  m_axi_rmem4_ARVALID,
+  m_axi_rmem4_AWADDR,
+  m_axi_rmem4_AWBURST,
+  m_axi_rmem4_AWCACHE,
+  m_axi_rmem4_AWID,
+  m_axi_rmem4_AWLEN,
+  m_axi_rmem4_AWLOCK,
+  m_axi_rmem4_AWPROT,
+  m_axi_rmem4_AWQOS,
+  m_axi_rmem4_AWREADY,
+  m_axi_rmem4_AWSIZE,
+  m_axi_rmem4_AWVALID,
+  m_axi_rmem4_BID,
+  m_axi_rmem4_BREADY,
+  m_axi_rmem4_BRESP,
+  m_axi_rmem4_BVALID,
+  m_axi_rmem4_RDATA,
+  m_axi_rmem4_RID,
+  m_axi_rmem4_RLAST,
+  m_axi_rmem4_RREADY,
+  m_axi_rmem4_RRESP,
+  m_axi_rmem4_RVALID,
+  m_axi_rmem4_WDATA,
+  m_axi_rmem4_WLAST,
+  m_axi_rmem4_WREADY,
+  m_axi_rmem4_WSTRB,
+  m_axi_rmem4_WVALID,
+  m_axi_rmem5_ARADDR,
+  m_axi_rmem5_ARBURST,
+  m_axi_rmem5_ARCACHE,
+  m_axi_rmem5_ARID,
+  m_axi_rmem5_ARLEN,
+  m_axi_rmem5_ARLOCK,
+  m_axi_rmem5_ARPROT,
+  m_axi_rmem5_ARQOS,
+  m_axi_rmem5_ARREADY,
+  m_axi_rmem5_ARSIZE,
+  m_axi_rmem5_ARVALID,
+  m_axi_rmem5_AWADDR,
+  m_axi_rmem5_AWBURST,
+  m_axi_rmem5_AWCACHE,
+  m_axi_rmem5_AWID,
+  m_axi_rmem5_AWLEN,
+  m_axi_rmem5_AWLOCK,
+  m_axi_rmem5_AWPROT,
+  m_axi_rmem5_AWQOS,
+  m_axi_rmem5_AWREADY,
+  m_axi_rmem5_AWSIZE,
+  m_axi_rmem5_AWVALID,
+  m_axi_rmem5_BID,
+  m_axi_rmem5_BREADY,
+  m_axi_rmem5_BRESP,
+  m_axi_rmem5_BVALID,
+  m_axi_rmem5_RDATA,
+  m_axi_rmem5_RID,
+  m_axi_rmem5_RLAST,
+  m_axi_rmem5_RREADY,
+  m_axi_rmem5_RRESP,
+  m_axi_rmem5_RVALID,
+  m_axi_rmem5_WDATA,
+  m_axi_rmem5_WLAST,
+  m_axi_rmem5_WREADY,
+  m_axi_rmem5_WSTRB,
+  m_axi_rmem5_WVALID,
+  m_axi_rmem6_ARADDR,
+  m_axi_rmem6_ARBURST,
+  m_axi_rmem6_ARCACHE,
+  m_axi_rmem6_ARID,
+  m_axi_rmem6_ARLEN,
+  m_axi_rmem6_ARLOCK,
+  m_axi_rmem6_ARPROT,
+  m_axi_rmem6_ARQOS,
+  m_axi_rmem6_ARREADY,
+  m_axi_rmem6_ARSIZE,
+  m_axi_rmem6_ARVALID,
+  m_axi_rmem6_AWADDR,
+  m_axi_rmem6_AWBURST,
+  m_axi_rmem6_AWCACHE,
+  m_axi_rmem6_AWID,
+  m_axi_rmem6_AWLEN,
+  m_axi_rmem6_AWLOCK,
+  m_axi_rmem6_AWPROT,
+  m_axi_rmem6_AWQOS,
+  m_axi_rmem6_AWREADY,
+  m_axi_rmem6_AWSIZE,
+  m_axi_rmem6_AWVALID,
+  m_axi_rmem6_BID,
+  m_axi_rmem6_BREADY,
+  m_axi_rmem6_BRESP,
+  m_axi_rmem6_BVALID,
+  m_axi_rmem6_RDATA,
+  m_axi_rmem6_RID,
+  m_axi_rmem6_RLAST,
+  m_axi_rmem6_RREADY,
+  m_axi_rmem6_RRESP,
+  m_axi_rmem6_RVALID,
+  m_axi_rmem6_WDATA,
+  m_axi_rmem6_WLAST,
+  m_axi_rmem6_WREADY,
+  m_axi_rmem6_WSTRB,
+  m_axi_rmem6_WVALID,
+  m_axi_rmem7_ARADDR,
+  m_axi_rmem7_ARBURST,
+  m_axi_rmem7_ARCACHE,
+  m_axi_rmem7_ARID,
+  m_axi_rmem7_ARLEN,
+  m_axi_rmem7_ARLOCK,
+  m_axi_rmem7_ARPROT,
+  m_axi_rmem7_ARQOS,
+  m_axi_rmem7_ARREADY,
+  m_axi_rmem7_ARSIZE,
+  m_axi_rmem7_ARVALID,
+  m_axi_rmem7_AWADDR,
+  m_axi_rmem7_AWBURST,
+  m_axi_rmem7_AWCACHE,
+  m_axi_rmem7_AWID,
+  m_axi_rmem7_AWLEN,
+  m_axi_rmem7_AWLOCK,
+  m_axi_rmem7_AWPROT,
+  m_axi_rmem7_AWQOS,
+  m_axi_rmem7_AWREADY,
+  m_axi_rmem7_AWSIZE,
+  m_axi_rmem7_AWVALID,
+  m_axi_rmem7_BID,
+  m_axi_rmem7_BREADY,
+  m_axi_rmem7_BRESP,
+  m_axi_rmem7_BVALID,
+  m_axi_rmem7_RDATA,
+  m_axi_rmem7_RID,
+  m_axi_rmem7_RLAST,
+  m_axi_rmem7_RREADY,
+  m_axi_rmem7_RRESP,
+  m_axi_rmem7_RVALID,
+  m_axi_rmem7_WDATA,
+  m_axi_rmem7_WLAST,
+  m_axi_rmem7_WREADY,
+  m_axi_rmem7_WSTRB,
+  m_axi_rmem7_WVALID,
+  m_axi_rmem8_ARADDR,
+  m_axi_rmem8_ARBURST,
+  m_axi_rmem8_ARCACHE,
+  m_axi_rmem8_ARID,
+  m_axi_rmem8_ARLEN,
+  m_axi_rmem8_ARLOCK,
+  m_axi_rmem8_ARPROT,
+  m_axi_rmem8_ARQOS,
+  m_axi_rmem8_ARREADY,
+  m_axi_rmem8_ARSIZE,
+  m_axi_rmem8_ARVALID,
+  m_axi_rmem8_AWADDR,
+  m_axi_rmem8_AWBURST,
+  m_axi_rmem8_AWCACHE,
+  m_axi_rmem8_AWID,
+  m_axi_rmem8_AWLEN,
+  m_axi_rmem8_AWLOCK,
+  m_axi_rmem8_AWPROT,
+  m_axi_rmem8_AWQOS,
+  m_axi_rmem8_AWREADY,
+  m_axi_rmem8_AWSIZE,
+  m_axi_rmem8_AWVALID,
+  m_axi_rmem8_BID,
+  m_axi_rmem8_BREADY,
+  m_axi_rmem8_BRESP,
+  m_axi_rmem8_BVALID,
+  m_axi_rmem8_RDATA,
+  m_axi_rmem8_RID,
+  m_axi_rmem8_RLAST,
+  m_axi_rmem8_RREADY,
+  m_axi_rmem8_RRESP,
+  m_axi_rmem8_RVALID,
+  m_axi_rmem8_WDATA,
+  m_axi_rmem8_WLAST,
+  m_axi_rmem8_WREADY,
+  m_axi_rmem8_WSTRB,
+  m_axi_rmem8_WVALID,
+  m_axi_rmem9_ARADDR,
+  m_axi_rmem9_ARBURST,
+  m_axi_rmem9_ARCACHE,
+  m_axi_rmem9_ARID,
+  m_axi_rmem9_ARLEN,
+  m_axi_rmem9_ARLOCK,
+  m_axi_rmem9_ARPROT,
+  m_axi_rmem9_ARQOS,
+  m_axi_rmem9_ARREADY,
+  m_axi_rmem9_ARSIZE,
+  m_axi_rmem9_ARVALID,
+  m_axi_rmem9_AWADDR,
+  m_axi_rmem9_AWBURST,
+  m_axi_rmem9_AWCACHE,
+  m_axi_rmem9_AWID,
+  m_axi_rmem9_AWLEN,
+  m_axi_rmem9_AWLOCK,
+  m_axi_rmem9_AWPROT,
+  m_axi_rmem9_AWQOS,
+  m_axi_rmem9_AWREADY,
+  m_axi_rmem9_AWSIZE,
+  m_axi_rmem9_AWVALID,
+  m_axi_rmem9_BID,
+  m_axi_rmem9_BREADY,
+  m_axi_rmem9_BRESP,
+  m_axi_rmem9_BVALID,
+  m_axi_rmem9_RDATA,
+  m_axi_rmem9_RID,
+  m_axi_rmem9_RLAST,
+  m_axi_rmem9_RREADY,
+  m_axi_rmem9_RRESP,
+  m_axi_rmem9_RVALID,
+  m_axi_rmem9_WDATA,
+  m_axi_rmem9_WLAST,
+  m_axi_rmem9_WREADY,
+  m_axi_rmem9_WSTRB,
+  m_axi_rmem9_WVALID,
+  m_axi_rmem10_ARADDR,
+  m_axi_rmem10_ARBURST,
+  m_axi_rmem10_ARCACHE,
+  m_axi_rmem10_ARID,
+  m_axi_rmem10_ARLEN,
+  m_axi_rmem10_ARLOCK,
+  m_axi_rmem10_ARPROT,
+  m_axi_rmem10_ARQOS,
+  m_axi_rmem10_ARREADY,
+  m_axi_rmem10_ARSIZE,
+  m_axi_rmem10_ARVALID,
+  m_axi_rmem10_AWADDR,
+  m_axi_rmem10_AWBURST,
+  m_axi_rmem10_AWCACHE,
+  m_axi_rmem10_AWID,
+  m_axi_rmem10_AWLEN,
+  m_axi_rmem10_AWLOCK,
+  m_axi_rmem10_AWPROT,
+  m_axi_rmem10_AWQOS,
+  m_axi_rmem10_AWREADY,
+  m_axi_rmem10_AWSIZE,
+  m_axi_rmem10_AWVALID,
+  m_axi_rmem10_BID,
+  m_axi_rmem10_BREADY,
+  m_axi_rmem10_BRESP,
+  m_axi_rmem10_BVALID,
+  m_axi_rmem10_RDATA,
+  m_axi_rmem10_RID,
+  m_axi_rmem10_RLAST,
+  m_axi_rmem10_RREADY,
+  m_axi_rmem10_RRESP,
+  m_axi_rmem10_RVALID,
+  m_axi_rmem10_WDATA,
+  m_axi_rmem10_WLAST,
+  m_axi_rmem10_WREADY,
+  m_axi_rmem10_WSTRB,
+  m_axi_rmem10_WVALID,
+  m_axi_rmem11_ARADDR,
+  m_axi_rmem11_ARBURST,
+  m_axi_rmem11_ARCACHE,
+  m_axi_rmem11_ARID,
+  m_axi_rmem11_ARLEN,
+  m_axi_rmem11_ARLOCK,
+  m_axi_rmem11_ARPROT,
+  m_axi_rmem11_ARQOS,
+  m_axi_rmem11_ARREADY,
+  m_axi_rmem11_ARSIZE,
+  m_axi_rmem11_ARVALID,
+  m_axi_rmem11_AWADDR,
+  m_axi_rmem11_AWBURST,
+  m_axi_rmem11_AWCACHE,
+  m_axi_rmem11_AWID,
+  m_axi_rmem11_AWLEN,
+  m_axi_rmem11_AWLOCK,
+  m_axi_rmem11_AWPROT,
+  m_axi_rmem11_AWQOS,
+  m_axi_rmem11_AWREADY,
+  m_axi_rmem11_AWSIZE,
+  m_axi_rmem11_AWVALID,
+  m_axi_rmem11_BID,
+  m_axi_rmem11_BREADY,
+  m_axi_rmem11_BRESP,
+  m_axi_rmem11_BVALID,
+  m_axi_rmem11_RDATA,
+  m_axi_rmem11_RID,
+  m_axi_rmem11_RLAST,
+  m_axi_rmem11_RREADY,
+  m_axi_rmem11_RRESP,
+  m_axi_rmem11_RVALID,
+  m_axi_rmem11_WDATA,
+  m_axi_rmem11_WLAST,
+  m_axi_rmem11_WREADY,
+  m_axi_rmem11_WSTRB,
+  m_axi_rmem11_WVALID,
+  m_axi_rmem12_ARADDR,
+  m_axi_rmem12_ARBURST,
+  m_axi_rmem12_ARCACHE,
+  m_axi_rmem12_ARID,
+  m_axi_rmem12_ARLEN,
+  m_axi_rmem12_ARLOCK,
+  m_axi_rmem12_ARPROT,
+  m_axi_rmem12_ARQOS,
+  m_axi_rmem12_ARREADY,
+  m_axi_rmem12_ARSIZE,
+  m_axi_rmem12_ARVALID,
+  m_axi_rmem12_AWADDR,
+  m_axi_rmem12_AWBURST,
+  m_axi_rmem12_AWCACHE,
+  m_axi_rmem12_AWID,
+  m_axi_rmem12_AWLEN,
+  m_axi_rmem12_AWLOCK,
+  m_axi_rmem12_AWPROT,
+  m_axi_rmem12_AWQOS,
+  m_axi_rmem12_AWREADY,
+  m_axi_rmem12_AWSIZE,
+  m_axi_rmem12_AWVALID,
+  m_axi_rmem12_BID,
+  m_axi_rmem12_BREADY,
+  m_axi_rmem12_BRESP,
+  m_axi_rmem12_BVALID,
+  m_axi_rmem12_RDATA,
+  m_axi_rmem12_RID,
+  m_axi_rmem12_RLAST,
+  m_axi_rmem12_RREADY,
+  m_axi_rmem12_RRESP,
+  m_axi_rmem12_RVALID,
+  m_axi_rmem12_WDATA,
+  m_axi_rmem12_WLAST,
+  m_axi_rmem12_WREADY,
+  m_axi_rmem12_WSTRB,
+  m_axi_rmem12_WVALID,
+  m_axi_rmem13_ARADDR,
+  m_axi_rmem13_ARBURST,
+  m_axi_rmem13_ARCACHE,
+  m_axi_rmem13_ARID,
+  m_axi_rmem13_ARLEN,
+  m_axi_rmem13_ARLOCK,
+  m_axi_rmem13_ARPROT,
+  m_axi_rmem13_ARQOS,
+  m_axi_rmem13_ARREADY,
+  m_axi_rmem13_ARSIZE,
+  m_axi_rmem13_ARVALID,
+  m_axi_rmem13_AWADDR,
+  m_axi_rmem13_AWBURST,
+  m_axi_rmem13_AWCACHE,
+  m_axi_rmem13_AWID,
+  m_axi_rmem13_AWLEN,
+  m_axi_rmem13_AWLOCK,
+  m_axi_rmem13_AWPROT,
+  m_axi_rmem13_AWQOS,
+  m_axi_rmem13_AWREADY,
+  m_axi_rmem13_AWSIZE,
+  m_axi_rmem13_AWVALID,
+  m_axi_rmem13_BID,
+  m_axi_rmem13_BREADY,
+  m_axi_rmem13_BRESP,
+  m_axi_rmem13_BVALID,
+  m_axi_rmem13_RDATA,
+  m_axi_rmem13_RID,
+  m_axi_rmem13_RLAST,
+  m_axi_rmem13_RREADY,
+  m_axi_rmem13_RRESP,
+  m_axi_rmem13_RVALID,
+  m_axi_rmem13_WDATA,
+  m_axi_rmem13_WLAST,
+  m_axi_rmem13_WREADY,
+  m_axi_rmem13_WSTRB,
+  m_axi_rmem13_WVALID,
+  m_axi_rmem14_ARADDR,
+  m_axi_rmem14_ARBURST,
+  m_axi_rmem14_ARCACHE,
+  m_axi_rmem14_ARID,
+  m_axi_rmem14_ARLEN,
+  m_axi_rmem14_ARLOCK,
+  m_axi_rmem14_ARPROT,
+  m_axi_rmem14_ARQOS,
+  m_axi_rmem14_ARREADY,
+  m_axi_rmem14_ARSIZE,
+  m_axi_rmem14_ARVALID,
+  m_axi_rmem14_AWADDR,
+  m_axi_rmem14_AWBURST,
+  m_axi_rmem14_AWCACHE,
+  m_axi_rmem14_AWID,
+  m_axi_rmem14_AWLEN,
+  m_axi_rmem14_AWLOCK,
+  m_axi_rmem14_AWPROT,
+  m_axi_rmem14_AWQOS,
+  m_axi_rmem14_AWREADY,
+  m_axi_rmem14_AWSIZE,
+  m_axi_rmem14_AWVALID,
+  m_axi_rmem14_BID,
+  m_axi_rmem14_BREADY,
+  m_axi_rmem14_BRESP,
+  m_axi_rmem14_BVALID,
+  m_axi_rmem14_RDATA,
+  m_axi_rmem14_RID,
+  m_axi_rmem14_RLAST,
+  m_axi_rmem14_RREADY,
+  m_axi_rmem14_RRESP,
+  m_axi_rmem14_RVALID,
+  m_axi_rmem14_WDATA,
+  m_axi_rmem14_WLAST,
+  m_axi_rmem14_WREADY,
+  m_axi_rmem14_WSTRB,
+  m_axi_rmem14_WVALID,
+  m_axi_rmem15_ARADDR,
+  m_axi_rmem15_ARBURST,
+  m_axi_rmem15_ARCACHE,
+  m_axi_rmem15_ARID,
+  m_axi_rmem15_ARLEN,
+  m_axi_rmem15_ARLOCK,
+  m_axi_rmem15_ARPROT,
+  m_axi_rmem15_ARQOS,
+  m_axi_rmem15_ARREADY,
+  m_axi_rmem15_ARSIZE,
+  m_axi_rmem15_ARVALID,
+  m_axi_rmem15_AWADDR,
+  m_axi_rmem15_AWBURST,
+  m_axi_rmem15_AWCACHE,
+  m_axi_rmem15_AWID,
+  m_axi_rmem15_AWLEN,
+  m_axi_rmem15_AWLOCK,
+  m_axi_rmem15_AWPROT,
+  m_axi_rmem15_AWQOS,
+  m_axi_rmem15_AWREADY,
+  m_axi_rmem15_AWSIZE,
+  m_axi_rmem15_AWVALID,
+  m_axi_rmem15_BID,
+  m_axi_rmem15_BREADY,
+  m_axi_rmem15_BRESP,
+  m_axi_rmem15_BVALID,
+  m_axi_rmem15_RDATA,
+  m_axi_rmem15_RID,
+  m_axi_rmem15_RLAST,
+  m_axi_rmem15_RREADY,
+  m_axi_rmem15_RRESP,
+  m_axi_rmem15_RVALID,
+  m_axi_rmem15_WDATA,
+  m_axi_rmem15_WLAST,
+  m_axi_rmem15_WREADY,
+  m_axi_rmem15_WSTRB,
+  m_axi_rmem15_WVALID,
+  m_axi_rmem16_ARADDR,
+  m_axi_rmem16_ARBURST,
+  m_axi_rmem16_ARCACHE,
+  m_axi_rmem16_ARID,
+  m_axi_rmem16_ARLEN,
+  m_axi_rmem16_ARLOCK,
+  m_axi_rmem16_ARPROT,
+  m_axi_rmem16_ARQOS,
+  m_axi_rmem16_ARREADY,
+  m_axi_rmem16_ARSIZE,
+  m_axi_rmem16_ARVALID,
+  m_axi_rmem16_AWADDR,
+  m_axi_rmem16_AWBURST,
+  m_axi_rmem16_AWCACHE,
+  m_axi_rmem16_AWID,
+  m_axi_rmem16_AWLEN,
+  m_axi_rmem16_AWLOCK,
+  m_axi_rmem16_AWPROT,
+  m_axi_rmem16_AWQOS,
+  m_axi_rmem16_AWREADY,
+  m_axi_rmem16_AWSIZE,
+  m_axi_rmem16_AWVALID,
+  m_axi_rmem16_BID,
+  m_axi_rmem16_BREADY,
+  m_axi_rmem16_BRESP,
+  m_axi_rmem16_BVALID,
+  m_axi_rmem16_RDATA,
+  m_axi_rmem16_RID,
+  m_axi_rmem16_RLAST,
+  m_axi_rmem16_RREADY,
+  m_axi_rmem16_RRESP,
+  m_axi_rmem16_RVALID,
+  m_axi_rmem16_WDATA,
+  m_axi_rmem16_WLAST,
+  m_axi_rmem16_WREADY,
+  m_axi_rmem16_WSTRB,
+  m_axi_rmem16_WVALID,
+  m_axi_rmem17_ARADDR,
+  m_axi_rmem17_ARBURST,
+  m_axi_rmem17_ARCACHE,
+  m_axi_rmem17_ARID,
+  m_axi_rmem17_ARLEN,
+  m_axi_rmem17_ARLOCK,
+  m_axi_rmem17_ARPROT,
+  m_axi_rmem17_ARQOS,
+  m_axi_rmem17_ARREADY,
+  m_axi_rmem17_ARSIZE,
+  m_axi_rmem17_ARVALID,
+  m_axi_rmem17_AWADDR,
+  m_axi_rmem17_AWBURST,
+  m_axi_rmem17_AWCACHE,
+  m_axi_rmem17_AWID,
+  m_axi_rmem17_AWLEN,
+  m_axi_rmem17_AWLOCK,
+  m_axi_rmem17_AWPROT,
+  m_axi_rmem17_AWQOS,
+  m_axi_rmem17_AWREADY,
+  m_axi_rmem17_AWSIZE,
+  m_axi_rmem17_AWVALID,
+  m_axi_rmem17_BID,
+  m_axi_rmem17_BREADY,
+  m_axi_rmem17_BRESP,
+  m_axi_rmem17_BVALID,
+  m_axi_rmem17_RDATA,
+  m_axi_rmem17_RID,
+  m_axi_rmem17_RLAST,
+  m_axi_rmem17_RREADY,
+  m_axi_rmem17_RRESP,
+  m_axi_rmem17_RVALID,
+  m_axi_rmem17_WDATA,
+  m_axi_rmem17_WLAST,
+  m_axi_rmem17_WREADY,
+  m_axi_rmem17_WSTRB,
+  m_axi_rmem17_WVALID,
+  m_axi_rmem18_ARADDR,
+  m_axi_rmem18_ARBURST,
+  m_axi_rmem18_ARCACHE,
+  m_axi_rmem18_ARID,
+  m_axi_rmem18_ARLEN,
+  m_axi_rmem18_ARLOCK,
+  m_axi_rmem18_ARPROT,
+  m_axi_rmem18_ARQOS,
+  m_axi_rmem18_ARREADY,
+  m_axi_rmem18_ARSIZE,
+  m_axi_rmem18_ARVALID,
+  m_axi_rmem18_AWADDR,
+  m_axi_rmem18_AWBURST,
+  m_axi_rmem18_AWCACHE,
+  m_axi_rmem18_AWID,
+  m_axi_rmem18_AWLEN,
+  m_axi_rmem18_AWLOCK,
+  m_axi_rmem18_AWPROT,
+  m_axi_rmem18_AWQOS,
+  m_axi_rmem18_AWREADY,
+  m_axi_rmem18_AWSIZE,
+  m_axi_rmem18_AWVALID,
+  m_axi_rmem18_BID,
+  m_axi_rmem18_BREADY,
+  m_axi_rmem18_BRESP,
+  m_axi_rmem18_BVALID,
+  m_axi_rmem18_RDATA,
+  m_axi_rmem18_RID,
+  m_axi_rmem18_RLAST,
+  m_axi_rmem18_RREADY,
+  m_axi_rmem18_RRESP,
+  m_axi_rmem18_RVALID,
+  m_axi_rmem18_WDATA,
+  m_axi_rmem18_WLAST,
+  m_axi_rmem18_WREADY,
+  m_axi_rmem18_WSTRB,
+  m_axi_rmem18_WVALID,
+  m_axi_rmem19_ARADDR,
+  m_axi_rmem19_ARBURST,
+  m_axi_rmem19_ARCACHE,
+  m_axi_rmem19_ARID,
+  m_axi_rmem19_ARLEN,
+  m_axi_rmem19_ARLOCK,
+  m_axi_rmem19_ARPROT,
+  m_axi_rmem19_ARQOS,
+  m_axi_rmem19_ARREADY,
+  m_axi_rmem19_ARSIZE,
+  m_axi_rmem19_ARVALID,
+  m_axi_rmem19_AWADDR,
+  m_axi_rmem19_AWBURST,
+  m_axi_rmem19_AWCACHE,
+  m_axi_rmem19_AWID,
+  m_axi_rmem19_AWLEN,
+  m_axi_rmem19_AWLOCK,
+  m_axi_rmem19_AWPROT,
+  m_axi_rmem19_AWQOS,
+  m_axi_rmem19_AWREADY,
+  m_axi_rmem19_AWSIZE,
+  m_axi_rmem19_AWVALID,
+  m_axi_rmem19_BID,
+  m_axi_rmem19_BREADY,
+  m_axi_rmem19_BRESP,
+  m_axi_rmem19_BVALID,
+  m_axi_rmem19_RDATA,
+  m_axi_rmem19_RID,
+  m_axi_rmem19_RLAST,
+  m_axi_rmem19_RREADY,
+  m_axi_rmem19_RRESP,
+  m_axi_rmem19_RVALID,
+  m_axi_rmem19_WDATA,
+  m_axi_rmem19_WLAST,
+  m_axi_rmem19_WREADY,
+  m_axi_rmem19_WSTRB,
+  m_axi_rmem19_WVALID,
+  m_axi_rmem20_ARADDR,
+  m_axi_rmem20_ARBURST,
+  m_axi_rmem20_ARCACHE,
+  m_axi_rmem20_ARID,
+  m_axi_rmem20_ARLEN,
+  m_axi_rmem20_ARLOCK,
+  m_axi_rmem20_ARPROT,
+  m_axi_rmem20_ARQOS,
+  m_axi_rmem20_ARREADY,
+  m_axi_rmem20_ARSIZE,
+  m_axi_rmem20_ARVALID,
+  m_axi_rmem20_AWADDR,
+  m_axi_rmem20_AWBURST,
+  m_axi_rmem20_AWCACHE,
+  m_axi_rmem20_AWID,
+  m_axi_rmem20_AWLEN,
+  m_axi_rmem20_AWLOCK,
+  m_axi_rmem20_AWPROT,
+  m_axi_rmem20_AWQOS,
+  m_axi_rmem20_AWREADY,
+  m_axi_rmem20_AWSIZE,
+  m_axi_rmem20_AWVALID,
+  m_axi_rmem20_BID,
+  m_axi_rmem20_BREADY,
+  m_axi_rmem20_BRESP,
+  m_axi_rmem20_BVALID,
+  m_axi_rmem20_RDATA,
+  m_axi_rmem20_RID,
+  m_axi_rmem20_RLAST,
+  m_axi_rmem20_RREADY,
+  m_axi_rmem20_RRESP,
+  m_axi_rmem20_RVALID,
+  m_axi_rmem20_WDATA,
+  m_axi_rmem20_WLAST,
+  m_axi_rmem20_WREADY,
+  m_axi_rmem20_WSTRB,
+  m_axi_rmem20_WVALID,
+  m_axi_rmem21_ARADDR,
+  m_axi_rmem21_ARBURST,
+  m_axi_rmem21_ARCACHE,
+  m_axi_rmem21_ARID,
+  m_axi_rmem21_ARLEN,
+  m_axi_rmem21_ARLOCK,
+  m_axi_rmem21_ARPROT,
+  m_axi_rmem21_ARQOS,
+  m_axi_rmem21_ARREADY,
+  m_axi_rmem21_ARSIZE,
+  m_axi_rmem21_ARVALID,
+  m_axi_rmem21_AWADDR,
+  m_axi_rmem21_AWBURST,
+  m_axi_rmem21_AWCACHE,
+  m_axi_rmem21_AWID,
+  m_axi_rmem21_AWLEN,
+  m_axi_rmem21_AWLOCK,
+  m_axi_rmem21_AWPROT,
+  m_axi_rmem21_AWQOS,
+  m_axi_rmem21_AWREADY,
+  m_axi_rmem21_AWSIZE,
+  m_axi_rmem21_AWVALID,
+  m_axi_rmem21_BID,
+  m_axi_rmem21_BREADY,
+  m_axi_rmem21_BRESP,
+  m_axi_rmem21_BVALID,
+  m_axi_rmem21_RDATA,
+  m_axi_rmem21_RID,
+  m_axi_rmem21_RLAST,
+  m_axi_rmem21_RREADY,
+  m_axi_rmem21_RRESP,
+  m_axi_rmem21_RVALID,
+  m_axi_rmem21_WDATA,
+  m_axi_rmem21_WLAST,
+  m_axi_rmem21_WREADY,
+  m_axi_rmem21_WSTRB,
+  m_axi_rmem21_WVALID,
+  m_axi_rmem22_ARADDR,
+  m_axi_rmem22_ARBURST,
+  m_axi_rmem22_ARCACHE,
+  m_axi_rmem22_ARID,
+  m_axi_rmem22_ARLEN,
+  m_axi_rmem22_ARLOCK,
+  m_axi_rmem22_ARPROT,
+  m_axi_rmem22_ARQOS,
+  m_axi_rmem22_ARREADY,
+  m_axi_rmem22_ARSIZE,
+  m_axi_rmem22_ARVALID,
+  m_axi_rmem22_AWADDR,
+  m_axi_rmem22_AWBURST,
+  m_axi_rmem22_AWCACHE,
+  m_axi_rmem22_AWID,
+  m_axi_rmem22_AWLEN,
+  m_axi_rmem22_AWLOCK,
+  m_axi_rmem22_AWPROT,
+  m_axi_rmem22_AWQOS,
+  m_axi_rmem22_AWREADY,
+  m_axi_rmem22_AWSIZE,
+  m_axi_rmem22_AWVALID,
+  m_axi_rmem22_BID,
+  m_axi_rmem22_BREADY,
+  m_axi_rmem22_BRESP,
+  m_axi_rmem22_BVALID,
+  m_axi_rmem22_RDATA,
+  m_axi_rmem22_RID,
+  m_axi_rmem22_RLAST,
+  m_axi_rmem22_RREADY,
+  m_axi_rmem22_RRESP,
+  m_axi_rmem22_RVALID,
+  m_axi_rmem22_WDATA,
+  m_axi_rmem22_WLAST,
+  m_axi_rmem22_WREADY,
+  m_axi_rmem22_WSTRB,
+  m_axi_rmem22_WVALID,
+  m_axi_rmem23_ARADDR,
+  m_axi_rmem23_ARBURST,
+  m_axi_rmem23_ARCACHE,
+  m_axi_rmem23_ARID,
+  m_axi_rmem23_ARLEN,
+  m_axi_rmem23_ARLOCK,
+  m_axi_rmem23_ARPROT,
+  m_axi_rmem23_ARQOS,
+  m_axi_rmem23_ARREADY,
+  m_axi_rmem23_ARSIZE,
+  m_axi_rmem23_ARVALID,
+  m_axi_rmem23_AWADDR,
+  m_axi_rmem23_AWBURST,
+  m_axi_rmem23_AWCACHE,
+  m_axi_rmem23_AWID,
+  m_axi_rmem23_AWLEN,
+  m_axi_rmem23_AWLOCK,
+  m_axi_rmem23_AWPROT,
+  m_axi_rmem23_AWQOS,
+  m_axi_rmem23_AWREADY,
+  m_axi_rmem23_AWSIZE,
+  m_axi_rmem23_AWVALID,
+  m_axi_rmem23_BID,
+  m_axi_rmem23_BREADY,
+  m_axi_rmem23_BRESP,
+  m_axi_rmem23_BVALID,
+  m_axi_rmem23_RDATA,
+  m_axi_rmem23_RID,
+  m_axi_rmem23_RLAST,
+  m_axi_rmem23_RREADY,
+  m_axi_rmem23_RRESP,
+  m_axi_rmem23_RVALID,
+  m_axi_rmem23_WDATA,
+  m_axi_rmem23_WLAST,
+  m_axi_rmem23_WREADY,
+  m_axi_rmem23_WSTRB,
+  m_axi_rmem23_WVALID,
+  m_axi_rmem24_ARADDR,
+  m_axi_rmem24_ARBURST,
+  m_axi_rmem24_ARCACHE,
+  m_axi_rmem24_ARID,
+  m_axi_rmem24_ARLEN,
+  m_axi_rmem24_ARLOCK,
+  m_axi_rmem24_ARPROT,
+  m_axi_rmem24_ARQOS,
+  m_axi_rmem24_ARREADY,
+  m_axi_rmem24_ARSIZE,
+  m_axi_rmem24_ARVALID,
+  m_axi_rmem24_AWADDR,
+  m_axi_rmem24_AWBURST,
+  m_axi_rmem24_AWCACHE,
+  m_axi_rmem24_AWID,
+  m_axi_rmem24_AWLEN,
+  m_axi_rmem24_AWLOCK,
+  m_axi_rmem24_AWPROT,
+  m_axi_rmem24_AWQOS,
+  m_axi_rmem24_AWREADY,
+  m_axi_rmem24_AWSIZE,
+  m_axi_rmem24_AWVALID,
+  m_axi_rmem24_BID,
+  m_axi_rmem24_BREADY,
+  m_axi_rmem24_BRESP,
+  m_axi_rmem24_BVALID,
+  m_axi_rmem24_RDATA,
+  m_axi_rmem24_RID,
+  m_axi_rmem24_RLAST,
+  m_axi_rmem24_RREADY,
+  m_axi_rmem24_RRESP,
+  m_axi_rmem24_RVALID,
+  m_axi_rmem24_WDATA,
+  m_axi_rmem24_WLAST,
+  m_axi_rmem24_WREADY,
+  m_axi_rmem24_WSTRB,
+  m_axi_rmem24_WVALID,
+  m_axi_rmem25_ARADDR,
+  m_axi_rmem25_ARBURST,
+  m_axi_rmem25_ARCACHE,
+  m_axi_rmem25_ARID,
+  m_axi_rmem25_ARLEN,
+  m_axi_rmem25_ARLOCK,
+  m_axi_rmem25_ARPROT,
+  m_axi_rmem25_ARQOS,
+  m_axi_rmem25_ARREADY,
+  m_axi_rmem25_ARSIZE,
+  m_axi_rmem25_ARVALID,
+  m_axi_rmem25_AWADDR,
+  m_axi_rmem25_AWBURST,
+  m_axi_rmem25_AWCACHE,
+  m_axi_rmem25_AWID,
+  m_axi_rmem25_AWLEN,
+  m_axi_rmem25_AWLOCK,
+  m_axi_rmem25_AWPROT,
+  m_axi_rmem25_AWQOS,
+  m_axi_rmem25_AWREADY,
+  m_axi_rmem25_AWSIZE,
+  m_axi_rmem25_AWVALID,
+  m_axi_rmem25_BID,
+  m_axi_rmem25_BREADY,
+  m_axi_rmem25_BRESP,
+  m_axi_rmem25_BVALID,
+  m_axi_rmem25_RDATA,
+  m_axi_rmem25_RID,
+  m_axi_rmem25_RLAST,
+  m_axi_rmem25_RREADY,
+  m_axi_rmem25_RRESP,
+  m_axi_rmem25_RVALID,
+  m_axi_rmem25_WDATA,
+  m_axi_rmem25_WLAST,
+  m_axi_rmem25_WREADY,
+  m_axi_rmem25_WSTRB,
+  m_axi_rmem25_WVALID,
+  m_axi_rmem26_ARADDR,
+  m_axi_rmem26_ARBURST,
+  m_axi_rmem26_ARCACHE,
+  m_axi_rmem26_ARID,
+  m_axi_rmem26_ARLEN,
+  m_axi_rmem26_ARLOCK,
+  m_axi_rmem26_ARPROT,
+  m_axi_rmem26_ARQOS,
+  m_axi_rmem26_ARREADY,
+  m_axi_rmem26_ARSIZE,
+  m_axi_rmem26_ARVALID,
+  m_axi_rmem26_AWADDR,
+  m_axi_rmem26_AWBURST,
+  m_axi_rmem26_AWCACHE,
+  m_axi_rmem26_AWID,
+  m_axi_rmem26_AWLEN,
+  m_axi_rmem26_AWLOCK,
+  m_axi_rmem26_AWPROT,
+  m_axi_rmem26_AWQOS,
+  m_axi_rmem26_AWREADY,
+  m_axi_rmem26_AWSIZE,
+  m_axi_rmem26_AWVALID,
+  m_axi_rmem26_BID,
+  m_axi_rmem26_BREADY,
+  m_axi_rmem26_BRESP,
+  m_axi_rmem26_BVALID,
+  m_axi_rmem26_RDATA,
+  m_axi_rmem26_RID,
+  m_axi_rmem26_RLAST,
+  m_axi_rmem26_RREADY,
+  m_axi_rmem26_RRESP,
+  m_axi_rmem26_RVALID,
+  m_axi_rmem26_WDATA,
+  m_axi_rmem26_WLAST,
+  m_axi_rmem26_WREADY,
+  m_axi_rmem26_WSTRB,
+  m_axi_rmem26_WVALID,
+  m_axi_rmem27_ARADDR,
+  m_axi_rmem27_ARBURST,
+  m_axi_rmem27_ARCACHE,
+  m_axi_rmem27_ARID,
+  m_axi_rmem27_ARLEN,
+  m_axi_rmem27_ARLOCK,
+  m_axi_rmem27_ARPROT,
+  m_axi_rmem27_ARQOS,
+  m_axi_rmem27_ARREADY,
+  m_axi_rmem27_ARSIZE,
+  m_axi_rmem27_ARVALID,
+  m_axi_rmem27_AWADDR,
+  m_axi_rmem27_AWBURST,
+  m_axi_rmem27_AWCACHE,
+  m_axi_rmem27_AWID,
+  m_axi_rmem27_AWLEN,
+  m_axi_rmem27_AWLOCK,
+  m_axi_rmem27_AWPROT,
+  m_axi_rmem27_AWQOS,
+  m_axi_rmem27_AWREADY,
+  m_axi_rmem27_AWSIZE,
+  m_axi_rmem27_AWVALID,
+  m_axi_rmem27_BID,
+  m_axi_rmem27_BREADY,
+  m_axi_rmem27_BRESP,
+  m_axi_rmem27_BVALID,
+  m_axi_rmem27_RDATA,
+  m_axi_rmem27_RID,
+  m_axi_rmem27_RLAST,
+  m_axi_rmem27_RREADY,
+  m_axi_rmem27_RRESP,
+  m_axi_rmem27_RVALID,
+  m_axi_rmem27_WDATA,
+  m_axi_rmem27_WLAST,
+  m_axi_rmem27_WREADY,
+  m_axi_rmem27_WSTRB,
+  m_axi_rmem27_WVALID
+);
+
+  parameter C_S_AXI_CONTROL_DATA_WIDTH = 32;
+  parameter C_S_AXI_CONTROL_ADDR_WIDTH = 9;
+  parameter C_S_AXI_DATA_WIDTH = 32;
+  parameter C_S_AXI_CONTROL_WSTRB_WIDTH = 32 / 8;
+  parameter C_S_AXI_WSTRB_WIDTH = 32 / 8;
+  (* RS_HS = "s_axi_control_AW.valid" *)input s_axi_control_AWVALID;
+  (* RS_HS = "s_axi_control_AW.ready" *)output s_axi_control_AWREADY;
+  (* RS_HS = "s_axi_control_AW.data" *)input [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR;
+  (* RS_HS = "s_axi_control_W.valid" *)input s_axi_control_WVALID;
+  (* RS_HS = "s_axi_control_W.ready" *)output s_axi_control_WREADY;
+  (* RS_HS = "s_axi_control_W.data" *)input [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA;
+  (* RS_HS = "s_axi_control_W.data" *)input [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB;
+  (* RS_HS = "s_axi_control_AR.valid" *)input s_axi_control_ARVALID;
+  (* RS_HS = "s_axi_control_AR.ready" *)output s_axi_control_ARREADY;
+  (* RS_HS = "s_axi_control_AR.data" *)input [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_ARADDR;
+  (* RS_HS = "s_axi_control_R.valid" *)output s_axi_control_RVALID;
+  (* RS_HS = "s_axi_control_R.ready" *)input s_axi_control_RREADY;
+  (* RS_HS = "s_axi_control_R.data" *)output [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_RDATA;
+  (* RS_HS = "s_axi_control_R.data" *)output [1:0] s_axi_control_RRESP;
+  (* RS_HS = "s_axi_control_B.valid" *)output s_axi_control_BVALID;
+  (* RS_HS = "s_axi_control_B.ready" *)input s_axi_control_BREADY;
+  (* RS_HS = "s_axi_control_B.data" *)output [1:0] s_axi_control_BRESP;
+  (* RS_CLK *)input ap_clk;
+  (* RS_RST = "ff" *)input ap_rst_n;
+  (* RS_FF = "interrupt" *)output interrupt;
+  (* RS_HS = "m_axi_rmem0_AR.data" *)output [63:0] m_axi_rmem0_ARADDR;
+  (* RS_HS = "m_axi_rmem0_AR.data" *)output [1:0] m_axi_rmem0_ARBURST;
+  (* RS_HS = "m_axi_rmem0_AR.data" *)output [3:0] m_axi_rmem0_ARCACHE;
+  (* RS_HS = "m_axi_rmem0_AR.data" *)output [1:0] m_axi_rmem0_ARID;
+  (* RS_HS = "m_axi_rmem0_AR.data" *)output [7:0] m_axi_rmem0_ARLEN;
+  (* RS_HS = "m_axi_rmem0_AR.data" *)output m_axi_rmem0_ARLOCK;
+  (* RS_HS = "m_axi_rmem0_AR.data" *)output [2:0] m_axi_rmem0_ARPROT;
+  (* RS_HS = "m_axi_rmem0_AR.data" *)output [3:0] m_axi_rmem0_ARQOS;
+  (* RS_HS = "m_axi_rmem0_AR.ready" *)input m_axi_rmem0_ARREADY;
+  (* RS_HS = "m_axi_rmem0_AR.data" *)output [2:0] m_axi_rmem0_ARSIZE;
+  (* RS_HS = "m_axi_rmem0_AR.valid" *)output m_axi_rmem0_ARVALID;
+  (* RS_HS = "m_axi_rmem0_AW.data" *)output [63:0] m_axi_rmem0_AWADDR;
+  (* RS_HS = "m_axi_rmem0_AW.data" *)output [1:0] m_axi_rmem0_AWBURST;
+  (* RS_HS = "m_axi_rmem0_AW.data" *)output [3:0] m_axi_rmem0_AWCACHE;
+  (* RS_HS = "m_axi_rmem0_AW.data" *)output [1:0] m_axi_rmem0_AWID;
+  (* RS_HS = "m_axi_rmem0_AW.data" *)output [7:0] m_axi_rmem0_AWLEN;
+  (* RS_HS = "m_axi_rmem0_AW.data" *)output m_axi_rmem0_AWLOCK;
+  (* RS_HS = "m_axi_rmem0_AW.data" *)output [2:0] m_axi_rmem0_AWPROT;
+  (* RS_HS = "m_axi_rmem0_AW.data" *)output [3:0] m_axi_rmem0_AWQOS;
+  (* RS_HS = "m_axi_rmem0_AW.ready" *)input m_axi_rmem0_AWREADY;
+  (* RS_HS = "m_axi_rmem0_AW.data" *)output [2:0] m_axi_rmem0_AWSIZE;
+  (* RS_HS = "m_axi_rmem0_AW.valid" *)output m_axi_rmem0_AWVALID;
+  (* RS_HS = "m_axi_rmem0_B.data" *)input [1:0] m_axi_rmem0_BID;
+  (* RS_HS = "m_axi_rmem0_B.ready" *)output m_axi_rmem0_BREADY;
+  (* RS_HS = "m_axi_rmem0_B.data" *)input [1:0] m_axi_rmem0_BRESP;
+  (* RS_HS = "m_axi_rmem0_B.valid" *)input m_axi_rmem0_BVALID;
+  (* RS_HS = "m_axi_rmem0_R.data" *)input [511:0] m_axi_rmem0_RDATA;
+  (* RS_HS = "m_axi_rmem0_R.data" *)input [1:0] m_axi_rmem0_RID;
+  (* RS_HS = "m_axi_rmem0_R.data" *)input m_axi_rmem0_RLAST;
+  (* RS_HS = "m_axi_rmem0_R.ready" *)output m_axi_rmem0_RREADY;
+  (* RS_HS = "m_axi_rmem0_R.data" *)input [1:0] m_axi_rmem0_RRESP;
+  (* RS_HS = "m_axi_rmem0_R.valid" *)input m_axi_rmem0_RVALID;
+  (* RS_HS = "m_axi_rmem0_W.data" *)output [511:0] m_axi_rmem0_WDATA;
+  (* RS_HS = "m_axi_rmem0_W.data" *)output m_axi_rmem0_WLAST;
+  (* RS_HS = "m_axi_rmem0_W.ready" *)input m_axi_rmem0_WREADY;
+  (* RS_HS = "m_axi_rmem0_W.data" *)output [63:0] m_axi_rmem0_WSTRB;
+  (* RS_HS = "m_axi_rmem0_W.valid" *)output m_axi_rmem0_WVALID;
+  (* RS_HS = "m_axi_rmem1_AR.data" *)output [63:0] m_axi_rmem1_ARADDR;
+  (* RS_HS = "m_axi_rmem1_AR.data" *)output [1:0] m_axi_rmem1_ARBURST;
+  (* RS_HS = "m_axi_rmem1_AR.data" *)output [3:0] m_axi_rmem1_ARCACHE;
+  (* RS_HS = "m_axi_rmem1_AR.data" *)output [1:0] m_axi_rmem1_ARID;
+  (* RS_HS = "m_axi_rmem1_AR.data" *)output [7:0] m_axi_rmem1_ARLEN;
+  (* RS_HS = "m_axi_rmem1_AR.data" *)output m_axi_rmem1_ARLOCK;
+  (* RS_HS = "m_axi_rmem1_AR.data" *)output [2:0] m_axi_rmem1_ARPROT;
+  (* RS_HS = "m_axi_rmem1_AR.data" *)output [3:0] m_axi_rmem1_ARQOS;
+  (* RS_HS = "m_axi_rmem1_AR.ready" *)input m_axi_rmem1_ARREADY;
+  (* RS_HS = "m_axi_rmem1_AR.data" *)output [2:0] m_axi_rmem1_ARSIZE;
+  (* RS_HS = "m_axi_rmem1_AR.valid" *)output m_axi_rmem1_ARVALID;
+  (* RS_HS = "m_axi_rmem1_AW.data" *)output [63:0] m_axi_rmem1_AWADDR;
+  (* RS_HS = "m_axi_rmem1_AW.data" *)output [1:0] m_axi_rmem1_AWBURST;
+  (* RS_HS = "m_axi_rmem1_AW.data" *)output [3:0] m_axi_rmem1_AWCACHE;
+  (* RS_HS = "m_axi_rmem1_AW.data" *)output [1:0] m_axi_rmem1_AWID;
+  (* RS_HS = "m_axi_rmem1_AW.data" *)output [7:0] m_axi_rmem1_AWLEN;
+  (* RS_HS = "m_axi_rmem1_AW.data" *)output m_axi_rmem1_AWLOCK;
+  (* RS_HS = "m_axi_rmem1_AW.data" *)output [2:0] m_axi_rmem1_AWPROT;
+  (* RS_HS = "m_axi_rmem1_AW.data" *)output [3:0] m_axi_rmem1_AWQOS;
+  (* RS_HS = "m_axi_rmem1_AW.ready" *)input m_axi_rmem1_AWREADY;
+  (* RS_HS = "m_axi_rmem1_AW.data" *)output [2:0] m_axi_rmem1_AWSIZE;
+  (* RS_HS = "m_axi_rmem1_AW.valid" *)output m_axi_rmem1_AWVALID;
+  (* RS_HS = "m_axi_rmem1_B.data" *)input [1:0] m_axi_rmem1_BID;
+  (* RS_HS = "m_axi_rmem1_B.ready" *)output m_axi_rmem1_BREADY;
+  (* RS_HS = "m_axi_rmem1_B.data" *)input [1:0] m_axi_rmem1_BRESP;
+  (* RS_HS = "m_axi_rmem1_B.valid" *)input m_axi_rmem1_BVALID;
+  (* RS_HS = "m_axi_rmem1_R.data" *)input [511:0] m_axi_rmem1_RDATA;
+  (* RS_HS = "m_axi_rmem1_R.data" *)input [1:0] m_axi_rmem1_RID;
+  (* RS_HS = "m_axi_rmem1_R.data" *)input m_axi_rmem1_RLAST;
+  (* RS_HS = "m_axi_rmem1_R.ready" *)output m_axi_rmem1_RREADY;
+  (* RS_HS = "m_axi_rmem1_R.data" *)input [1:0] m_axi_rmem1_RRESP;
+  (* RS_HS = "m_axi_rmem1_R.valid" *)input m_axi_rmem1_RVALID;
+  (* RS_HS = "m_axi_rmem1_W.data" *)output [511:0] m_axi_rmem1_WDATA;
+  (* RS_HS = "m_axi_rmem1_W.data" *)output m_axi_rmem1_WLAST;
+  (* RS_HS = "m_axi_rmem1_W.ready" *)input m_axi_rmem1_WREADY;
+  (* RS_HS = "m_axi_rmem1_W.data" *)output [63:0] m_axi_rmem1_WSTRB;
+  (* RS_HS = "m_axi_rmem1_W.valid" *)output m_axi_rmem1_WVALID;
+  (* RS_HS = "m_axi_rmem2_AR.data" *)output [63:0] m_axi_rmem2_ARADDR;
+  (* RS_HS = "m_axi_rmem2_AR.data" *)output [1:0] m_axi_rmem2_ARBURST;
+  (* RS_HS = "m_axi_rmem2_AR.data" *)output [3:0] m_axi_rmem2_ARCACHE;
+  (* RS_HS = "m_axi_rmem2_AR.data" *)output [1:0] m_axi_rmem2_ARID;
+  (* RS_HS = "m_axi_rmem2_AR.data" *)output [7:0] m_axi_rmem2_ARLEN;
+  (* RS_HS = "m_axi_rmem2_AR.data" *)output m_axi_rmem2_ARLOCK;
+  (* RS_HS = "m_axi_rmem2_AR.data" *)output [2:0] m_axi_rmem2_ARPROT;
+  (* RS_HS = "m_axi_rmem2_AR.data" *)output [3:0] m_axi_rmem2_ARQOS;
+  (* RS_HS = "m_axi_rmem2_AR.ready" *)input m_axi_rmem2_ARREADY;
+  (* RS_HS = "m_axi_rmem2_AR.data" *)output [2:0] m_axi_rmem2_ARSIZE;
+  (* RS_HS = "m_axi_rmem2_AR.valid" *)output m_axi_rmem2_ARVALID;
+  (* RS_HS = "m_axi_rmem2_AW.data" *)output [63:0] m_axi_rmem2_AWADDR;
+  (* RS_HS = "m_axi_rmem2_AW.data" *)output [1:0] m_axi_rmem2_AWBURST;
+  (* RS_HS = "m_axi_rmem2_AW.data" *)output [3:0] m_axi_rmem2_AWCACHE;
+  (* RS_HS = "m_axi_rmem2_AW.data" *)output [1:0] m_axi_rmem2_AWID;
+  (* RS_HS = "m_axi_rmem2_AW.data" *)output [7:0] m_axi_rmem2_AWLEN;
+  (* RS_HS = "m_axi_rmem2_AW.data" *)output m_axi_rmem2_AWLOCK;
+  (* RS_HS = "m_axi_rmem2_AW.data" *)output [2:0] m_axi_rmem2_AWPROT;
+  (* RS_HS = "m_axi_rmem2_AW.data" *)output [3:0] m_axi_rmem2_AWQOS;
+  (* RS_HS = "m_axi_rmem2_AW.ready" *)input m_axi_rmem2_AWREADY;
+  (* RS_HS = "m_axi_rmem2_AW.data" *)output [2:0] m_axi_rmem2_AWSIZE;
+  (* RS_HS = "m_axi_rmem2_AW.valid" *)output m_axi_rmem2_AWVALID;
+  (* RS_HS = "m_axi_rmem2_B.data" *)input [1:0] m_axi_rmem2_BID;
+  (* RS_HS = "m_axi_rmem2_B.ready" *)output m_axi_rmem2_BREADY;
+  (* RS_HS = "m_axi_rmem2_B.data" *)input [1:0] m_axi_rmem2_BRESP;
+  (* RS_HS = "m_axi_rmem2_B.valid" *)input m_axi_rmem2_BVALID;
+  (* RS_HS = "m_axi_rmem2_R.data" *)input [511:0] m_axi_rmem2_RDATA;
+  (* RS_HS = "m_axi_rmem2_R.data" *)input [1:0] m_axi_rmem2_RID;
+  (* RS_HS = "m_axi_rmem2_R.data" *)input m_axi_rmem2_RLAST;
+  (* RS_HS = "m_axi_rmem2_R.ready" *)output m_axi_rmem2_RREADY;
+  (* RS_HS = "m_axi_rmem2_R.data" *)input [1:0] m_axi_rmem2_RRESP;
+  (* RS_HS = "m_axi_rmem2_R.valid" *)input m_axi_rmem2_RVALID;
+  (* RS_HS = "m_axi_rmem2_W.data" *)output [511:0] m_axi_rmem2_WDATA;
+  (* RS_HS = "m_axi_rmem2_W.data" *)output m_axi_rmem2_WLAST;
+  (* RS_HS = "m_axi_rmem2_W.ready" *)input m_axi_rmem2_WREADY;
+  (* RS_HS = "m_axi_rmem2_W.data" *)output [63:0] m_axi_rmem2_WSTRB;
+  (* RS_HS = "m_axi_rmem2_W.valid" *)output m_axi_rmem2_WVALID;
+  (* RS_HS = "m_axi_rmem3_AR.data" *)output [63:0] m_axi_rmem3_ARADDR;
+  (* RS_HS = "m_axi_rmem3_AR.data" *)output [1:0] m_axi_rmem3_ARBURST;
+  (* RS_HS = "m_axi_rmem3_AR.data" *)output [3:0] m_axi_rmem3_ARCACHE;
+  (* RS_HS = "m_axi_rmem3_AR.data" *)output [1:0] m_axi_rmem3_ARID;
+  (* RS_HS = "m_axi_rmem3_AR.data" *)output [7:0] m_axi_rmem3_ARLEN;
+  (* RS_HS = "m_axi_rmem3_AR.data" *)output m_axi_rmem3_ARLOCK;
+  (* RS_HS = "m_axi_rmem3_AR.data" *)output [2:0] m_axi_rmem3_ARPROT;
+  (* RS_HS = "m_axi_rmem3_AR.data" *)output [3:0] m_axi_rmem3_ARQOS;
+  (* RS_HS = "m_axi_rmem3_AR.ready" *)input m_axi_rmem3_ARREADY;
+  (* RS_HS = "m_axi_rmem3_AR.data" *)output [2:0] m_axi_rmem3_ARSIZE;
+  (* RS_HS = "m_axi_rmem3_AR.valid" *)output m_axi_rmem3_ARVALID;
+  (* RS_HS = "m_axi_rmem3_AW.data" *)output [63:0] m_axi_rmem3_AWADDR;
+  (* RS_HS = "m_axi_rmem3_AW.data" *)output [1:0] m_axi_rmem3_AWBURST;
+  (* RS_HS = "m_axi_rmem3_AW.data" *)output [3:0] m_axi_rmem3_AWCACHE;
+  (* RS_HS = "m_axi_rmem3_AW.data" *)output [1:0] m_axi_rmem3_AWID;
+  (* RS_HS = "m_axi_rmem3_AW.data" *)output [7:0] m_axi_rmem3_AWLEN;
+  (* RS_HS = "m_axi_rmem3_AW.data" *)output m_axi_rmem3_AWLOCK;
+  (* RS_HS = "m_axi_rmem3_AW.data" *)output [2:0] m_axi_rmem3_AWPROT;
+  (* RS_HS = "m_axi_rmem3_AW.data" *)output [3:0] m_axi_rmem3_AWQOS;
+  (* RS_HS = "m_axi_rmem3_AW.ready" *)input m_axi_rmem3_AWREADY;
+  (* RS_HS = "m_axi_rmem3_AW.data" *)output [2:0] m_axi_rmem3_AWSIZE;
+  (* RS_HS = "m_axi_rmem3_AW.valid" *)output m_axi_rmem3_AWVALID;
+  (* RS_HS = "m_axi_rmem3_B.data" *)input [1:0] m_axi_rmem3_BID;
+  (* RS_HS = "m_axi_rmem3_B.ready" *)output m_axi_rmem3_BREADY;
+  (* RS_HS = "m_axi_rmem3_B.data" *)input [1:0] m_axi_rmem3_BRESP;
+  (* RS_HS = "m_axi_rmem3_B.valid" *)input m_axi_rmem3_BVALID;
+  (* RS_HS = "m_axi_rmem3_R.data" *)input [511:0] m_axi_rmem3_RDATA;
+  (* RS_HS = "m_axi_rmem3_R.data" *)input [1:0] m_axi_rmem3_RID;
+  (* RS_HS = "m_axi_rmem3_R.data" *)input m_axi_rmem3_RLAST;
+  (* RS_HS = "m_axi_rmem3_R.ready" *)output m_axi_rmem3_RREADY;
+  (* RS_HS = "m_axi_rmem3_R.data" *)input [1:0] m_axi_rmem3_RRESP;
+  (* RS_HS = "m_axi_rmem3_R.valid" *)input m_axi_rmem3_RVALID;
+  (* RS_HS = "m_axi_rmem3_W.data" *)output [511:0] m_axi_rmem3_WDATA;
+  (* RS_HS = "m_axi_rmem3_W.data" *)output m_axi_rmem3_WLAST;
+  (* RS_HS = "m_axi_rmem3_W.ready" *)input m_axi_rmem3_WREADY;
+  (* RS_HS = "m_axi_rmem3_W.data" *)output [63:0] m_axi_rmem3_WSTRB;
+  (* RS_HS = "m_axi_rmem3_W.valid" *)output m_axi_rmem3_WVALID;
+  (* RS_HS = "m_axi_rmem4_AR.data" *)output [63:0] m_axi_rmem4_ARADDR;
+  (* RS_HS = "m_axi_rmem4_AR.data" *)output [1:0] m_axi_rmem4_ARBURST;
+  (* RS_HS = "m_axi_rmem4_AR.data" *)output [3:0] m_axi_rmem4_ARCACHE;
+  (* RS_HS = "m_axi_rmem4_AR.data" *)output [1:0] m_axi_rmem4_ARID;
+  (* RS_HS = "m_axi_rmem4_AR.data" *)output [7:0] m_axi_rmem4_ARLEN;
+  (* RS_HS = "m_axi_rmem4_AR.data" *)output m_axi_rmem4_ARLOCK;
+  (* RS_HS = "m_axi_rmem4_AR.data" *)output [2:0] m_axi_rmem4_ARPROT;
+  (* RS_HS = "m_axi_rmem4_AR.data" *)output [3:0] m_axi_rmem4_ARQOS;
+  (* RS_HS = "m_axi_rmem4_AR.ready" *)input m_axi_rmem4_ARREADY;
+  (* RS_HS = "m_axi_rmem4_AR.data" *)output [2:0] m_axi_rmem4_ARSIZE;
+  (* RS_HS = "m_axi_rmem4_AR.valid" *)output m_axi_rmem4_ARVALID;
+  (* RS_HS = "m_axi_rmem4_AW.data" *)output [63:0] m_axi_rmem4_AWADDR;
+  (* RS_HS = "m_axi_rmem4_AW.data" *)output [1:0] m_axi_rmem4_AWBURST;
+  (* RS_HS = "m_axi_rmem4_AW.data" *)output [3:0] m_axi_rmem4_AWCACHE;
+  (* RS_HS = "m_axi_rmem4_AW.data" *)output [1:0] m_axi_rmem4_AWID;
+  (* RS_HS = "m_axi_rmem4_AW.data" *)output [7:0] m_axi_rmem4_AWLEN;
+  (* RS_HS = "m_axi_rmem4_AW.data" *)output m_axi_rmem4_AWLOCK;
+  (* RS_HS = "m_axi_rmem4_AW.data" *)output [2:0] m_axi_rmem4_AWPROT;
+  (* RS_HS = "m_axi_rmem4_AW.data" *)output [3:0] m_axi_rmem4_AWQOS;
+  (* RS_HS = "m_axi_rmem4_AW.ready" *)input m_axi_rmem4_AWREADY;
+  (* RS_HS = "m_axi_rmem4_AW.data" *)output [2:0] m_axi_rmem4_AWSIZE;
+  (* RS_HS = "m_axi_rmem4_AW.valid" *)output m_axi_rmem4_AWVALID;
+  (* RS_HS = "m_axi_rmem4_B.data" *)input [1:0] m_axi_rmem4_BID;
+  (* RS_HS = "m_axi_rmem4_B.ready" *)output m_axi_rmem4_BREADY;
+  (* RS_HS = "m_axi_rmem4_B.data" *)input [1:0] m_axi_rmem4_BRESP;
+  (* RS_HS = "m_axi_rmem4_B.valid" *)input m_axi_rmem4_BVALID;
+  (* RS_HS = "m_axi_rmem4_R.data" *)input [511:0] m_axi_rmem4_RDATA;
+  (* RS_HS = "m_axi_rmem4_R.data" *)input [1:0] m_axi_rmem4_RID;
+  (* RS_HS = "m_axi_rmem4_R.data" *)input m_axi_rmem4_RLAST;
+  (* RS_HS = "m_axi_rmem4_R.ready" *)output m_axi_rmem4_RREADY;
+  (* RS_HS = "m_axi_rmem4_R.data" *)input [1:0] m_axi_rmem4_RRESP;
+  (* RS_HS = "m_axi_rmem4_R.valid" *)input m_axi_rmem4_RVALID;
+  (* RS_HS = "m_axi_rmem4_W.data" *)output [511:0] m_axi_rmem4_WDATA;
+  (* RS_HS = "m_axi_rmem4_W.data" *)output m_axi_rmem4_WLAST;
+  (* RS_HS = "m_axi_rmem4_W.ready" *)input m_axi_rmem4_WREADY;
+  (* RS_HS = "m_axi_rmem4_W.data" *)output [63:0] m_axi_rmem4_WSTRB;
+  (* RS_HS = "m_axi_rmem4_W.valid" *)output m_axi_rmem4_WVALID;
+  (* RS_HS = "m_axi_rmem5_AR.data" *)output [63:0] m_axi_rmem5_ARADDR;
+  (* RS_HS = "m_axi_rmem5_AR.data" *)output [1:0] m_axi_rmem5_ARBURST;
+  (* RS_HS = "m_axi_rmem5_AR.data" *)output [3:0] m_axi_rmem5_ARCACHE;
+  (* RS_HS = "m_axi_rmem5_AR.data" *)output [1:0] m_axi_rmem5_ARID;
+  (* RS_HS = "m_axi_rmem5_AR.data" *)output [7:0] m_axi_rmem5_ARLEN;
+  (* RS_HS = "m_axi_rmem5_AR.data" *)output m_axi_rmem5_ARLOCK;
+  (* RS_HS = "m_axi_rmem5_AR.data" *)output [2:0] m_axi_rmem5_ARPROT;
+  (* RS_HS = "m_axi_rmem5_AR.data" *)output [3:0] m_axi_rmem5_ARQOS;
+  (* RS_HS = "m_axi_rmem5_AR.ready" *)input m_axi_rmem5_ARREADY;
+  (* RS_HS = "m_axi_rmem5_AR.data" *)output [2:0] m_axi_rmem5_ARSIZE;
+  (* RS_HS = "m_axi_rmem5_AR.valid" *)output m_axi_rmem5_ARVALID;
+  (* RS_HS = "m_axi_rmem5_AW.data" *)output [63:0] m_axi_rmem5_AWADDR;
+  (* RS_HS = "m_axi_rmem5_AW.data" *)output [1:0] m_axi_rmem5_AWBURST;
+  (* RS_HS = "m_axi_rmem5_AW.data" *)output [3:0] m_axi_rmem5_AWCACHE;
+  (* RS_HS = "m_axi_rmem5_AW.data" *)output [1:0] m_axi_rmem5_AWID;
+  (* RS_HS = "m_axi_rmem5_AW.data" *)output [7:0] m_axi_rmem5_AWLEN;
+  (* RS_HS = "m_axi_rmem5_AW.data" *)output m_axi_rmem5_AWLOCK;
+  (* RS_HS = "m_axi_rmem5_AW.data" *)output [2:0] m_axi_rmem5_AWPROT;
+  (* RS_HS = "m_axi_rmem5_AW.data" *)output [3:0] m_axi_rmem5_AWQOS;
+  (* RS_HS = "m_axi_rmem5_AW.ready" *)input m_axi_rmem5_AWREADY;
+  (* RS_HS = "m_axi_rmem5_AW.data" *)output [2:0] m_axi_rmem5_AWSIZE;
+  (* RS_HS = "m_axi_rmem5_AW.valid" *)output m_axi_rmem5_AWVALID;
+  (* RS_HS = "m_axi_rmem5_B.data" *)input [1:0] m_axi_rmem5_BID;
+  (* RS_HS = "m_axi_rmem5_B.ready" *)output m_axi_rmem5_BREADY;
+  (* RS_HS = "m_axi_rmem5_B.data" *)input [1:0] m_axi_rmem5_BRESP;
+  (* RS_HS = "m_axi_rmem5_B.valid" *)input m_axi_rmem5_BVALID;
+  (* RS_HS = "m_axi_rmem5_R.data" *)input [511:0] m_axi_rmem5_RDATA;
+  (* RS_HS = "m_axi_rmem5_R.data" *)input [1:0] m_axi_rmem5_RID;
+  (* RS_HS = "m_axi_rmem5_R.data" *)input m_axi_rmem5_RLAST;
+  (* RS_HS = "m_axi_rmem5_R.ready" *)output m_axi_rmem5_RREADY;
+  (* RS_HS = "m_axi_rmem5_R.data" *)input [1:0] m_axi_rmem5_RRESP;
+  (* RS_HS = "m_axi_rmem5_R.valid" *)input m_axi_rmem5_RVALID;
+  (* RS_HS = "m_axi_rmem5_W.data" *)output [511:0] m_axi_rmem5_WDATA;
+  (* RS_HS = "m_axi_rmem5_W.data" *)output m_axi_rmem5_WLAST;
+  (* RS_HS = "m_axi_rmem5_W.ready" *)input m_axi_rmem5_WREADY;
+  (* RS_HS = "m_axi_rmem5_W.data" *)output [63:0] m_axi_rmem5_WSTRB;
+  (* RS_HS = "m_axi_rmem5_W.valid" *)output m_axi_rmem5_WVALID;
+  (* RS_HS = "m_axi_rmem6_AR.data" *)output [63:0] m_axi_rmem6_ARADDR;
+  (* RS_HS = "m_axi_rmem6_AR.data" *)output [1:0] m_axi_rmem6_ARBURST;
+  (* RS_HS = "m_axi_rmem6_AR.data" *)output [3:0] m_axi_rmem6_ARCACHE;
+  (* RS_HS = "m_axi_rmem6_AR.data" *)output [1:0] m_axi_rmem6_ARID;
+  (* RS_HS = "m_axi_rmem6_AR.data" *)output [7:0] m_axi_rmem6_ARLEN;
+  (* RS_HS = "m_axi_rmem6_AR.data" *)output m_axi_rmem6_ARLOCK;
+  (* RS_HS = "m_axi_rmem6_AR.data" *)output [2:0] m_axi_rmem6_ARPROT;
+  (* RS_HS = "m_axi_rmem6_AR.data" *)output [3:0] m_axi_rmem6_ARQOS;
+  (* RS_HS = "m_axi_rmem6_AR.ready" *)input m_axi_rmem6_ARREADY;
+  (* RS_HS = "m_axi_rmem6_AR.data" *)output [2:0] m_axi_rmem6_ARSIZE;
+  (* RS_HS = "m_axi_rmem6_AR.valid" *)output m_axi_rmem6_ARVALID;
+  (* RS_HS = "m_axi_rmem6_AW.data" *)output [63:0] m_axi_rmem6_AWADDR;
+  (* RS_HS = "m_axi_rmem6_AW.data" *)output [1:0] m_axi_rmem6_AWBURST;
+  (* RS_HS = "m_axi_rmem6_AW.data" *)output [3:0] m_axi_rmem6_AWCACHE;
+  (* RS_HS = "m_axi_rmem6_AW.data" *)output [1:0] m_axi_rmem6_AWID;
+  (* RS_HS = "m_axi_rmem6_AW.data" *)output [7:0] m_axi_rmem6_AWLEN;
+  (* RS_HS = "m_axi_rmem6_AW.data" *)output m_axi_rmem6_AWLOCK;
+  (* RS_HS = "m_axi_rmem6_AW.data" *)output [2:0] m_axi_rmem6_AWPROT;
+  (* RS_HS = "m_axi_rmem6_AW.data" *)output [3:0] m_axi_rmem6_AWQOS;
+  (* RS_HS = "m_axi_rmem6_AW.ready" *)input m_axi_rmem6_AWREADY;
+  (* RS_HS = "m_axi_rmem6_AW.data" *)output [2:0] m_axi_rmem6_AWSIZE;
+  (* RS_HS = "m_axi_rmem6_AW.valid" *)output m_axi_rmem6_AWVALID;
+  (* RS_HS = "m_axi_rmem6_B.data" *)input [1:0] m_axi_rmem6_BID;
+  (* RS_HS = "m_axi_rmem6_B.ready" *)output m_axi_rmem6_BREADY;
+  (* RS_HS = "m_axi_rmem6_B.data" *)input [1:0] m_axi_rmem6_BRESP;
+  (* RS_HS = "m_axi_rmem6_B.valid" *)input m_axi_rmem6_BVALID;
+  (* RS_HS = "m_axi_rmem6_R.data" *)input [511:0] m_axi_rmem6_RDATA;
+  (* RS_HS = "m_axi_rmem6_R.data" *)input [1:0] m_axi_rmem6_RID;
+  (* RS_HS = "m_axi_rmem6_R.data" *)input m_axi_rmem6_RLAST;
+  (* RS_HS = "m_axi_rmem6_R.ready" *)output m_axi_rmem6_RREADY;
+  (* RS_HS = "m_axi_rmem6_R.data" *)input [1:0] m_axi_rmem6_RRESP;
+  (* RS_HS = "m_axi_rmem6_R.valid" *)input m_axi_rmem6_RVALID;
+  (* RS_HS = "m_axi_rmem6_W.data" *)output [511:0] m_axi_rmem6_WDATA;
+  (* RS_HS = "m_axi_rmem6_W.data" *)output m_axi_rmem6_WLAST;
+  (* RS_HS = "m_axi_rmem6_W.ready" *)input m_axi_rmem6_WREADY;
+  (* RS_HS = "m_axi_rmem6_W.data" *)output [63:0] m_axi_rmem6_WSTRB;
+  (* RS_HS = "m_axi_rmem6_W.valid" *)output m_axi_rmem6_WVALID;
+  (* RS_HS = "m_axi_rmem7_AR.data" *)output [63:0] m_axi_rmem7_ARADDR;
+  (* RS_HS = "m_axi_rmem7_AR.data" *)output [1:0] m_axi_rmem7_ARBURST;
+  (* RS_HS = "m_axi_rmem7_AR.data" *)output [3:0] m_axi_rmem7_ARCACHE;
+  (* RS_HS = "m_axi_rmem7_AR.data" *)output [1:0] m_axi_rmem7_ARID;
+  (* RS_HS = "m_axi_rmem7_AR.data" *)output [7:0] m_axi_rmem7_ARLEN;
+  (* RS_HS = "m_axi_rmem7_AR.data" *)output m_axi_rmem7_ARLOCK;
+  (* RS_HS = "m_axi_rmem7_AR.data" *)output [2:0] m_axi_rmem7_ARPROT;
+  (* RS_HS = "m_axi_rmem7_AR.data" *)output [3:0] m_axi_rmem7_ARQOS;
+  (* RS_HS = "m_axi_rmem7_AR.ready" *)input m_axi_rmem7_ARREADY;
+  (* RS_HS = "m_axi_rmem7_AR.data" *)output [2:0] m_axi_rmem7_ARSIZE;
+  (* RS_HS = "m_axi_rmem7_AR.valid" *)output m_axi_rmem7_ARVALID;
+  (* RS_HS = "m_axi_rmem7_AW.data" *)output [63:0] m_axi_rmem7_AWADDR;
+  (* RS_HS = "m_axi_rmem7_AW.data" *)output [1:0] m_axi_rmem7_AWBURST;
+  (* RS_HS = "m_axi_rmem7_AW.data" *)output [3:0] m_axi_rmem7_AWCACHE;
+  (* RS_HS = "m_axi_rmem7_AW.data" *)output [1:0] m_axi_rmem7_AWID;
+  (* RS_HS = "m_axi_rmem7_AW.data" *)output [7:0] m_axi_rmem7_AWLEN;
+  (* RS_HS = "m_axi_rmem7_AW.data" *)output m_axi_rmem7_AWLOCK;
+  (* RS_HS = "m_axi_rmem7_AW.data" *)output [2:0] m_axi_rmem7_AWPROT;
+  (* RS_HS = "m_axi_rmem7_AW.data" *)output [3:0] m_axi_rmem7_AWQOS;
+  (* RS_HS = "m_axi_rmem7_AW.ready" *)input m_axi_rmem7_AWREADY;
+  (* RS_HS = "m_axi_rmem7_AW.data" *)output [2:0] m_axi_rmem7_AWSIZE;
+  (* RS_HS = "m_axi_rmem7_AW.valid" *)output m_axi_rmem7_AWVALID;
+  (* RS_HS = "m_axi_rmem7_B.data" *)input [1:0] m_axi_rmem7_BID;
+  (* RS_HS = "m_axi_rmem7_B.ready" *)output m_axi_rmem7_BREADY;
+  (* RS_HS = "m_axi_rmem7_B.data" *)input [1:0] m_axi_rmem7_BRESP;
+  (* RS_HS = "m_axi_rmem7_B.valid" *)input m_axi_rmem7_BVALID;
+  (* RS_HS = "m_axi_rmem7_R.data" *)input [511:0] m_axi_rmem7_RDATA;
+  (* RS_HS = "m_axi_rmem7_R.data" *)input [1:0] m_axi_rmem7_RID;
+  (* RS_HS = "m_axi_rmem7_R.data" *)input m_axi_rmem7_RLAST;
+  (* RS_HS = "m_axi_rmem7_R.ready" *)output m_axi_rmem7_RREADY;
+  (* RS_HS = "m_axi_rmem7_R.data" *)input [1:0] m_axi_rmem7_RRESP;
+  (* RS_HS = "m_axi_rmem7_R.valid" *)input m_axi_rmem7_RVALID;
+  (* RS_HS = "m_axi_rmem7_W.data" *)output [511:0] m_axi_rmem7_WDATA;
+  (* RS_HS = "m_axi_rmem7_W.data" *)output m_axi_rmem7_WLAST;
+  (* RS_HS = "m_axi_rmem7_W.ready" *)input m_axi_rmem7_WREADY;
+  (* RS_HS = "m_axi_rmem7_W.data" *)output [63:0] m_axi_rmem7_WSTRB;
+  (* RS_HS = "m_axi_rmem7_W.valid" *)output m_axi_rmem7_WVALID;
+  (* RS_HS = "m_axi_rmem8_AR.data" *)output [63:0] m_axi_rmem8_ARADDR;
+  (* RS_HS = "m_axi_rmem8_AR.data" *)output [1:0] m_axi_rmem8_ARBURST;
+  (* RS_HS = "m_axi_rmem8_AR.data" *)output [3:0] m_axi_rmem8_ARCACHE;
+  (* RS_HS = "m_axi_rmem8_AR.data" *)output [1:0] m_axi_rmem8_ARID;
+  (* RS_HS = "m_axi_rmem8_AR.data" *)output [7:0] m_axi_rmem8_ARLEN;
+  (* RS_HS = "m_axi_rmem8_AR.data" *)output m_axi_rmem8_ARLOCK;
+  (* RS_HS = "m_axi_rmem8_AR.data" *)output [2:0] m_axi_rmem8_ARPROT;
+  (* RS_HS = "m_axi_rmem8_AR.data" *)output [3:0] m_axi_rmem8_ARQOS;
+  (* RS_HS = "m_axi_rmem8_AR.ready" *)input m_axi_rmem8_ARREADY;
+  (* RS_HS = "m_axi_rmem8_AR.data" *)output [2:0] m_axi_rmem8_ARSIZE;
+  (* RS_HS = "m_axi_rmem8_AR.valid" *)output m_axi_rmem8_ARVALID;
+  (* RS_HS = "m_axi_rmem8_AW.data" *)output [63:0] m_axi_rmem8_AWADDR;
+  (* RS_HS = "m_axi_rmem8_AW.data" *)output [1:0] m_axi_rmem8_AWBURST;
+  (* RS_HS = "m_axi_rmem8_AW.data" *)output [3:0] m_axi_rmem8_AWCACHE;
+  (* RS_HS = "m_axi_rmem8_AW.data" *)output [1:0] m_axi_rmem8_AWID;
+  (* RS_HS = "m_axi_rmem8_AW.data" *)output [7:0] m_axi_rmem8_AWLEN;
+  (* RS_HS = "m_axi_rmem8_AW.data" *)output m_axi_rmem8_AWLOCK;
+  (* RS_HS = "m_axi_rmem8_AW.data" *)output [2:0] m_axi_rmem8_AWPROT;
+  (* RS_HS = "m_axi_rmem8_AW.data" *)output [3:0] m_axi_rmem8_AWQOS;
+  (* RS_HS = "m_axi_rmem8_AW.ready" *)input m_axi_rmem8_AWREADY;
+  (* RS_HS = "m_axi_rmem8_AW.data" *)output [2:0] m_axi_rmem8_AWSIZE;
+  (* RS_HS = "m_axi_rmem8_AW.valid" *)output m_axi_rmem8_AWVALID;
+  (* RS_HS = "m_axi_rmem8_B.data" *)input [1:0] m_axi_rmem8_BID;
+  (* RS_HS = "m_axi_rmem8_B.ready" *)output m_axi_rmem8_BREADY;
+  (* RS_HS = "m_axi_rmem8_B.data" *)input [1:0] m_axi_rmem8_BRESP;
+  (* RS_HS = "m_axi_rmem8_B.valid" *)input m_axi_rmem8_BVALID;
+  (* RS_HS = "m_axi_rmem8_R.data" *)input [511:0] m_axi_rmem8_RDATA;
+  (* RS_HS = "m_axi_rmem8_R.data" *)input [1:0] m_axi_rmem8_RID;
+  (* RS_HS = "m_axi_rmem8_R.data" *)input m_axi_rmem8_RLAST;
+  (* RS_HS = "m_axi_rmem8_R.ready" *)output m_axi_rmem8_RREADY;
+  (* RS_HS = "m_axi_rmem8_R.data" *)input [1:0] m_axi_rmem8_RRESP;
+  (* RS_HS = "m_axi_rmem8_R.valid" *)input m_axi_rmem8_RVALID;
+  (* RS_HS = "m_axi_rmem8_W.data" *)output [511:0] m_axi_rmem8_WDATA;
+  (* RS_HS = "m_axi_rmem8_W.data" *)output m_axi_rmem8_WLAST;
+  (* RS_HS = "m_axi_rmem8_W.ready" *)input m_axi_rmem8_WREADY;
+  (* RS_HS = "m_axi_rmem8_W.data" *)output [63:0] m_axi_rmem8_WSTRB;
+  (* RS_HS = "m_axi_rmem8_W.valid" *)output m_axi_rmem8_WVALID;
+  (* RS_HS = "m_axi_rmem9_AR.data" *)output [63:0] m_axi_rmem9_ARADDR;
+  (* RS_HS = "m_axi_rmem9_AR.data" *)output [1:0] m_axi_rmem9_ARBURST;
+  (* RS_HS = "m_axi_rmem9_AR.data" *)output [3:0] m_axi_rmem9_ARCACHE;
+  (* RS_HS = "m_axi_rmem9_AR.data" *)output [1:0] m_axi_rmem9_ARID;
+  (* RS_HS = "m_axi_rmem9_AR.data" *)output [7:0] m_axi_rmem9_ARLEN;
+  (* RS_HS = "m_axi_rmem9_AR.data" *)output m_axi_rmem9_ARLOCK;
+  (* RS_HS = "m_axi_rmem9_AR.data" *)output [2:0] m_axi_rmem9_ARPROT;
+  (* RS_HS = "m_axi_rmem9_AR.data" *)output [3:0] m_axi_rmem9_ARQOS;
+  (* RS_HS = "m_axi_rmem9_AR.ready" *)input m_axi_rmem9_ARREADY;
+  (* RS_HS = "m_axi_rmem9_AR.data" *)output [2:0] m_axi_rmem9_ARSIZE;
+  (* RS_HS = "m_axi_rmem9_AR.valid" *)output m_axi_rmem9_ARVALID;
+  (* RS_HS = "m_axi_rmem9_AW.data" *)output [63:0] m_axi_rmem9_AWADDR;
+  (* RS_HS = "m_axi_rmem9_AW.data" *)output [1:0] m_axi_rmem9_AWBURST;
+  (* RS_HS = "m_axi_rmem9_AW.data" *)output [3:0] m_axi_rmem9_AWCACHE;
+  (* RS_HS = "m_axi_rmem9_AW.data" *)output [1:0] m_axi_rmem9_AWID;
+  (* RS_HS = "m_axi_rmem9_AW.data" *)output [7:0] m_axi_rmem9_AWLEN;
+  (* RS_HS = "m_axi_rmem9_AW.data" *)output m_axi_rmem9_AWLOCK;
+  (* RS_HS = "m_axi_rmem9_AW.data" *)output [2:0] m_axi_rmem9_AWPROT;
+  (* RS_HS = "m_axi_rmem9_AW.data" *)output [3:0] m_axi_rmem9_AWQOS;
+  (* RS_HS = "m_axi_rmem9_AW.ready" *)input m_axi_rmem9_AWREADY;
+  (* RS_HS = "m_axi_rmem9_AW.data" *)output [2:0] m_axi_rmem9_AWSIZE;
+  (* RS_HS = "m_axi_rmem9_AW.valid" *)output m_axi_rmem9_AWVALID;
+  (* RS_HS = "m_axi_rmem9_B.data" *)input [1:0] m_axi_rmem9_BID;
+  (* RS_HS = "m_axi_rmem9_B.ready" *)output m_axi_rmem9_BREADY;
+  (* RS_HS = "m_axi_rmem9_B.data" *)input [1:0] m_axi_rmem9_BRESP;
+  (* RS_HS = "m_axi_rmem9_B.valid" *)input m_axi_rmem9_BVALID;
+  (* RS_HS = "m_axi_rmem9_R.data" *)input [511:0] m_axi_rmem9_RDATA;
+  (* RS_HS = "m_axi_rmem9_R.data" *)input [1:0] m_axi_rmem9_RID;
+  (* RS_HS = "m_axi_rmem9_R.data" *)input m_axi_rmem9_RLAST;
+  (* RS_HS = "m_axi_rmem9_R.ready" *)output m_axi_rmem9_RREADY;
+  (* RS_HS = "m_axi_rmem9_R.data" *)input [1:0] m_axi_rmem9_RRESP;
+  (* RS_HS = "m_axi_rmem9_R.valid" *)input m_axi_rmem9_RVALID;
+  (* RS_HS = "m_axi_rmem9_W.data" *)output [511:0] m_axi_rmem9_WDATA;
+  (* RS_HS = "m_axi_rmem9_W.data" *)output m_axi_rmem9_WLAST;
+  (* RS_HS = "m_axi_rmem9_W.ready" *)input m_axi_rmem9_WREADY;
+  (* RS_HS = "m_axi_rmem9_W.data" *)output [63:0] m_axi_rmem9_WSTRB;
+  (* RS_HS = "m_axi_rmem9_W.valid" *)output m_axi_rmem9_WVALID;
+  (* RS_HS = "m_axi_rmem10_AR.data" *)output [63:0] m_axi_rmem10_ARADDR;
+  (* RS_HS = "m_axi_rmem10_AR.data" *)output [1:0] m_axi_rmem10_ARBURST;
+  (* RS_HS = "m_axi_rmem10_AR.data" *)output [3:0] m_axi_rmem10_ARCACHE;
+  (* RS_HS = "m_axi_rmem10_AR.data" *)output [1:0] m_axi_rmem10_ARID;
+  (* RS_HS = "m_axi_rmem10_AR.data" *)output [7:0] m_axi_rmem10_ARLEN;
+  (* RS_HS = "m_axi_rmem10_AR.data" *)output m_axi_rmem10_ARLOCK;
+  (* RS_HS = "m_axi_rmem10_AR.data" *)output [2:0] m_axi_rmem10_ARPROT;
+  (* RS_HS = "m_axi_rmem10_AR.data" *)output [3:0] m_axi_rmem10_ARQOS;
+  (* RS_HS = "m_axi_rmem10_AR.ready" *)input m_axi_rmem10_ARREADY;
+  (* RS_HS = "m_axi_rmem10_AR.data" *)output [2:0] m_axi_rmem10_ARSIZE;
+  (* RS_HS = "m_axi_rmem10_AR.valid" *)output m_axi_rmem10_ARVALID;
+  (* RS_HS = "m_axi_rmem10_AW.data" *)output [63:0] m_axi_rmem10_AWADDR;
+  (* RS_HS = "m_axi_rmem10_AW.data" *)output [1:0] m_axi_rmem10_AWBURST;
+  (* RS_HS = "m_axi_rmem10_AW.data" *)output [3:0] m_axi_rmem10_AWCACHE;
+  (* RS_HS = "m_axi_rmem10_AW.data" *)output [1:0] m_axi_rmem10_AWID;
+  (* RS_HS = "m_axi_rmem10_AW.data" *)output [7:0] m_axi_rmem10_AWLEN;
+  (* RS_HS = "m_axi_rmem10_AW.data" *)output m_axi_rmem10_AWLOCK;
+  (* RS_HS = "m_axi_rmem10_AW.data" *)output [2:0] m_axi_rmem10_AWPROT;
+  (* RS_HS = "m_axi_rmem10_AW.data" *)output [3:0] m_axi_rmem10_AWQOS;
+  (* RS_HS = "m_axi_rmem10_AW.ready" *)input m_axi_rmem10_AWREADY;
+  (* RS_HS = "m_axi_rmem10_AW.data" *)output [2:0] m_axi_rmem10_AWSIZE;
+  (* RS_HS = "m_axi_rmem10_AW.valid" *)output m_axi_rmem10_AWVALID;
+  (* RS_HS = "m_axi_rmem10_B.data" *)input [1:0] m_axi_rmem10_BID;
+  (* RS_HS = "m_axi_rmem10_B.ready" *)output m_axi_rmem10_BREADY;
+  (* RS_HS = "m_axi_rmem10_B.data" *)input [1:0] m_axi_rmem10_BRESP;
+  (* RS_HS = "m_axi_rmem10_B.valid" *)input m_axi_rmem10_BVALID;
+  (* RS_HS = "m_axi_rmem10_R.data" *)input [511:0] m_axi_rmem10_RDATA;
+  (* RS_HS = "m_axi_rmem10_R.data" *)input [1:0] m_axi_rmem10_RID;
+  (* RS_HS = "m_axi_rmem10_R.data" *)input m_axi_rmem10_RLAST;
+  (* RS_HS = "m_axi_rmem10_R.ready" *)output m_axi_rmem10_RREADY;
+  (* RS_HS = "m_axi_rmem10_R.data" *)input [1:0] m_axi_rmem10_RRESP;
+  (* RS_HS = "m_axi_rmem10_R.valid" *)input m_axi_rmem10_RVALID;
+  (* RS_HS = "m_axi_rmem10_W.data" *)output [511:0] m_axi_rmem10_WDATA;
+  (* RS_HS = "m_axi_rmem10_W.data" *)output m_axi_rmem10_WLAST;
+  (* RS_HS = "m_axi_rmem10_W.ready" *)input m_axi_rmem10_WREADY;
+  (* RS_HS = "m_axi_rmem10_W.data" *)output [63:0] m_axi_rmem10_WSTRB;
+  (* RS_HS = "m_axi_rmem10_W.valid" *)output m_axi_rmem10_WVALID;
+  (* RS_HS = "m_axi_rmem11_AR.data" *)output [63:0] m_axi_rmem11_ARADDR;
+  (* RS_HS = "m_axi_rmem11_AR.data" *)output [1:0] m_axi_rmem11_ARBURST;
+  (* RS_HS = "m_axi_rmem11_AR.data" *)output [3:0] m_axi_rmem11_ARCACHE;
+  (* RS_HS = "m_axi_rmem11_AR.data" *)output [1:0] m_axi_rmem11_ARID;
+  (* RS_HS = "m_axi_rmem11_AR.data" *)output [7:0] m_axi_rmem11_ARLEN;
+  (* RS_HS = "m_axi_rmem11_AR.data" *)output m_axi_rmem11_ARLOCK;
+  (* RS_HS = "m_axi_rmem11_AR.data" *)output [2:0] m_axi_rmem11_ARPROT;
+  (* RS_HS = "m_axi_rmem11_AR.data" *)output [3:0] m_axi_rmem11_ARQOS;
+  (* RS_HS = "m_axi_rmem11_AR.ready" *)input m_axi_rmem11_ARREADY;
+  (* RS_HS = "m_axi_rmem11_AR.data" *)output [2:0] m_axi_rmem11_ARSIZE;
+  (* RS_HS = "m_axi_rmem11_AR.valid" *)output m_axi_rmem11_ARVALID;
+  (* RS_HS = "m_axi_rmem11_AW.data" *)output [63:0] m_axi_rmem11_AWADDR;
+  (* RS_HS = "m_axi_rmem11_AW.data" *)output [1:0] m_axi_rmem11_AWBURST;
+  (* RS_HS = "m_axi_rmem11_AW.data" *)output [3:0] m_axi_rmem11_AWCACHE;
+  (* RS_HS = "m_axi_rmem11_AW.data" *)output [1:0] m_axi_rmem11_AWID;
+  (* RS_HS = "m_axi_rmem11_AW.data" *)output [7:0] m_axi_rmem11_AWLEN;
+  (* RS_HS = "m_axi_rmem11_AW.data" *)output m_axi_rmem11_AWLOCK;
+  (* RS_HS = "m_axi_rmem11_AW.data" *)output [2:0] m_axi_rmem11_AWPROT;
+  (* RS_HS = "m_axi_rmem11_AW.data" *)output [3:0] m_axi_rmem11_AWQOS;
+  (* RS_HS = "m_axi_rmem11_AW.ready" *)input m_axi_rmem11_AWREADY;
+  (* RS_HS = "m_axi_rmem11_AW.data" *)output [2:0] m_axi_rmem11_AWSIZE;
+  (* RS_HS = "m_axi_rmem11_AW.valid" *)output m_axi_rmem11_AWVALID;
+  (* RS_HS = "m_axi_rmem11_B.data" *)input [1:0] m_axi_rmem11_BID;
+  (* RS_HS = "m_axi_rmem11_B.ready" *)output m_axi_rmem11_BREADY;
+  (* RS_HS = "m_axi_rmem11_B.data" *)input [1:0] m_axi_rmem11_BRESP;
+  (* RS_HS = "m_axi_rmem11_B.valid" *)input m_axi_rmem11_BVALID;
+  (* RS_HS = "m_axi_rmem11_R.data" *)input [511:0] m_axi_rmem11_RDATA;
+  (* RS_HS = "m_axi_rmem11_R.data" *)input [1:0] m_axi_rmem11_RID;
+  (* RS_HS = "m_axi_rmem11_R.data" *)input m_axi_rmem11_RLAST;
+  (* RS_HS = "m_axi_rmem11_R.ready" *)output m_axi_rmem11_RREADY;
+  (* RS_HS = "m_axi_rmem11_R.data" *)input [1:0] m_axi_rmem11_RRESP;
+  (* RS_HS = "m_axi_rmem11_R.valid" *)input m_axi_rmem11_RVALID;
+  (* RS_HS = "m_axi_rmem11_W.data" *)output [511:0] m_axi_rmem11_WDATA;
+  (* RS_HS = "m_axi_rmem11_W.data" *)output m_axi_rmem11_WLAST;
+  (* RS_HS = "m_axi_rmem11_W.ready" *)input m_axi_rmem11_WREADY;
+  (* RS_HS = "m_axi_rmem11_W.data" *)output [63:0] m_axi_rmem11_WSTRB;
+  (* RS_HS = "m_axi_rmem11_W.valid" *)output m_axi_rmem11_WVALID;
+  (* RS_HS = "m_axi_rmem12_AR.data" *)output [63:0] m_axi_rmem12_ARADDR;
+  (* RS_HS = "m_axi_rmem12_AR.data" *)output [1:0] m_axi_rmem12_ARBURST;
+  (* RS_HS = "m_axi_rmem12_AR.data" *)output [3:0] m_axi_rmem12_ARCACHE;
+  (* RS_HS = "m_axi_rmem12_AR.data" *)output [1:0] m_axi_rmem12_ARID;
+  (* RS_HS = "m_axi_rmem12_AR.data" *)output [7:0] m_axi_rmem12_ARLEN;
+  (* RS_HS = "m_axi_rmem12_AR.data" *)output m_axi_rmem12_ARLOCK;
+  (* RS_HS = "m_axi_rmem12_AR.data" *)output [2:0] m_axi_rmem12_ARPROT;
+  (* RS_HS = "m_axi_rmem12_AR.data" *)output [3:0] m_axi_rmem12_ARQOS;
+  (* RS_HS = "m_axi_rmem12_AR.ready" *)input m_axi_rmem12_ARREADY;
+  (* RS_HS = "m_axi_rmem12_AR.data" *)output [2:0] m_axi_rmem12_ARSIZE;
+  (* RS_HS = "m_axi_rmem12_AR.valid" *)output m_axi_rmem12_ARVALID;
+  (* RS_HS = "m_axi_rmem12_AW.data" *)output [63:0] m_axi_rmem12_AWADDR;
+  (* RS_HS = "m_axi_rmem12_AW.data" *)output [1:0] m_axi_rmem12_AWBURST;
+  (* RS_HS = "m_axi_rmem12_AW.data" *)output [3:0] m_axi_rmem12_AWCACHE;
+  (* RS_HS = "m_axi_rmem12_AW.data" *)output [1:0] m_axi_rmem12_AWID;
+  (* RS_HS = "m_axi_rmem12_AW.data" *)output [7:0] m_axi_rmem12_AWLEN;
+  (* RS_HS = "m_axi_rmem12_AW.data" *)output m_axi_rmem12_AWLOCK;
+  (* RS_HS = "m_axi_rmem12_AW.data" *)output [2:0] m_axi_rmem12_AWPROT;
+  (* RS_HS = "m_axi_rmem12_AW.data" *)output [3:0] m_axi_rmem12_AWQOS;
+  (* RS_HS = "m_axi_rmem12_AW.ready" *)input m_axi_rmem12_AWREADY;
+  (* RS_HS = "m_axi_rmem12_AW.data" *)output [2:0] m_axi_rmem12_AWSIZE;
+  (* RS_HS = "m_axi_rmem12_AW.valid" *)output m_axi_rmem12_AWVALID;
+  (* RS_HS = "m_axi_rmem12_B.data" *)input [1:0] m_axi_rmem12_BID;
+  (* RS_HS = "m_axi_rmem12_B.ready" *)output m_axi_rmem12_BREADY;
+  (* RS_HS = "m_axi_rmem12_B.data" *)input [1:0] m_axi_rmem12_BRESP;
+  (* RS_HS = "m_axi_rmem12_B.valid" *)input m_axi_rmem12_BVALID;
+  (* RS_HS = "m_axi_rmem12_R.data" *)input [511:0] m_axi_rmem12_RDATA;
+  (* RS_HS = "m_axi_rmem12_R.data" *)input [1:0] m_axi_rmem12_RID;
+  (* RS_HS = "m_axi_rmem12_R.data" *)input m_axi_rmem12_RLAST;
+  (* RS_HS = "m_axi_rmem12_R.ready" *)output m_axi_rmem12_RREADY;
+  (* RS_HS = "m_axi_rmem12_R.data" *)input [1:0] m_axi_rmem12_RRESP;
+  (* RS_HS = "m_axi_rmem12_R.valid" *)input m_axi_rmem12_RVALID;
+  (* RS_HS = "m_axi_rmem12_W.data" *)output [511:0] m_axi_rmem12_WDATA;
+  (* RS_HS = "m_axi_rmem12_W.data" *)output m_axi_rmem12_WLAST;
+  (* RS_HS = "m_axi_rmem12_W.ready" *)input m_axi_rmem12_WREADY;
+  (* RS_HS = "m_axi_rmem12_W.data" *)output [63:0] m_axi_rmem12_WSTRB;
+  (* RS_HS = "m_axi_rmem12_W.valid" *)output m_axi_rmem12_WVALID;
+  (* RS_HS = "m_axi_rmem13_AR.data" *)output [63:0] m_axi_rmem13_ARADDR;
+  (* RS_HS = "m_axi_rmem13_AR.data" *)output [1:0] m_axi_rmem13_ARBURST;
+  (* RS_HS = "m_axi_rmem13_AR.data" *)output [3:0] m_axi_rmem13_ARCACHE;
+  (* RS_HS = "m_axi_rmem13_AR.data" *)output [1:0] m_axi_rmem13_ARID;
+  (* RS_HS = "m_axi_rmem13_AR.data" *)output [7:0] m_axi_rmem13_ARLEN;
+  (* RS_HS = "m_axi_rmem13_AR.data" *)output m_axi_rmem13_ARLOCK;
+  (* RS_HS = "m_axi_rmem13_AR.data" *)output [2:0] m_axi_rmem13_ARPROT;
+  (* RS_HS = "m_axi_rmem13_AR.data" *)output [3:0] m_axi_rmem13_ARQOS;
+  (* RS_HS = "m_axi_rmem13_AR.ready" *)input m_axi_rmem13_ARREADY;
+  (* RS_HS = "m_axi_rmem13_AR.data" *)output [2:0] m_axi_rmem13_ARSIZE;
+  (* RS_HS = "m_axi_rmem13_AR.valid" *)output m_axi_rmem13_ARVALID;
+  (* RS_HS = "m_axi_rmem13_AW.data" *)output [63:0] m_axi_rmem13_AWADDR;
+  (* RS_HS = "m_axi_rmem13_AW.data" *)output [1:0] m_axi_rmem13_AWBURST;
+  (* RS_HS = "m_axi_rmem13_AW.data" *)output [3:0] m_axi_rmem13_AWCACHE;
+  (* RS_HS = "m_axi_rmem13_AW.data" *)output [1:0] m_axi_rmem13_AWID;
+  (* RS_HS = "m_axi_rmem13_AW.data" *)output [7:0] m_axi_rmem13_AWLEN;
+  (* RS_HS = "m_axi_rmem13_AW.data" *)output m_axi_rmem13_AWLOCK;
+  (* RS_HS = "m_axi_rmem13_AW.data" *)output [2:0] m_axi_rmem13_AWPROT;
+  (* RS_HS = "m_axi_rmem13_AW.data" *)output [3:0] m_axi_rmem13_AWQOS;
+  (* RS_HS = "m_axi_rmem13_AW.ready" *)input m_axi_rmem13_AWREADY;
+  (* RS_HS = "m_axi_rmem13_AW.data" *)output [2:0] m_axi_rmem13_AWSIZE;
+  (* RS_HS = "m_axi_rmem13_AW.valid" *)output m_axi_rmem13_AWVALID;
+  (* RS_HS = "m_axi_rmem13_B.data" *)input [1:0] m_axi_rmem13_BID;
+  (* RS_HS = "m_axi_rmem13_B.ready" *)output m_axi_rmem13_BREADY;
+  (* RS_HS = "m_axi_rmem13_B.data" *)input [1:0] m_axi_rmem13_BRESP;
+  (* RS_HS = "m_axi_rmem13_B.valid" *)input m_axi_rmem13_BVALID;
+  (* RS_HS = "m_axi_rmem13_R.data" *)input [511:0] m_axi_rmem13_RDATA;
+  (* RS_HS = "m_axi_rmem13_R.data" *)input [1:0] m_axi_rmem13_RID;
+  (* RS_HS = "m_axi_rmem13_R.data" *)input m_axi_rmem13_RLAST;
+  (* RS_HS = "m_axi_rmem13_R.ready" *)output m_axi_rmem13_RREADY;
+  (* RS_HS = "m_axi_rmem13_R.data" *)input [1:0] m_axi_rmem13_RRESP;
+  (* RS_HS = "m_axi_rmem13_R.valid" *)input m_axi_rmem13_RVALID;
+  (* RS_HS = "m_axi_rmem13_W.data" *)output [511:0] m_axi_rmem13_WDATA;
+  (* RS_HS = "m_axi_rmem13_W.data" *)output m_axi_rmem13_WLAST;
+  (* RS_HS = "m_axi_rmem13_W.ready" *)input m_axi_rmem13_WREADY;
+  (* RS_HS = "m_axi_rmem13_W.data" *)output [63:0] m_axi_rmem13_WSTRB;
+  (* RS_HS = "m_axi_rmem13_W.valid" *)output m_axi_rmem13_WVALID;
+  (* RS_HS = "m_axi_rmem14_AR.data" *)output [63:0] m_axi_rmem14_ARADDR;
+  (* RS_HS = "m_axi_rmem14_AR.data" *)output [1:0] m_axi_rmem14_ARBURST;
+  (* RS_HS = "m_axi_rmem14_AR.data" *)output [3:0] m_axi_rmem14_ARCACHE;
+  (* RS_HS = "m_axi_rmem14_AR.data" *)output [1:0] m_axi_rmem14_ARID;
+  (* RS_HS = "m_axi_rmem14_AR.data" *)output [7:0] m_axi_rmem14_ARLEN;
+  (* RS_HS = "m_axi_rmem14_AR.data" *)output m_axi_rmem14_ARLOCK;
+  (* RS_HS = "m_axi_rmem14_AR.data" *)output [2:0] m_axi_rmem14_ARPROT;
+  (* RS_HS = "m_axi_rmem14_AR.data" *)output [3:0] m_axi_rmem14_ARQOS;
+  (* RS_HS = "m_axi_rmem14_AR.ready" *)input m_axi_rmem14_ARREADY;
+  (* RS_HS = "m_axi_rmem14_AR.data" *)output [2:0] m_axi_rmem14_ARSIZE;
+  (* RS_HS = "m_axi_rmem14_AR.valid" *)output m_axi_rmem14_ARVALID;
+  (* RS_HS = "m_axi_rmem14_AW.data" *)output [63:0] m_axi_rmem14_AWADDR;
+  (* RS_HS = "m_axi_rmem14_AW.data" *)output [1:0] m_axi_rmem14_AWBURST;
+  (* RS_HS = "m_axi_rmem14_AW.data" *)output [3:0] m_axi_rmem14_AWCACHE;
+  (* RS_HS = "m_axi_rmem14_AW.data" *)output [1:0] m_axi_rmem14_AWID;
+  (* RS_HS = "m_axi_rmem14_AW.data" *)output [7:0] m_axi_rmem14_AWLEN;
+  (* RS_HS = "m_axi_rmem14_AW.data" *)output m_axi_rmem14_AWLOCK;
+  (* RS_HS = "m_axi_rmem14_AW.data" *)output [2:0] m_axi_rmem14_AWPROT;
+  (* RS_HS = "m_axi_rmem14_AW.data" *)output [3:0] m_axi_rmem14_AWQOS;
+  (* RS_HS = "m_axi_rmem14_AW.ready" *)input m_axi_rmem14_AWREADY;
+  (* RS_HS = "m_axi_rmem14_AW.data" *)output [2:0] m_axi_rmem14_AWSIZE;
+  (* RS_HS = "m_axi_rmem14_AW.valid" *)output m_axi_rmem14_AWVALID;
+  (* RS_HS = "m_axi_rmem14_B.data" *)input [1:0] m_axi_rmem14_BID;
+  (* RS_HS = "m_axi_rmem14_B.ready" *)output m_axi_rmem14_BREADY;
+  (* RS_HS = "m_axi_rmem14_B.data" *)input [1:0] m_axi_rmem14_BRESP;
+  (* RS_HS = "m_axi_rmem14_B.valid" *)input m_axi_rmem14_BVALID;
+  (* RS_HS = "m_axi_rmem14_R.data" *)input [511:0] m_axi_rmem14_RDATA;
+  (* RS_HS = "m_axi_rmem14_R.data" *)input [1:0] m_axi_rmem14_RID;
+  (* RS_HS = "m_axi_rmem14_R.data" *)input m_axi_rmem14_RLAST;
+  (* RS_HS = "m_axi_rmem14_R.ready" *)output m_axi_rmem14_RREADY;
+  (* RS_HS = "m_axi_rmem14_R.data" *)input [1:0] m_axi_rmem14_RRESP;
+  (* RS_HS = "m_axi_rmem14_R.valid" *)input m_axi_rmem14_RVALID;
+  (* RS_HS = "m_axi_rmem14_W.data" *)output [511:0] m_axi_rmem14_WDATA;
+  (* RS_HS = "m_axi_rmem14_W.data" *)output m_axi_rmem14_WLAST;
+  (* RS_HS = "m_axi_rmem14_W.ready" *)input m_axi_rmem14_WREADY;
+  (* RS_HS = "m_axi_rmem14_W.data" *)output [63:0] m_axi_rmem14_WSTRB;
+  (* RS_HS = "m_axi_rmem14_W.valid" *)output m_axi_rmem14_WVALID;
+  (* RS_HS = "m_axi_rmem15_AR.data" *)output [63:0] m_axi_rmem15_ARADDR;
+  (* RS_HS = "m_axi_rmem15_AR.data" *)output [1:0] m_axi_rmem15_ARBURST;
+  (* RS_HS = "m_axi_rmem15_AR.data" *)output [3:0] m_axi_rmem15_ARCACHE;
+  (* RS_HS = "m_axi_rmem15_AR.data" *)output [1:0] m_axi_rmem15_ARID;
+  (* RS_HS = "m_axi_rmem15_AR.data" *)output [7:0] m_axi_rmem15_ARLEN;
+  (* RS_HS = "m_axi_rmem15_AR.data" *)output m_axi_rmem15_ARLOCK;
+  (* RS_HS = "m_axi_rmem15_AR.data" *)output [2:0] m_axi_rmem15_ARPROT;
+  (* RS_HS = "m_axi_rmem15_AR.data" *)output [3:0] m_axi_rmem15_ARQOS;
+  (* RS_HS = "m_axi_rmem15_AR.ready" *)input m_axi_rmem15_ARREADY;
+  (* RS_HS = "m_axi_rmem15_AR.data" *)output [2:0] m_axi_rmem15_ARSIZE;
+  (* RS_HS = "m_axi_rmem15_AR.valid" *)output m_axi_rmem15_ARVALID;
+  (* RS_HS = "m_axi_rmem15_AW.data" *)output [63:0] m_axi_rmem15_AWADDR;
+  (* RS_HS = "m_axi_rmem15_AW.data" *)output [1:0] m_axi_rmem15_AWBURST;
+  (* RS_HS = "m_axi_rmem15_AW.data" *)output [3:0] m_axi_rmem15_AWCACHE;
+  (* RS_HS = "m_axi_rmem15_AW.data" *)output [1:0] m_axi_rmem15_AWID;
+  (* RS_HS = "m_axi_rmem15_AW.data" *)output [7:0] m_axi_rmem15_AWLEN;
+  (* RS_HS = "m_axi_rmem15_AW.data" *)output m_axi_rmem15_AWLOCK;
+  (* RS_HS = "m_axi_rmem15_AW.data" *)output [2:0] m_axi_rmem15_AWPROT;
+  (* RS_HS = "m_axi_rmem15_AW.data" *)output [3:0] m_axi_rmem15_AWQOS;
+  (* RS_HS = "m_axi_rmem15_AW.ready" *)input m_axi_rmem15_AWREADY;
+  (* RS_HS = "m_axi_rmem15_AW.data" *)output [2:0] m_axi_rmem15_AWSIZE;
+  (* RS_HS = "m_axi_rmem15_AW.valid" *)output m_axi_rmem15_AWVALID;
+  (* RS_HS = "m_axi_rmem15_B.data" *)input [1:0] m_axi_rmem15_BID;
+  (* RS_HS = "m_axi_rmem15_B.ready" *)output m_axi_rmem15_BREADY;
+  (* RS_HS = "m_axi_rmem15_B.data" *)input [1:0] m_axi_rmem15_BRESP;
+  (* RS_HS = "m_axi_rmem15_B.valid" *)input m_axi_rmem15_BVALID;
+  (* RS_HS = "m_axi_rmem15_R.data" *)input [511:0] m_axi_rmem15_RDATA;
+  (* RS_HS = "m_axi_rmem15_R.data" *)input [1:0] m_axi_rmem15_RID;
+  (* RS_HS = "m_axi_rmem15_R.data" *)input m_axi_rmem15_RLAST;
+  (* RS_HS = "m_axi_rmem15_R.ready" *)output m_axi_rmem15_RREADY;
+  (* RS_HS = "m_axi_rmem15_R.data" *)input [1:0] m_axi_rmem15_RRESP;
+  (* RS_HS = "m_axi_rmem15_R.valid" *)input m_axi_rmem15_RVALID;
+  (* RS_HS = "m_axi_rmem15_W.data" *)output [511:0] m_axi_rmem15_WDATA;
+  (* RS_HS = "m_axi_rmem15_W.data" *)output m_axi_rmem15_WLAST;
+  (* RS_HS = "m_axi_rmem15_W.ready" *)input m_axi_rmem15_WREADY;
+  (* RS_HS = "m_axi_rmem15_W.data" *)output [63:0] m_axi_rmem15_WSTRB;
+  (* RS_HS = "m_axi_rmem15_W.valid" *)output m_axi_rmem15_WVALID;
+  (* RS_HS = "m_axi_rmem16_AR.data" *)output [63:0] m_axi_rmem16_ARADDR;
+  (* RS_HS = "m_axi_rmem16_AR.data" *)output [1:0] m_axi_rmem16_ARBURST;
+  (* RS_HS = "m_axi_rmem16_AR.data" *)output [3:0] m_axi_rmem16_ARCACHE;
+  (* RS_HS = "m_axi_rmem16_AR.data" *)output [1:0] m_axi_rmem16_ARID;
+  (* RS_HS = "m_axi_rmem16_AR.data" *)output [7:0] m_axi_rmem16_ARLEN;
+  (* RS_HS = "m_axi_rmem16_AR.data" *)output m_axi_rmem16_ARLOCK;
+  (* RS_HS = "m_axi_rmem16_AR.data" *)output [2:0] m_axi_rmem16_ARPROT;
+  (* RS_HS = "m_axi_rmem16_AR.data" *)output [3:0] m_axi_rmem16_ARQOS;
+  (* RS_HS = "m_axi_rmem16_AR.ready" *)input m_axi_rmem16_ARREADY;
+  (* RS_HS = "m_axi_rmem16_AR.data" *)output [2:0] m_axi_rmem16_ARSIZE;
+  (* RS_HS = "m_axi_rmem16_AR.valid" *)output m_axi_rmem16_ARVALID;
+  (* RS_HS = "m_axi_rmem16_AW.data" *)output [63:0] m_axi_rmem16_AWADDR;
+  (* RS_HS = "m_axi_rmem16_AW.data" *)output [1:0] m_axi_rmem16_AWBURST;
+  (* RS_HS = "m_axi_rmem16_AW.data" *)output [3:0] m_axi_rmem16_AWCACHE;
+  (* RS_HS = "m_axi_rmem16_AW.data" *)output [1:0] m_axi_rmem16_AWID;
+  (* RS_HS = "m_axi_rmem16_AW.data" *)output [7:0] m_axi_rmem16_AWLEN;
+  (* RS_HS = "m_axi_rmem16_AW.data" *)output m_axi_rmem16_AWLOCK;
+  (* RS_HS = "m_axi_rmem16_AW.data" *)output [2:0] m_axi_rmem16_AWPROT;
+  (* RS_HS = "m_axi_rmem16_AW.data" *)output [3:0] m_axi_rmem16_AWQOS;
+  (* RS_HS = "m_axi_rmem16_AW.ready" *)input m_axi_rmem16_AWREADY;
+  (* RS_HS = "m_axi_rmem16_AW.data" *)output [2:0] m_axi_rmem16_AWSIZE;
+  (* RS_HS = "m_axi_rmem16_AW.valid" *)output m_axi_rmem16_AWVALID;
+  (* RS_HS = "m_axi_rmem16_B.data" *)input [1:0] m_axi_rmem16_BID;
+  (* RS_HS = "m_axi_rmem16_B.ready" *)output m_axi_rmem16_BREADY;
+  (* RS_HS = "m_axi_rmem16_B.data" *)input [1:0] m_axi_rmem16_BRESP;
+  (* RS_HS = "m_axi_rmem16_B.valid" *)input m_axi_rmem16_BVALID;
+  (* RS_HS = "m_axi_rmem16_R.data" *)input [511:0] m_axi_rmem16_RDATA;
+  (* RS_HS = "m_axi_rmem16_R.data" *)input [1:0] m_axi_rmem16_RID;
+  (* RS_HS = "m_axi_rmem16_R.data" *)input m_axi_rmem16_RLAST;
+  (* RS_HS = "m_axi_rmem16_R.ready" *)output m_axi_rmem16_RREADY;
+  (* RS_HS = "m_axi_rmem16_R.data" *)input [1:0] m_axi_rmem16_RRESP;
+  (* RS_HS = "m_axi_rmem16_R.valid" *)input m_axi_rmem16_RVALID;
+  (* RS_HS = "m_axi_rmem16_W.data" *)output [511:0] m_axi_rmem16_WDATA;
+  (* RS_HS = "m_axi_rmem16_W.data" *)output m_axi_rmem16_WLAST;
+  (* RS_HS = "m_axi_rmem16_W.ready" *)input m_axi_rmem16_WREADY;
+  (* RS_HS = "m_axi_rmem16_W.data" *)output [63:0] m_axi_rmem16_WSTRB;
+  (* RS_HS = "m_axi_rmem16_W.valid" *)output m_axi_rmem16_WVALID;
+  (* RS_HS = "m_axi_rmem17_AR.data" *)output [63:0] m_axi_rmem17_ARADDR;
+  (* RS_HS = "m_axi_rmem17_AR.data" *)output [1:0] m_axi_rmem17_ARBURST;
+  (* RS_HS = "m_axi_rmem17_AR.data" *)output [3:0] m_axi_rmem17_ARCACHE;
+  (* RS_HS = "m_axi_rmem17_AR.data" *)output [1:0] m_axi_rmem17_ARID;
+  (* RS_HS = "m_axi_rmem17_AR.data" *)output [7:0] m_axi_rmem17_ARLEN;
+  (* RS_HS = "m_axi_rmem17_AR.data" *)output m_axi_rmem17_ARLOCK;
+  (* RS_HS = "m_axi_rmem17_AR.data" *)output [2:0] m_axi_rmem17_ARPROT;
+  (* RS_HS = "m_axi_rmem17_AR.data" *)output [3:0] m_axi_rmem17_ARQOS;
+  (* RS_HS = "m_axi_rmem17_AR.ready" *)input m_axi_rmem17_ARREADY;
+  (* RS_HS = "m_axi_rmem17_AR.data" *)output [2:0] m_axi_rmem17_ARSIZE;
+  (* RS_HS = "m_axi_rmem17_AR.valid" *)output m_axi_rmem17_ARVALID;
+  (* RS_HS = "m_axi_rmem17_AW.data" *)output [63:0] m_axi_rmem17_AWADDR;
+  (* RS_HS = "m_axi_rmem17_AW.data" *)output [1:0] m_axi_rmem17_AWBURST;
+  (* RS_HS = "m_axi_rmem17_AW.data" *)output [3:0] m_axi_rmem17_AWCACHE;
+  (* RS_HS = "m_axi_rmem17_AW.data" *)output [1:0] m_axi_rmem17_AWID;
+  (* RS_HS = "m_axi_rmem17_AW.data" *)output [7:0] m_axi_rmem17_AWLEN;
+  (* RS_HS = "m_axi_rmem17_AW.data" *)output m_axi_rmem17_AWLOCK;
+  (* RS_HS = "m_axi_rmem17_AW.data" *)output [2:0] m_axi_rmem17_AWPROT;
+  (* RS_HS = "m_axi_rmem17_AW.data" *)output [3:0] m_axi_rmem17_AWQOS;
+  (* RS_HS = "m_axi_rmem17_AW.ready" *)input m_axi_rmem17_AWREADY;
+  (* RS_HS = "m_axi_rmem17_AW.data" *)output [2:0] m_axi_rmem17_AWSIZE;
+  (* RS_HS = "m_axi_rmem17_AW.valid" *)output m_axi_rmem17_AWVALID;
+  (* RS_HS = "m_axi_rmem17_B.data" *)input [1:0] m_axi_rmem17_BID;
+  (* RS_HS = "m_axi_rmem17_B.ready" *)output m_axi_rmem17_BREADY;
+  (* RS_HS = "m_axi_rmem17_B.data" *)input [1:0] m_axi_rmem17_BRESP;
+  (* RS_HS = "m_axi_rmem17_B.valid" *)input m_axi_rmem17_BVALID;
+  (* RS_HS = "m_axi_rmem17_R.data" *)input [511:0] m_axi_rmem17_RDATA;
+  (* RS_HS = "m_axi_rmem17_R.data" *)input [1:0] m_axi_rmem17_RID;
+  (* RS_HS = "m_axi_rmem17_R.data" *)input m_axi_rmem17_RLAST;
+  (* RS_HS = "m_axi_rmem17_R.ready" *)output m_axi_rmem17_RREADY;
+  (* RS_HS = "m_axi_rmem17_R.data" *)input [1:0] m_axi_rmem17_RRESP;
+  (* RS_HS = "m_axi_rmem17_R.valid" *)input m_axi_rmem17_RVALID;
+  (* RS_HS = "m_axi_rmem17_W.data" *)output [511:0] m_axi_rmem17_WDATA;
+  (* RS_HS = "m_axi_rmem17_W.data" *)output m_axi_rmem17_WLAST;
+  (* RS_HS = "m_axi_rmem17_W.ready" *)input m_axi_rmem17_WREADY;
+  (* RS_HS = "m_axi_rmem17_W.data" *)output [63:0] m_axi_rmem17_WSTRB;
+  (* RS_HS = "m_axi_rmem17_W.valid" *)output m_axi_rmem17_WVALID;
+  (* RS_HS = "m_axi_rmem18_AR.data" *)output [63:0] m_axi_rmem18_ARADDR;
+  (* RS_HS = "m_axi_rmem18_AR.data" *)output [1:0] m_axi_rmem18_ARBURST;
+  (* RS_HS = "m_axi_rmem18_AR.data" *)output [3:0] m_axi_rmem18_ARCACHE;
+  (* RS_HS = "m_axi_rmem18_AR.data" *)output [1:0] m_axi_rmem18_ARID;
+  (* RS_HS = "m_axi_rmem18_AR.data" *)output [7:0] m_axi_rmem18_ARLEN;
+  (* RS_HS = "m_axi_rmem18_AR.data" *)output m_axi_rmem18_ARLOCK;
+  (* RS_HS = "m_axi_rmem18_AR.data" *)output [2:0] m_axi_rmem18_ARPROT;
+  (* RS_HS = "m_axi_rmem18_AR.data" *)output [3:0] m_axi_rmem18_ARQOS;
+  (* RS_HS = "m_axi_rmem18_AR.ready" *)input m_axi_rmem18_ARREADY;
+  (* RS_HS = "m_axi_rmem18_AR.data" *)output [2:0] m_axi_rmem18_ARSIZE;
+  (* RS_HS = "m_axi_rmem18_AR.valid" *)output m_axi_rmem18_ARVALID;
+  (* RS_HS = "m_axi_rmem18_AW.data" *)output [63:0] m_axi_rmem18_AWADDR;
+  (* RS_HS = "m_axi_rmem18_AW.data" *)output [1:0] m_axi_rmem18_AWBURST;
+  (* RS_HS = "m_axi_rmem18_AW.data" *)output [3:0] m_axi_rmem18_AWCACHE;
+  (* RS_HS = "m_axi_rmem18_AW.data" *)output [1:0] m_axi_rmem18_AWID;
+  (* RS_HS = "m_axi_rmem18_AW.data" *)output [7:0] m_axi_rmem18_AWLEN;
+  (* RS_HS = "m_axi_rmem18_AW.data" *)output m_axi_rmem18_AWLOCK;
+  (* RS_HS = "m_axi_rmem18_AW.data" *)output [2:0] m_axi_rmem18_AWPROT;
+  (* RS_HS = "m_axi_rmem18_AW.data" *)output [3:0] m_axi_rmem18_AWQOS;
+  (* RS_HS = "m_axi_rmem18_AW.ready" *)input m_axi_rmem18_AWREADY;
+  (* RS_HS = "m_axi_rmem18_AW.data" *)output [2:0] m_axi_rmem18_AWSIZE;
+  (* RS_HS = "m_axi_rmem18_AW.valid" *)output m_axi_rmem18_AWVALID;
+  (* RS_HS = "m_axi_rmem18_B.data" *)input [1:0] m_axi_rmem18_BID;
+  (* RS_HS = "m_axi_rmem18_B.ready" *)output m_axi_rmem18_BREADY;
+  (* RS_HS = "m_axi_rmem18_B.data" *)input [1:0] m_axi_rmem18_BRESP;
+  (* RS_HS = "m_axi_rmem18_B.valid" *)input m_axi_rmem18_BVALID;
+  (* RS_HS = "m_axi_rmem18_R.data" *)input [511:0] m_axi_rmem18_RDATA;
+  (* RS_HS = "m_axi_rmem18_R.data" *)input [1:0] m_axi_rmem18_RID;
+  (* RS_HS = "m_axi_rmem18_R.data" *)input m_axi_rmem18_RLAST;
+  (* RS_HS = "m_axi_rmem18_R.ready" *)output m_axi_rmem18_RREADY;
+  (* RS_HS = "m_axi_rmem18_R.data" *)input [1:0] m_axi_rmem18_RRESP;
+  (* RS_HS = "m_axi_rmem18_R.valid" *)input m_axi_rmem18_RVALID;
+  (* RS_HS = "m_axi_rmem18_W.data" *)output [511:0] m_axi_rmem18_WDATA;
+  (* RS_HS = "m_axi_rmem18_W.data" *)output m_axi_rmem18_WLAST;
+  (* RS_HS = "m_axi_rmem18_W.ready" *)input m_axi_rmem18_WREADY;
+  (* RS_HS = "m_axi_rmem18_W.data" *)output [63:0] m_axi_rmem18_WSTRB;
+  (* RS_HS = "m_axi_rmem18_W.valid" *)output m_axi_rmem18_WVALID;
+  (* RS_HS = "m_axi_rmem19_AR.data" *)output [63:0] m_axi_rmem19_ARADDR;
+  (* RS_HS = "m_axi_rmem19_AR.data" *)output [1:0] m_axi_rmem19_ARBURST;
+  (* RS_HS = "m_axi_rmem19_AR.data" *)output [3:0] m_axi_rmem19_ARCACHE;
+  (* RS_HS = "m_axi_rmem19_AR.data" *)output [1:0] m_axi_rmem19_ARID;
+  (* RS_HS = "m_axi_rmem19_AR.data" *)output [7:0] m_axi_rmem19_ARLEN;
+  (* RS_HS = "m_axi_rmem19_AR.data" *)output m_axi_rmem19_ARLOCK;
+  (* RS_HS = "m_axi_rmem19_AR.data" *)output [2:0] m_axi_rmem19_ARPROT;
+  (* RS_HS = "m_axi_rmem19_AR.data" *)output [3:0] m_axi_rmem19_ARQOS;
+  (* RS_HS = "m_axi_rmem19_AR.ready" *)input m_axi_rmem19_ARREADY;
+  (* RS_HS = "m_axi_rmem19_AR.data" *)output [2:0] m_axi_rmem19_ARSIZE;
+  (* RS_HS = "m_axi_rmem19_AR.valid" *)output m_axi_rmem19_ARVALID;
+  (* RS_HS = "m_axi_rmem19_AW.data" *)output [63:0] m_axi_rmem19_AWADDR;
+  (* RS_HS = "m_axi_rmem19_AW.data" *)output [1:0] m_axi_rmem19_AWBURST;
+  (* RS_HS = "m_axi_rmem19_AW.data" *)output [3:0] m_axi_rmem19_AWCACHE;
+  (* RS_HS = "m_axi_rmem19_AW.data" *)output [1:0] m_axi_rmem19_AWID;
+  (* RS_HS = "m_axi_rmem19_AW.data" *)output [7:0] m_axi_rmem19_AWLEN;
+  (* RS_HS = "m_axi_rmem19_AW.data" *)output m_axi_rmem19_AWLOCK;
+  (* RS_HS = "m_axi_rmem19_AW.data" *)output [2:0] m_axi_rmem19_AWPROT;
+  (* RS_HS = "m_axi_rmem19_AW.data" *)output [3:0] m_axi_rmem19_AWQOS;
+  (* RS_HS = "m_axi_rmem19_AW.ready" *)input m_axi_rmem19_AWREADY;
+  (* RS_HS = "m_axi_rmem19_AW.data" *)output [2:0] m_axi_rmem19_AWSIZE;
+  (* RS_HS = "m_axi_rmem19_AW.valid" *)output m_axi_rmem19_AWVALID;
+  (* RS_HS = "m_axi_rmem19_B.data" *)input [1:0] m_axi_rmem19_BID;
+  (* RS_HS = "m_axi_rmem19_B.ready" *)output m_axi_rmem19_BREADY;
+  (* RS_HS = "m_axi_rmem19_B.data" *)input [1:0] m_axi_rmem19_BRESP;
+  (* RS_HS = "m_axi_rmem19_B.valid" *)input m_axi_rmem19_BVALID;
+  (* RS_HS = "m_axi_rmem19_R.data" *)input [511:0] m_axi_rmem19_RDATA;
+  (* RS_HS = "m_axi_rmem19_R.data" *)input [1:0] m_axi_rmem19_RID;
+  (* RS_HS = "m_axi_rmem19_R.data" *)input m_axi_rmem19_RLAST;
+  (* RS_HS = "m_axi_rmem19_R.ready" *)output m_axi_rmem19_RREADY;
+  (* RS_HS = "m_axi_rmem19_R.data" *)input [1:0] m_axi_rmem19_RRESP;
+  (* RS_HS = "m_axi_rmem19_R.valid" *)input m_axi_rmem19_RVALID;
+  (* RS_HS = "m_axi_rmem19_W.data" *)output [511:0] m_axi_rmem19_WDATA;
+  (* RS_HS = "m_axi_rmem19_W.data" *)output m_axi_rmem19_WLAST;
+  (* RS_HS = "m_axi_rmem19_W.ready" *)input m_axi_rmem19_WREADY;
+  (* RS_HS = "m_axi_rmem19_W.data" *)output [63:0] m_axi_rmem19_WSTRB;
+  (* RS_HS = "m_axi_rmem19_W.valid" *)output m_axi_rmem19_WVALID;
+  (* RS_HS = "m_axi_rmem20_AR.data" *)output [63:0] m_axi_rmem20_ARADDR;
+  (* RS_HS = "m_axi_rmem20_AR.data" *)output [1:0] m_axi_rmem20_ARBURST;
+  (* RS_HS = "m_axi_rmem20_AR.data" *)output [3:0] m_axi_rmem20_ARCACHE;
+  (* RS_HS = "m_axi_rmem20_AR.data" *)output [1:0] m_axi_rmem20_ARID;
+  (* RS_HS = "m_axi_rmem20_AR.data" *)output [7:0] m_axi_rmem20_ARLEN;
+  (* RS_HS = "m_axi_rmem20_AR.data" *)output m_axi_rmem20_ARLOCK;
+  (* RS_HS = "m_axi_rmem20_AR.data" *)output [2:0] m_axi_rmem20_ARPROT;
+  (* RS_HS = "m_axi_rmem20_AR.data" *)output [3:0] m_axi_rmem20_ARQOS;
+  (* RS_HS = "m_axi_rmem20_AR.ready" *)input m_axi_rmem20_ARREADY;
+  (* RS_HS = "m_axi_rmem20_AR.data" *)output [2:0] m_axi_rmem20_ARSIZE;
+  (* RS_HS = "m_axi_rmem20_AR.valid" *)output m_axi_rmem20_ARVALID;
+  (* RS_HS = "m_axi_rmem20_AW.data" *)output [63:0] m_axi_rmem20_AWADDR;
+  (* RS_HS = "m_axi_rmem20_AW.data" *)output [1:0] m_axi_rmem20_AWBURST;
+  (* RS_HS = "m_axi_rmem20_AW.data" *)output [3:0] m_axi_rmem20_AWCACHE;
+  (* RS_HS = "m_axi_rmem20_AW.data" *)output [1:0] m_axi_rmem20_AWID;
+  (* RS_HS = "m_axi_rmem20_AW.data" *)output [7:0] m_axi_rmem20_AWLEN;
+  (* RS_HS = "m_axi_rmem20_AW.data" *)output m_axi_rmem20_AWLOCK;
+  (* RS_HS = "m_axi_rmem20_AW.data" *)output [2:0] m_axi_rmem20_AWPROT;
+  (* RS_HS = "m_axi_rmem20_AW.data" *)output [3:0] m_axi_rmem20_AWQOS;
+  (* RS_HS = "m_axi_rmem20_AW.ready" *)input m_axi_rmem20_AWREADY;
+  (* RS_HS = "m_axi_rmem20_AW.data" *)output [2:0] m_axi_rmem20_AWSIZE;
+  (* RS_HS = "m_axi_rmem20_AW.valid" *)output m_axi_rmem20_AWVALID;
+  (* RS_HS = "m_axi_rmem20_B.data" *)input [1:0] m_axi_rmem20_BID;
+  (* RS_HS = "m_axi_rmem20_B.ready" *)output m_axi_rmem20_BREADY;
+  (* RS_HS = "m_axi_rmem20_B.data" *)input [1:0] m_axi_rmem20_BRESP;
+  (* RS_HS = "m_axi_rmem20_B.valid" *)input m_axi_rmem20_BVALID;
+  (* RS_HS = "m_axi_rmem20_R.data" *)input [511:0] m_axi_rmem20_RDATA;
+  (* RS_HS = "m_axi_rmem20_R.data" *)input [1:0] m_axi_rmem20_RID;
+  (* RS_HS = "m_axi_rmem20_R.data" *)input m_axi_rmem20_RLAST;
+  (* RS_HS = "m_axi_rmem20_R.ready" *)output m_axi_rmem20_RREADY;
+  (* RS_HS = "m_axi_rmem20_R.data" *)input [1:0] m_axi_rmem20_RRESP;
+  (* RS_HS = "m_axi_rmem20_R.valid" *)input m_axi_rmem20_RVALID;
+  (* RS_HS = "m_axi_rmem20_W.data" *)output [511:0] m_axi_rmem20_WDATA;
+  (* RS_HS = "m_axi_rmem20_W.data" *)output m_axi_rmem20_WLAST;
+  (* RS_HS = "m_axi_rmem20_W.ready" *)input m_axi_rmem20_WREADY;
+  (* RS_HS = "m_axi_rmem20_W.data" *)output [63:0] m_axi_rmem20_WSTRB;
+  (* RS_HS = "m_axi_rmem20_W.valid" *)output m_axi_rmem20_WVALID;
+  (* RS_HS = "m_axi_rmem21_AR.data" *)output [63:0] m_axi_rmem21_ARADDR;
+  (* RS_HS = "m_axi_rmem21_AR.data" *)output [1:0] m_axi_rmem21_ARBURST;
+  (* RS_HS = "m_axi_rmem21_AR.data" *)output [3:0] m_axi_rmem21_ARCACHE;
+  (* RS_HS = "m_axi_rmem21_AR.data" *)output [1:0] m_axi_rmem21_ARID;
+  (* RS_HS = "m_axi_rmem21_AR.data" *)output [7:0] m_axi_rmem21_ARLEN;
+  (* RS_HS = "m_axi_rmem21_AR.data" *)output m_axi_rmem21_ARLOCK;
+  (* RS_HS = "m_axi_rmem21_AR.data" *)output [2:0] m_axi_rmem21_ARPROT;
+  (* RS_HS = "m_axi_rmem21_AR.data" *)output [3:0] m_axi_rmem21_ARQOS;
+  (* RS_HS = "m_axi_rmem21_AR.ready" *)input m_axi_rmem21_ARREADY;
+  (* RS_HS = "m_axi_rmem21_AR.data" *)output [2:0] m_axi_rmem21_ARSIZE;
+  (* RS_HS = "m_axi_rmem21_AR.valid" *)output m_axi_rmem21_ARVALID;
+  (* RS_HS = "m_axi_rmem21_AW.data" *)output [63:0] m_axi_rmem21_AWADDR;
+  (* RS_HS = "m_axi_rmem21_AW.data" *)output [1:0] m_axi_rmem21_AWBURST;
+  (* RS_HS = "m_axi_rmem21_AW.data" *)output [3:0] m_axi_rmem21_AWCACHE;
+  (* RS_HS = "m_axi_rmem21_AW.data" *)output [1:0] m_axi_rmem21_AWID;
+  (* RS_HS = "m_axi_rmem21_AW.data" *)output [7:0] m_axi_rmem21_AWLEN;
+  (* RS_HS = "m_axi_rmem21_AW.data" *)output m_axi_rmem21_AWLOCK;
+  (* RS_HS = "m_axi_rmem21_AW.data" *)output [2:0] m_axi_rmem21_AWPROT;
+  (* RS_HS = "m_axi_rmem21_AW.data" *)output [3:0] m_axi_rmem21_AWQOS;
+  (* RS_HS = "m_axi_rmem21_AW.ready" *)input m_axi_rmem21_AWREADY;
+  (* RS_HS = "m_axi_rmem21_AW.data" *)output [2:0] m_axi_rmem21_AWSIZE;
+  (* RS_HS = "m_axi_rmem21_AW.valid" *)output m_axi_rmem21_AWVALID;
+  (* RS_HS = "m_axi_rmem21_B.data" *)input [1:0] m_axi_rmem21_BID;
+  (* RS_HS = "m_axi_rmem21_B.ready" *)output m_axi_rmem21_BREADY;
+  (* RS_HS = "m_axi_rmem21_B.data" *)input [1:0] m_axi_rmem21_BRESP;
+  (* RS_HS = "m_axi_rmem21_B.valid" *)input m_axi_rmem21_BVALID;
+  (* RS_HS = "m_axi_rmem21_R.data" *)input [511:0] m_axi_rmem21_RDATA;
+  (* RS_HS = "m_axi_rmem21_R.data" *)input [1:0] m_axi_rmem21_RID;
+  (* RS_HS = "m_axi_rmem21_R.data" *)input m_axi_rmem21_RLAST;
+  (* RS_HS = "m_axi_rmem21_R.ready" *)output m_axi_rmem21_RREADY;
+  (* RS_HS = "m_axi_rmem21_R.data" *)input [1:0] m_axi_rmem21_RRESP;
+  (* RS_HS = "m_axi_rmem21_R.valid" *)input m_axi_rmem21_RVALID;
+  (* RS_HS = "m_axi_rmem21_W.data" *)output [511:0] m_axi_rmem21_WDATA;
+  (* RS_HS = "m_axi_rmem21_W.data" *)output m_axi_rmem21_WLAST;
+  (* RS_HS = "m_axi_rmem21_W.ready" *)input m_axi_rmem21_WREADY;
+  (* RS_HS = "m_axi_rmem21_W.data" *)output [63:0] m_axi_rmem21_WSTRB;
+  (* RS_HS = "m_axi_rmem21_W.valid" *)output m_axi_rmem21_WVALID;
+  (* RS_HS = "m_axi_rmem22_AR.data" *)output [63:0] m_axi_rmem22_ARADDR;
+  (* RS_HS = "m_axi_rmem22_AR.data" *)output [1:0] m_axi_rmem22_ARBURST;
+  (* RS_HS = "m_axi_rmem22_AR.data" *)output [3:0] m_axi_rmem22_ARCACHE;
+  (* RS_HS = "m_axi_rmem22_AR.data" *)output [1:0] m_axi_rmem22_ARID;
+  (* RS_HS = "m_axi_rmem22_AR.data" *)output [7:0] m_axi_rmem22_ARLEN;
+  (* RS_HS = "m_axi_rmem22_AR.data" *)output m_axi_rmem22_ARLOCK;
+  (* RS_HS = "m_axi_rmem22_AR.data" *)output [2:0] m_axi_rmem22_ARPROT;
+  (* RS_HS = "m_axi_rmem22_AR.data" *)output [3:0] m_axi_rmem22_ARQOS;
+  (* RS_HS = "m_axi_rmem22_AR.ready" *)input m_axi_rmem22_ARREADY;
+  (* RS_HS = "m_axi_rmem22_AR.data" *)output [2:0] m_axi_rmem22_ARSIZE;
+  (* RS_HS = "m_axi_rmem22_AR.valid" *)output m_axi_rmem22_ARVALID;
+  (* RS_HS = "m_axi_rmem22_AW.data" *)output [63:0] m_axi_rmem22_AWADDR;
+  (* RS_HS = "m_axi_rmem22_AW.data" *)output [1:0] m_axi_rmem22_AWBURST;
+  (* RS_HS = "m_axi_rmem22_AW.data" *)output [3:0] m_axi_rmem22_AWCACHE;
+  (* RS_HS = "m_axi_rmem22_AW.data" *)output [1:0] m_axi_rmem22_AWID;
+  (* RS_HS = "m_axi_rmem22_AW.data" *)output [7:0] m_axi_rmem22_AWLEN;
+  (* RS_HS = "m_axi_rmem22_AW.data" *)output m_axi_rmem22_AWLOCK;
+  (* RS_HS = "m_axi_rmem22_AW.data" *)output [2:0] m_axi_rmem22_AWPROT;
+  (* RS_HS = "m_axi_rmem22_AW.data" *)output [3:0] m_axi_rmem22_AWQOS;
+  (* RS_HS = "m_axi_rmem22_AW.ready" *)input m_axi_rmem22_AWREADY;
+  (* RS_HS = "m_axi_rmem22_AW.data" *)output [2:0] m_axi_rmem22_AWSIZE;
+  (* RS_HS = "m_axi_rmem22_AW.valid" *)output m_axi_rmem22_AWVALID;
+  (* RS_HS = "m_axi_rmem22_B.data" *)input [1:0] m_axi_rmem22_BID;
+  (* RS_HS = "m_axi_rmem22_B.ready" *)output m_axi_rmem22_BREADY;
+  (* RS_HS = "m_axi_rmem22_B.data" *)input [1:0] m_axi_rmem22_BRESP;
+  (* RS_HS = "m_axi_rmem22_B.valid" *)input m_axi_rmem22_BVALID;
+  (* RS_HS = "m_axi_rmem22_R.data" *)input [511:0] m_axi_rmem22_RDATA;
+  (* RS_HS = "m_axi_rmem22_R.data" *)input [1:0] m_axi_rmem22_RID;
+  (* RS_HS = "m_axi_rmem22_R.data" *)input m_axi_rmem22_RLAST;
+  (* RS_HS = "m_axi_rmem22_R.ready" *)output m_axi_rmem22_RREADY;
+  (* RS_HS = "m_axi_rmem22_R.data" *)input [1:0] m_axi_rmem22_RRESP;
+  (* RS_HS = "m_axi_rmem22_R.valid" *)input m_axi_rmem22_RVALID;
+  (* RS_HS = "m_axi_rmem22_W.data" *)output [511:0] m_axi_rmem22_WDATA;
+  (* RS_HS = "m_axi_rmem22_W.data" *)output m_axi_rmem22_WLAST;
+  (* RS_HS = "m_axi_rmem22_W.ready" *)input m_axi_rmem22_WREADY;
+  (* RS_HS = "m_axi_rmem22_W.data" *)output [63:0] m_axi_rmem22_WSTRB;
+  (* RS_HS = "m_axi_rmem22_W.valid" *)output m_axi_rmem22_WVALID;
+  (* RS_HS = "m_axi_rmem23_AR.data" *)output [63:0] m_axi_rmem23_ARADDR;
+  (* RS_HS = "m_axi_rmem23_AR.data" *)output [1:0] m_axi_rmem23_ARBURST;
+  (* RS_HS = "m_axi_rmem23_AR.data" *)output [3:0] m_axi_rmem23_ARCACHE;
+  (* RS_HS = "m_axi_rmem23_AR.data" *)output [1:0] m_axi_rmem23_ARID;
+  (* RS_HS = "m_axi_rmem23_AR.data" *)output [7:0] m_axi_rmem23_ARLEN;
+  (* RS_HS = "m_axi_rmem23_AR.data" *)output m_axi_rmem23_ARLOCK;
+  (* RS_HS = "m_axi_rmem23_AR.data" *)output [2:0] m_axi_rmem23_ARPROT;
+  (* RS_HS = "m_axi_rmem23_AR.data" *)output [3:0] m_axi_rmem23_ARQOS;
+  (* RS_HS = "m_axi_rmem23_AR.ready" *)input m_axi_rmem23_ARREADY;
+  (* RS_HS = "m_axi_rmem23_AR.data" *)output [2:0] m_axi_rmem23_ARSIZE;
+  (* RS_HS = "m_axi_rmem23_AR.valid" *)output m_axi_rmem23_ARVALID;
+  (* RS_HS = "m_axi_rmem23_AW.data" *)output [63:0] m_axi_rmem23_AWADDR;
+  (* RS_HS = "m_axi_rmem23_AW.data" *)output [1:0] m_axi_rmem23_AWBURST;
+  (* RS_HS = "m_axi_rmem23_AW.data" *)output [3:0] m_axi_rmem23_AWCACHE;
+  (* RS_HS = "m_axi_rmem23_AW.data" *)output [1:0] m_axi_rmem23_AWID;
+  (* RS_HS = "m_axi_rmem23_AW.data" *)output [7:0] m_axi_rmem23_AWLEN;
+  (* RS_HS = "m_axi_rmem23_AW.data" *)output m_axi_rmem23_AWLOCK;
+  (* RS_HS = "m_axi_rmem23_AW.data" *)output [2:0] m_axi_rmem23_AWPROT;
+  (* RS_HS = "m_axi_rmem23_AW.data" *)output [3:0] m_axi_rmem23_AWQOS;
+  (* RS_HS = "m_axi_rmem23_AW.ready" *)input m_axi_rmem23_AWREADY;
+  (* RS_HS = "m_axi_rmem23_AW.data" *)output [2:0] m_axi_rmem23_AWSIZE;
+  (* RS_HS = "m_axi_rmem23_AW.valid" *)output m_axi_rmem23_AWVALID;
+  (* RS_HS = "m_axi_rmem23_B.data" *)input [1:0] m_axi_rmem23_BID;
+  (* RS_HS = "m_axi_rmem23_B.ready" *)output m_axi_rmem23_BREADY;
+  (* RS_HS = "m_axi_rmem23_B.data" *)input [1:0] m_axi_rmem23_BRESP;
+  (* RS_HS = "m_axi_rmem23_B.valid" *)input m_axi_rmem23_BVALID;
+  (* RS_HS = "m_axi_rmem23_R.data" *)input [511:0] m_axi_rmem23_RDATA;
+  (* RS_HS = "m_axi_rmem23_R.data" *)input [1:0] m_axi_rmem23_RID;
+  (* RS_HS = "m_axi_rmem23_R.data" *)input m_axi_rmem23_RLAST;
+  (* RS_HS = "m_axi_rmem23_R.ready" *)output m_axi_rmem23_RREADY;
+  (* RS_HS = "m_axi_rmem23_R.data" *)input [1:0] m_axi_rmem23_RRESP;
+  (* RS_HS = "m_axi_rmem23_R.valid" *)input m_axi_rmem23_RVALID;
+  (* RS_HS = "m_axi_rmem23_W.data" *)output [511:0] m_axi_rmem23_WDATA;
+  (* RS_HS = "m_axi_rmem23_W.data" *)output m_axi_rmem23_WLAST;
+  (* RS_HS = "m_axi_rmem23_W.ready" *)input m_axi_rmem23_WREADY;
+  (* RS_HS = "m_axi_rmem23_W.data" *)output [63:0] m_axi_rmem23_WSTRB;
+  (* RS_HS = "m_axi_rmem23_W.valid" *)output m_axi_rmem23_WVALID;
+  (* RS_HS = "m_axi_rmem24_AR.data" *)output [63:0] m_axi_rmem24_ARADDR;
+  (* RS_HS = "m_axi_rmem24_AR.data" *)output [1:0] m_axi_rmem24_ARBURST;
+  (* RS_HS = "m_axi_rmem24_AR.data" *)output [3:0] m_axi_rmem24_ARCACHE;
+  (* RS_HS = "m_axi_rmem24_AR.data" *)output [1:0] m_axi_rmem24_ARID;
+  (* RS_HS = "m_axi_rmem24_AR.data" *)output [7:0] m_axi_rmem24_ARLEN;
+  (* RS_HS = "m_axi_rmem24_AR.data" *)output m_axi_rmem24_ARLOCK;
+  (* RS_HS = "m_axi_rmem24_AR.data" *)output [2:0] m_axi_rmem24_ARPROT;
+  (* RS_HS = "m_axi_rmem24_AR.data" *)output [3:0] m_axi_rmem24_ARQOS;
+  (* RS_HS = "m_axi_rmem24_AR.ready" *)input m_axi_rmem24_ARREADY;
+  (* RS_HS = "m_axi_rmem24_AR.data" *)output [2:0] m_axi_rmem24_ARSIZE;
+  (* RS_HS = "m_axi_rmem24_AR.valid" *)output m_axi_rmem24_ARVALID;
+  (* RS_HS = "m_axi_rmem24_AW.data" *)output [63:0] m_axi_rmem24_AWADDR;
+  (* RS_HS = "m_axi_rmem24_AW.data" *)output [1:0] m_axi_rmem24_AWBURST;
+  (* RS_HS = "m_axi_rmem24_AW.data" *)output [3:0] m_axi_rmem24_AWCACHE;
+  (* RS_HS = "m_axi_rmem24_AW.data" *)output [1:0] m_axi_rmem24_AWID;
+  (* RS_HS = "m_axi_rmem24_AW.data" *)output [7:0] m_axi_rmem24_AWLEN;
+  (* RS_HS = "m_axi_rmem24_AW.data" *)output m_axi_rmem24_AWLOCK;
+  (* RS_HS = "m_axi_rmem24_AW.data" *)output [2:0] m_axi_rmem24_AWPROT;
+  (* RS_HS = "m_axi_rmem24_AW.data" *)output [3:0] m_axi_rmem24_AWQOS;
+  (* RS_HS = "m_axi_rmem24_AW.ready" *)input m_axi_rmem24_AWREADY;
+  (* RS_HS = "m_axi_rmem24_AW.data" *)output [2:0] m_axi_rmem24_AWSIZE;
+  (* RS_HS = "m_axi_rmem24_AW.valid" *)output m_axi_rmem24_AWVALID;
+  (* RS_HS = "m_axi_rmem24_B.data" *)input [1:0] m_axi_rmem24_BID;
+  (* RS_HS = "m_axi_rmem24_B.ready" *)output m_axi_rmem24_BREADY;
+  (* RS_HS = "m_axi_rmem24_B.data" *)input [1:0] m_axi_rmem24_BRESP;
+  (* RS_HS = "m_axi_rmem24_B.valid" *)input m_axi_rmem24_BVALID;
+  (* RS_HS = "m_axi_rmem24_R.data" *)input [511:0] m_axi_rmem24_RDATA;
+  (* RS_HS = "m_axi_rmem24_R.data" *)input [1:0] m_axi_rmem24_RID;
+  (* RS_HS = "m_axi_rmem24_R.data" *)input m_axi_rmem24_RLAST;
+  (* RS_HS = "m_axi_rmem24_R.ready" *)output m_axi_rmem24_RREADY;
+  (* RS_HS = "m_axi_rmem24_R.data" *)input [1:0] m_axi_rmem24_RRESP;
+  (* RS_HS = "m_axi_rmem24_R.valid" *)input m_axi_rmem24_RVALID;
+  (* RS_HS = "m_axi_rmem24_W.data" *)output [511:0] m_axi_rmem24_WDATA;
+  (* RS_HS = "m_axi_rmem24_W.data" *)output m_axi_rmem24_WLAST;
+  (* RS_HS = "m_axi_rmem24_W.ready" *)input m_axi_rmem24_WREADY;
+  (* RS_HS = "m_axi_rmem24_W.data" *)output [63:0] m_axi_rmem24_WSTRB;
+  (* RS_HS = "m_axi_rmem24_W.valid" *)output m_axi_rmem24_WVALID;
+  (* RS_HS = "m_axi_rmem25_AR.data" *)output [63:0] m_axi_rmem25_ARADDR;
+  (* RS_HS = "m_axi_rmem25_AR.data" *)output [1:0] m_axi_rmem25_ARBURST;
+  (* RS_HS = "m_axi_rmem25_AR.data" *)output [3:0] m_axi_rmem25_ARCACHE;
+  (* RS_HS = "m_axi_rmem25_AR.data" *)output [1:0] m_axi_rmem25_ARID;
+  (* RS_HS = "m_axi_rmem25_AR.data" *)output [7:0] m_axi_rmem25_ARLEN;
+  (* RS_HS = "m_axi_rmem25_AR.data" *)output m_axi_rmem25_ARLOCK;
+  (* RS_HS = "m_axi_rmem25_AR.data" *)output [2:0] m_axi_rmem25_ARPROT;
+  (* RS_HS = "m_axi_rmem25_AR.data" *)output [3:0] m_axi_rmem25_ARQOS;
+  (* RS_HS = "m_axi_rmem25_AR.ready" *)input m_axi_rmem25_ARREADY;
+  (* RS_HS = "m_axi_rmem25_AR.data" *)output [2:0] m_axi_rmem25_ARSIZE;
+  (* RS_HS = "m_axi_rmem25_AR.valid" *)output m_axi_rmem25_ARVALID;
+  (* RS_HS = "m_axi_rmem25_AW.data" *)output [63:0] m_axi_rmem25_AWADDR;
+  (* RS_HS = "m_axi_rmem25_AW.data" *)output [1:0] m_axi_rmem25_AWBURST;
+  (* RS_HS = "m_axi_rmem25_AW.data" *)output [3:0] m_axi_rmem25_AWCACHE;
+  (* RS_HS = "m_axi_rmem25_AW.data" *)output [1:0] m_axi_rmem25_AWID;
+  (* RS_HS = "m_axi_rmem25_AW.data" *)output [7:0] m_axi_rmem25_AWLEN;
+  (* RS_HS = "m_axi_rmem25_AW.data" *)output m_axi_rmem25_AWLOCK;
+  (* RS_HS = "m_axi_rmem25_AW.data" *)output [2:0] m_axi_rmem25_AWPROT;
+  (* RS_HS = "m_axi_rmem25_AW.data" *)output [3:0] m_axi_rmem25_AWQOS;
+  (* RS_HS = "m_axi_rmem25_AW.ready" *)input m_axi_rmem25_AWREADY;
+  (* RS_HS = "m_axi_rmem25_AW.data" *)output [2:0] m_axi_rmem25_AWSIZE;
+  (* RS_HS = "m_axi_rmem25_AW.valid" *)output m_axi_rmem25_AWVALID;
+  (* RS_HS = "m_axi_rmem25_B.data" *)input [1:0] m_axi_rmem25_BID;
+  (* RS_HS = "m_axi_rmem25_B.ready" *)output m_axi_rmem25_BREADY;
+  (* RS_HS = "m_axi_rmem25_B.data" *)input [1:0] m_axi_rmem25_BRESP;
+  (* RS_HS = "m_axi_rmem25_B.valid" *)input m_axi_rmem25_BVALID;
+  (* RS_HS = "m_axi_rmem25_R.data" *)input [511:0] m_axi_rmem25_RDATA;
+  (* RS_HS = "m_axi_rmem25_R.data" *)input [1:0] m_axi_rmem25_RID;
+  (* RS_HS = "m_axi_rmem25_R.data" *)input m_axi_rmem25_RLAST;
+  (* RS_HS = "m_axi_rmem25_R.ready" *)output m_axi_rmem25_RREADY;
+  (* RS_HS = "m_axi_rmem25_R.data" *)input [1:0] m_axi_rmem25_RRESP;
+  (* RS_HS = "m_axi_rmem25_R.valid" *)input m_axi_rmem25_RVALID;
+  (* RS_HS = "m_axi_rmem25_W.data" *)output [511:0] m_axi_rmem25_WDATA;
+  (* RS_HS = "m_axi_rmem25_W.data" *)output m_axi_rmem25_WLAST;
+  (* RS_HS = "m_axi_rmem25_W.ready" *)input m_axi_rmem25_WREADY;
+  (* RS_HS = "m_axi_rmem25_W.data" *)output [63:0] m_axi_rmem25_WSTRB;
+  (* RS_HS = "m_axi_rmem25_W.valid" *)output m_axi_rmem25_WVALID;
+  (* RS_HS = "m_axi_rmem26_AR.data" *)output [63:0] m_axi_rmem26_ARADDR;
+  (* RS_HS = "m_axi_rmem26_AR.data" *)output [1:0] m_axi_rmem26_ARBURST;
+  (* RS_HS = "m_axi_rmem26_AR.data" *)output [3:0] m_axi_rmem26_ARCACHE;
+  (* RS_HS = "m_axi_rmem26_AR.data" *)output [1:0] m_axi_rmem26_ARID;
+  (* RS_HS = "m_axi_rmem26_AR.data" *)output [7:0] m_axi_rmem26_ARLEN;
+  (* RS_HS = "m_axi_rmem26_AR.data" *)output m_axi_rmem26_ARLOCK;
+  (* RS_HS = "m_axi_rmem26_AR.data" *)output [2:0] m_axi_rmem26_ARPROT;
+  (* RS_HS = "m_axi_rmem26_AR.data" *)output [3:0] m_axi_rmem26_ARQOS;
+  (* RS_HS = "m_axi_rmem26_AR.ready" *)input m_axi_rmem26_ARREADY;
+  (* RS_HS = "m_axi_rmem26_AR.data" *)output [2:0] m_axi_rmem26_ARSIZE;
+  (* RS_HS = "m_axi_rmem26_AR.valid" *)output m_axi_rmem26_ARVALID;
+  (* RS_HS = "m_axi_rmem26_AW.data" *)output [63:0] m_axi_rmem26_AWADDR;
+  (* RS_HS = "m_axi_rmem26_AW.data" *)output [1:0] m_axi_rmem26_AWBURST;
+  (* RS_HS = "m_axi_rmem26_AW.data" *)output [3:0] m_axi_rmem26_AWCACHE;
+  (* RS_HS = "m_axi_rmem26_AW.data" *)output [1:0] m_axi_rmem26_AWID;
+  (* RS_HS = "m_axi_rmem26_AW.data" *)output [7:0] m_axi_rmem26_AWLEN;
+  (* RS_HS = "m_axi_rmem26_AW.data" *)output m_axi_rmem26_AWLOCK;
+  (* RS_HS = "m_axi_rmem26_AW.data" *)output [2:0] m_axi_rmem26_AWPROT;
+  (* RS_HS = "m_axi_rmem26_AW.data" *)output [3:0] m_axi_rmem26_AWQOS;
+  (* RS_HS = "m_axi_rmem26_AW.ready" *)input m_axi_rmem26_AWREADY;
+  (* RS_HS = "m_axi_rmem26_AW.data" *)output [2:0] m_axi_rmem26_AWSIZE;
+  (* RS_HS = "m_axi_rmem26_AW.valid" *)output m_axi_rmem26_AWVALID;
+  (* RS_HS = "m_axi_rmem26_B.data" *)input [1:0] m_axi_rmem26_BID;
+  (* RS_HS = "m_axi_rmem26_B.ready" *)output m_axi_rmem26_BREADY;
+  (* RS_HS = "m_axi_rmem26_B.data" *)input [1:0] m_axi_rmem26_BRESP;
+  (* RS_HS = "m_axi_rmem26_B.valid" *)input m_axi_rmem26_BVALID;
+  (* RS_HS = "m_axi_rmem26_R.data" *)input [511:0] m_axi_rmem26_RDATA;
+  (* RS_HS = "m_axi_rmem26_R.data" *)input [1:0] m_axi_rmem26_RID;
+  (* RS_HS = "m_axi_rmem26_R.data" *)input m_axi_rmem26_RLAST;
+  (* RS_HS = "m_axi_rmem26_R.ready" *)output m_axi_rmem26_RREADY;
+  (* RS_HS = "m_axi_rmem26_R.data" *)input [1:0] m_axi_rmem26_RRESP;
+  (* RS_HS = "m_axi_rmem26_R.valid" *)input m_axi_rmem26_RVALID;
+  (* RS_HS = "m_axi_rmem26_W.data" *)output [511:0] m_axi_rmem26_WDATA;
+  (* RS_HS = "m_axi_rmem26_W.data" *)output m_axi_rmem26_WLAST;
+  (* RS_HS = "m_axi_rmem26_W.ready" *)input m_axi_rmem26_WREADY;
+  (* RS_HS = "m_axi_rmem26_W.data" *)output [63:0] m_axi_rmem26_WSTRB;
+  (* RS_HS = "m_axi_rmem26_W.valid" *)output m_axi_rmem26_WVALID;
+  (* RS_HS = "m_axi_rmem27_AR.data" *)output [63:0] m_axi_rmem27_ARADDR;
+  (* RS_HS = "m_axi_rmem27_AR.data" *)output [1:0] m_axi_rmem27_ARBURST;
+  (* RS_HS = "m_axi_rmem27_AR.data" *)output [3:0] m_axi_rmem27_ARCACHE;
+  (* RS_HS = "m_axi_rmem27_AR.data" *)output [1:0] m_axi_rmem27_ARID;
+  (* RS_HS = "m_axi_rmem27_AR.data" *)output [7:0] m_axi_rmem27_ARLEN;
+  (* RS_HS = "m_axi_rmem27_AR.data" *)output m_axi_rmem27_ARLOCK;
+  (* RS_HS = "m_axi_rmem27_AR.data" *)output [2:0] m_axi_rmem27_ARPROT;
+  (* RS_HS = "m_axi_rmem27_AR.data" *)output [3:0] m_axi_rmem27_ARQOS;
+  (* RS_HS = "m_axi_rmem27_AR.ready" *)input m_axi_rmem27_ARREADY;
+  (* RS_HS = "m_axi_rmem27_AR.data" *)output [2:0] m_axi_rmem27_ARSIZE;
+  (* RS_HS = "m_axi_rmem27_AR.valid" *)output m_axi_rmem27_ARVALID;
+  (* RS_HS = "m_axi_rmem27_AW.data" *)output [63:0] m_axi_rmem27_AWADDR;
+  (* RS_HS = "m_axi_rmem27_AW.data" *)output [1:0] m_axi_rmem27_AWBURST;
+  (* RS_HS = "m_axi_rmem27_AW.data" *)output [3:0] m_axi_rmem27_AWCACHE;
+  (* RS_HS = "m_axi_rmem27_AW.data" *)output [1:0] m_axi_rmem27_AWID;
+  (* RS_HS = "m_axi_rmem27_AW.data" *)output [7:0] m_axi_rmem27_AWLEN;
+  (* RS_HS = "m_axi_rmem27_AW.data" *)output m_axi_rmem27_AWLOCK;
+  (* RS_HS = "m_axi_rmem27_AW.data" *)output [2:0] m_axi_rmem27_AWPROT;
+  (* RS_HS = "m_axi_rmem27_AW.data" *)output [3:0] m_axi_rmem27_AWQOS;
+  (* RS_HS = "m_axi_rmem27_AW.ready" *)input m_axi_rmem27_AWREADY;
+  (* RS_HS = "m_axi_rmem27_AW.data" *)output [2:0] m_axi_rmem27_AWSIZE;
+  (* RS_HS = "m_axi_rmem27_AW.valid" *)output m_axi_rmem27_AWVALID;
+  (* RS_HS = "m_axi_rmem27_B.data" *)input [1:0] m_axi_rmem27_BID;
+  (* RS_HS = "m_axi_rmem27_B.ready" *)output m_axi_rmem27_BREADY;
+  (* RS_HS = "m_axi_rmem27_B.data" *)input [1:0] m_axi_rmem27_BRESP;
+  (* RS_HS = "m_axi_rmem27_B.valid" *)input m_axi_rmem27_BVALID;
+  (* RS_HS = "m_axi_rmem27_R.data" *)input [511:0] m_axi_rmem27_RDATA;
+  (* RS_HS = "m_axi_rmem27_R.data" *)input [1:0] m_axi_rmem27_RID;
+  (* RS_HS = "m_axi_rmem27_R.data" *)input m_axi_rmem27_RLAST;
+  (* RS_HS = "m_axi_rmem27_R.ready" *)output m_axi_rmem27_RREADY;
+  (* RS_HS = "m_axi_rmem27_R.data" *)input [1:0] m_axi_rmem27_RRESP;
+  (* RS_HS = "m_axi_rmem27_R.valid" *)input m_axi_rmem27_RVALID;
+  (* RS_HS = "m_axi_rmem27_W.data" *)output [511:0] m_axi_rmem27_WDATA;
+  (* RS_HS = "m_axi_rmem27_W.data" *)output m_axi_rmem27_WLAST;
+  (* RS_HS = "m_axi_rmem27_W.ready" *)input m_axi_rmem27_WREADY;
+  (* RS_HS = "m_axi_rmem27_W.data" *)output [63:0] m_axi_rmem27_WSTRB;
+  (* RS_HS = "m_axi_rmem27_W.valid" *)output m_axi_rmem27_WVALID;
+
+endmodule
diff --git a/benchmarks/vivado_flow/vck5000_dfx/xdc/pdef.xdc b/benchmarks/vivado_flow/vck5000_dfx/xdc/pdef.xdc
index 9ac360da..853a5014 100644
--- a/benchmarks/vivado_flow/vck5000_dfx/xdc/pdef.xdc
+++ b/benchmarks/vivado_flow/vck5000_dfx/xdc/pdef.xdc
@@ -1,4 +1,3 @@
-
 # Copyright (c) 2024 RapidStream Design Automation, Inc. and contributors.  All rights reserved.
 # The contributor(s) of this file has/have agreed to the RapidStream Contributor License Agreement.
 
diff --git a/benchmarks/vivado_flow/vck5000_dfx/xdc/pdef1.xdc b/benchmarks/vivado_flow/vck5000_dfx/xdc/pdef1.xdc
new file mode 100644
index 00000000..692ea66b
--- /dev/null
+++ b/benchmarks/vivado_flow/vck5000_dfx/xdc/pdef1.xdc
@@ -0,0 +1,22 @@
+# Copyright (c) 2024 RapidStream Design Automation, Inc. and contributors.  All rights reserved.
+# The contributor(s) of this file has/have agreed to the RapidStream Contributor License Agreement.
+
+create_pblock tapa_region
+add_cells_to_pblock [get_pblocks tapa_region] [get_cells -quiet [list design_1_i/vadd_bw_0/inst]]
+resize_pblock [get_pblocks tapa_region] -add {SLICE_X52Y12:SLICE_X331Y326}
+resize_pblock [get_pblocks tapa_region] -add {BUFG_FABRIC_X0Y95:BUFG_FABRIC_X4Y0}
+resize_pblock [get_pblocks tapa_region] -add {DSP58_CPLX_X0Y6:DSP58_CPLX_X5Y162}
+resize_pblock [get_pblocks tapa_region] -add {DSP_X0Y6:DSP_X11Y162}
+resize_pblock [get_pblocks tapa_region] -add {GCLK_DELAY_X1Y191:GCLK_DELAY_X5Y0}
+resize_pblock [get_pblocks tapa_region] -add {GCLK_PD_X3Y0:GCLK_PD_X13Y239 GCLK_PD_X2Y24:GCLK_PD_X2Y215}
+resize_pblock [get_pblocks tapa_region] -add {GCLK_TAPS_DECODE_VNOC_X0Y3:GCLK_TAPS_DECODE_VNOC_X3Y0}
+resize_pblock [get_pblocks tapa_region] -add {GCLK_TAPS_DECODE_VNOC_PS_X0Y0:GCLK_TAPS_DECODE_VNOC_PS_X0Y0}
+resize_pblock [get_pblocks tapa_region] -add {IRI_QUAD_X36Y76:IRI_QUAD_X206Y1335}
+resize_pblock [get_pblocks tapa_region] -add {RAMB18_X1Y8:RAMB18_X11Y163}
+resize_pblock [get_pblocks tapa_region] -add {RAMB36_X1Y4:RAMB36_X11Y81}
+resize_pblock [get_pblocks tapa_region] -add {URAM288_X1Y4:URAM288_X4Y81}
+resize_pblock [get_pblocks tapa_region] -add {URAM_CAS_DLY_X1Y0:URAM_CAS_DLY_X4Y2}
+set_property SNAPPING_MODE ON [get_pblocks tapa_region]
+
+set_property DONT_TOUCH true [get_cells design_1_i/vadd_bw_0/inst]
+set_property HD.RECONFIGURABLE true [get_cells design_1_i/vadd_bw_0/inst]