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g04_lab03.map.rpt
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g04_lab03.map.rpt
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Analysis & Synthesis report for g04_lab03
Thu Apr 09 18:50:20 2015
Quartus II 64-Bit Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Parallel Compilation
5. Analysis & Synthesis Source Files Read
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
8. Analysis & Synthesis RAM Summary
9. General Register Statistics
10. Inverted Register Statistics
11. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body
12. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst
13. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_kps3:auto_generated
14. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_kps3:auto_generated|altsyncram_3eq1:altsyncram1
15. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|LPM_COUNTER:\adv_point_3_and_more:advance_pointer_counter
16. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|LPM_COUNTER:read_pointer_counter
17. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|LPM_COUNTER:status_advance_pointer_counter
18. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|LPM_COUNTER:status_read_pointer_counter
19. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr
20. Source assignments for sld_hub:auto_hub
21. Source assignments for sld_hub:auto_hub|sld_rom_sr:hub_info_reg
22. Parameter Settings for Inferred Entity Instance: sld_signaltap:auto_signaltap_0
23. Parameter Settings for Inferred Entity Instance: sld_hub:auto_hub
24. SignalTap II Logic Analyzer Settings
25. Connections to In-System Debugging Instance "auto_signaltap_0"
26. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+-----------------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Apr 09 18:50:19 2015 ;
; Quartus II 64-Bit Version ; 9.1 Build 350 03/24/2010 SP 2 SJ Full Version ;
; Revision Name ; g04_lab03 ;
; Top-level Entity Name ; g04_note_timer ;
; Family ; Cyclone II ;
; Total logic elements ; 729 ;
; Total combinational functions ; 486 ;
; Dedicated logic registers ; 524 ;
; Total registers ; 524 ;
; Total pins ; 8 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 131,072 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Total PLLs ; 0 ;
+------------------------------------+-----------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device ; EP2C20F484C7 ; ;
; Top-level entity name ; g04_note_timer ; g04_lab03 ;
; Family name ; Cyclone II ; Stratix II ;
; Use Generated Physical Constraints File ; Off ; ;
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Parallel Synthesis ; On ; On ;
; DSP Block Balancing ; Auto ; Auto ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique ; Balanced ; Balanced ;
; Carry Chain Length ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Strict RAM Replacement ; Off ; Off ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Timing-Driven Synthesis ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Synchronization Register Chain Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Auto Gated Clock Conversion ; Off ; Off ;
; Block Design Naming ; Auto ; Auto ;
; SDC constraint protection ; Off ; Off ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
; Resource Aware Inference For Block RAM ; On ; On ;
+----------------------------------------------------------------------------+--------------------+--------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 4 ;
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 1 ;
; ; ;
; Usage by Processor ; % Time Used ;
; 1 processor ; 100.0% ;
; 2-4 processors ; 0.0% ;
+----------------------------+-------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+-------------------------------------------------------------+-----------------+------------------------------+------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+-------------------------------------------------------------+-----------------+------------------------------+------------------------------------------------------------------------------+
; g04_note_timer.vhd ; yes ; User VHDL File ; H:/My Documents/Lab3/g04_note_timer.vhd ;
; sld_signaltap.vhd ; yes ; Encrypted Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/sld_signaltap.vhd ;
; sld_ela_control.vhd ; yes ; Encrypted Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/sld_ela_control.vhd ;
; lpm_shiftreg.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_shiftreg.tdf ;
; sld_mbpmg.vhd ; yes ; Encrypted Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/sld_mbpmg.vhd ;
; sld_ela_trigger_flow_mgr.vhd ; yes ; Encrypted Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd ;
; sld_buffer_manager.vhd ; yes ; Encrypted Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/sld_buffer_manager.vhd ;
; altsyncram.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/altsyncram.tdf ;
; db/altsyncram_kps3.tdf ; yes ; Auto-Generated Megafunction ; H:/My Documents/Lab3/db/altsyncram_kps3.tdf ;
; db/altsyncram_3eq1.tdf ; yes ; Auto-Generated Megafunction ; H:/My Documents/Lab3/db/altsyncram_3eq1.tdf ;
; db/decode_4oa.tdf ; yes ; Auto-Generated Megafunction ; H:/My Documents/Lab3/db/decode_4oa.tdf ;
; db/mux_kib.tdf ; yes ; Auto-Generated Megafunction ; H:/My Documents/Lab3/db/mux_kib.tdf ;
; altdpram.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/altdpram.tdf ;
; lpm_mux.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_mux.tdf ;
; db/mux_foc.tdf ; yes ; Auto-Generated Megafunction ; H:/My Documents/Lab3/db/mux_foc.tdf ;
; lpm_decode.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_decode.tdf ;
; db/decode_rqf.tdf ; yes ; Auto-Generated Megafunction ; H:/My Documents/Lab3/db/decode_rqf.tdf ;
; lpm_counter.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_counter.tdf ;
; db/cntr_dai.tdf ; yes ; Auto-Generated Megafunction ; H:/My Documents/Lab3/db/cntr_dai.tdf ;
; db/cntr_p6j.tdf ; yes ; Auto-Generated Megafunction ; H:/My Documents/Lab3/db/cntr_p6j.tdf ;
; db/cntr_2ci.tdf ; yes ; Auto-Generated Megafunction ; H:/My Documents/Lab3/db/cntr_2ci.tdf ;
; db/cmpr_9cc.tdf ; yes ; Auto-Generated Megafunction ; H:/My Documents/Lab3/db/cmpr_9cc.tdf ;
; db/cntr_gui.tdf ; yes ; Auto-Generated Megafunction ; H:/My Documents/Lab3/db/cntr_gui.tdf ;
; db/cmpr_5cc.tdf ; yes ; Auto-Generated Megafunction ; H:/My Documents/Lab3/db/cmpr_5cc.tdf ;
; sld_rom_sr.vhd ; yes ; Encrypted Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/sld_rom_sr.vhd ;
; sld_hub.vhd ; yes ; Encrypted Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/sld_hub.vhd ;
; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_rom.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_rom.tdf ;
; c:/altera/91sp2/quartus/libraries/megafunctions/altrom.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/altrom.tdf ;
; H:/My Documents/Lab3/db/altsyncram_7f01.tdf ; yes ; Auto-Generated Megafunction ; H:/My Documents/Lab3/db/altsyncram_7f01.tdf ;
; H:/My Documents/Lab3/db/cntr_8kk.tdf ; yes ; Auto-Generated Megafunction ; H:/My Documents/Lab3/db/cntr_8kk.tdf ;
; H:/My Documents/Lab3/db/cntr_g7l.tdf ; yes ; Auto-Generated Megafunction ; H:/My Documents/Lab3/db/cntr_g7l.tdf ;
; H:/My Documents/Lab3/db/altsyncram_ml01.tdf ; yes ; Auto-Generated Megafunction ; H:/My Documents/Lab3/db/altsyncram_ml01.tdf ;
; H:/My Documents/Lab3/db/altsyncram_lms3.tdf ; yes ; Auto-Generated Megafunction ; H:/My Documents/Lab3/db/altsyncram_lms3.tdf ;
; H:/My Documents/Lab3/db/mux_aoc.tdf ; yes ; Auto-Generated Megafunction ; H:/My Documents/Lab3/db/mux_aoc.tdf ;
; H:/My Documents/Lab3/db/cntr_cai.tdf ; yes ; Auto-Generated Megafunction ; H:/My Documents/Lab3/db/cntr_cai.tdf ;
; H:/My Documents/Lab3/db/cmpr_7cc.tdf ; yes ; Auto-Generated Megafunction ; H:/My Documents/Lab3/db/cmpr_7cc.tdf ;
; H:/My Documents/Lab3/db/cntr_02j.tdf ; yes ; Auto-Generated Megafunction ; H:/My Documents/Lab3/db/cntr_02j.tdf ;
; H:/My Documents/Lab3/db/cntr_sbi.tdf ; yes ; Auto-Generated Megafunction ; H:/My Documents/Lab3/db/cntr_sbi.tdf ;
; H:/My Documents/Lab3/db/cmpr_8cc.tdf ; yes ; Auto-Generated Megafunction ; H:/My Documents/Lab3/db/cmpr_8cc.tdf ;
+-------------------------------------------------------------+-----------------+------------------------------+------------------------------------------------------------------------------+
+------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+--------------------------+
; Resource ; Usage ;
+---------------------------------------------+--------------------------+
; Estimated Total logic elements ; 729 ;
; ; ;
; Total combinational functions ; 486 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 216 ;
; -- 3 input functions ; 149 ;
; -- <=2 input functions ; 121 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 405 ;
; -- arithmetic mode ; 81 ;
; ; ;
; Total registers ; 524 ;
; -- Dedicated logic registers ; 524 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 8 ;
; Total memory bits ; 131072 ;
; Maximum fan-out node ; altera_internal_jtag~TDO ;
; Maximum fan-out ; 328 ;
; Total fan-out ; 4128 ;
; Average fan-out ; 3.91 ;
+---------------------------------------------+--------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+------------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+------------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; |g04_note_timer ; 486 (40) ; 524 (10) ; 131072 ; 0 ; 0 ; 0 ; 8 ; 0 ; |g04_note_timer ; work ;
; |sld_hub:auto_hub| ; 103 (64) ; 73 (45) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |g04_note_timer|sld_hub:auto_hub ; ;
; |sld_rom_sr:hub_info_reg| ; 22 (22) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |g04_note_timer|sld_hub:auto_hub|sld_rom_sr:hub_info_reg ; ;
; |sld_shadow_jsm:shadow_jsm| ; 17 (17) ; 19 (19) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |g04_note_timer|sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm ; ;
; |sld_signaltap:auto_signaltap_0| ; 343 (1) ; 441 (0) ; 131072 ; 0 ; 0 ; 0 ; 0 ; 0 ; |g04_note_timer|sld_signaltap:auto_signaltap_0 ; ;
; |sld_signaltap_impl:sld_signaltap_body| ; 342 (20) ; 441 (88) ; 131072 ; 0 ; 0 ; 0 ; 0 ; 0 ; |g04_note_timer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body ; ;
; |altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem| ; 31 (0) ; 88 (88) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |g04_note_timer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem ; ;
; |lpm_decode:wdecoder| ; 2 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |g04_note_timer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_decode:wdecoder ; ;
; |decode_rqf:auto_generated| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |g04_note_timer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_decode:wdecoder|decode_rqf:auto_generated ; ;
; |lpm_mux:mux| ; 29 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |g04_note_timer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_mux:mux ; ;
; |mux_foc:auto_generated| ; 29 (29) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |g04_note_timer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_mux:mux|mux_foc:auto_generated ; ;
; |altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram| ; 22 (0) ; 2 (0) ; 131072 ; 0 ; 0 ; 0 ; 0 ; 0 ; |g04_note_timer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram ; ;
; |altsyncram_kps3:auto_generated| ; 22 (0) ; 2 (0) ; 131072 ; 0 ; 0 ; 0 ; 0 ; 0 ; |g04_note_timer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_kps3:auto_generated ; ;
; |altsyncram_3eq1:altsyncram1| ; 22 (0) ; 2 (2) ; 131072 ; 0 ; 0 ; 0 ; 0 ; 0 ; |g04_note_timer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_kps3:auto_generated|altsyncram_3eq1:altsyncram1 ; ;
; |decode_4oa:decode4| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |g04_note_timer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_kps3:auto_generated|altsyncram_3eq1:altsyncram1|decode_4oa:decode4 ; ;
; |decode_4oa:decode_a| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |g04_note_timer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_kps3:auto_generated|altsyncram_3eq1:altsyncram1|decode_4oa:decode_a ; ;
; |mux_kib:mux5| ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |g04_note_timer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_kps3:auto_generated|altsyncram_3eq1:altsyncram1|mux_kib:mux5 ; ;
; |lpm_shiftreg:segment_offset_config_deserialize| ; 0 (0) ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |g04_note_timer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|lpm_shiftreg:segment_offset_config_deserialize ; ;
; |lpm_shiftreg:status_register| ; 17 (17) ; 17 (17) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |g04_note_timer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|lpm_shiftreg:status_register ; ;
; |sld_buffer_manager:sld_buffer_manager_inst| ; 106 (106) ; 79 (79) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |g04_note_timer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst ; ;
; |sld_ela_control:ela_control| ; 20 (1) ; 56 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |g04_note_timer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control ; ;
; |lpm_shiftreg:trigger_config_deserialize| ; 0 (0) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |g04_note_timer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|lpm_shiftreg:trigger_config_deserialize ; ;
; |sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm| ; 16 (0) ; 40 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |g04_note_timer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm ; ;
; |lpm_shiftreg:trigger_condition_deserialize| ; 0 (0) ; 24 (24) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |g04_note_timer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize ; ;
; |sld_mbpmg:\trigger_modules_gen:0:trigger_match| ; 16 (0) ; 16 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |g04_note_timer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match ; ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |g04_note_timer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1 ; ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |g04_note_timer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1 ; ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |g04_note_timer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1 ; ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |g04_note_timer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1 ; ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |g04_note_timer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1 ; ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |g04_note_timer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1 ; ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |g04_note_timer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1 ; ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:7:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |g04_note_timer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:7:sm1 ; ;
; |sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity| ; 3 (3) ; 11 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |g04_note_timer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity ; ;
; |lpm_shiftreg:trigger_config_deserialize| ; 0 (0) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |g04_note_timer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|lpm_shiftreg:trigger_config_deserialize ; ;
; |sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst| ; 106 (11) ; 89 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |g04_note_timer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst ; ;
; |lpm_counter:\adv_point_3_and_more:advance_pointer_counter| ; 3 (0) ; 3 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |g04_note_timer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter ; ;
; |cntr_dai:auto_generated| ; 3 (3) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |g04_note_timer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter|cntr_dai:auto_generated ; ;
; |lpm_counter:read_pointer_counter| ; 14 (0) ; 14 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |g04_note_timer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter ; ;
; |cntr_p6j:auto_generated| ; 14 (14) ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |g04_note_timer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter|cntr_p6j:auto_generated ; ;
; |lpm_counter:status_advance_pointer_counter| ; 7 (0) ; 5 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |g04_note_timer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_advance_pointer_counter ; ;
; |cntr_2ci:auto_generated| ; 7 (7) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |g04_note_timer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_advance_pointer_counter|cntr_2ci:auto_generated ; ;
; |lpm_counter:status_read_pointer_counter| ; 3 (0) ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |g04_note_timer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_read_pointer_counter ; ;
; |cntr_gui:auto_generated| ; 3 (3) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |g04_note_timer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_read_pointer_counter|cntr_gui:auto_generated ; ;
; |lpm_shiftreg:info_data_shift_out| ; 29 (29) ; 29 (29) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |g04_note_timer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:info_data_shift_out ; ;
; |lpm_shiftreg:ram_data_shift_out| ; 10 (10) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |g04_note_timer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out ; ;
; |lpm_shiftreg:status_data_shift_out| ; 29 (29) ; 29 (29) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |g04_note_timer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:status_data_shift_out ; ;
; |sld_rom_sr:crc_rom_sr| ; 20 (20) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |g04_note_timer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr ; ;
+------------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+--------+------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+--------+------+
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_kps3:auto_generated|altsyncram_3eq1:altsyncram1|ALTSYNCRAM ; AUTO ; True Dual Port ; 16384 ; 8 ; 16384 ; 8 ; 131072 ; None ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+--------+------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 524 ;
; Number of registers using Synchronous Clear ; 22 ;
; Number of registers using Synchronous Load ; 24 ;
; Number of registers using Asynchronous Clear ; 252 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 306 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Inverted Register Statistics ;
+-----------------------------------------------------------------------------------------------------------------------------------------+---------+
; Inverted Register ; Fan out ;
+-----------------------------------------------------------------------------------------------------------------------------------------+---------+
; TRIGGER~reg0 ; 2 ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[1] ; 1 ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[2] ; 1 ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[3] ; 1 ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[4] ; 1 ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[5] ; 1 ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[6] ; 1 ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[7] ; 1 ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[8] ; 1 ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[9] ; 1 ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[10] ; 1 ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[11] ; 1 ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[12] ; 1 ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[13] ; 1 ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[14] ; 1 ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[0] ; 1 ;
; sld_hub:auto_hub|tdo ; 2 ;
; Total number of inverted registers = 17 ; ;
+-----------------------------------------------------------------------------------------------------------------------------------------+---------+
+---------------------------------------------------------------------------------------------+
; Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body ;
+---------------------------------+-------+------+--------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+-------+------+--------------------------------------------+
; NOT_GATE_PUSH_BACK ; OFF ; - ; - ;
; POWER_UP_LEVEL ; LOW ; - ; - ;
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ;
+---------------------------------+-------+------+--------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst ;
+--------------------+-------+------+----------------------------------------------------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+--------------------+-------+------+----------------------------------------------------------------------------------------------------+
; NOT_GATE_PUSH_BACK ; ON ; - ; modified_post_count[7] ;
; NOT_GATE_PUSH_BACK ; ON ; - ; modified_post_count[6] ;
; NOT_GATE_PUSH_BACK ; ON ; - ; modified_post_count[5] ;
; NOT_GATE_PUSH_BACK ; ON ; - ; modified_post_count[4] ;
; NOT_GATE_PUSH_BACK ; ON ; - ; modified_post_count[3] ;
; NOT_GATE_PUSH_BACK ; ON ; - ; modified_post_count[2] ;
; NOT_GATE_PUSH_BACK ; ON ; - ; modified_post_count[1] ;
; NOT_GATE_PUSH_BACK ; ON ; - ; modified_post_count[0] ;
; NOT_GATE_PUSH_BACK ; ON ; - ; modified_post_count[8] ;
; NOT_GATE_PUSH_BACK ; ON ; - ; modified_post_count[9] ;
; NOT_GATE_PUSH_BACK ; ON ; - ; modified_post_count[10] ;
; NOT_GATE_PUSH_BACK ; ON ; - ; modified_post_count[11] ;
; NOT_GATE_PUSH_BACK ; ON ; - ; modified_post_count[12] ;
; NOT_GATE_PUSH_BACK ; ON ; - ; modified_post_count[13] ;
; NOT_GATE_PUSH_BACK ; ON ; - ; modified_post_count[14] ;
+--------------------+-------+------+----------------------------------------------------------------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_kps3:auto_generated ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_kps3:auto_generated|altsyncram_3eq1:altsyncram1 ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|LPM_COUNTER:\adv_point_3_and_more:advance_pointer_counter ;
+---------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SUPPRESS_DA_RULE_INTERNAL ; a101 ; - ; - ;
; SUPPRESS_DA_RULE_INTERNAL ; s102 ; - ; - ;
; SUPPRESS_DA_RULE_INTERNAL ; s103 ; - ; - ;
+---------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|LPM_COUNTER:read_pointer_counter ;
+---------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SUPPRESS_DA_RULE_INTERNAL ; a101 ; - ; - ;
; SUPPRESS_DA_RULE_INTERNAL ; s102 ; - ; - ;
; SUPPRESS_DA_RULE_INTERNAL ; s103 ; - ; - ;
+---------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|LPM_COUNTER:status_advance_pointer_counter ;
+---------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SUPPRESS_DA_RULE_INTERNAL ; a101 ; - ; - ;
; SUPPRESS_DA_RULE_INTERNAL ; s102 ; - ; - ;
; SUPPRESS_DA_RULE_INTERNAL ; s103 ; - ; - ;
+---------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|LPM_COUNTER:status_read_pointer_counter ;
+---------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SUPPRESS_DA_RULE_INTERNAL ; a101 ; - ; - ;
; SUPPRESS_DA_RULE_INTERNAL ; s102 ; - ; - ;
; SUPPRESS_DA_RULE_INTERNAL ; s103 ; - ; - ;
+---------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+-------------------------------------------------------------------------------------------------------------------+
; Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr ;
+----------------------+-------+------+-----------------------------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+----------------------+-------+------+-----------------------------------------------------------------------------+
; AUTO_ROM_RECOGNITION ; OFF ; - ; - ;
+----------------------+-------+------+-----------------------------------------------------------------------------+
+-------------------------------------------------------+
; Source assignments for sld_hub:auto_hub ;
+------------------------------+-------+------+---------+
; Assignment ; Value ; From ; To ;
+------------------------------+-------+------+---------+
; IGNORE_LCELL_BUFFERS ; OFF ; - ; - ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; OFF ; - ; - ;
; NOT_GATE_PUSH_BACK ; OFF ; - ; clr_reg ;
; POWER_UP_LEVEL ; LOW ; - ; clr_reg ;
+------------------------------+-------+------+---------+
+-----------------------------------------------------------------+
; Source assignments for sld_hub:auto_hub|sld_rom_sr:hub_info_reg ;
+----------------------+-------+------+---------------------------+
; Assignment ; Value ; From ; To ;
+----------------------+-------+------+---------------------------+
; AUTO_ROM_RECOGNITION ; OFF ; - ; - ;
+----------------------+-------+------+---------------------------+
+-------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: sld_signaltap:auto_signaltap_0 ;
+-------------------------------------------------+------------------------------------------------------+----------------+
; Parameter Name ; Value ; Type ;
+-------------------------------------------------+------------------------------------------------------+----------------+
; lpm_type ; sld_signaltap ; String ;
; sld_node_info ; 805334528 ; Untyped ;
; SLD_IP_VERSION ; 6 ; Signed Integer ;
; SLD_IP_MINOR_VERSION ; 0 ; Signed Integer ;
; SLD_COMMON_IP_VERSION ; 0 ; Signed Integer ;
; sld_data_bits ; 8 ; Untyped ;
; sld_trigger_bits ; 8 ; Untyped ;
; SLD_NODE_CRC_BITS ; 32 ; Signed Integer ;
; sld_node_crc_hiword ; 15127 ; Untyped ;
; sld_node_crc_loword ; 33202 ; Untyped ;
; SLD_INCREMENTAL_ROUTING ; 0 ; Signed Integer ;
; sld_sample_depth ; 16384 ; Untyped ;
; sld_segment_size ; 16384 ; Untyped ;
; SLD_RAM_BLOCK_TYPE ; AUTO ; String ;
; sld_state_bits ; 11 ; Untyped ;
; sld_buffer_full_stop ; 1 ; Untyped ;
; SLD_MEM_ADDRESS_BITS ; 7 ; Signed Integer ;
; SLD_DATA_BIT_CNTR_BITS ; 4 ; Signed Integer ;
; sld_trigger_level ; 1 ; Untyped ;
; sld_trigger_in_enabled ; 0 ; Untyped ;
; sld_advanced_trigger_entity ; basic,1, ; Untyped ;
; sld_trigger_level_pipeline ; 1 ; Untyped ;
; sld_enable_advanced_trigger ; 0 ; Untyped ;
; SLD_ADVANCED_TRIGGER_1 ; NONE ; String ;
; SLD_ADVANCED_TRIGGER_2 ; NONE ; String ;
; SLD_ADVANCED_TRIGGER_3 ; NONE ; String ;
; SLD_ADVANCED_TRIGGER_4 ; NONE ; String ;
; SLD_ADVANCED_TRIGGER_5 ; NONE ; String ;
; SLD_ADVANCED_TRIGGER_6 ; NONE ; String ;
; SLD_ADVANCED_TRIGGER_7 ; NONE ; String ;
; SLD_ADVANCED_TRIGGER_8 ; NONE ; String ;
; SLD_ADVANCED_TRIGGER_9 ; NONE ; String ;
; SLD_ADVANCED_TRIGGER_10 ; NONE ; String ;
; sld_inversion_mask_length ; 52 ; Untyped ;
; sld_inversion_mask ; 0000000000000000000000000000000000000000000000000000 ; Untyped ;
; sld_power_up_trigger ; 0 ; Untyped ;
; SLD_STATE_FLOW_MGR_ENTITY ; state_flow_mgr_entity.vhd ; String ;
; sld_state_flow_use_generated ; 0 ; Untyped ;
; sld_current_resource_width ; 1 ; Untyped ;
; sld_attribute_mem_mode ; OFF ; Untyped ;
; SLD_STORAGE_QUALIFIER_BITS ; 1 ; Signed Integer ;
; SLD_STORAGE_QUALIFIER_GAP_RECORD ; 0 ; Signed Integer ;
; SLD_STORAGE_QUALIFIER_MODE ; OFF ; String ;
; SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION ; 0 ; Signed Integer ;
; sld_storage_qualifier_inversion_mask_length ; 0 ; Untyped ;
; SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY ; basic ; String ;
; SLD_STORAGE_QUALIFIER_PIPELINE ; 0 ; Signed Integer ;
+-------------------------------------------------+------------------------------------------------------+----------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: sld_hub:auto_hub ;
+--------------------------+----------------------------------+-----------------+
; Parameter Name ; Value ; Type ;
+--------------------------+----------------------------------+-----------------+
; sld_hub_ip_version ; 1 ; Untyped ;
; sld_hub_ip_minor_version ; 4 ; Untyped ;
; sld_common_ip_version ; 0 ; Untyped ;
; device_family ; Cyclone II ; Untyped ;
; n_nodes ; 1 ; Untyped ;
; n_sel_bits ; 1 ; Untyped ;
; n_node_ir_bits ; 8 ; Untyped ;
; node_info ; 00110000000000000110111000000000 ; Unsigned Binary ;
; compilation_mode ; 1 ; Untyped ;
; BROADCAST_FEATURE ; 1 ; Signed Integer ;
; FORCE_IR_CAPTURE_FEATURE ; 1 ; Signed Integer ;
+--------------------------+----------------------------------+-----------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SignalTap II Logic Analyzer Settings ;
+----------------+------------------+---------------------+------------------+--------------+----------+----------------------+--------------------+-----------------------------+-----------------+------------------+--------------------------+
; Instance Index ; Instance Name ; Trigger Input Width ; Data Input Width ; Sample Depth ; Segments ; Trigger Flow Control ; Trigger Conditions ; Advanced Trigger Conditions ; Trigger In Used ; Trigger Out Used ; Power-Up Trigger Enabled ;
+----------------+------------------+---------------------+------------------+--------------+----------+----------------------+--------------------+-----------------------------+-----------------+------------------+--------------------------+
; 0 ; auto_signaltap_0 ; 8 ; 8 ; 16384 ; 1 ; sequential ; 1 ; 0 ; no ; no ; no ;
+----------------+------------------+---------------------+------------------+--------------+----------+----------------------+--------------------+-----------------------------+-----------------+------------------+--------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Connections to In-System Debugging Instance "auto_signaltap_0" ;
+--------------+---------------+-----------+----------------+-------------------+-------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Name ; Type ; Status ; Partition Name ; Netlist Type Used ; Actual Connection ; Details ;
+--------------+---------------+-----------+----------------+-------------------+-------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; beat ; pre-synthesis ; missing ; Top ; post-synthesis ; GND ; The name does not exist in your design or refers to an invalid hierarchy or bus element. You may have modified your design after creating the debug instance. ;
; beat ; pre-synthesis ; missing ; Top ; post-synthesis ; GND ; The name does not exist in your design or refers to an invalid hierarchy or bus element. You may have modified your design after creating the debug instance. ;
; clk ; pre-synthesis ; connected ; Top ; post-synthesis ; clk ; N/A ;
; count2[0] ; pre-synthesis ; missing ; Top ; post-synthesis ; GND ; The name does not exist in your design or refers to an invalid hierarchy or bus element. You may have modified your design after creating the debug instance. ;
; count2[0] ; pre-synthesis ; missing ; Top ; post-synthesis ; GND ; The name does not exist in your design or refers to an invalid hierarchy or bus element. You may have modified your design after creating the debug instance. ;
; count2[1] ; pre-synthesis ; missing ; Top ; post-synthesis ; GND ; The name does not exist in your design or refers to an invalid hierarchy or bus element. You may have modified your design after creating the debug instance. ;
; count2[1] ; pre-synthesis ; missing ; Top ; post-synthesis ; GND ; The name does not exist in your design or refers to an invalid hierarchy or bus element. You may have modified your design after creating the debug instance. ;
; count2[2] ; pre-synthesis ; missing ; Top ; post-synthesis ; GND ; The name does not exist in your design or refers to an invalid hierarchy or bus element. You may have modified your design after creating the debug instance. ;
; count2[2] ; pre-synthesis ; missing ; Top ; post-synthesis ; GND ; The name does not exist in your design or refers to an invalid hierarchy or bus element. You may have modified your design after creating the debug instance. ;
; count2[3] ; pre-synthesis ; missing ; Top ; post-synthesis ; GND ; The name does not exist in your design or refers to an invalid hierarchy or bus element. You may have modified your design after creating the debug instance. ;
; count2[3] ; pre-synthesis ; missing ; Top ; post-synthesis ; GND ; The name does not exist in your design or refers to an invalid hierarchy or bus element. You may have modified your design after creating the debug instance. ;
; count2[4] ; pre-synthesis ; missing ; Top ; post-synthesis ; GND ; The name does not exist in your design or refers to an invalid hierarchy or bus element. You may have modified your design after creating the debug instance. ;
; count2[4] ; pre-synthesis ; missing ; Top ; post-synthesis ; GND ; The name does not exist in your design or refers to an invalid hierarchy or bus element. You may have modified your design after creating the debug instance. ;
; reset ; pre-synthesis ; connected ; Top ; post-synthesis ; reset ; N/A ;
; reset ; pre-synthesis ; connected ; Top ; post-synthesis ; reset ; N/A ;
; tempo_enable ; pre-synthesis ; connected ; Top ; post-synthesis ; tempo_enable ; N/A ;
; tempo_enable ; pre-synthesis ; connected ; Top ; post-synthesis ; tempo_enable ; N/A ;
+--------------+---------------+-----------+----------------+-------------------+-------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Full Version
Info: Processing started: Thu Apr 09 18:49:59 2015
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off g04_lab03 -c g04_lab03
Info: Parallel compilation is enabled and will use 4 of the 4 processors detected
Info: Found 2 design units, including 1 entities, in source file g04_tempo.vhd
Info: Found design unit 1: g04_tempo-implementation
Info: Found entity 1: g04_tempo
Info: Found 2 design units, including 1 entities, in source file test.vhd
Info: Found design unit 1: test-SYN
Info: Found entity 1: test
Info: Found 2 design units, including 1 entities, in source file g04_bin2bcd.vhd
Info: Found design unit 1: g04_bin2bcd-implementation
Info: Found entity 1: g04_bin2bcd
Info: Found 2 design units, including 1 entities, in source file g04_7_segment_decoder.vhd
Info: Found design unit 1: g04_7_segment_decoder-implementation
Info: Found entity 1: g04_7_segment_decoder
Info: Found 2 design units, including 1 entities, in source file g04_integration.vhd
Info: Found design unit 1: g04_integration-implementation
Info: Found entity 1: g04_integration
Info: Found 2 design units, including 1 entities, in source file g04_note_timer.vhd
Info: Found design unit 1: g04_note_timer-implementation
Info: Found entity 1: g04_note_timer
Info: Found 2 design units, including 1 entities, in source file altera_up_flash_memory_controller.vhd
Info: Found design unit 1: Altera_UP_Flash_Memory_Controller-rtl
Info: Found entity 1: Altera_UP_Flash_Memory_Controller
Info: Found 2 design units, including 1 entities, in source file altera_up_flash_memory_ip_core_standalone.vhd
Info: Found design unit 1: Slowed_Altera_UP_Flash_Memory_UP_Core_Standalone-rtl
Info: Found entity 1: Slowed_Altera_UP_Flash_Memory_UP_Core_Standalone
Info: Found 2 design units, including 1 entities, in source file altera_up_flash_memory_user_interface.vhd
Info: Found design unit 1: Altera_UP_Flash_Memory_User_Interface-rtl
Info: Found entity 1: Altera_UP_Flash_Memory_User_Interface
Info: Found 2 design units, including 1 entities, in source file g04_audio_interface.vhd
Info: Found design unit 1: g00_audio_interface-a
Info: Found entity 1: g00_audio_interface
Info: Found 2 design units, including 1 entities, in source file g04_fsm_controller.vhd
Info: Found design unit 1: g04_FSM_Controller-a
Info: Found entity 1: g04_FSM_Controller
Info: Found 2 design units, including 1 entities, in source file g04_altera_display.vhd
Info: Found design unit 1: g04_altera_display-bdf_type
Info: Found entity 1: g04_altera_display
Info: Found 2 design units, including 1 entities, in source file g04_read_flash_control.vhd
Info: Found design unit 1: g04_flash_read_control-a
Info: Found entity 1: g04_flash_read_control
Info: Elaborating entity "g04_note_timer" for the top level hierarchy
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_kps3.tdf
Info: Found entity 1: altsyncram_kps3
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_3eq1.tdf
Info: Found entity 1: altsyncram_3eq1
Info: Found 1 design units, including 1 entities, in source file db/decode_4oa.tdf
Info: Found entity 1: decode_4oa
Info: Found 1 design units, including 1 entities, in source file db/mux_kib.tdf
Info: Found entity 1: mux_kib
Info: Found 1 design units, including 1 entities, in source file db/mux_foc.tdf
Info: Found entity 1: mux_foc
Info: Found 1 design units, including 1 entities, in source file db/decode_rqf.tdf
Info: Found entity 1: decode_rqf
Info: Found 1 design units, including 1 entities, in source file db/cntr_dai.tdf
Info: Found entity 1: cntr_dai
Info: Found 1 design units, including 1 entities, in source file db/cntr_p6j.tdf
Info: Found entity 1: cntr_p6j
Info: Found 1 design units, including 1 entities, in source file db/cntr_2ci.tdf
Info: Found entity 1: cntr_2ci
Info: Found 1 design units, including 1 entities, in source file db/cmpr_9cc.tdf
Info: Found entity 1: cmpr_9cc
Info: Found 1 design units, including 1 entities, in source file db/cntr_gui.tdf
Info: Found entity 1: cntr_gui
Info: Found 1 design units, including 1 entities, in source file db/cmpr_5cc.tdf
Info: Found entity 1: cmpr_5cc
Info: Analysis and Synthesis generated SignalTap II or debug node instance "auto_signaltap_0"
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Critical Warning: Partially connected in-system debug instance "auto_signaltap_0" to 5 of its 17 required data inputs, trigger inputs, acquisition clocks, and dynamic pins. There were 0 illegal, 0 inaccessible, and 12 missing sources or connections.
Info: Implemented 794 device resources after synthesis - the final resource count might be different
Info: Implemented 10 input pins
Info: Implemented 2 output pins
Info: Implemented 749 logic cells
Info: Implemented 32 RAM segments
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 1 warning
Info: Peak virtual memory: 338 megabytes
Info: Processing ended: Thu Apr 09 18:50:20 2015
Info: Elapsed time: 00:00:21
Info: Total CPU time (on all processors): 00:00:09