tcl: fix esp riscv configs

Fixes tcl configs to enable esp RISC-V boards Signed-off-by: Samuel Obuch <samuel.obuch@espressif.com>
riscv-collab · Jan 13, 2025 · 16f6f1e · 16f6f1e
1 parent f82c5a7
commit 16f6f1e
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Showing 5 changed files with 14 additions and 7 deletions.
diff --git a/tcl/target/esp32c2.cfg b/tcl/target/esp32c2.cfg
@@ -5,7 +5,7 @@
 source [find target/esp_common.cfg]
 
 # Target specific global variables
-set _CHIPNAME 					"riscv"
+set _CHIPNAME 					"esp32c2"
 set _CPUTAPID 					0x0000cc25
 set _ESP_ARCH 					"riscv"
 set _ONLYCPU					1

diff --git a/tcl/target/esp32c3.cfg b/tcl/target/esp32c3.cfg
@@ -5,7 +5,7 @@
 source [find target/esp_common.cfg]
 
 # Target specific global variables
-set _CHIPNAME 					"riscv"
+set _CHIPNAME 					"esp32c3"
 set _CPUTAPID 					0x00005c25
 set _ESP_ARCH					"riscv"
 set _ONLYCPU					1

diff --git a/tcl/target/esp32c6.cfg b/tcl/target/esp32c6.cfg
@@ -5,7 +5,7 @@
 source [find target/esp_common.cfg]
 
 # Target specific global variables
-set _CHIPNAME 					"riscv"
+set _CHIPNAME 					"esp32c6"
 set _CPUTAPID 					0x0000dc25
 set _ESP_ARCH					"riscv"
 set _ONLYCPU					1

diff --git a/tcl/target/esp32h2.cfg b/tcl/target/esp32h2.cfg
@@ -5,7 +5,7 @@
 source [find target/esp_common.cfg]
 
 # Target specific global variables
-set _CHIPNAME 					"riscv"
+set _CHIPNAME 					"esp32h2"
 set _CPUTAPID 					0x00010c25
 set _ESP_ARCH					"riscv"
 set _ONLYCPU					1

diff --git a/tcl/target/esp_common.cfg b/tcl/target/esp_common.cfg
@@ -33,6 +33,7 @@ proc set_esp_common_variables { } {
 	global _CHIPNAME _ONLYCPU _ESP_SMP_TARGET
 	global _CPUNAME_0 _CPUNAME_1 _TARGETNAME_0 _TARGETNAME_1 _TAPNAME_0 _TAPNAME_1
 	global _ESP_WDT_DISABLE _ESP_SOC_RESET _ESP_MEMPROT_IS_ENABLED
+	global _TARGET_TYPE _ESP_ARCH
 
 	# For now we support dual core at most.
 	if { $_ONLYCPU == 1 && $_ESP_SMP_TARGET == 0} {
@@ -51,6 +52,12 @@ proc set_esp_common_variables { } {
 	set _ESP_WDT_DISABLE 			"${_CHIPNAME}_wdt_disable"
 	set _ESP_SOC_RESET 				"${_CHIPNAME}_soc_reset"
 	set _ESP_MEMPROT_IS_ENABLED 	"${_CHIPNAME}_memprot_is_enabled"
+
+	if {$_ESP_ARCH == "riscv"} {
+		set _TARGET_TYPE $_ESP_ARCH
+	} else {
+		set _TARGET_TYPE $_CHIPNAME
+	}
 }
 
 proc create_esp_jtag { } {
@@ -64,11 +71,11 @@ proc create_esp_jtag { } {
 }
 
 proc create_openocd_targets  { } {
-	global _TARGETNAME_0 _TARGETNAME_1 _TAPNAME_0 _TAPNAME_1 _RTOS _CHIPNAME _ONLYCPU
+	global _TARGETNAME_0 _TARGETNAME_1 _TAPNAME_0 _TAPNAME_1 _RTOS _CHIPNAME _ONLYCPU _TARGET_TYPE
 
-	target create $_TARGETNAME_0 $_CHIPNAME -chain-position $_TAPNAME_0 -coreid 0 -rtos $_RTOS
+	target create $_TARGETNAME_0 $_TARGET_TYPE -chain-position $_TAPNAME_0 -coreid 0 -rtos $_RTOS
 	if { $_ONLYCPU != 1 } {
-		target create $_TARGETNAME_1 $_CHIPNAME -chain-position $_TAPNAME_1 -coreid 1 -rtos $_RTOS
+		target create $_TARGETNAME_1 $_TARGET_TYPE -chain-position $_TAPNAME_1 -coreid 1 -rtos $_RTOS
 		target smp $_TARGETNAME_0 $_TARGETNAME_1
 	}
 }