From cdedaa5ce49b05786f1065fdd9c06e0e11297e90 Mon Sep 17 00:00:00 2001 From: Pavel Pisa Date: Thu, 4 Jul 2024 16:13:38 +0200 Subject: [PATCH] CTU Computer Architectures course correct university link and add QtRvSim online links Signed-off-by: Pavel Pisa --- README.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index 0aa4bca..12de963 100644 --- a/README.md +++ b/README.md @@ -68,7 +68,7 @@ For those with little or no knowledge of digital logic design. After studying th |---|---|---|---|---| | **Digital Design and Computer Architecture RISC-V edition** (good starting point) | Sarah L. Harris, David M. Harris | Covers the foundational knowledge of digital logic design and segues smoothly into RISC-V Processor implementation.

Topics: Number systems and digital representation, Semiconductors and transistors, Logic gates and Digital design, C Programming, RISC-V architecture, RISC-V assembly, Memory systems, Embedded I/O systems | [Amazon book link]| 2024-01-10 | | **The RISC-V Reader: An Open Architecture Atlas** | David Patterson, Andrew Waterman| A beginner-friendly introduction to the RISC-V instruction set architecture as readers can start programming after the 2nd chapter.

Topics: Computer architecture, RISC-V Instruction Set Architecture (ISA) | [Available in Chineses, Japanese, Spanish, Portuguese and Korean]| 2024-03-05 | -|**Computer Architecture Basics** | [CTU Prague](https://cw.fel.cvut.cz/wiki/start) | This course introduces the fundamentals of computer architecture, covering topics such as binary number representation, CPU design, memory hierarchy, pipelined execution, and speculative execution techniques.

Topics: Computer architecture
| [Online course videos]| 2024-04-16 | +|**Computer Architecture Basics** | [CTU Prague - FEE](https://fel.cvut.cz/en) (Pavel Pisa) | This course introduces the fundamentals of computer architecture, covering topics such as binary number representation, CPU design, memory hierarchy, pipelined execution, and speculative execution techniques. It is paired with QtRvSim for demonstrations.

Topics: Computer architecture
| [Online course videos]| 2024-04-16 | | **Nand2Tetris** (optional) | Noam Nisan, Shimon Schocken | A free hands-on tutorial on building a general-purpose computer from logic gates using a hardware simulator.

Topics: Logic gates|[webpage] | 2024-01-10 | |**learn-FPGA episode I: from blinky to RISC-V**|[BrunoLevy](https://github.com/BrunoLevy)|A beginner's introduction to the digital design of a RISC-V softcore on FPGAs. Episode I gently starts from a very basic blinker in Verilog and morphs it step by step into a basic yet fully functional RISC-V SoC. It also explains how to write programs in C and assembly for the SoC.

Topics: Digital design, FPGA, C Programming, RISC-V assembly
Requirement: Basic knowledge of Verilog|[GitHub]| 2024-01-10 | |**Hands-on RISC-V Processor Design**|[Rahul Behl](https://github.com/raulbehl)|This practical tutorial offers a deep dive into the world of computer architecture and processor design, with a specific focus on the RISC-V Instruction Set Architecture (ISA).

Topics: Computer architecture, Processor design, RISC-V Instruction Set Architecture (ISA), SystemVerilog, RISC-V assembly
Requirements: SystemVerilog but not necessary|[webpage] | 2024-01-10 | @@ -108,7 +108,7 @@ A collection of tools that can be used along with the beginner or intermediate-l | **emulsiV** | Guillaume Savaton, ESEO | emulsiV is a visual simulator for a simple RISC processor called Virgule. Virgule is a 32-bit RISC processor core that implements a minimal subset of the RISC-V instruction set. Here, “minimal” means that Virgule accepts only the instructions that a C compiler would generate from a pure stand-alone C program. | [website] | 2023-20-12 | | **RISC-V Instruction Encoder/Decoder** | LupLab @ University of California, Davis | This tool is an online encoder/decoder for RISC-V instructions. Users can input RISC-V instructions in their assembly or binary format and get the full conversion from one to the other. | [website] | 2023-20-12 | | **CREATOR** | Diego Camarmas Alonso,Félix García Carballeira,Alejandro Calderón Mateos,Elías del Pozo Puñal | CREATOR is a didactic simulator that allows the development, simulation, and debugging of RISC-V (RV32IMFD) assembly programs intuitively and interactively. It is a web application, so it can be used on any type of device (desktop, tablet, smartphone, etc.) without installing additional software. Only a modern web browser (Google Chrome, Mozilla Firefox, Apple Safari, etc.) is required. | [website] | 2023-20-12 | -| **QtRvSim** - RISC-V CPU Simulator with Cache and Pipeline Visualization | Computer Architectures Education project at Czech Technical University | QtRvSim is educational simulator with pipeline and cache visualization (RV32IMA/RV64IMA). It supports even M-mode ecalls, ACLINT MTIMER, MSWI, SSWI, related CSR registers, serial port Rx and Tx interrupts and more. | [Github] | 2023-20-12 | +| **QtRvSim** - RISC-V CPU Simulator with Cache and Pipeline Visualization | Computer Architectures Education team at Czech Technical University | QtRvSim is educational simulator with pipeline and cache visualization (RV32IMA/RV64IMA). It supports even M-mode ecalls, ACLINT MTIMER, MSWI, SSWI, related CSR registers, serial port Rx and Tx interrupts and more. | [Github] and [Online] | 2023-20-12 | | **RVV intrinsics viewer** | dzaima | A third party documentation website for the vector extension intrinsics, currently including pretty much all intrinsics variations, and fuzzy search. This can be a useful resource when writing rvv code. | [website] | 2023-20-12 | #### Open RISC-V Implementations