From 2cf4a5248296806e178ea4f8c3eac866eada213e Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Wed, 2 Oct 2024 18:25:23 -0500 Subject: [PATCH] G-stage PTE D-bit update relaxation --- src/supervisor.adoc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/supervisor.adoc b/src/supervisor.adoc index 5d93955f1..8ad8fe51d 100644 --- a/src/supervisor.adoc +++ b/src/supervisor.adoc @@ -1442,8 +1442,9 @@ Two schemes to manage the A and D bits are defined: architecturally. However, updates to the D bit, resulting from an explicit store, must be exact (i.e., non-speculative), and observed in program order by the local hart. When two-stage address translation is - active, updates of the D bit in G-stage PTEs may be performed as a - result of speculative updates of the A bit in VS-stage PTEs. + + active, updates to the D bit in G-stage PTEs may be performed by an + implicit access to a VS-stage PTE, if the G-stage PTE provides write + permission, before any speculative access to the VS-stage PTE. + + The PTE update must appear in the global memory order before the memory access that caused the PTE update and before any subsequent