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Encrypt_map.mrp
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Release 14.7 Map P.20131013 (lin64)
Xilinx Mapping Report File for Design 'Encrypt'
Design Information
------------------
Command Line : map -intstyle ise -p xc3s400-pq208-4 -cm area -ir off -pr off
-c 100 -o Encrypt_map.ncd Encrypt.ngd Encrypt.pcf
Target Device : xc3s400
Target Package : pq208
Target Speed : -4
Mapper Version : spartan3 -- $Revision: 1.55 $
Mapped Date : Sat Mar 24 12:50:04 2018
ERROR:Pack:18 - The design is too large for the given device and package.
Please check the Design Summary section to see which resource requirement for
your design exceeds the resources available in the device.
NOTE: An NCD file will still be generated to allow you to examine the mapped
design. This file is intended for evaluation use only, and will not process
successfully through PAR.
This mapped NCD file can be used to evaluate how the design's logic has been
mapped into FPGA logic resources. It can also be used to analyze
preliminary, logic-level (pre-route) timing with one of the Xilinx static
timing analysis tools (TRCE or Timing Analyzer).
Design Summary
--------------
Number of errors: 2
Number of warnings: 2
Logic Utilization:
Number of Slice Latches: 390 out of 7,168 5%
Number of 4 input LUTs: 1,084 out of 7,168 15%
Logic Distribution:
Number of occupied Slices: 555 out of 3,584 15%
Number of Slices containing only related logic: 555 out of 555 100%
Number of Slices containing unrelated logic: 0 out of 555 0%
*See NOTES below for an explanation of the effects of unrelated logic.
Total Number of 4 input LUTs: 1,084 out of 7,168 15%
Number of bonded IOBs: 385 out of 141 273% (OVERMAPPED)
IOB Latches: 256
Number of BUFGMUXs: 4 out of 8 50%
Average Fanout of Non-Clock Nets: 2.89
Peak Memory Usage: 555 MB
Total REAL time to MAP completion: 3 secs
Total CPU time to MAP completion: 3 secs
NOTES:
Related logic is defined as being logic that shares connectivity - e.g. two
LUTs are "related" if they share common inputs. When assembling slices,
Map gives priority to combine logic that is related. Doing so results in
the best timing performance.
Unrelated logic shares no connectivity. Map will only begin packing
unrelated logic into a slice once 99% of the slices are occupied through
related logic packing.
Note that once logic distribution reaches the 99% level through related
logic packing, this does not mean the device is completely utilized.
Unrelated logic packing will then begin, continuing until all usable LUTs
and FFs are occupied. Depending on your timing budget, increased levels of
unrelated logic packing may adversely affect the overall timing performance
of your design.
Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Timing Report
Section 11 - Configuration String Information
Section 12 - Control Set Information
Section 13 - Utilization by Hierarchy
Section 1 - Errors
------------------
ERROR:Pack:2309 - Too many bonded comps of type "IOB" found to fit this device.
ERROR:Pack:18 - The design is too large for the given device and package.
Please check the Design Summary section to see which resource requirement for
your design exceeds the resources available in the device.
NOTE: An NCD file will still be generated to allow you to examine the mapped
design. This file is intended for evaluation use only, and will not process
successfully through PAR.
This mapped NCD file can be used to evaluate how the design's logic has been
mapped into FPGA logic resources. It can also be used to analyze
preliminary, logic-level (pre-route) timing with one of the Xilinx static
timing analysis tools (TRCE or Timing Analyzer).
Section 2 - Warnings
--------------------
WARNING:PhysDesignRules:372 - Gated clock. Clock net update_type_not0001 is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net counter_or0000 is sourced
by a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
Section 3 - Informational
-------------------------
INFO:LIT:243 - Logical network next has no load.
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
can be dramatically reduced by designating them as fast outputs.
Section 4 - Removed Logic Summary
---------------------------------
2 block(s) optimized away
Section 5 - Removed Logic
-------------------------
Optimized Block(s):
TYPE BLOCK
GND XST_GND
VCC XST_VCC
To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.
Section 6 - IOB Properties
--------------------------
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB |
| | | | | Term | Strength | Rate | | | Delay |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| Block<0> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<1> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<2> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<3> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<4> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<5> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<6> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<7> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<8> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<9> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<10> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<11> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<12> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<13> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<14> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<15> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<16> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<17> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<18> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<19> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<20> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<21> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<22> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<23> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<24> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<25> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<26> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<27> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<28> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<29> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<30> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<31> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<32> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<33> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<34> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<35> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<36> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<37> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<38> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<39> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<40> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<41> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<42> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<43> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<44> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<45> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<46> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<47> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<48> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<49> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<50> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<51> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<52> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<53> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<54> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<55> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<56> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<57> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<58> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<59> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<60> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<61> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<62> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<63> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<64> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<65> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<66> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<67> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<68> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<69> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<70> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<71> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<72> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<73> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<74> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<75> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<76> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<77> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<78> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<79> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<80> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<81> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<82> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<83> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<84> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<85> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<86> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<87> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<88> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<89> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<90> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<91> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<92> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<93> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<94> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<95> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<96> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<97> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<98> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<99> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<100> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<101> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<102> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<103> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<104> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<105> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<106> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<107> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<108> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<109> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<110> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<111> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<112> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<113> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<114> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<115> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<116> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<117> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<118> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<119> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<120> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<121> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<122> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<123> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<124> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<125> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<126> | IOB | INPUT | LVCMOS25 | | | | | | |
| Block<127> | IOB | INPUT | LVCMOS25 | | | | | | |
| Key<0> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<1> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<2> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<3> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<4> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<5> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<6> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<7> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<8> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<9> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<10> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<11> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<12> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<13> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<14> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<15> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<16> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<17> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<18> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<19> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<20> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<21> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<22> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<23> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<24> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<25> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<26> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<27> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<28> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<29> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<30> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<31> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<32> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<33> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<34> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<35> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<36> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<37> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<38> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<39> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<40> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<41> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<42> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<43> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<44> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<45> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<46> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<47> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<48> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<49> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<50> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<51> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<52> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<53> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<54> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<55> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<56> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<57> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<58> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<59> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<60> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<61> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<62> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<63> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<64> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<65> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<66> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<67> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<68> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<69> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<70> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<71> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<72> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<73> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<74> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<75> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<76> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<77> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<78> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<79> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<80> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<81> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<82> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<83> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<84> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<85> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<86> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<87> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<88> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<89> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<90> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<91> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<92> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<93> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<94> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<95> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<96> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<97> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<98> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<99> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<100> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<101> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<102> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<103> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<104> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<105> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<106> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<107> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<108> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<109> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<110> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<111> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<112> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<113> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<114> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<115> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<116> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<117> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<118> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<119> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<120> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<121> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<122> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<123> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<124> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<125> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<126> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Key<127> | IOB | INPUT | LVCMOS25 | | | | INLATCH1 | | IFD |
| Result<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<8> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<9> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<10> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<11> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<12> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<13> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<14> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<15> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<16> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<17> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<18> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<19> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<20> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<21> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<22> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<23> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<24> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<25> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<26> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<27> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<28> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<29> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<30> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<31> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<32> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<33> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<34> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<35> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<36> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<37> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<38> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<39> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<40> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<41> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<42> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<43> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<44> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<45> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<46> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<47> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<48> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<49> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<50> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<51> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<52> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<53> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<54> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<55> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<56> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<57> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<58> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<59> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<60> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<61> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<62> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<63> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<64> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<65> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<66> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<67> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<68> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<69> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<70> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<71> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<72> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<73> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<74> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<75> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<76> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<77> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<78> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<79> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<80> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<81> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<82> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<83> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<84> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<85> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<86> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<87> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<88> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<89> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<90> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<91> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<92> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<93> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<94> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<95> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<96> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<97> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<98> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<99> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<100> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<101> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<102> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<103> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<104> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<105> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<106> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<107> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<108> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<109> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<110> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<111> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<112> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<113> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<114> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<115> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<116> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<117> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<118> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<119> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<120> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<121> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<122> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<123> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<124> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<125> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<126> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| Result<127> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OLATCH1 | | |
| ready | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
Section 7 - RPMs
----------------
Section 8 - Guide Report
------------------------
Guide not run on this design.
Section 9 - Area Group and Partition Summary
--------------------------------------------
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Area Group Information
----------------------
No area groups were found in this design.
----------------------
Section 10 - Timing Report
--------------------------
This design was not run using timing mode.
Section 11 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings
Section 12 - Control Set Information
------------------------------------
No control set information for this architecture.
Section 13 - Utilization by Hierarchy
-------------------------------------
Use the "-detail" map option to print out the Utilization by Hierarchy section.