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TestBench.cmd_log
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xst -intstyle ise -ifn "/home/superuser/Workspace/Verilog/AES/AES/TestBench.xst" -ofn "/home/superuser/Workspace/Verilog/AES/AES/TestBench.syr"
xst -intstyle ise -ifn "/home/superuser/Workspace/Verilog/AES/AES/TestBench.xst" -ofn "/home/superuser/Workspace/Verilog/AES/AES/TestBench.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc3s400-pq208-4 TestBench.ngc TestBench.ngd
map -intstyle ise -p xc3s400-pq208-4 -cm area -ir off -pr off -c 100 -o TestBench_map.ncd TestBench.ngd TestBench.pcf
ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc3s400-pq208-4 TestBench.ngc TestBench.ngd
map -intstyle ise -p xc3s400-pq208-4 -cm area -ir off -pr off -c 100 -o TestBench_map.ncd TestBench.ngd TestBench.pcf
xst -intstyle ise -ifn "/home/superuser/Workspace/Verilog/AES/AES/TestBench.xst" -ofn "/home/superuser/Workspace/Verilog/AES/AES/TestBench.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s400-pq208-4 TestBench.ngc TestBench.ngd
map -intstyle ise -p xc3s400-pq208-4 -cm area -ir off -pr off -c 100 -o TestBench_map.ncd TestBench.ngd TestBench.pcf
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s400-pq208-4 TestBench.ngc TestBench.ngd
map -intstyle ise -p xc3s400-pq208-4 -cm area -ir off -pr off -c 100 -o TestBench_map.ncd TestBench.ngd TestBench.pcf
par -w -intstyle ise -ol high -t 1 TestBench_map.ncd TestBench.ncd TestBench.pcf
trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml TestBench.twx TestBench.ncd -o TestBench.twr TestBench.pcf -ucf pins.ucf
bitgen -intstyle ise -f TestBench.ut TestBench.ncd
xst -intstyle ise -ifn "/home/superuser/Workspace/Verilog/AES/AES/TestBench.xst" -ofn "/home/superuser/Workspace/Verilog/AES/AES/TestBench.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s400-pq208-4 TestBench.ngc TestBench.ngd
map -intstyle ise -p xc3s400-pq208-4 -cm area -ir off -pr off -c 100 -o TestBench_map.ncd TestBench.ngd TestBench.pcf
par -w -intstyle ise -ol high -t 1 TestBench_map.ncd TestBench.ncd TestBench.pcf
trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml TestBench.twx TestBench.ncd -o TestBench.twr TestBench.pcf -ucf pins.ucf
bitgen -intstyle ise -f TestBench.ut TestBench.ncd
xst -intstyle ise -ifn "/home/superuser/Workspace/Verilog/AES/AES/TestBench.xst" -ofn "/home/superuser/Workspace/Verilog/AES/AES/TestBench.syr"
xst -intstyle ise -ifn "/home/superuser/Workspace/Verilog/AES/AES/TestBench.xst" -ofn "/home/superuser/Workspace/Verilog/AES/AES/TestBench.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s400-pq208-4 TestBench.ngc TestBench.ngd
map -intstyle ise -p xc3s400-pq208-4 -cm area -ir off -pr off -c 100 -o TestBench_map.ncd TestBench.ngd TestBench.pcf
par -w -intstyle ise -ol high -t 1 TestBench_map.ncd TestBench.ncd TestBench.pcf
trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml TestBench.twx TestBench.ncd -o TestBench.twr TestBench.pcf -ucf pins.ucf
bitgen -intstyle ise -f TestBench.ut TestBench.ncd
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s400-pq208-4 TestBench.ngc TestBench.ngd
map -intstyle ise -p xc3s400-pq208-4 -cm area -ir off -pr off -c 100 -o TestBench_map.ncd TestBench.ngd TestBench.pcf
par -w -intstyle ise -ol high -t 1 TestBench_map.ncd TestBench.ncd TestBench.pcf
trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml TestBench.twx TestBench.ncd -o TestBench.twr TestBench.pcf -ucf pins.ucf
bitgen -intstyle ise -f TestBench.ut TestBench.ncd
xst -intstyle ise -ifn "/home/superuser/Workspace/Verilog/AES/AES/TestBench.xst" -ofn "/home/superuser/Workspace/Verilog/AES/AES/TestBench.syr"
xst -intstyle ise -ifn "/home/superuser/Workspace/Verilog/AES/AES/TestBench.xst" -ofn "/home/superuser/Workspace/Verilog/AES/AES/TestBench.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s400-pq208-4 TestBench.ngc TestBench.ngd
map -intstyle ise -p xc3s400-pq208-4 -cm area -ir off -pr off -c 100 -o TestBench_map.ncd TestBench.ngd TestBench.pcf
par -w -intstyle ise -ol high -t 1 TestBench_map.ncd TestBench.ncd TestBench.pcf
trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml TestBench.twx TestBench.ncd -o TestBench.twr TestBench.pcf -ucf pins.ucf
xst -intstyle ise -ifn "/home/superuser/Workspace/Verilog/AES/AES/TestBench.xst" -ofn "/home/superuser/Workspace/Verilog/AES/AES/TestBench.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s400-pq208-4 TestBench.ngc TestBench.ngd
map -intstyle ise -p xc3s400-pq208-4 -cm area -ir off -pr off -c 100 -o TestBench_map.ncd TestBench.ngd TestBench.pcf
par -w -intstyle ise -ol high -t 1 TestBench_map.ncd TestBench.ncd TestBench.pcf
trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml TestBench.twx TestBench.ncd -o TestBench.twr TestBench.pcf -ucf pins.ucf
bitgen -intstyle ise -f TestBench.ut TestBench.ncd
xst -intstyle ise -ifn "/home/superuser/Workspace/Verilog/AES/AES/TestBench.xst" -ofn "/home/superuser/Workspace/Verilog/AES/AES/TestBench.syr"
xst -intstyle ise -ifn "/home/superuser/Workspace/Verilog/AES/AES/TestBench.xst" -ofn "/home/superuser/Workspace/Verilog/AES/AES/TestBench.syr"
xst -intstyle ise -ifn "/home/superuser/Workspace/Verilog/AES/AES/TestBench.xst" -ofn "/home/superuser/Workspace/Verilog/AES/AES/TestBench.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s400-pq208-4 TestBench.ngc TestBench.ngd
map -intstyle ise -p xc3s400-pq208-4 -cm area -ir off -pr off -c 100 -o TestBench_map.ncd TestBench.ngd TestBench.pcf
par -w -intstyle ise -ol high -t 1 TestBench_map.ncd TestBench.ncd TestBench.pcf
trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml TestBench.twx TestBench.ncd -o TestBench.twr TestBench.pcf -ucf pins.ucf
bitgen -intstyle ise -f TestBench.ut TestBench.ncd
xst -intstyle ise -ifn "/home/superuser/Workspace/Verilog/AES/AES/TestBench.xst" -ofn "/home/superuser/Workspace/Verilog/AES/AES/TestBench.syr"
xst -intstyle ise -ifn "/home/superuser/Workspace/Verilog/AES/AES/TestBench.xst" -ofn "/home/superuser/Workspace/Verilog/AES/AES/TestBench.syr"
xst -intstyle ise -ifn "/home/superuser/Workspace/Verilog/AES/AES/TestBench.xst" -ofn "/home/superuser/Workspace/Verilog/AES/AES/TestBench.syr"