From 920d41bd680af5f2438695321f697b7fc4e9d2ce Mon Sep 17 00:00:00 2001 From: Fawaz Tirmizi Date: Tue, 11 Oct 2022 15:15:17 -0700 Subject: [PATCH] Reimplement `register::mtvec` --- CHANGELOG.md | 1 + src/register/addresses.rs | 1 - src/register/mod.rs | 2 +- src/register/mtvec.rs | 90 ++++++++++++++++++++++----------------- 4 files changed, 53 insertions(+), 41 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 8c603949..94c77475 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -10,6 +10,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/). - Replaced CSR macros with new ones using `tock-registers` - Reimplemeted CSR modules using new base functions: - `mcause` + - `mtvec` ## [v0.9.0] - 2022-10-06 diff --git a/src/register/addresses.rs b/src/register/addresses.rs index dd841234..153cefe5 100644 --- a/src/register/addresses.rs +++ b/src/register/addresses.rs @@ -204,7 +204,6 @@ pub const CSR_MEDELEG: u16 = 0x302; pub const CSR_MIDELEG: u16 = 0x303; #[allow(unused)] pub const CSR_MIE: u16 = 0x304; -#[allow(unused)] pub const CSR_MTVEC: u16 = 0x305; #[allow(unused)] pub const CSR_MCOUNTEREN: u16 = 0x306; diff --git a/src/register/mod.rs b/src/register/mod.rs index e32ff923..ad16cc04 100644 --- a/src/register/mod.rs +++ b/src/register/mod.rs @@ -70,7 +70,7 @@ mod addresses; //pub mod mie; //pub mod misa; //pub mod mstatus; -//pub mod mtvec; +pub mod mtvec; // Machine Trap Handling pub mod mcause; diff --git a/src/register/mtvec.rs b/src/register/mtvec.rs index cc77011e..bbfc3c62 100644 --- a/src/register/mtvec.rs +++ b/src/register/mtvec.rs @@ -1,50 +1,62 @@ +// Copyright (c) 2022 by Rivos Inc. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + //! mtvec register -/// mtvec register -#[derive(Clone, Copy, Debug)] -pub struct Mtvec { - bits: usize, +rw_csr!(mtvec, usize); + +register_bitfields![usize, + #[cfg(target_pointer_width = "32")] + pub mtvec [ + mode OFFSET(0) NUMBITS(2) [ + Direct = 0, + Vectored = 1, + ], + base OFFSET(2) NUMBITS(30) [], + ], + #[cfg(target_pointer_width = "64")] + pub mtvec [ + mode OFFSET(0) NUMBITS(2) [ + Direct = 0, + Vectored = 1, + ], + base OFFSET(2) NUMBITS(62) [], + ], +]; + +/// Returns true if the trap vector mode is set to `Direct`. +#[inline] +pub fn is_direct() -> bool { + read_field(mode) == 0x0 } -/// Trap mode -#[derive(Copy, Clone, Debug, Eq, PartialEq)] -pub enum TrapMode { - Direct = 0, - Vectored = 1, +/// Returns true if the trap vector mode is set to `Vectored`. +#[inline] +pub fn is_vectored() -> bool { + read_field(mode) == 0x1 } -impl Mtvec { - /// Returns the contents of the register as raw bits - #[inline] - pub fn bits(&self) -> usize { - self.bits - } - - /// Returns the trap-vector base-address - #[inline] - pub fn address(&self) -> usize { - self.bits - (self.bits & 0b11) - } - - /// Returns the trap-vector mode - #[inline] - pub fn trap_mode(&self) -> Option { - let mode = self.bits & 0b11; - match mode { - 0 => Some(TrapMode::Direct), - 1 => Some(TrapMode::Vectored), - _ => None, - } - } +/// Sets the trap vector mode to `Direct`. +#[inline] +pub fn set_direct() { + let mut local = read_local(); + local.write(mode::Direct); + write_local(local); } -read_csr_as!(Mtvec, 0x305); - -write_csr!(0x305); +/// Sets the trap vector mode to `Vectored`. +#[inline] +pub fn set_vectored() { + let mut local = read_local(); + local.write(mode::Vectored); + write_local(local); +} -/// Writes the CSR +/// Sets the trap vector base. #[inline] -pub unsafe fn write(addr: usize, mode: TrapMode) { - let bits = addr + mode as usize; - _write(bits); +pub fn set_base(base_val: usize) { + let mut local = read_local(); + local.write(base.val(base_val)); + write_local(local); }