diff --git a/Makefile b/Makefile index 2650d4c..24e6050 100644 --- a/Makefile +++ b/Makefile @@ -41,6 +41,7 @@ BINS := \ $(OUT)/os_sifive_u32 \ $(OUT)/os_hifive1_revb \ $(OUT)/os_ox64 \ + $(OUT)/os_star64 \ $(OUT)/os_d1 \ $(OUT)/os_virt @@ -113,6 +114,8 @@ OS_VIRT_DEPS = $(BASE_DEPS) \ src/vm.c OS_OX64_DEPS = $(BASE_DEPS) \ src/machine/ox64/timer.c src/drivers/uart/uart-ox64.c +OS_STAR64_DEPS = $(BASE_DEPS) \ + src/machine/star64/timer.c src/drivers/uart/uart-star64.c OS_D1_DEPS = $(BASE_DEPS) \ src/machine/d1/timer.c src/drivers/uart/uart-d1.c @@ -206,6 +209,18 @@ $(OUT)/os_ox64.bin: $(OUT)/os_ox64 $(OUT)/os_ox64.s: $(OUT)/os_ox64 $(RISCV64_OBJDUMP) --source --all-headers --demangle --line-numbers --wide -D $< > $@ +$(OUT)/os_star64: ${OS_STAR64_DEPS} + $(RISCV64_GCC) -march=rv64g -mabi=lp64 $(GCC_FLAGS) \ + -Wl,--defsym,RAM_START=0x80200000 -g \ + -include include/machine/star64.h \ + ${OS_STAR64_DEPS} -o $@ + +$(OUT)/os_star64.bin: $(OUT)/os_star64 + $(RISCV64_OBJCOPY) -O binary $< $@ + +$(OUT)/os_star64.s: $(OUT)/os_star64 + $(RISCV64_OBJDUMP) --source --all-headers --demangle --line-numbers --wide -D $< > $@ + $(OUT)/os_d1: ${OS_D1_DEPS} $(RISCV64_GCC) -march=rv64g -mabi=lp64 $(GCC_FLAGS) \ -Wl,--defsym,RAM_START=0x40200000 -g \ diff --git a/docs/star64-boot.md b/docs/star64-boot.md new file mode 100644 index 0000000..1b12d18 --- /dev/null +++ b/docs/star64-boot.md @@ -0,0 +1,25 @@ +# Booting Pine64 Star64 + +### Connecting + +TODO + +### Regular boot + +1. Run picocom with gkermit (`scripts/star64-term.sh` does that) +1. Interrupt U-Boot into its shell + * i.e. hit any key when it does the countdown: `Hit any key to stop autoboot: 2` +1. Run `loadb
` in U-Boot shell: + * `loadb 80200000 115200` +1. When it says `Ready for binary (kermit) download to 0x80200000 at 115200 bps...`, + hit Ctrl-A, Ctrl-S to get it to prompt for a file, then type out the file name: + * `*** file: out/os_d1.bin` +1. When done loading, it will get back to U-Boot prompt, it’s time to boot: + * `booti 0x80200000 - fffc6aa0 + +Commands repeated here for more convenient copy-pasting: +``` +loadb 80200000 115200 +out/os_star64.bin +booti 0x80200000 - fffc6aa0 +``` diff --git a/docs/star64.dts b/docs/star64.dts new file mode 100644 index 0000000..3234fb2 --- /dev/null +++ b/docs/star64.dts @@ -0,0 +1,1489 @@ +/* +Obtained from the device itself (burned into the EEPROM?) with this U-Boot +command: + + StarFive # fdt print + +*/ + +/ { + compatible = "starfive,jh7110"; + #address-cells = <0x00000002>; + #size-cells = <0x00000002>; + model = "StarFive VisionFive V2"; + osc { + compatible = "fixed-clock"; + #clock-cells = <0x00000000>; + clock-frequency = <0x016e3600>; + u-boot,dm-spl; + phandle = <0x00000008>; + }; + gmac1_rmii_refin { + compatible = "fixed-clock"; + #clock-cells = <0x00000000>; + clock-frequency = <0x02faf080>; + u-boot,dm-spl; + phandle = <0x00000009>; + }; + gmac1_rgmii_rxin { + compatible = "fixed-clock"; + #clock-cells = <0x00000000>; + clock-frequency = <0x07735940>; + phandle = <0x00000021>; + }; + i2stx_bclk_ext { + compatible = "fixed-clock"; + #clock-cells = <0x00000000>; + clock-frequency = <0x00bb8000>; + phandle = <0x00000022>; + }; + i2stx_lrck_ext { + compatible = "fixed-clock"; + #clock-cells = <0x00000000>; + clock-frequency = <0x0002ee00>; + phandle = <0x00000023>; + }; + i2srx_bclk_ext { + compatible = "fixed-clock"; + #clock-cells = <0x00000000>; + clock-frequency = <0x00bb8000>; + phandle = <0x00000024>; + }; + i2srx_lrck_ext { + compatible = "fixed-clock"; + #clock-cells = <0x00000000>; + clock-frequency = <0x0002ee00>; + phandle = <0x00000025>; + }; + tdm_ext { + compatible = "fixed-clock"; + #clock-cells = <0x00000000>; + clock-frequency = <0x02ee0000>; + phandle = <0x00000026>; + }; + mclk_ext { + compatible = "fixed-clock"; + #clock-cells = <0x00000000>; + clock-frequency = <0x02ee0000>; + phandle = <0x00000027>; + }; + jtag_tck_inner { + compatible = "fixed-clock"; + #clock-cells = <0x00000000>; + clock-frequency = <0x02faf080>; + phandle = <0x00000028>; + }; + bist_apb { + compatible = "fixed-clock"; + #clock-cells = <0x00000000>; + clock-frequency = <0x02faf080>; + phandle = <0x00000029>; + }; + stg_apb { + compatible = "fixed-clock"; + #clock-cells = <0x00000000>; + clock-frequency = <0x030d4000>; + u-boot,dm-spl; + phandle = <0x0000000a>; + }; + gmac0_rmii_refin { + compatible = "fixed-clock"; + #clock-cells = <0x00000000>; + clock-frequency = <0x02faf080>; + u-boot,dm-spl; + phandle = <0x0000000b>; + }; + gmac0_rgmii_rxin { + compatible = "fixed-clock"; + #clock-cells = <0x00000000>; + clock-frequency = <0x07735940>; + phandle = <0x0000002a>; + }; + clk_rtc { + compatible = "fixed-clock"; + #clock-cells = <0x00000000>; + clock-frequency = <0x00008000>; + phandle = <0x0000002b>; + }; + hdmitx0_pixelclk { + compatible = "fixed-clock"; + #clock-cells = <0x00000000>; + clock-frequency = <0x11b3dc40>; + phandle = <0x0000000c>; + }; + mipitx_dphy_rxesc { + compatible = "fixed-clock"; + #clock-cells = <0x00000000>; + clock-frequency = <0x00989680>; + phandle = <0x0000000d>; + }; + mipitx_dphy_txbytehs { + compatible = "fixed-clock"; + #clock-cells = <0x00000000>; + clock-frequency = <0x11b3dc40>; + phandle = <0x0000000e>; + }; + cpus { + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + u-boot,dm-spl; + timebase-frequency = "", "= "; + phandle = <0x0000002c>; + cpu@0 { + compatible = "sifive,u74-mc", "riscv"; + reg = <0x00000000>; + d-cache-block-size = <0x00000040>; + d-cache-sets = <0x00000040>; + d-cache-size = <0x00002000>; + d-tlb-sets = <0x00000001>; + d-tlb-size = <0x00000028>; + device_type = "cpu"; + i-cache-block-size = <0x00000040>; + i-cache-sets = <0x00000040>; + i-cache-size = <0x00004000>; + i-tlb-sets = <0x00000001>; + i-tlb-size = <0x00000028>; + mmu-type = "riscv,sv39"; + next-level-cache = <0x00000001>; + riscv,isa = "rv64imacu"; + tlb-split; + status = "okay"; + u-boot,dm-spl; + phandle = <0x0000002d>; + interrupt-controller { + #interrupt-cells = <0x00000001>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + u-boot,dm-spl; + phandle = <0x00000003>; + }; + }; + cpu@1 { + compatible = "sifive,u74-mc", "riscv"; + reg = <0x00000001>; + d-cache-block-size = <0x00000040>; + d-cache-sets = <0x00000040>; + d-cache-size = <0x00008000>; + d-tlb-sets = <0x00000001>; + d-tlb-size = <0x00000028>; + device_type = "cpu"; + i-cache-block-size = <0x00000040>; + i-cache-sets = <0x00000040>; + i-cache-size = <0x00008000>; + i-tlb-sets = <0x00000001>; + i-tlb-size = <0x00000028>; + mmu-type = "riscv,sv39"; + next-level-cache = <0x00000001>; + riscv,isa = "rv64imafdcbsux"; + tlb-split; + status = "okay"; + u-boot,dm-spl; + phandle = <0x0000002e>; + interrupt-controller { + #interrupt-cells = <0x00000001>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + u-boot,dm-spl; + phandle = <0x00000004>; + }; + }; + cpu@2 { + compatible = "sifive,u74-mc", "riscv"; + reg = <0x00000002>; + d-cache-block-size = <0x00000040>; + d-cache-sets = <0x00000040>; + d-cache-size = <0x00008000>; + d-tlb-sets = <0x00000001>; + d-tlb-size = <0x00000028>; + device_type = "cpu"; + i-cache-block-size = <0x00000040>; + i-cache-sets = <0x00000040>; + i-cache-size = <0x00008000>; + i-tlb-sets = <0x00000001>; + i-tlb-size = <0x00000028>; + mmu-type = "riscv,sv39"; + next-level-cache = <0x00000001>; + riscv,isa = "rv64imafdcbsux"; + tlb-split; + status = "okay"; + u-boot,dm-spl; + phandle = <0x0000002f>; + interrupt-controller { + #interrupt-cells = <0x00000001>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + u-boot,dm-spl; + phandle = <0x00000005>; + }; + }; + cpu@3 { + compatible = "sifive,u74-mc", "riscv"; + reg = <0x00000003>; + d-cache-block-size = <0x00000040>; + d-cache-sets = <0x00000040>; + d-cache-size = <0x00008000>; + d-tlb-sets = <0x00000001>; + d-tlb-size = <0x00000028>; + device_type = "cpu"; + i-cache-block-size = <0x00000040>; + i-cache-sets = <0x00000040>; + i-cache-size = <0x00008000>; + i-tlb-sets = <0x00000001>; + i-tlb-size = <0x00000028>; + mmu-type = "riscv,sv39"; + next-level-cache = <0x00000001>; + riscv,isa = "rv64imafdcbsux"; + tlb-split; + status = "okay"; + u-boot,dm-spl; + phandle = <0x00000030>; + interrupt-controller { + #interrupt-cells = <0x00000001>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + u-boot,dm-spl; + phandle = <0x00000006>; + }; + }; + cpu@4 { + compatible = "sifive,u74-mc", "riscv"; + reg = <0x00000004>; + d-cache-block-size = <0x00000040>; + d-cache-sets = <0x00000040>; + d-cache-size = <0x00008000>; + d-tlb-sets = <0x00000001>; + d-tlb-size = <0x00000028>; + device_type = "cpu"; + i-cache-block-size = <0x00000040>; + i-cache-sets = <0x00000040>; + i-cache-size = <0x00008000>; + i-tlb-sets = <0x00000001>; + i-tlb-size = <0x00000028>; + mmu-type = "riscv,sv39"; + next-level-cache = <0x00000001>; + riscv,isa = "rv64imafdcbsux"; + tlb-split; + status = "okay"; + u-boot,dm-spl; + phandle = <0x00000031>; + interrupt-controller { + #interrupt-cells = <0x00000001>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + u-boot,dm-spl; + phandle = <0x00000007>; + }; + }; + }; + soc { + compatible = "simple-bus"; + interrupt-parent = <0x00000002>; + #address-cells = <0x00000002>; + #size-cells = <0x00000002>; + #clock-cells = <0x00000001>; + ranges; + u-boot,dm-spl; + phandle = <0x00000032>; + pmu { + compatible = "riscv,pmu"; + riscv,event-to-mhpmcounters = <0x00000005 0x00000006 0x00000018 0x00000008 0x00000009 0x00000018>; + riscv,event-to-mhpmevent = <0x00000005 0x00000000 0x00004000 0x00000006 0x00000000 0x00004001 0x00000008 0x00000000 0x00004008 0x00000009 0x00000000 0x00004009>; + riscv,raw-event-to-mhpmcounters = <0x00000000 0x00000100 0xffffffff 0xffffffff 0x00000018 0x00000000 0x00000200 0xffffffff 0xffffffff 0x00000018 0x00000000 0x00000400 0xffffffff 0xffffffff 0x00000018 0x00000000 0x00000800 0xffffffff 0xffffffff 0x00000018 0x00000000 0x00001000 0xffffffff 0xffffffff 0x00000018 0x00000000 0x00002000 0xffffffff 0xffffffff 0x00000018 0x00000000 0x00004000 0xffffffff 0xffffffff 0x00000018 0x00000000 0x00008000 0xffffffff 0xffffffff 0x00000018 0x00000000 0x00010000 0xffffffff 0xffffffff 0x00000018 0x00000000 0x00020000 0xffffffff 0xffffffff 0x00000018 0x00000000 0x00040000 0xffffffff 0xffffffff 0x00000018 0x00000000 0x00080000 0xffffffff 0xffffffff 0x00000018 0x00000000 0x00100000 0xffffffff 0xffffffff 0x00000018 0x00000000 0x00200000 0xffffffff 0xffffffff 0x00000018 0x00000000 0x00400000 0xffffffff 0xffffffff 0x00000018 0x00000000 0x00800000 0xffffffff 0xffffffff 0x00000018 0x00000000 0x01000000 0xffffffff 0xffffffff 0x00000018 0x00000000 0x02000000 0xffffffff 0xffffffff 0x00000018 0x00000000 0x00000101 0xffffffff 0xffffffff 0x00000018 0x00000000 0x00000201 0xffffffff 0xffffffff 0x00000018 0x00000000 0x00000401 0xffffffff 0xffffffff 0x00000018 0x00000000 0x00000801 0xffffffff 0xffffffff 0x00000018 0x00000000 0x00001001 0xffffffff 0xffffffff 0x00000018 0x00000000 0x00002001 0xffffffff 0xffffffff 0x00000018 0x00000000 0x00004001 0xffffffff 0xffffffff 0x00000018 0x00000000 0x00008001 0xffffffff 0xffffffff 0x00000018 0x00000000 0x00010001 0xffffffff 0xffffffff 0x00000018 0x00000000 0x00020001 0xffffffff 0xffffffff 0x00000018 0x00000000 0x00040001 0xffffffff 0xffffffff 0x00000018 0x00000000 0x00000102 0xffffffff 0xffffffff 0x00000018 0x00000000 0x00000202 0xffffffff 0xffffffff 0x00000018 0x00000000 0x00000402 0xffffffff 0xffffffff 0x00000018 0x00000000 0x00000802 0xffffffff 0xffffffff 0x00000018 0x00000000 0x00001002 0xffffffff 0xffffffff 0x00000018 0x00000000 0x00002002 0xffffffff 0xffffffff 0x00000018>; + }; + cache-controller@2010000 { + compatible = "sifive,fu740-c000-ccache", "cache"; + reg = <0x00000000 0x02010000 0x00000000 0x00004000 0x00000000 0x08000000 0x00000000 0x02000000>; + reg-names = "control", "sideband"; + interrupts = <0x00000001 0x00000003 0x00000004 0x00000002>; + cache-block-size = <0x00000040>; + cache-level = <0x00000002>; + cache-sets = <0x00000800>; + cache-size = <0x00200000>; + cache-unified; + phandle = <0x00000001>; + }; + aon_syscon@17010000 { + compatible = "syscon"; + reg = <0x00000000 0x17010000 0x00000000 0x00001000>; + phandle = <0x00000033>; + }; + stg_syscon@10240000 { + compatible = "syscon"; + reg = <0x00000000 0x10240000 0x00000000 0x00001000>; + phandle = <0x00000011>; + }; + sys_syscon@13030000 { + compatible = "syscon"; + reg = <0x00000000 0x13030000 0x00000000 0x00001000>; + phandle = <0x00000012>; + }; + clint@2000000 { + compatible = "riscv,clint0"; + reg = <0x00000000 0x02000000 0x00000000 0x00010000>; + reg-names = "control"; + interrupts-extended = <0x00000003 0x00000003 0x00000003 0x00000007 0x00000004 0x00000003 0x00000004 0x00000007 0x00000005 0x00000003 0x00000005 0x00000007 0x00000006 0x00000003 0x00000006 0x00000007 0x00000007 0x00000003 0x00000007 0x00000007>; + #interrupt-cells = <0x00000001>; + u-boot,dm-spl; + phandle = <0x00000034>; + }; + plic@c000000 { + compatible = "riscv,plic0"; + reg = <0x00000000 0x0c000000 0x00000000 0x04000000>; + reg-names = "control"; + interrupts-extended = <0x00000003 0x0000000b 0x00000004 0x0000000b 0x00000004 0x00000009 0x00000005 0x0000000b 0x00000005 0x00000009 0x00000006 0x0000000b 0x00000006 0x00000009 0x00000007 0x0000000b 0x00000007 0x00000009>; + interrupt-controller; + #interrupt-cells = <0x00000001>; + riscv,max-priority = <0x00000007>; + riscv,ndev = <0x00000088>; + phandle = <0x00000002>; + }; + clock-controller { + compatible = "starfive,jh7110-clkgen"; + reg = <0x00000000 0x13020000 0x00000000 0x00010000 0x00000000 0x10230000 0x00000000 0x00010000 0x00000000 0x17000000 0x00000000 0x00010000>; + reg-names = "sys", "stg", "aon"; + clocks = <0x00000008 0x00000009 0x0000000a 0x0000000b>; + clock-names = "osc", "gmac1_rmii_refin", "stg_apb", "gmac0_rmii_refin"; + #clock-cells = <0x00000001>; + status = "okay"; + u-boot,dm-spl; + phandle = <0x0000000f>; + }; + clock-controller@295C0000 { + compatible = "starfive,jh7110-clk-vout"; + reg = <0x00000000 0x295c0000 0x00000000 0x00010000>; + reg-names = "vout"; + clocks = <0x0000000c 0x0000000d 0x0000000e>; + clock-names = "hdmitx0_pixelclk", "mipitx_dphy_rxesc", "mipitx_dphy_txbytehs"; + #clock-cells = <0x00000001>; + status = "disabled"; + phandle = <0x0000001c>; + }; + clock-controller@19810000 { + compatible = "starfive,jh7110-clk-isp"; + reg = <0x00000000 0x19810000 0x00000000 0x00010000>; + reg-names = "isp"; + #clock-cells = <0x00000001>; + clocks = <0x0000000f 0x0000010a 0x0000000f 0x00000033 0x0000000f 0x00000034>; + clock-names = "u0_dom_isp_top_clk_dom_isp_top_clk_dvp", "u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x", "u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi"; + resets = <0x00000010 0x00000029 0x00000010 0x0000002a>; + reset-names = "rst_isp_top_n", "rst_isp_top_axi"; + status = "disabled"; + phandle = <0x00000017>; + }; + spi@13010000 { + compatible = "cdns,qspi-nor"; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + reg = <0x00000000 0x13010000 0x00000000 0x00010000 0x00000000 0x21000000 0x00000000 0x00400000>; + clocks = <0x0000000f 0x0000005a>; + clock-names = "clk_ref"; + resets = <0x00000010 0x0000003e 0x00000010 0x0000003d 0x00000010 0x0000003f>; + resets-names = "rst_apb", "rst_ahb", "rst_ref"; + cdns,fifo-depth = <0x00000100>; + cdns,fifo-width = <0x00000004>; + spi-max-frequency = <0x0ee6b280>; + status = "okay"; + u-boot,dm-spl; + phandle = <0x00000035>; + nor-flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x00000000>; + spi-max-frequency = <0x05f5e100>; + cdns,tshsl-ns = <0x00000001>; + cdns,tsd2d-ns = <0x00000001>; + cdns,tchsh-ns = <0x00000001>; + cdns,tslch-ns = <0x00000001>; + u-boot,dm-spl; + phandle = <0x00000036>; + }; + }; + otp@17050000 { + compatible = "starfive,jh7110-otp"; + reg = <0x00000000 0x17050000 0x00000000 0x00010000>; + clock-frequency = "", "= "; + clocks = <0x0000000f 0x000000e4>; + clock-names = "apb"; + phandle = <0x00000037>; + }; + usbdrd { + compatible = "starfive,jh7110-cdns3"; + #address-cells = <0x00000002>; + #size-cells = <0x00000002>; + clocks = <0x0000000f 0x000000c4 0x0000000f 0x000000c2 0x0000000f 0x000000c3 0x0000000f 0x000000bf 0x0000000f 0x000000c1 0x0000000f 0x000000c0>; + clock-names = "app", "lpm", "stb", "apb", "axi", "utmi"; + resets = <0x00000010 0x0000008a 0x00000010 0x00000088 0x00000010 0x00000087 0x00000010 0x00000089>; + reset-names = "pwrup", "apb", "axi", "utmi"; + starfive,stg-syscon = <0x00000011 0x00000004>; + starfive,sys-syscon = <0x00000012 0x00000018>; + status = "okay"; + phandle = <0x00000038>; + usb@10100000 { + compatible = "cdns,usb3"; + reg = <0x00000000 0x10100000 0x00000000 0x00010000 0x00000000 0x10110000 0x00000000 0x00010000 0x00000000 0x10120000 0x00000000 0x00010000>; + reg-names = "otg", "xhci", "dev"; + interrupts = <0x0000006c 0x0000006d 0x0000006e>; + interrupt-names = "host", "peripheral", "otg"; + phy-names = "cdns3,usb3-phy", "cnds3,usb2-phy"; + maximum-speed = "super-speed"; + dr_mode = "host"; + phandle = <0x00000039>; + }; + }; + timer@13050000 { + compatible = "starfive,si5-timers"; + reg = <0x00000000 0x13050000 0x00000000 0x00010000>; + interrupts = <0x00000045 0x00000046 0x00000047 0x00000048>; + interrupt-names = "timer0", "timer1", "timer2", "timer3"; + clocks = <0x0000000f 0x0000007d 0x0000000f 0x0000007e 0x0000000f 0x0000007f 0x0000000f 0x00000080 0x0000000f 0x0000007c>; + clock-names = "timer0", "timer1", "timer2", "timer3", "apb_clk"; + clock-frequency = <0x001e8480>; + status = "disabled"; + phandle = <0x0000003a>; + }; + wdog@13070000 { + compatible = "starfive,dskit-wdt"; + reg = <0x00000000 0x13070000 0x00000000 0x00010000>; + interrupts = <0x00000044>; + interrupt-names = "wdog"; + clock-frequency = <0x001e8480>; + clocks = <0x0000000f 0x0000007b 0x0000000f 0x0000007a>; + clock-names = "core_clk", "apb_clk"; + resets = <0x00000010 0x0000006d 0x00000010 0x0000006e>; + reset-names = "rst_apb", "rst_core"; + timeout-sec = <0x0000000f>; + status = "disabled"; + phandle = <0x0000003b>; + }; + rtc@17040000 { + compatible = "starfive,rtc_hms"; + reg = <0x00000000 0x17040000 0x00000000 0x00010000>; + interrupts = <0x0000000a 0x0000000b 0x0000000c>; + interrupt-names = "rtc_ms_pulse", "rtc_sec_pulse", "rtc"; + clocks = <0x0000000f 0x000000e5 0x0000000f 0x000000e8>; + clock-names = "pclk", "cal_clk"; + resets = <0x00000010 0x000000a5 0x00000010 0x000000a6 0x00000010 0x000000a7>; + reset-names = "rst_apb", "rst_cal", "rst_osc"; + rtc,cal-clock-freq = <0x000f4240>; + status = "okay"; + phandle = <0x0000003c>; + }; + pmu@17030000 { + compatible = "starfive,jh7110-pmu"; + reg = <0x00000000 0x17030000 0x00000000 0x00010000>; + interrupts = <0x0000006f>; + status = "okay"; + phandle = <0x0000003d>; + }; + serial@10000000 { + compatible = "snps,dw-apb-uart"; + reg = <0x00000000 0x10000000 0x00000000 0x00010000>; + reg-io-width = <0x00000004>; + reg-shift = <0x00000002>; + clocks = <0x0000000f 0x00000092 0x0000000f 0x00000091>; + clock-names = "baudclk", "apb_pclk"; + resets = <0x00000010 0x00000053 0x00000010 0x00000054>; + interrupts = <0x00000020>; + status = "okay"; + reg-offset = <0x00000000>; + current-speed = <0x0001c200>; + pinctrl-names = "default"; + pinctrl-0 = <0x00000013>; + clock-frequency = <0x016e3600>; + u-boot,dm-spl; + phandle = <0x0000003e>; + }; + serial@10010000 { + compatible = "snps,dw-apb-uart"; + reg = <0x00000000 0x10010000 0x00000000 0x00010000>; + reg-io-width = <0x00000004>; + reg-shift = <0x00000002>; + clocks = <0x0000000f 0x00000094 0x0000000f 0x00000093>; + clock-names = "baudclk", "apb_pclk"; + resets = <0x00000010 0x00000055 0x00000010 0x00000056>; + interrupts = <0x00000021>; + status = "disabled"; + phandle = <0x0000003f>; + }; + serial@10020000 { + compatible = "snps,dw-apb-uart"; + reg = <0x00000000 0x10020000 0x00000000 0x00010000>; + reg-io-width = <0x00000004>; + reg-shift = <0x00000002>; + clocks = <0x0000000f 0x00000096 0x0000000f 0x00000095>; + clock-names = "baudclk", "apb_pclk"; + resets = <0x00000010 0x00000057 0x00000010 0x00000058>; + interrupts = <0x00000022>; + status = "disabled"; + phandle = <0x00000040>; + }; + serial@12000000 { + compatible = "snps,dw-apb-uart"; + reg = <0x00000000 0x12000000 0x00000000 0x00010000>; + reg-io-width = <0x00000004>; + reg-shift = <0x00000002>; + clocks = <0x0000000f 0x00000098 0x0000000f 0x00000097>; + clock-names = "baudclk", "apb_pclk"; + resets = <0x00000010 0x00000059 0x00000010 0x0000005a>; + interrupts = <0x0000002d>; + status = "disabled"; + phandle = <0x00000041>; + }; + serial@12010000 { + compatible = "snps,dw-apb-uart"; + reg = <0x00000000 0x12010000 0x00000000 0x00010000>; + reg-io-width = <0x00000004>; + reg-shift = <0x00000002>; + clocks = <0x0000000f 0x0000009a 0x0000000f 0x00000099>; + clock-names = "baudclk", "apb_pclk"; + resets = <0x00000010 0x0000005b 0x00000010 0x0000005c>; + interrupts = <0x0000002e>; + status = "disabled"; + phandle = <0x00000042>; + }; + serial@12020000 { + compatible = "snps,dw-apb-uart"; + reg = <0x00000000 0x12020000 0x00000000 0x00010000>; + reg-io-width = <0x00000004>; + reg-shift = <0x00000002>; + clocks = <0x0000000f 0x0000009c 0x0000000f 0x0000009b>; + clock-names = "baudclk", "apb_pclk"; + resets = <0x00000010 0x0000005d 0x00000010 0x0000005e>; + interrupts = <0x0000002f>; + status = "disabled"; + phandle = <0x00000043>; + }; + dma-controller@16050000 { + compatible = "starfive,axi-dma"; + reg = <0x00000000 0x16050000 0x00000000 0x00010000>; + clocks = <0x0000000f 0x000000d9 0x0000000f 0x000000da>; + clock-names = "core-clk", "cfgr-clk"; + resets = <0x00000010 0x00000085 0x00000010 0x00000086>; + reset-names = "rst_axi", "rst_ahb"; + interrupts = <0x00000049>; + #dma-cells = <0x00000002>; + dma-channels = <0x00000004>; + snps,dma-masters = <0x00000001>; + snps,data-width = <0x00000003>; + snps,num-hs-if = <0x00000038>; + snps,block-size = <0x00010000 0x00010000 0x00010000 0x00010000>; + snps,priority = <0x00000000 0x00000001 0x00000002 0x00000003>; + snps,axi-max-burst-len = <0x00000010>; + status = "disabled"; + phandle = <0x00000019>; + }; + gpio@13040000 { + compatible = "starfive,jh7110-sys-pinctrl"; + reg = <0x00000000 0x13040000 0x00000000 0x00010000>; + reg-names = "control"; + interrupts = <0x0000005b>; + interrupt-controller; + #gpio-cells = <0x00000002>; + ngpios = <0x00000040>; + status = "okay"; + phandle = <0x00000044>; + uart0-0 { + phandle = <0x00000013>; + tx-pins { + pinmux = <0xff140005>; + bias-disable; + drive-strength = <0x0000000c>; + input-disable; + input-schmitt-disable; + slew-rate = <0x00000000>; + }; + rx-pins { + pinmux = <0x0e000406>; + bias-pull-up; + drive-strength = <0x00000002>; + input-enable; + input-schmitt-enable; + slew-rate = <0x00000000>; + }; + }; + mmc0-pins { + phandle = <0x00000015>; + mmc0-pins-rest { + pinmux = <0xff13003e>; + bias-pull-up; + drive-strength = <0x0000000c>; + input-disable; + input-schmitt-disable; + slew-rate = <0x00000000>; + }; + }; + sdcard1-pins { + phandle = <0x00000016>; + sdcard1-pins0 { + pinmux = "�7", " +"; + bias-pull-up; + drive-strength = <0x0000000c>; + input-disable; + input-schmitt-disable; + slew-rate = <0x00000000>; + }; + sdcard1-pins1 { + pinmux = <0x2c394c09>; + bias-pull-up; + drive-strength = <0x0000000c>; + input-enable; + input-schmitt-enable; + slew-rate = <0x00000000>; + }; + sdcard1-pins2 { + pinmux = <0x2d3a500b>; + bias-pull-up; + drive-strength = <0x0000000c>; + input-enable; + input-schmitt-enable; + slew-rate = <0x00000000>; + }; + sdcard1-pins3 { + pinmux = <0x2e3b540c>; + bias-pull-up; + drive-strength = <0x0000000c>; + input-enable; + input-schmitt-enable; + slew-rate = <0x00000000>; + }; + sdcard1-pins4 { + pinmux = <0x2f3c5807>; + bias-pull-up; + drive-strength = <0x0000000c>; + input-enable; + input-schmitt-enable; + slew-rate = <0x00000000>; + }; + sdcard1-pins5 { + pinmux = <0x303d5c08>; + bias-pull-up; + drive-strength = <0x0000000c>; + input-enable; + input-schmitt-enable; + slew-rate = <0x00000000>; + }; + }; + }; + gpio@17020000 { + compatible = "starfive,jh7110-aon-pinctrl"; + reg = <0x00000000 0x17020000 0x00000000 0x00010000>; + reg-names = "control"; + interrupts = <0x0000005a>; + interrupt-controller; + #gpio-cells = <0x00000002>; + ngpios = <0x00000004>; + status = "disabled"; + phandle = <0x00000045>; + }; + trng@1600C000 { + compatible = "starfive,trng"; + reg = <0x00000000 0x1600c000 0x00000000 0x00004000>; + clocks = <0x0000000f 0x000000cd 0x0000000f 0x000000ce>; + clock-names = "hclk", "miscahb_clk"; + resets = <0x00000010 0x00000083>; + interrupts = <0x0000001e>; + status = "disabled"; + phandle = <0x00000046>; + }; + sec_dma@16008000 { + compatible = "starfive,pl080"; + reg = <0x00000000 0x16008000 0x00000000 0x00004000>; + reg-names = "sec_dma"; + interrupts = <0x0000001d>; + clocks = <0x0000000f 0x000000cd 0x0000000f 0x000000ce>; + clock-names = "sec_hclk", "sec_ahb"; + resets = <0x00000010 0x00000083>; + reset-names = "sec_hre"; + lli-bus-interface-ahb1; + mem-bus-interface-ahb1; + memcpy-burst-size = <0x00000100>; + memcpy-bus-width = <0x00000020>; + #dma-cells = <0x00000002>; + status = "disabled"; + phandle = <0x00000014>; + }; + crypto@16000000 { + compatible = "starfive,jh7110-sec"; + reg = <0x00000000 0x16000000 0x00000000 0x00004000 0x00000000 0x16008000 0x00000000 0x00004000>; + reg-names = "secreg", "secdma"; + interrupts = <0x0000001c 0x0000001d>; + interrupt-names = "secirq", "dmairq"; + clocks = <0x0000000f 0x000000cd 0x0000000f 0x000000ce>; + clock-names = "sec_hclk", "sec_ahb"; + resets = <0x00000010 0x00000083>; + reset-names = "sec_hre"; + enable-dma = "true"; + dmas = <0x00000014 0x00000001 0x00000002 0x00000014 0x00000000 0x00000002>; + dma-names = "sec_m", "sec_p"; + status = "disabled"; + phandle = <0x00000047>; + }; + i2c@12060000 { + compatible = "snps,designware-i2c"; + reg = <0x00000000 0x12060000 0x00000000 0x00010000>; + clocks = <0x0000000f 0x0000012b 0x0000000f 0x00000090>; + clock-names = "ref", "pclk"; + resets = <0x00000010 0x00000052>; + interrupts = <0x00000033>; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + status = "disabled"; + phandle = <0x00000048>; + }; + i2c@10030000 { + compatible = "snps,designware-i2c"; + reg = <0x00000000 0x10030000 0x00000000 0x00010000>; + clocks = <0x0000000f 0x00000125 0x0000000f 0x0000008a>; + clock-names = "ref", "pclk"; + resets = <0x00000010 0x0000004c>; + interrupts = <0x00000023>; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + status = "disabled"; + phandle = <0x00000049>; + }; + i2c@10040000 { + compatible = "snps,designware-i2c"; + reg = <0x00000000 0x10040000 0x00000000 0x00010000>; + clocks = <0x0000000f 0x00000126 0x0000000f 0x0000008b>; + clock-names = "ref", "pclk"; + resets = <0x00000010 0x0000004d>; + interrupts = <0x00000024>; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + status = "disabled"; + phandle = <0x0000004a>; + }; + i2c5@12050000 { + compatible = "snps,designware-i2c"; + reg = <0x00000000 0x12050000 0x00000000 0x00010000>; + clocks = <0x0000000f 0x0000012a 0x0000000f 0x0000008f>; + clock-names = "ref", "pclk"; + resets = <0x00000010 0x00000051>; + interrupts = <0x00000032>; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + status = "okay"; + clock-frequency = <0x000186a0>; + i2c-sda-hold-time-ns = <0x0000012c>; + i2c-sda-falling-time-ns = <0x00000bb8>; + i2c-scl-falling-time-ns = <0x00000bb8>; + auto_calc_scl_lhcnt; + u-boot,dm-spl; + phandle = <0x0000004b>; + eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x00000050>; + pagesize = <0x00000010>; + u-boot,dm-spl; + }; + axp15060_reg@36 { + compatible = "stf,axp15060-regulator"; + reg = <0x00000036>; + phandle = <0x0000004c>; + }; + }; + sdio0@16010000 { + compatible = "snps,dw-mshc"; + reg = <0x00000000 0x16010000 0x00000000 0x00010000>; + clocks = <0x0000000f 0x0000005b 0x0000000f 0x0000005d>; + clock-names = "biu", "ciu"; + resets = <0x00000010 0x00000040>; + reset-names = "reset"; + fifo-depth = <0x00000020>; + bus-width = <0x00000008>; + pinctrl-names = "default"; + pinctrl-0 = <0x00000015>; + status = "okay"; + u-boot,dm-spl; + phandle = <0x0000004d>; + }; + sdio1@16020000 { + compatible = "snps,dw-mshc"; + reg = <0x00000000 0x16020000 0x00000000 0x00010000>; + clocks = <0x0000000f 0x0000005c 0x0000000f 0x0000005e>; + clock-names = "biu", "ciu"; + resets = <0x00000010 0x00000041>; + reset-names = "reset"; + fifo-depth = <0x00000020>; + bus-width = <0x00000004>; + pinctrl-names = "default"; + pinctrl-0 = <0x00000016>; + status = "okay"; + u-boot,dm-spl; + phandle = <0x0000004e>; + }; + vin_sysctl@19800000 { + compatible = "starfive,stf-vin"; + reg = <0x00000000 0x19800000 0x00000000 0x00010000 0x00000000 0x19810000 0x00000000 0x00010000 0x00000000 0x19820000 0x00000000 0x00010000 0x00000000 0x19830000 0x00000000 0x00010000 0x00000000 0x19840000 0x00000000 0x00010000 0x00000000 0x19870000 0x00000000 0x00030000 0x00000000 0x198a0000 0x00000000 0x00030000 0x00000000 0x11840000 0x00000000 0x00010000 0x00000000 0x17030000 0x00000000 0x00010000 0x00000000 0x13020000 0x00000000 0x00010000>; + reg-names = "mipi0", "vclk", "vrst", "mipi1", "sctrl", "isp0", "isp1", "trst", "pmu", "syscrg"; + clocks = <0x00000017 0x00000000 0x00000017 0x00000006 0x00000017 0x00000007 0x00000017 0x0000000d 0x00000017 0x00000002 0x00000017 0x0000000c 0x00000017 0x00000001 0x00000017 0x00000008 0x00000017 0x00000009 0x00000017 0x0000000a 0x00000017 0x0000000b>; + clock-names = "clk_apb_func", "clk_pclk", "clk_sys_clk", "clk_wrapper_clk_c", "clk_dvp_inv", "clk_axiwr", "clk_mipi_rx0_pxl", "clk_pixel_clk_if0", "clk_pixel_clk_if1", "clk_pixel_clk_if2", "clk_pixel_clk_if3"; + resets = <0x00000010 0x000000c0 0x00000010 0x000000c1 0x00000010 0x000000c4 0x00000010 0x000000c9 0x00000010 0x000000ca 0x00000010 0x000000cb 0x00000010 0x000000c5 0x00000010 0x000000c6 0x00000010 0x000000c7 0x00000010 0x000000c8 0x00000010 0x000000c2 0x00000010 0x000000c3>; + reset-names = "rst_wrapper_p", "rst_wrapper_c", "rst_pclk", "rst_sys_clk", "rst_axird", "rst_axiwr", "rst_pixel_clk_if0", "rst_pixel_clk_if1", "rst_pixel_clk_if2", "rst_pixel_clk_if3", "rst_m31dphy_hw", "rst_m31dphy_b09_always_on"; + interrupts = <0x0000005c 0x00000057 0x00000056>; + status = "disabled"; + phandle = <0x0000004f>; + }; + jpu@11900000 { + compatible = "starfive,jpu"; + reg = <0x00000000 0x13090000 0x00000000 0x00000300>; + interrupts = <0x0000000e>; + clocks = <0x0000000f 0x00000042 0x0000000f 0x00000043 0x0000000f 0x00000044>; + clock-names = "axi_clk", "core_clk", "apb_clk"; + resets = <0x00000010 0x0000002c 0x00000010 0x0000002d 0x00000010 0x0000002e>; + reset-names = "rst_axi", "rst_core", "rst_apb"; + status = "disabled"; + phandle = <0x00000050>; + }; + vpu_dec@130A0000 { + compatible = "starfive,vdec"; + reg = <0x00000000 0x130a0000 0x00000000 0x00010000>; + interrupts = <0x0000000d>; + clocks = <0x0000000f 0x00000046 0x0000000f 0x00000047 0x0000000f 0x00000048 0x0000000f 0x00000049 0x0000000f 0x0000004c>; + clock-names = "axi_clk", "bpu_clk", "vce_clk", "apb_clk", "noc_bus"; + resets = <0x00000010 0x0000002f 0x00000010 0x00000030 0x00000010 0x00000031 0x00000010 0x00000032 0x00000010 0x00000035>; + reset-names = "rst_axi", "rst_bpu", "rst_vce", "rst_apb", "rst_sram"; + starfive,vdec_noc_ctrl; + status = "disabled"; + phandle = <0x00000051>; + }; + vpu_enc@130B0000 { + compatible = "starfive,venc"; + reg = <0x00000000 0x130b0000 0x00000000 0x00010000>; + interrupts = <0x0000000f>; + clocks = <0x0000000f 0x0000004e 0x0000000f 0x0000004f 0x0000000f 0x00000050 0x0000000f 0x00000051 0x0000000f 0x00000052>; + clock-names = "axi_clk", "bpu_clk", "vce_clk", "apb_clk", "noc_bus"; + resets = <0x00000010 0x00000036 0x00000010 0x00000037 0x00000010 0x00000038 0x00000010 0x00000039 0x00000010 0x0000003a>; + reset-names = "rst_axi", "rst_bpu", "rst_vce", "rst_apb", "rst_sram"; + starfive,venc_noc_ctrl; + status = "disabled"; + phandle = <0x00000052>; + }; + reset-controller { + compatible = "starfive,jh7110-reset"; + reg = <0x00000000 0x13020000 0x00000000 0x00010000 0x00000000 0x10230000 0x00000000 0x00010000 0x00000000 0x17000000 0x00000000 0x00010000 0x00000000 0x19810000 0x00000000 0x00010000 0x00000000 0x295c0000 0x00000000 0x00010000>; + reg-names = "syscrg", "stgcrg", "aoncrg", "ispcrg", "voutcrg"; + #reset-cells = <0x00000001>; + status = "okay"; + u-boot,dm-spl; + phandle = <0x00000010>; + }; + stmmac-axi-config { + snps,wr_osr_lmt = <0x0000000f>; + snps,rd_osr_lmt = <0x0000000f>; + snps,blen = <0x00000100 0x00000080 0x00000040 0x00000020 0x00000000 0x00000000 0x00000000>; + phandle = <0x00000018>; + }; + ethernet@16030000 { + compatible = "starfive,jh7110-eqos-5.20"; + reg = <0x00000000 0x16030000 0x00000000 0x00010000>; + clock-names = "gtx", "tx", "ptp_ref", "stmmaceth", "pclk", "gtxc", "rmii_rtx"; + clocks = <0x0000000f 0x0000006c 0x0000000f 0x000000e0 0x0000000f 0x0000006d 0x0000000f 0x000000dd 0x0000000f 0x000000de 0x0000000f 0x0000006f 0x0000000f 0x000000df>; + resets = <0x00000010 0x000000a1 0x00000010 0x000000a0>; + reset-names = "ahb", "stmmaceth"; + interrupts = <0x00000007 0x00000006 0x00000005>; + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; + max-frame-size = <0x00002328>; + phy-mode = "rgmii-id"; + snps,multicast-filter-bins = <0x00000100>; + snps,perfect-filter-entries = <0x00000080>; + rx-fifo-depth = <0x00040000>; + tx-fifo-depth = <0x00020000>; + snps,fixed-burst; + snps,no-pbl-x8; + snps,force_thresh_dma_mode; + snps,axi-config = <0x00000018>; + snps,tso; + snps,en-tx-lpi-clockgating; + snps,en-lpi; + snps,write-requests = <0x00000002>; + snps,read-requests = <0x00000010>; + snps,burst-map = <0x00000007>; + snps,txpbl = <0x00000010>; + snps,rxpbl = <0x00000010>; + status = "okay"; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + phandle = <0x00000053>; + ethernet-phy@0 { + rxc_dly_en = <0x00000001>; + tx_delay_sel_fe = <0x00000005>; + tx_delay_sel = <0x0000000a>; + tx_inverted_10 = <0x00000001>; + tx_inverted_100 = <0x00000001>; + tx_inverted_1000 = <0x00000001>; + phandle = <0x00000054>; + }; + }; + ethernet@16040000 { + compatible = "starfive,jh7110-eqos-5.20"; + reg = <0x00000000 0x16040000 0x00000000 0x00010000>; + clock-names = "gtx", "tx", "ptp_ref", "stmmaceth", "pclk", "gtxc", "rmii_rtx"; + clocks = <0x0000000f 0x00000064 0x0000000f 0x00000069 0x0000000f 0x00000066 0x0000000f 0x00000061 0x0000000f 0x00000062 0x0000000f 0x0000006b 0x0000000f 0x00000065>; + resets = <0x00000010 0x00000043 0x00000010 0x00000042>; + reset-names = "ahb", "stmmaceth"; + interrupts = <0x0000004e 0x0000004d 0x0000004c>; + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; + max-frame-size = <0x00002328>; + phy-mode = "rgmii-id"; + snps,multicast-filter-bins = <0x00000100>; + snps,perfect-filter-entries = <0x00000080>; + rx-fifo-depth = <0x00040000>; + tx-fifo-depth = <0x00020000>; + snps,fixed-burst; + snps,no-pbl-x8; + snps,force_thresh_dma_mode; + snps,axi-config = <0x00000018>; + snps,tso; + snps,en-tx-lpi-clockgating; + snps,en-lpi; + snps,write-requests = <0x00000002>; + snps,read-requests = <0x00000010>; + snps,burst-map = <0x00000007>; + snps,txpbl = <0x00000010>; + snps,rxpbl = <0x00000010>; + status = "okay"; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + phandle = <0x00000055>; + ethernet-phy@1 { + tx_delay_sel_fe = <0x00000005>; + tx_delay_sel = <0x00000000>; + rxc_dly_en = <0x00000000>; + tx_inverted_10 = <0x00000001>; + tx_inverted_100 = <0x00000001>; + tx_inverted_1000 = <0x00000000>; + phandle = <0x00000056>; + }; + }; + gpu@18000000 { + compatible = "img-gpu"; + reg = <0x00000000 0x18000000 0x00000000 0x00100000 0x00000000 0x0130c000 0x00000000 0x00010000>; + clocks = <0x0000000f 0x00000030 0x0000000f 0x00000031 0x0000000f 0x0000002e 0x0000000f 0x0000002f 0x0000000f 0x00000032>; + clock-names = "clk_apb", "clk_rtc", "clk_core", "clk_sys", "clk_axi"; + resets = <0x00000010 0x00000015 0x00000010 0x00000016>; + reset-names = "rst_apb", "rst_doma"; + interrupts = <0x00000052>; + current-clock = <0x007a1200>; + status = "disabled"; + phandle = <0x00000057>; + }; + can@130d0000 { + compatible = "ipms,can"; + reg = <0x00000000 0x130d0000 0x00000000 0x00001000>; + interrupts = <0x00000070>; + clocks = <0x0000000f 0x00000073 0x0000000f 0x00000075 0x0000000f 0x00000074>; + clock-names = "apb_clk", "core_clk", "timer_clk"; + resets = <0x00000010 0x0000006f 0x00000010 0x00000070 0x00000010 0x00000071>; + reset-names = "rst_apb", "rst_core", "rst_timer"; + starfive,sys-syscon = <0x00000012 0x00000010 0x00000003 0x00000008>; + syscon,can_or_canfd = <0x00000000>; + status = "disabled"; + phandle = <0x00000058>; + }; + can@130e0000 { + compatible = "ipms,can"; + reg = <0x00000000 0x130e0000 0x00000000 0x00001000>; + interrupts = <0x00000071>; + clocks = <0x0000000f 0x00000076 0x0000000f 0x00000078 0x0000000f 0x00000077>; + clock-names = "apb_clk", "core_clk", "timer_clk"; + resets = <0x00000010 0x00000072 0x00000010 0x00000073 0x00000010 0x00000074>; + reset-names = "rst_apb", "rst_core", "rst_timer"; + starfive,sys-syscon = <0x00000012 0x00000088 0x00000012 0x00040000>; + syscon,can_or_canfd = <0x00000000>; + status = "disabled"; + phandle = <0x00000059>; + }; + tdm@10090000 { + compatible = "starfive,sf-tdm"; + reg = <0x00000000 0x10090000 0x00000000 0x00001000>; + reg-names = "tdm"; + clocks = <0x0000000f 0x00000009 0x0000000f 0x000000b8 0x0000000f 0x0000000c 0x0000000f 0x000000b9 0x0000000f 0x000000ba>; + clock-names = "clk_ahb0", "clk_tdm_ahb", "clk_apb0", "clk_tdm_apb", "clk_tdm_intl"; + resets = <0x00000010 0x00000069 0x00000010 0x0000006b 0x00000010 0x0000006a>; + reset-names = "tdm_ahb", "tdm_apb", "tdm_rst"; + dmas = <0x00000019 0x00000014 0x00000001 0x00000019 0x00000015 0x00000001>; + dma-names = "rx", "tx"; + #sound-dai-cells = <0x00000000>; + status = "disabled"; + phandle = <0x0000005a>; + }; + spdif0@100a0000 { + compatible = "starfive,sf-spdif"; + reg = <0x00000000 0x100a0000 0x00000000 0x00001000>; + clocks = <0x0000000f 0x0000009f 0x0000000f 0x000000a0 0x0000000f 0x00000012>; + clock-names = "spdif-apb", "spdif-core", "audioclk"; + resets = <0x00000010 0x0000005f>; + reset-names = "rst_apb"; + interrupts = <0x00000054>; + interrupt-names = "tx"; + #sound-dai-cells = <0x00000000>; + status = "disabled"; + phandle = <0x0000005b>; + }; + pwmdac@100b0000 { + compatible = "starfive,pwmdac"; + reg = <0x00000000 0x100b0000 0x00000000 0x00001000>; + clocks = <0x0000000f 0x0000000c 0x0000000f 0x0000009d 0x0000000f 0x0000009e>; + clock-names = "apb0", "pwmdac-apb", "pwmdac-core"; + resets = <0x00000010 0x00000060>; + reset-names = "rst-apb"; + dmas = <0x00000019 0x00000016 0x00000001>; + dma-names = "tx"; + #sound-dai-cells = <0x00000000>; + status = "disabled"; + phandle = <0x0000001f>; + }; + i2stx@100c0000 { + compatible = "snps,designware-i2stx"; + reg = <0x00000000 0x100c0000 0x00000000 0x00001000>; + clocks = <0x0000000f 0x0000000c>; + clock-names = "i2sclk"; + interrupt-names = "tx"; + #sound-dai-cells = <0x00000000>; + dmas = <0x00000019 0x0000001c 0x00000001>; + dma-names = "rx"; + status = "disabled"; + phandle = <0x0000005c>; + }; + pdm@100d0000 { + compatible = "starfive,sf-pdm"; + reg = <0x00000000 0x100d0000 0x00000000 0x00001000>; + reg-names = "pdm"; + clocks = <0x0000000f 0x000000b6 0x0000000f 0x0000000c 0x0000000f 0x000000b7 0x0000000f 0x00000130 0x0000000f 0x00000131 0x0000000f 0x00000132 0x0000000f 0x00000133 0x0000000f 0x000000b3>; + clock-names = "pdm_dmic", "clk_apb0", "pdm_apb", "pdm_dmic0_bclk", "pdm_dmic0_lrck", "pdm_dmic1_bclk", "pdm_dmic1_lrck", "u0_i2srx_3ch_bclk"; + resets = <0x00000010 0x00000061 0x00000010 0x00000062>; + reset-names = "pdm_dmic", "pdm_apb"; + #sound-dai-cells = <0x00000000>; + status = "disabled"; + phandle = <0x0000005d>; + }; + i2srx_3ch@100e0000 { + compatible = "snps,designware-i2srx"; + reg = <0x00000000 0x100e0000 0x00000000 0x00001000>; + clocks = <0x0000000f 0x0000000c 0x0000000f 0x000000af 0x0000000f 0x000000b0>; + clock-names = "apb0", "3ch-apb", "3ch-bclk"; + resets = <0x00000010 0x00000063 0x00000010 0x00000064>; + reset-names = "rst_apb_rx", "rst_bclk_rx"; + interrupts = <0x0000002a>; + interrupt-names = "rx"; + dmas = <0x00000019 0x00000018 0x00000001>; + dma-names = "rx"; + #sound-dai-cells = <0x00000000>; + status = "disabled"; + phandle = <0x0000005e>; + }; + i2stx_4ch0@120b0000 { + compatible = "snps,designware-i2stx-4ch0"; + reg = <0x00000000 0x120b0000 0x00000000 0x00001000>; + clocks = <0x0000000f 0x00000011 0x0000000f 0x000000a2 0x0000000f 0x000000a4 0x0000000f 0x00000012 0x0000000f 0x000000a5 0x0000000f 0x000000a7>; + clock-names = "inner", "bclk-mst", "lrck-mst", "mclk", "bclk0", "lrck0"; + resets = <0x00000010 0x00000065 0x00000010 0x00000066>; + reset-names = "rst_apb0", "rst_bclk0"; + interrupts = <0x0000003a>; + interrupt-names = "tx"; + dmas = <0x00000019 0x0000002f 0x00000001>; + dma-names = "tx"; + #sound-dai-cells = <0x00000000>; + status = "disabled"; + phandle = <0x0000005f>; + }; + i2stx_4ch1@120c0000 { + compatible = "snps,designware-i2stx-4ch1"; + reg = <0x00000000 0x120c0000 0x00000000 0x00001000>; + clocks = <0x0000000f 0x00000011 0x0000000f 0x000000a9 0x0000000f 0x000000ab 0x0000000f 0x00000012 0x0000000f 0x000000ac 0x0000000f 0x000000ae>; + clock-names = "inner", "bclk-mst1", "lrck-mst1", "mclk", "bclk1", "lrck1"; + resets = <0x00000010 0x00000067 0x00000010 0x00000068>; + reset-names = "rst_apb1", "rst_bclk1"; + interrupts = <0x0000003b>; + interrupt-names = "tx"; + dmas = <0x00000019 0x00000030 0x00000001>; + dma-names = "tx"; + #sound-dai-cells = <0x00000000>; + status = "disabled"; + phandle = <0x00000060>; + }; + pwm@120d0000 { + compatible = "starfive,pwm0"; + reg = <0x00000000 0x120d0000 0x00000000 0x00010000>; + reg-names = "control"; + clocks = <0x0000000f 0x00000079>; + resets = <0x00000010 0x0000006c>; + starfive,approx-period = <0x001e8480>; + #pwm-cells = <0x00000003>; + starfive,npwm = <0x00000008>; + status = "disabled"; + phandle = <0x00000061>; + }; + spdif_transmitter { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0x00000000>; + status = "disabled"; + phandle = <0x00000062>; + }; + spdif_receiver { + compatible = "linux,spdif-dir"; + #sound-dai-cells = <0x00000000>; + status = "disabled"; + phandle = <0x00000063>; + }; + pwmdac-transmitter { + compatible = "linux,pwmdac-dit"; + #sound-dai-cells = <0x00000000>; + status = "disabled"; + phandle = <0x00000020>; + }; + dmic_codec { + compatible = "dmic-codec"; + #sound-dai-cells = <0x00000000>; + status = "disabled"; + phandle = <0x00000064>; + }; + spi@10060000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x00000000 0x10060000 0x00000000 0x00010000>; + clocks = <0x0000000f 0x00000083>; + clock-names = "apb_pclk"; + resets = <0x00000010 0x00000045>; + reset-names = "rst_apb"; + interrupts = <0x00000026>; + dmas = <0x00000019 0x0000000e 0x00000001 0x00000019 0x0000000f 0x00000001>; + dma-names = "rx", "tx"; + arm,primecell-periphid = <0x00041022>; + num-cs = <0x00000001>; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + status = "disabled"; + phandle = <0x00000065>; + }; + pcie@2B000000 { + compatible = "plda,pci-xpressrich3-axi"; + #address-cells = <0x00000003>; + #size-cells = <0x00000002>; + #interrupt-cells = <0x00000001>; + reg = <0x00000000 0x2b000000 0x00000000 0x01000000 0x00000009 0x40000000 0x00000000 0x10000000>; + reg-names = "reg", "config"; + device_type = "pci"; + starfive,stg-syscon = <0x00000011 0x000000c0 0x000000c4 0x00000130>; + bus-range = <0x00000000 0x000000ff>; + ranges = <0x82000000 0x00000000 0x30000000 0x00000000 0x30000000 0x00000000 0x06000000>; + msi-parent = <0x00000002>; + interrupts = <0x00000038>; + interrupt-controller; + interrupt-names = "msi"; + interrupt-parent = <0x00000002>; + interrupt-map-mask = <0x00000000 0x00000000 0x00000000 0x00000007>; + interrupt-map = <0x00000000 0x00000000 0x00000000 0x00000001 0x00000002 0x00000001 0x00000000 0x00000000 0x00000000 0x00000002 0x00000002 0x00000002 0x00000000 0x00000000 0x00000000 0x00000003 0x00000002 0x00000003 0x00000000 0x00000000 0x00000000 0x00000004 0x00000002 0x00000004>; + resets = <0x00000010 0x0000008b 0x00000010 0x0000008c 0x00000010 0x0000008d 0x00000010 0x0000008e 0x00000010 0x0000008f 0x00000010 0x00000090>; + reset-names = "rst_mst0", "rst_slv0", "rst_slv", "rst_brg", "rst_core", "rst_apb"; + clocks = <0x0000000f 0x000000c8 0x0000000f 0x000000c6 0x0000000f 0x000000c7>; + clock-names = "tl", "axi_mst0", "apb"; + status = "disabled"; + phandle = <0x00000066>; + }; + pcie@2C000000 { + compatible = "plda,pci-xpressrich3-axi"; + #address-cells = <0x00000003>; + #size-cells = <0x00000002>; + #interrupt-cells = <0x00000001>; + reg = <0x00000000 0x2c000000 0x00000000 0x01000000 0x00000009 0xc0000000 0x00000000 0x10000000>; + reg-names = "reg", "config"; + device_type = "pci"; + starfive,stg-syscon = <0x00000011 0x00000270 0x00000274 0x000002e0>; + bus-range = <0x00000000 0x000000ff>; + ranges = <0x82000000 0x00000000 0x38000000 0x00000000 0x38000000 0x00000000 0x06000000>; + msi-parent = <0x00000002>; + interrupts = <0x00000039>; + interrupt-controller; + interrupt-names = "msi"; + interrupt-parent = <0x00000002>; + interrupt-map-mask = <0x00000000 0x00000000 0x00000000 0x00000007>; + interrupt-map = <0x00000000 0x00000000 0x00000000 0x00000001 0x00000002 0x00000001 0x00000000 0x00000000 0x00000000 0x00000002 0x00000002 0x00000002 0x00000000 0x00000000 0x00000000 0x00000003 0x00000002 0x00000003 0x00000000 0x00000000 0x00000000 0x00000004 0x00000002 0x00000004>; + resets = <0x00000010 0x00000091 0x00000010 0x00000092 0x00000010 0x00000093 0x00000010 0x00000094 0x00000010 0x00000095 0x00000010 0x00000096>; + reset-names = "rst_mst0", "rst_slv0", "rst_slv", "rst_brg", "rst_core", "rst_apb"; + clocks = <0x0000000f 0x000000cb 0x0000000f 0x000000c9 0x0000000f 0x000000ca>; + clock-names = "tl", "axi_mst0", "apb"; + status = "disabled"; + phandle = <0x00000067>; + }; + mailbox@0 { + compatible = "starfive,mail_box"; + reg = <0x00000000 0x13060000 0x00000000 0x00001000>; + clocks = <0x0000000f 0x00000071>; + clock-names = "clk_apb"; + resets = <0x00000010 0x00000044>; + reset-names = "mbx_rre"; + interrupts = <0x0000001a 0x0000001b>; + #mbox-cells = <0x00000002>; + status = "disabled"; + phandle = <0x0000001a>; + }; + mailbox_client@0 { + compatible = "starfive,mailbox-test"; + mbox-names = "rx", "tx"; + mboxes = <0x0000001a 0x00000000 0x00000001 0x0000001a 0x00000001 0x00000000>; + status = "disabled"; + phandle = <0x00000068>; + }; + dssctrl@295B0000 { + compatible = "verisilicon,dss-ctrl", "syscon"; + reg = <0x00000000 0x295b0000 0x00000000 0x00000090>; + phandle = <0x0000001b>; + }; + hdmi-output { + compatible = "verisilicon,hdmi-encoder"; + verisilicon,dss-syscon = <0x0000001b>; + verisilicon,mux-mask = <0x00000070 0x00000380>; + verisilicon,mux-val = <0x00000040 0x00000280>; + status = "disabled"; + phandle = <0x00000069>; + }; + dc8200@29400000 { + compatible = "verisilicon,dc8200"; + reg = <0x00000000 0x29400000 0x00000000 0x00000100 0x00000000 0x29400800 0x00000000 0x00002000 0x00000000 0x17030000 0x00000000 0x00001000>; + interrupts = <0x0000005f>; + status = "disabled"; + clocks = <0x0000000f 0x00000026 0x0000000f 0x00000027 0x0000000f 0x00000032 0x0000000f 0x0000004c 0x0000000f 0x00000052 0x0000000f 0x0000003c 0x0000000f 0x00000035 0x0000000f 0x00000060 0x0000000f 0x0000003a 0x0000000f 0x0000003e 0x0000000f 0x0000000a 0x0000000f 0x0000003d 0x0000000f 0x0000003f 0x0000000f 0x000000a2 0x0000001c 0x00000169 0x0000001c 0x0000016a 0x0000001c 0x00000166 0x0000001c 0x00000167 0x0000001c 0x00000168>; + clock-names = "noc_cpu", "noc_cfg0", "noc_gpu", "noc_vdec", "noc_venc", "noc_disp", "noc_isp", "noc_stg", "vout_src", "top_vout_axi", "ahb1", "top_vout_ahb", "top_vout_hdmiTX0", "i2stx", "pix_clk", "vout_pix1", "axi_clk", "core_clk", "vout_ahb"; + resets = <0x00000010 0x0000002b 0x00000010 0x000000e0 0x00000010 0x000000e1 0x00000010 0x000000e2 0x00000010 0x00000019 0x00000010 0x00000018 0x00000010 0x00000017 0x00000010 0x0000001b 0x00000010 0x0000001f 0x00000010 0x00000000 0x00000010 0x0000001a 0x00000010 0x0000001c 0x00000010 0x0000001e 0x00000010 0x0000001d>; + reset-names = "rst_vout_src", "rst_axi", "rst_ahb", "rst_core", "rst_noc_cpu", "rst_noc_axicfg0", "rst_noc_apb", "rst_noc_gpu", "rst_noc_vdec", "rst_jtag2apb", "rst_noc_disp", "rst_noc_isp", "rst_noc_stg", "rst_noc_ddrc"; + phandle = <0x0000006a>; + }; + mipi-dphy@295e0000 { + compatible = "starfive,jh7100-mipi-dphy-tx"; + reg = <0x00000000 0x295e0000 0x00000000 0x00010000>; + clocks = <0x0000001c 0x00000170>; + clock-names = "dphy_txesc"; + resets = <0x00000010 0x000000ea 0x00000010 0x000000eb>; + reset-names = "dphy_sys", "dphy_txbytehs"; + #phy-cells = <0x00000000>; + status = "disabled"; + phandle = <0x0000001d>; + }; + mipi@295d0000 { + compatible = "cdns,dsi"; + reg = <0x00000000 0x295d0000 0x00000000 0x00010000>; + reg-names = "dsi"; + clocks = <0x0000001c 0x0000016d 0x0000001c 0x0000016c 0x0000001c 0x0000016f 0x0000001c 0x0000016e>; + clock-names = "sys", "apb", "txesc", "dpi"; + resets = <0x00000010 0x000000e3 0x00000010 0x000000e4 0x00000010 0x000000e5 0x00000010 0x000000e6 0x00000010 0x000000e7 0x00000010 0x000000e8>; + reset-names = "dsi_dpi", "dsi_apb", "dsi_rxesc", "dsi_sys", "dsi_txbytehs", "dsi_txesc"; + phys = <0x0000001d>; + phy-names = "dphy"; + status = "disabled"; + phandle = <0x0000006b>; + port { + endpoint { + phandle = <0x0000006c>; + }; + }; + panel@0 { + status = "disabled"; + phandle = <0x0000006d>; + }; + }; + hdmi@29590000 { + compatible = "rockchip,rk3036-inno-hdmi"; + reg = <0x00000000 0x29590000 0x00000000 0x00004000>; + status = "disabled"; + clocks = <0x0000001c 0x00000173 0x0000001c 0x00000171 0x0000001c 0x00000172>; + clock-names = "sysclk", "mclk", "bclk"; + resets = <0x00000010 0x000000e9>; + reset-names = "hdmi_tx"; + phandle = <0x0000006e>; + }; + snd-card { + compatible = "simple-audio-card"; + simple-audio-card,name = "Starfive-Multi-Sound-Card"; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + phandle = <0x0000006f>; + simple-audio-card,dai-link@0 { + reg = <0x00000000>; + format = "left_j"; + bitclock-master = <0x0000001e>; + frame-master = <0x0000001e>; + status = "okay"; + cpu { + sound-dai = <0x0000001f>; + phandle = <0x0000001e>; + }; + codec { + sound-dai = <0x00000020>; + }; + }; + }; + e24@0 { + compatible = "starfive,e24"; + reg = <0x00000000 0xc0110000 0x00000000 0x00001000 0x00000000 0xc0111000 0x00000000 0x0001f000>; + reg-names = "ecmd", "espace"; + clocks = <0x0000000f 0x000000d6 0x0000000f 0x000000d7 0x0000000f 0x000000d8>; + clock-names = "clk_rtc", "clk_core", "clk_dbg"; + resets = <0x00000010 0x00000084>; + reset-names = "e24_core"; + starfive,stg-syscon = <0x00000011>; + interrupt-parent = <0x00000002>; + firmware-name = "e24_elf"; + irq-mode = <0x00000001>; + mbox-names = "tx", "rx"; + mboxes = <0x0000001a 0x00000000 0x00000002 0x0000001a 0x00000002 0x00000000>; + #address-cells = <0x00000001>; + #size-cells = <0x00000001>; + ranges = <0xc0000000 0x00000000 0xc0000000 0x00200000>; + status = "disabled"; + phandle = <0x00000070>; + dsp@0 { + }; + }; + dmc@100b0000 { + compatible = "starfive,jh7110-dmc"; + reg = <0x00000000 0x15700000 0x00000000 0x00010000 0x00000000 0x13000000 0x00000000 0x00010000>; + resets = <0x00000010 0x00000026 0x00000010 0x00000027 0x00000010 0x00000028>; + reset-names = "axi", "osc", "apb"; + clock-frequency = <0x00000855>; + u-boot,dm-spl; + phandle = <0x00000071>; + }; + }; + aliases { + spi0 = "/soc/spi@13010000"; + gpio0 = "/soc/gpio@13040000"; + ethernet0 = "/soc/ethernet@16030000"; + ethernet1 = "/soc/ethernet@16040000"; + mmc0 = "/soc/sdio0@16010000"; + mmc1 = "/soc/sdio1@16020000"; + i2c0 = "/soc/i2c5@12050000"; + }; + chosen { + stdout-path = "/soc/serial@10000000:115200"; + starfive,boot-hart-id = <0x00000001>; + u-boot,dm-spl; + }; + memory@80000000 { + u-boot,dm-spl; + }; + firmware { + spi0 = "/soc/qspi@11860000"; + u-boot,dm-spl; + }; + config { + u-boot,dm-spl; + u-boot,spl-payload-offset = <0x00100000>; + }; + __symbols__ { + osc = "/osc"; + gmac1_rmii_refin = "/gmac1_rmii_refin"; + gmac1_rgmii_rxin = "/gmac1_rgmii_rxin"; + i2stx_bclk_ext = "/i2stx_bclk_ext"; + i2stx_lrck_ext = "/i2stx_lrck_ext"; + i2srx_bclk_ext = "/i2srx_bclk_ext"; + i2srx_lrck_ext = "/i2srx_lrck_ext"; + tdm_ext = "/tdm_ext"; + mclk_ext = "/mclk_ext"; + jtag_tck_inner = "/jtag_tck_inner"; + bist_apb = "/bist_apb"; + stg_apb = "/stg_apb"; + gmac0_rmii_refin = "/gmac0_rmii_refin"; + gmac0_rgmii_rxin = "/gmac0_rgmii_rxin"; + clk_rtc = "/clk_rtc"; + hdmitx0_pixelclk = "/hdmitx0_pixelclk"; + mipitx_dphy_rxesc = "/mipitx_dphy_rxesc"; + mipitx_dphy_txbytehs = "/mipitx_dphy_txbytehs"; + cpus = "/cpus"; + cpu0 = "/cpus/cpu@0"; + cpu0intctrl = "/cpus/cpu@0/interrupt-controller"; + cpu1 = "/cpus/cpu@1"; + cpu1intctrl = "/cpus/cpu@1/interrupt-controller"; + cpu2 = "/cpus/cpu@2"; + cpu2intctrl = "/cpus/cpu@2/interrupt-controller"; + cpu3 = "/cpus/cpu@3"; + cpu3intctrl = "/cpus/cpu@3/interrupt-controller"; + cpu4 = "/cpus/cpu@4"; + cpu4intctrl = "/cpus/cpu@4/interrupt-controller"; + soc = "/soc"; + cachectrl = "/soc/cache-controller@2010000"; + aon_syscon = "/soc/aon_syscon@17010000"; + stg_syscon = "/soc/stg_syscon@10240000"; + sys_syscon = "/soc/sys_syscon@13030000"; + clint = "/soc/clint@2000000"; + plic = "/soc/plic@c000000"; + clkgen = "/soc/clock-controller"; + clkvout = "/soc/clock-controller@295C0000"; + clkisp = "/soc/clock-controller@19810000"; + qspi = "/soc/spi@13010000"; + nor_flash = "/soc/spi@13010000/nor-flash@0"; + otp = "/soc/otp@17050000"; + usbdrd30 = "/soc/usbdrd"; + usbdrd_cdns3 = "/soc/usbdrd/usb@10100000"; + timer = "/soc/timer@13050000"; + wdog = "/soc/wdog@13070000"; + rtc = "/soc/rtc@17040000"; + pmu = "/soc/pmu@17030000"; + uart0 = "/soc/serial@10000000"; + uart1 = "/soc/serial@10010000"; + uart2 = "/soc/serial@10020000"; + uart3 = "/soc/serial@12000000"; + uart4 = "/soc/serial@12010000"; + uart5 = "/soc/serial@12020000"; + dma = "/soc/dma-controller@16050000"; + gpio = "/soc/gpio@13040000"; + uart0_pins = "/soc/gpio@13040000/uart0-0"; + mmc0_pins = "/soc/gpio@13040000/mmc0-pins"; + sdcard1_pins = "/soc/gpio@13040000/sdcard1-pins"; + gpioa = "/soc/gpio@17020000"; + trng = "/soc/trng@1600C000"; + sec_dma = "/soc/sec_dma@16008000"; + crypto = "/soc/crypto@16000000"; + i2c6 = "/soc/i2c@12060000"; + i2c0 = "/soc/i2c@10030000"; + i2c1 = "/soc/i2c@10040000"; + i2c5 = "/soc/i2c5@12050000"; + pmic = "/soc/i2c5@12050000/axp15060_reg@36"; + sdio0 = "/soc/sdio0@16010000"; + sdio1 = "/soc/sdio1@16020000"; + vin_sysctl = "/soc/vin_sysctl@19800000"; + jpu = "/soc/jpu@11900000"; + vpu_dec = "/soc/vpu_dec@130A0000"; + vpu_enc = "/soc/vpu_enc@130B0000"; + rstgen = "/soc/reset-controller"; + stmmac_axi_setup = "/soc/stmmac-axi-config"; + gmac0 = "/soc/ethernet@16030000"; + phy0 = "/soc/ethernet@16030000/ethernet-phy@0"; + gmac1 = "/soc/ethernet@16040000"; + phy1 = "/soc/ethernet@16040000/ethernet-phy@1"; + gpu = "/soc/gpu@18000000"; + can0 = "/soc/can@130d0000"; + can1 = "/soc/can@130e0000"; + tdm = "/soc/tdm@10090000"; + spdif0 = "/soc/spdif0@100a0000"; + pwmdac = "/soc/pwmdac@100b0000"; + i2stx = "/soc/i2stx@100c0000"; + pdm = "/soc/pdm@100d0000"; + i2srx_3ch = "/soc/i2srx_3ch@100e0000"; + i2stx_4ch0 = "/soc/i2stx_4ch0@120b0000"; + i2stx_4ch1 = "/soc/i2stx_4ch1@120c0000"; + ptc = "/soc/pwm@120d0000"; + spdif_transmitter = "/soc/spdif_transmitter"; + spdif_receiver = "/soc/spdif_receiver"; + pwmdac_codec = "/soc/pwmdac-transmitter"; + dmic_codec = "/soc/dmic_codec"; + spi0 = "/soc/spi@10060000"; + pcie0 = "/soc/pcie@2B000000"; + pcie1 = "/soc/pcie@2C000000"; + mailbox_contrl0 = "/soc/mailbox@0"; + mailbox_client0 = "/soc/mailbox_client@0"; + dssctrl = "/soc/dssctrl@295B0000"; + hdmi_output = "/soc/hdmi-output"; + dc8200 = "/soc/dc8200@29400000"; + mipi_dphy = "/soc/mipi-dphy@295e0000"; + mipi_dsi = "/soc/mipi@295d0000"; + dsi_out_port = "/soc/mipi@295d0000/port/endpoint"; + mipi_panel = "/soc/mipi@295d0000/panel@0"; + hdmi = "/soc/hdmi@29590000"; + sound = "/soc/snd-card"; + sndcpu0 = "/soc/snd-card/simple-audio-card,dai-link@0/cpu"; + co_process = "/soc/e24@0"; + dmc = "/soc/dmc@100b0000"; + }; +}; diff --git a/include/machine/plic-star64.h b/include/machine/plic-star64.h new file mode 100644 index 0000000..929bb94 --- /dev/null +++ b/include/machine/plic-star64.h @@ -0,0 +1,28 @@ +#ifndef _PLIC_STAR64_H_ +#define _PLIC_STAR64_H_ + +// definitions of PLIC constants for several machines: HiFive1-revB, Qemu +// sifive_u and Qemu sifive_e. + +#define PLIC_NUM_INTR_SOURCES 136 + +#if HAS_S_MODE +#define S_MODE_HART_MULTIPLIER_OFFS 1 +#else +#define S_MODE_HART_MULTIPLIER_OFFS 0 +#endif + +#define PLIC_ENABLE_HART_OFFS (0x80 * (BOOT_HART_ID + S_MODE_HART_MULTIPLIER_OFFS)) +#define PLIC_THRESH_HART_OFFS (0x1000 * (BOOT_HART_ID + S_MODE_HART_MULTIPLIER_OFFS)) +#define PLIC_CLAIM_HART_OFFS (0x1000 * (BOOT_HART_ID + S_MODE_HART_MULTIPLIER_OFFS)) + +#define PLIC_BASE 0x0c000000 +#define PLIC_PRIORITY (PLIC_BASE + 0x00000000) +#define PLIC_PENDING (PLIC_BASE + 0x00001000) +#define PLIC_ENABLE (PLIC_BASE + 0x00002000 + PLIC_ENABLE_HART_OFFS) +#define PLIC_THRESHOLD (PLIC_BASE + 0x00200000 + PLIC_THRESH_HART_OFFS) +#define PLIC_CLAIM_RW (PLIC_BASE + 0x00200004 + PLIC_CLAIM_HART_OFFS) + +#define PLIC_MAX_PRIORITY 7 + +#endif // ifndef _PLIC_STAR64_H_ diff --git a/include/machine/star64.h b/include/machine/star64.h new file mode 100644 index 0000000..fac8766 --- /dev/null +++ b/include/machine/star64.h @@ -0,0 +1,40 @@ +#ifndef _STAR64_H_ +#define _STAR64_H_ + +#define BOOT_HART_ID 1 + +#define BOOT_MODE_M 0 +#define HAS_S_MODE 1 + +#define PAGE_SIZE 512 // bytes + +#define LINUX_IMAGE_HEADER_TEXT_OFFSET 0x40200000 + +// wild guess: +// xtal-clk { +// compatible = "fixed-clock"; +// clock-frequency = <0x2625a00>; +#define ONE_SECOND 1000000 + +#define IRQ_NUM_BASE 16 + +// reg = <0x30002000 0x1000>; +// interrupts = <0x14 0x04>; +#define UART0_IRQ_NUM (IRQ_NUM_BASE + 4) + +#define UART_BASE 0x10000000 + +// reg = <0x200008c4 0x1000>; +#define GPIO_BASE 0x200008c4 + +// ox64.dts: +// timer@e4000000 { +// compatible = "thead,c900-clint"; +// reg = <0xe4000000 0xc000>; +#define CLINT0_BASE_ADDRESS 0x2000000 + +#define NUM_HARTS 1 + +#include "machine/plic-star64.h" + +#endif // ifndef _STAR64_H_ diff --git a/scripts/star64-term.sh b/scripts/star64-term.sh new file mode 100755 index 0000000..5dd44d4 --- /dev/null +++ b/scripts/star64-term.sh @@ -0,0 +1,3 @@ +#!/bin/bash + +sudo picocom -b 115200 --imap lfcrlf --send-cmd 'gkermit -iXvs' /dev/ttyUSB0 diff --git a/src/boot.S b/src/boot.S index 63f7847..9839f93 100644 --- a/src/boot.S +++ b/src/boot.S @@ -42,8 +42,8 @@ _start_kernel: // 2.1.3 Early Boot: Setup mtvec Register csrwi BOOT_REG_IE, 0 // > It is recommended to disable interrupts globally using mstatus.mie prior to changing mtvec. // > For sanity's sake we set up an early trap vector that just does nothing. - la t0, early_trap_vector - csrw BOOT_REG_TVEC, t0 + // la t0, early_trap_vector + // csrw BOOT_REG_TVEC, t0 #if BOOT_MODE_M && HAS_S_MODE csrwi mideleg, 0 // disable trap delegation, all interrupts and exceptions will be handled in machine mode @@ -72,6 +72,10 @@ _start_kernel: mv t1, a0 beq t0, t1, init_segments +park_nonboot: wfi // parked hart will sleep waiting for interrupt + j park_nonboot + +/* hart_sync_code: // Only non-boot harts run this code: // Step 1: every non-boot hart writes 1 to MSIP register: @@ -92,6 +96,7 @@ hart_sync_code: // now that we've gone through hart sync dance, continue to higher level // init code where each hart is allowed to run: j init + */ init_segments: @@ -102,12 +107,15 @@ init_segments: la t0, bss_start la t1, bss_end - bgeu t0, t1, synchronize_harts + // bgeu t0, t1, synchronize_harts + bgeu t0, t1, init + clean_bss_loop: sw zero, (t0) addi t0, t0, 4 bltu t0, t1, clean_bss_loop +/* // Now that the memory segments are init'ed, the boot hart will // synchronize all other harts: loop from 1 to NUM_HARTS, and for all of // them do the following: read its MSIP register, wait until they all @@ -147,6 +155,7 @@ per_hart_write_loop: skip_boot_hart2: addi t0, t0, 1 blt t0, t5, per_hart_write_loop // jump if hartID < NUM_HARTS +*/ init: diff --git a/src/drivers/uart/uart-star64.c b/src/drivers/uart/uart-star64.c new file mode 100644 index 0000000..8250155 --- /dev/null +++ b/src/drivers/uart/uart-star64.c @@ -0,0 +1,34 @@ +#include "mmreg.h" +#include "plic.h" +#include "drivers/uart/uart-ns16550a.h" + +#define read(reg) read8(UART_BASE + reg) +#define write(reg, val) write8(UART_BASE + reg, val) + +// uart_machine_init does a machine-specific initialization of UART. +void uart_machine_init() { + write(UART_LCR, 0b11); // 8 data bits in LCR[1:0] + write(UART_FCR, 0b1); // enable FIFO in FCR[0] + write(UART_IER, 0b1); // enable received data available interrupts in IER[0] + + // plic_set_intr_priority(UART0_IRQ_NUM, PLIC_MAX_PRIORITY); + // plic_set_threshold(PLIC_MAX_PRIORITY - 1); + // plic_enable_intr(UART0_IRQ_NUM); +} + +void uart_writechar(char ch) { + write(UART_THR, ch); +} + +int uart_rx_num_avail() { + uint8_t lsr = read(UART_LSR); + return lsr & 0b1; +} + +char uart_readchar() { + return read(UART_RBR); +} + +void uart_machine_wait_status() { + // no-op +} diff --git a/src/kernel.c b/src/kernel.c index c343a2a..4aa7346 100644 --- a/src/kernel.c +++ b/src/kernel.c @@ -20,6 +20,9 @@ spinlock init_lock = 0; int user_stack_size = 0; +// kinit: cpu 1FDs +// Welcome to s + void kinit(regsize_t hartid, uintptr_t fdt_header_addr) { acquire(&init_lock); unsigned int cpu_id = hartid; @@ -28,14 +31,15 @@ void kinit(regsize_t hartid, uintptr_t fdt_header_addr) { // TODO: support multi-core park_hart(); } - plic_init(); + // plic_init(); drivers_init(); #ifdef CONFIG_LCD_ENABLED lcd_init(); #endif - kprintf("kinit: cpu %d\n", cpu_id); - fdt_init(fdt_header_addr); - kprintf("bootargs: %s\n", fdt_get_bootargs()); + // kprintf("kinit: cpu %d\n", cpu_id); + // fdt_init(fdt_header_addr); + // kprintf("bootargs: %s\n", fdt_get_bootargs()); + // kprintf("yo\n"); init_trap_vector(); void* paged_mem_end = init_pmp(); init_timer(); // must go after init_trap_vector because it might rewrite mtvec/mscratch @@ -48,14 +52,14 @@ void kinit(regsize_t hartid, uintptr_t fdt_header_addr) { #endif char const* str = "foo"; // this is a random string to test out %s in kprintf() void *p = (void*)0xabcdf10a; // this is a random hex to test out %p in kprintf() - kprintf("kprintf test: str=%s, ptr=%p, pos int=%d, neg int=%d\n", - str, p, 1337, MAX_NEG_INT); + // kprintf("kprintf test: str=%s, ptr=%p, pos int=%d, neg int=%d\n", + // str, p, 1337, MAX_NEG_INT); uint32_t runflags = parse_runflags(); user_stack_size = (runflags == RUNFLAGS_TINY_STACK) ? 512 : PAGE_SIZE; int running_tests = runflags & RUNFLAGS_TESTS; init_paged_memory(paged_mem_end); if (!running_tests) { - do_page_report(paged_mem_end); + // do_page_report(paged_mem_end); } fs_init(); init_process_table(runflags, hartid); diff --git a/src/machine/star64/timer.c b/src/machine/star64/timer.c new file mode 100644 index 0000000..a195da1 --- /dev/null +++ b/src/machine/star64/timer.c @@ -0,0 +1,29 @@ +#include "mmreg.h" +#include "timer.h" + +#define STIMECMP_LO 0xd000 +#define STIMECMP_HI 0xd004 + +void init_timer() { + // nothing to be done on this machine +} + +uint64_t time_get_now() { + register uint64_t a0 asm ("a0"); + asm volatile ( + "csrr a0, time" + : "=r"(a0) // output in a0 + ); + return a0; +} + +void set_timer_after(uint64_t delta) { + uint64_t now = time_get_now(); + uint64_t future = now + delta; + + // write the uint64_t value in two separate 32-bit writes: + uint32_t future_lo = future & 0xffffffff; + uint32_t future_hi = future >> 32; + write32(CLINT0_BASE_ADDRESS + STIMECMP_LO, future_lo); + write32(CLINT0_BASE_ADDRESS + STIMECMP_HI, future_hi); +}