From 6a7f9b52850f9a438ece621878564e630388f0d2 Mon Sep 17 00:00:00 2001 From: Robin Mueller Date: Sun, 28 Sep 2025 14:46:49 +0200 Subject: [PATCH] add a lot of register derives + serde support for cortex-ar --- .github/workflows/build.yml | 2 +- cortex-ar/CHANGELOG.md | 2 ++ cortex-ar/Cargo.toml | 6 ++++-- cortex-ar/src/mmu.rs | 10 +++++++++- cortex-ar/src/pmsav7.rs | 1 + cortex-ar/src/register/actlr.rs | 3 +++ cortex-ar/src/register/actlr2.rs | 3 +++ cortex-ar/src/register/adfsr.rs | 3 +++ cortex-ar/src/register/aidr.rs | 3 +++ cortex-ar/src/register/aifsr.rs | 3 +++ cortex-ar/src/register/amair0.rs | 3 +++ cortex-ar/src/register/amair1.rs | 3 +++ cortex-ar/src/register/armv8r/cntfrq.rs | 3 +++ cortex-ar/src/register/armv8r/cnthctl.rs | 3 ++- cortex-ar/src/register/armv8r/cnthp_ctl.rs | 9 +++++---- cortex-ar/src/register/armv8r/cnthp_cval.rs | 3 +++ cortex-ar/src/register/armv8r/cnthp_tval.rs | 3 +++ cortex-ar/src/register/armv8r/cntkctl.rs | 3 ++- cortex-ar/src/register/armv8r/cntp_ctl.rs | 3 ++- cortex-ar/src/register/armv8r/cntp_cval.rs | 3 +++ cortex-ar/src/register/armv8r/cntp_tval.rs | 3 +++ cortex-ar/src/register/armv8r/cntpct.rs | 3 +++ cortex-ar/src/register/armv8r/cntv_ctl.rs | 3 ++- cortex-ar/src/register/armv8r/cntv_cval.rs | 3 +++ cortex-ar/src/register/armv8r/cntv_tval.rs | 3 +++ cortex-ar/src/register/armv8r/cntvct.rs | 3 +++ cortex-ar/src/register/armv8r/cntvoff.rs | 3 +++ cortex-ar/src/register/armv8r/hacr.rs | 3 +++ cortex-ar/src/register/armv8r/hactlr.rs | 1 + cortex-ar/src/register/armv8r/hactlr2.rs | 3 +++ cortex-ar/src/register/armv8r/hadfsr.rs | 3 +++ cortex-ar/src/register/armv8r/haifsr.rs | 3 +++ cortex-ar/src/register/armv8r/hamair0.rs | 3 +++ cortex-ar/src/register/armv8r/hamair1.rs | 3 +++ cortex-ar/src/register/armv8r/hcptr.rs | 3 +++ cortex-ar/src/register/armv8r/hcr.rs | 3 +++ cortex-ar/src/register/armv8r/hcr2.rs | 3 +++ cortex-ar/src/register/armv8r/hdcr.rs | 3 +++ cortex-ar/src/register/armv8r/hdfar.rs | 3 +++ cortex-ar/src/register/armv8r/hifar.rs | 3 +++ cortex-ar/src/register/armv8r/hmair0.rs | 3 +++ cortex-ar/src/register/armv8r/hmair1.rs | 3 +++ cortex-ar/src/register/armv8r/hmpuir.rs | 3 ++- cortex-ar/src/register/armv8r/hpfar.rs | 3 +++ cortex-ar/src/register/armv8r/hprbar.rs | 6 +++++- cortex-ar/src/register/armv8r/hprbar0.rs | 3 +++ cortex-ar/src/register/armv8r/hprbar1.rs | 3 +++ cortex-ar/src/register/armv8r/hprbar10.rs | 3 +++ cortex-ar/src/register/armv8r/hprbar11.rs | 3 +++ cortex-ar/src/register/armv8r/hprbar12.rs | 3 +++ cortex-ar/src/register/armv8r/hprbar13.rs | 3 +++ cortex-ar/src/register/armv8r/hprbar14.rs | 3 +++ cortex-ar/src/register/armv8r/hprbar15.rs | 3 +++ cortex-ar/src/register/armv8r/hprbar2.rs | 3 +++ cortex-ar/src/register/armv8r/hprbar3.rs | 3 +++ cortex-ar/src/register/armv8r/hprbar4.rs | 3 +++ cortex-ar/src/register/armv8r/hprbar5.rs | 3 +++ cortex-ar/src/register/armv8r/hprbar6.rs | 3 +++ cortex-ar/src/register/armv8r/hprbar7.rs | 3 +++ cortex-ar/src/register/armv8r/hprbar8.rs | 3 +++ cortex-ar/src/register/armv8r/hprbar9.rs | 3 +++ cortex-ar/src/register/armv8r/hprenr.rs | 3 +++ cortex-ar/src/register/armv8r/hprlar.rs | 2 +- cortex-ar/src/register/armv8r/hprlar0.rs | 3 +++ cortex-ar/src/register/armv8r/hprlar1.rs | 3 +++ cortex-ar/src/register/armv8r/hprlar10.rs | 3 +++ cortex-ar/src/register/armv8r/hprlar11.rs | 3 +++ cortex-ar/src/register/armv8r/hprlar12.rs | 3 +++ cortex-ar/src/register/armv8r/hprlar13.rs | 3 +++ cortex-ar/src/register/armv8r/hprlar14.rs | 3 +++ cortex-ar/src/register/armv8r/hprlar15.rs | 3 +++ cortex-ar/src/register/armv8r/hprlar2.rs | 3 +++ cortex-ar/src/register/armv8r/hprlar3.rs | 3 +++ cortex-ar/src/register/armv8r/hprlar4.rs | 3 +++ cortex-ar/src/register/armv8r/hprlar5.rs | 3 +++ cortex-ar/src/register/armv8r/hprlar6.rs | 3 +++ cortex-ar/src/register/armv8r/hprlar7.rs | 3 +++ cortex-ar/src/register/armv8r/hprlar8.rs | 3 +++ cortex-ar/src/register/armv8r/hprlar9.rs | 3 +++ cortex-ar/src/register/armv8r/hprselr.rs | 3 +++ cortex-ar/src/register/armv8r/hsctlr.rs | 2 +- cortex-ar/src/register/armv8r/hsr.rs | 3 +++ cortex-ar/src/register/armv8r/hstr.rs | 3 +++ cortex-ar/src/register/armv8r/htpidr.rs | 3 +++ cortex-ar/src/register/armv8r/prbar.rs | 6 +++++- cortex-ar/src/register/armv8r/prbar0.rs | 3 +++ cortex-ar/src/register/armv8r/prbar1.rs | 3 +++ cortex-ar/src/register/armv8r/prbar10.rs | 3 +++ cortex-ar/src/register/armv8r/prbar11.rs | 3 +++ cortex-ar/src/register/armv8r/prbar12.rs | 3 +++ cortex-ar/src/register/armv8r/prbar13.rs | 3 +++ cortex-ar/src/register/armv8r/prbar14.rs | 3 +++ cortex-ar/src/register/armv8r/prbar15.rs | 3 +++ cortex-ar/src/register/armv8r/prbar2.rs | 3 +++ cortex-ar/src/register/armv8r/prbar3.rs | 3 +++ cortex-ar/src/register/armv8r/prbar4.rs | 3 +++ cortex-ar/src/register/armv8r/prbar5.rs | 3 +++ cortex-ar/src/register/armv8r/prbar6.rs | 3 +++ cortex-ar/src/register/armv8r/prbar7.rs | 3 +++ cortex-ar/src/register/armv8r/prbar8.rs | 3 +++ cortex-ar/src/register/armv8r/prbar9.rs | 3 +++ cortex-ar/src/register/armv8r/prlar.rs | 2 +- cortex-ar/src/register/armv8r/prlar0.rs | 3 +++ cortex-ar/src/register/armv8r/prlar1.rs | 3 +++ cortex-ar/src/register/armv8r/prlar10.rs | 3 +++ cortex-ar/src/register/armv8r/prlar11.rs | 3 +++ cortex-ar/src/register/armv8r/prlar12.rs | 3 +++ cortex-ar/src/register/armv8r/prlar13.rs | 3 +++ cortex-ar/src/register/armv8r/prlar14.rs | 3 +++ cortex-ar/src/register/armv8r/prlar15.rs | 3 +++ cortex-ar/src/register/armv8r/prlar2.rs | 3 +++ cortex-ar/src/register/armv8r/prlar3.rs | 3 +++ cortex-ar/src/register/armv8r/prlar4.rs | 3 +++ cortex-ar/src/register/armv8r/prlar5.rs | 3 +++ cortex-ar/src/register/armv8r/prlar6.rs | 3 +++ cortex-ar/src/register/armv8r/prlar7.rs | 3 +++ cortex-ar/src/register/armv8r/prlar8.rs | 3 +++ cortex-ar/src/register/armv8r/prlar9.rs | 3 +++ cortex-ar/src/register/armv8r/prselr.rs | 3 +++ cortex-ar/src/register/armv8r/vbar.rs | 1 + cortex-ar/src/register/ccsidr.rs | 4 ++-- cortex-ar/src/register/clidr.rs | 3 +++ cortex-ar/src/register/contextidr.rs | 3 +++ cortex-ar/src/register/cpacr.rs | 3 +++ cortex-ar/src/register/cpsr.rs | 5 ++++- cortex-ar/src/register/csselr.rs | 7 +++++-- cortex-ar/src/register/ctr.rs | 3 +++ cortex-ar/src/register/dccimvac.rs | 3 +++ cortex-ar/src/register/dccisw.rs | 3 +++ cortex-ar/src/register/dccmvac.rs | 3 +++ cortex-ar/src/register/dccmvau.rs | 3 +++ cortex-ar/src/register/dccsw.rs | 3 +++ cortex-ar/src/register/dcimvac.rs | 3 +++ cortex-ar/src/register/dcisw.rs | 3 +++ cortex-ar/src/register/dfar.rs | 4 +++- cortex-ar/src/register/dfsr.rs | 6 ++++-- cortex-ar/src/register/dlr.rs | 3 +++ cortex-ar/src/register/dracr.rs | 3 ++- cortex-ar/src/register/drbar.rs | 2 ++ cortex-ar/src/register/drsr.rs | 4 +++- cortex-ar/src/register/dspsr.rs | 3 +++ cortex-ar/src/register/fcseidr.rs | 3 +++ cortex-ar/src/register/icc_pmr.rs | 3 +++ cortex-ar/src/register/id_afr0.rs | 3 +++ cortex-ar/src/register/id_dfr0.rs | 3 +++ cortex-ar/src/register/id_isar0.rs | 3 +++ cortex-ar/src/register/id_isar1.rs | 3 +++ cortex-ar/src/register/id_isar2.rs | 3 +++ cortex-ar/src/register/id_isar3.rs | 3 +++ cortex-ar/src/register/id_isar4.rs | 3 +++ cortex-ar/src/register/id_isar5.rs | 3 +++ cortex-ar/src/register/id_mmfr0.rs | 3 +++ cortex-ar/src/register/id_mmfr1.rs | 3 +++ cortex-ar/src/register/id_mmfr2.rs | 3 +++ cortex-ar/src/register/id_mmfr3.rs | 3 +++ cortex-ar/src/register/id_mmfr4.rs | 3 +++ cortex-ar/src/register/id_pfr0.rs | 3 +++ cortex-ar/src/register/id_pfr1.rs | 3 +++ cortex-ar/src/register/ifar.rs | 4 +++- cortex-ar/src/register/ifsr.rs | 7 +++++-- cortex-ar/src/register/imp/imp_atcmregionr.rs | 3 +++ cortex-ar/src/register/imp/imp_bpctlr.rs | 3 +++ cortex-ar/src/register/imp/imp_btcmregionr.rs | 3 +++ cortex-ar/src/register/imp/imp_buildoptr.rs | 3 +++ cortex-ar/src/register/imp/imp_bustimeoutr.rs | 3 +++ cortex-ar/src/register/imp/imp_cbar.rs | 5 +++-- cortex-ar/src/register/imp/imp_cdbgdcd.rs | 3 +++ cortex-ar/src/register/imp/imp_cdbgdci.rs | 3 +++ cortex-ar/src/register/imp/imp_cdbgdct.rs | 3 +++ cortex-ar/src/register/imp/imp_cdbgdr0.rs | 3 +++ cortex-ar/src/register/imp/imp_cdbgdr1.rs | 3 +++ cortex-ar/src/register/imp/imp_cdbgdr2.rs | 3 +++ cortex-ar/src/register/imp/imp_cdbgicd.rs | 3 +++ cortex-ar/src/register/imp/imp_cdbgict.rs | 3 +++ cortex-ar/src/register/imp/imp_csctlr.rs | 3 +++ cortex-ar/src/register/imp/imp_ctcmregionr.rs | 3 +++ cortex-ar/src/register/imp/imp_dcerr0.rs | 3 +++ cortex-ar/src/register/imp/imp_dcerr1.rs | 3 +++ cortex-ar/src/register/imp/imp_flasherr0.rs | 3 +++ cortex-ar/src/register/imp/imp_flasherr1.rs | 3 +++ cortex-ar/src/register/imp/imp_flashifregionr.rs | 3 +++ cortex-ar/src/register/imp/imp_icerr0.rs | 3 +++ cortex-ar/src/register/imp/imp_icerr1.rs | 3 +++ cortex-ar/src/register/imp/imp_intmonr.rs | 3 +++ cortex-ar/src/register/imp/imp_memprotctlr.rs | 3 +++ cortex-ar/src/register/imp/imp_periphpregionr.rs | 3 +++ cortex-ar/src/register/imp/imp_pinoptr.rs | 3 +++ cortex-ar/src/register/imp/imp_qosr.rs | 3 +++ cortex-ar/src/register/imp/imp_slavepctlr.rs | 3 +++ cortex-ar/src/register/imp/imp_tcmerr0.rs | 3 +++ cortex-ar/src/register/imp/imp_tcmerr1.rs | 3 +++ cortex-ar/src/register/imp/imp_tcmsyndr0.rs | 3 +++ cortex-ar/src/register/imp/imp_tcmsyndr1.rs | 3 +++ cortex-ar/src/register/imp/imp_testr0.rs | 3 +++ cortex-ar/src/register/iracr.rs | 3 ++- cortex-ar/src/register/irbar.rs | 2 ++ cortex-ar/src/register/irsr.rs | 3 ++- cortex-ar/src/register/mair0.rs | 3 +++ cortex-ar/src/register/mair1.rs | 3 +++ cortex-ar/src/register/mpidr.rs | 4 +++- cortex-ar/src/register/mpuir.rs | 1 + cortex-ar/src/register/nsacr.rs | 3 +++ cortex-ar/src/register/par.rs | 3 +++ cortex-ar/src/register/pmccfiltr.rs | 3 +++ cortex-ar/src/register/pmccntr.rs | 3 +++ cortex-ar/src/register/pmceid0.rs | 3 +++ cortex-ar/src/register/pmceid1.rs | 3 +++ cortex-ar/src/register/pmcntenclr.rs | 3 +++ cortex-ar/src/register/pmcntenset.rs | 3 +++ cortex-ar/src/register/pmcr.rs | 3 +++ cortex-ar/src/register/pmevcntr0.rs | 3 +++ cortex-ar/src/register/pmevcntr1.rs | 3 +++ cortex-ar/src/register/pmevcntr2.rs | 3 +++ cortex-ar/src/register/pmevcntr3.rs | 3 +++ cortex-ar/src/register/pmevtyper0.rs | 3 +++ cortex-ar/src/register/pmevtyper1.rs | 3 +++ cortex-ar/src/register/pmevtyper2.rs | 3 +++ cortex-ar/src/register/pmevtyper3.rs | 3 +++ cortex-ar/src/register/pmintenclr.rs | 3 +++ cortex-ar/src/register/pmintenset.rs | 3 +++ cortex-ar/src/register/pmovsr.rs | 3 +++ cortex-ar/src/register/pmovsset.rs | 3 +++ cortex-ar/src/register/pmselr.rs | 3 +++ cortex-ar/src/register/pmswinc.rs | 3 +++ cortex-ar/src/register/pmuserenr.rs | 3 +++ cortex-ar/src/register/pmxevcntr.rs | 3 +++ cortex-ar/src/register/pmxevtyper.rs | 3 +++ cortex-ar/src/register/revidr.rs | 3 +++ cortex-ar/src/register/rgnr.rs | 3 +++ cortex-ar/src/register/rvbar.rs | 3 +++ cortex-ar/src/register/sctlr.rs | 1 + cortex-ar/src/register/tcmtr.rs | 3 +++ cortex-ar/src/register/tlbtr.rs | 3 +++ cortex-ar/src/register/tpidrprw.rs | 3 +++ cortex-ar/src/register/tpidruro.rs | 3 +++ cortex-ar/src/register/tpidrurw.rs | 3 +++ cortex-ar/src/register/vmpidr.rs | 3 +++ cortex-ar/src/register/vpidr.rs | 3 +++ cortex-ar/src/register/vsctlr.rs | 3 +++ 239 files changed, 706 insertions(+), 36 deletions(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 5967999..e324e29 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -38,7 +38,7 @@ jobs: rustup target add ${{ matrix.target }} - name: Build run: | - cargo build --target ${{ matrix.target }} + cargo build --target ${{ matrix.target }} --features "serde, defmt" cargo build --target ${{ matrix.target }} --no-default-features build-versatileab: diff --git a/cortex-ar/CHANGELOG.md b/cortex-ar/CHANGELOG.md index 39ffd0f..fa90f29 100644 --- a/cortex-ar/CHANGELOG.md +++ b/cortex-ar/CHANGELOG.md @@ -17,6 +17,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/). maintenance by MVA (specific address). - Added new `L1Section::set_section_attrs` and `L1Section::section_attrs` method. Also added low-level `L1Section::new_with_addr_upper_bits_and_attrs` constructor. +- optional `serde` derives behind a `serde` feature gate +- lots of missing `Debug`, `Copy`, `Clone`, `defmt::Format` derives. ### Changed diff --git a/cortex-ar/Cargo.toml b/cortex-ar/Cargo.toml index d461d9e..d0d2ea3 100644 --- a/cortex-ar/Cargo.toml +++ b/cortex-ar/Cargo.toml @@ -26,11 +26,12 @@ version = "0.2.0" [dependencies] arbitrary-int = "2" -bitbybit = "1.3.3" +bitbybit = "1.4" num_enum = { version = "0.7", default-features = false } critical-section = {version = "1.2.0", features = ["restore-state-u8"], optional = true} thiserror = { version = "2", default-features = false } -defmt = {version = "1", optional = true} +defmt = { version = "1", optional = true } +serde = { version = "1", features = ["derive"], default-features = false, optional = true } [build-dependencies] arm-targets = {version = "0.2.0", path = "../arm-targets"} @@ -44,6 +45,7 @@ critical-section-single-core = ["critical-section"] critical-section-multi-core = ["critical-section"] # Adds defmt::Format implementation for the register types defmt = ["dep:defmt", "arbitrary-int/defmt"] +serde = ["dep:serde", "arbitrary-int/serde"] [package.metadata.docs.rs] targets = ["armv7r-none-eabihf", "armv7r-none-eabi", "armv7a-none-eabihf"] diff --git a/cortex-ar/src/mmu.rs b/cortex-ar/src/mmu.rs index 2ab36e3..b9ec065 100644 --- a/cortex-ar/src/mmu.rs +++ b/cortex-ar/src/mmu.rs @@ -2,11 +2,13 @@ use arbitrary_int::{u12, u2, u3, u4}; #[derive(Debug, thiserror::Error)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] #[error("invalid L1 entry type {0:?}")] pub struct InvalidL1EntryType(pub L1EntryType); #[bitbybit::bitenum(u3, exhaustive = true)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] #[derive(Debug, PartialEq, Eq)] pub enum AccessPermissions { PermissionFault = 0b000, @@ -40,6 +42,7 @@ impl AccessPermissions { #[bitbybit::bitenum(u2, exhaustive = true)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] #[derive(Debug, PartialEq, Eq)] #[repr(u8)] pub enum L1EntryType { @@ -60,6 +63,7 @@ pub enum L1EntryType { /// of the B, C, and TEX bits. #[derive(Debug, Copy, Clone, PartialEq, Eq)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct MemoryRegionAttributesRaw { /// TEX bits type_extensions: u3, @@ -80,6 +84,7 @@ impl MemoryRegionAttributesRaw { #[bitbybit::bitenum(u2, exhaustive = true)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] #[derive(Debug)] pub enum CacheableMemoryAttribute { NonCacheable = 0b00, @@ -90,6 +95,7 @@ pub enum CacheableMemoryAttribute { #[derive(Debug, Copy, Clone)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub enum MemoryRegionAttributes { StronglyOrdered, ShareableDevice, @@ -142,6 +148,7 @@ impl MemoryRegionAttributes { /// Individual section attributes for a L1 section. #[derive(Debug, Copy, Clone, PartialEq, Eq)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct SectionAttributes { /// NG bit pub non_global: bool, @@ -205,7 +212,8 @@ impl SectionAttributes { /// /// The ARM Cortex-A architecture programmers manual chapter 9.4 (p.163) or the ARMv7-A and ArmV7-R /// architecture reference manual p.1323 specify these attributes in more detail. -#[bitbybit::bitfield(u32, default = 0x00)] +#[bitbybit::bitfield(u32, default = 0, defmt_fields(feature = "defmt"))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] #[derive(PartialEq, Eq)] pub struct L1Section { /// Section base address upper bits. diff --git a/cortex-ar/src/pmsav7.rs b/cortex-ar/src/pmsav7.rs index f2f6699..d1252ae 100644 --- a/cortex-ar/src/pmsav7.rs +++ b/cortex-ar/src/pmsav7.rs @@ -13,6 +13,7 @@ pub use register::drsr::RegionSize; /// Ways this API can fail #[derive(Debug, Clone, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Error { /// Found too many regions TooManyRegions, diff --git a/cortex-ar/src/register/actlr.rs b/cortex-ar/src/register/actlr.rs index 723d9ab..d6cde04 100644 --- a/cortex-ar/src/register/actlr.rs +++ b/cortex-ar/src/register/actlr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// ACTLR (*Auxiliary Control Register*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Actlr(pub u32); impl SysReg for Actlr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/actlr2.rs b/cortex-ar/src/register/actlr2.rs index b678784..e0fbd1c 100644 --- a/cortex-ar/src/register/actlr2.rs +++ b/cortex-ar/src/register/actlr2.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// ACTLR2 (*Auxiliary Control Register 2*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Actlr2(pub u32); impl SysReg for Actlr2 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/adfsr.rs b/cortex-ar/src/register/adfsr.rs index a5b4c4e..c272efd 100644 --- a/cortex-ar/src/register/adfsr.rs +++ b/cortex-ar/src/register/adfsr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// ADFSR (*Auxiliary Data Fault Status Register*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Adfsr(pub u32); impl SysReg for Adfsr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/aidr.rs b/cortex-ar/src/register/aidr.rs index 99db1ec..ae6ac80 100644 --- a/cortex-ar/src/register/aidr.rs +++ b/cortex-ar/src/register/aidr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead}; /// AIDR (*Auxiliary ID Register*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Aidr(pub u32); impl SysReg for Aidr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/aifsr.rs b/cortex-ar/src/register/aifsr.rs index 88e0d64..6bbf801 100644 --- a/cortex-ar/src/register/aifsr.rs +++ b/cortex-ar/src/register/aifsr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// AIFSR (*Auxiliary Instruction Fault Status Register*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Aifsr(pub u32); impl SysReg for Aifsr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/amair0.rs b/cortex-ar/src/register/amair0.rs index 955a2e6..917023c 100644 --- a/cortex-ar/src/register/amair0.rs +++ b/cortex-ar/src/register/amair0.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// AMAIR0 (*Auxiliary Memory Attribute Indirection Register 0*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Amair0(pub u32); impl SysReg for Amair0 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/amair1.rs b/cortex-ar/src/register/amair1.rs index 144654a..55574e6 100644 --- a/cortex-ar/src/register/amair1.rs +++ b/cortex-ar/src/register/amair1.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// AMAIR1 (*Auxiliary Memory Attribute Indirection Register 1*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Amair1(pub u32); impl SysReg for Amair1 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/cntfrq.rs b/cortex-ar/src/register/armv8r/cntfrq.rs index 7d06d81..4df5969 100644 --- a/cortex-ar/src/register/armv8r/cntfrq.rs +++ b/cortex-ar/src/register/armv8r/cntfrq.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// CNTFRQ (*Counter-timer Frequency Register*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Cntfrq(pub u32); impl SysReg for Cntfrq { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/cnthctl.rs b/cortex-ar/src/register/armv8r/cnthctl.rs index 4c66233..3bbf894 100644 --- a/cortex-ar/src/register/armv8r/cnthctl.rs +++ b/cortex-ar/src/register/armv8r/cnthctl.rs @@ -5,7 +5,8 @@ use arbitrary_int::u4; use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// CNTHCTL (*Hyp Counter-timer Control Register*) -#[bitbybit::bitfield(u32)] +#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Cnthctl { #[bits(19..=19, rw)] cntpmask: bool, diff --git a/cortex-ar/src/register/armv8r/cnthp_ctl.rs b/cortex-ar/src/register/armv8r/cnthp_ctl.rs index 1df934d..9dd3aa9 100644 --- a/cortex-ar/src/register/armv8r/cnthp_ctl.rs +++ b/cortex-ar/src/register/armv8r/cnthp_ctl.rs @@ -3,19 +3,20 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// CNTHP_CTL (*Hyp Physical Counter-timer Control Register (EL2)*) -#[bitbybit::bitfield(u32)] +#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct CnthpCtl { /// The status of the timer interrupt. - #[bits(2..=2, r)] + #[bit(2, r)] istatus: bool, /// Timer interrupt mask bit. /// /// * true: masked /// * false: not masked - #[bits(1..=1, rw)] + #[bit(1, rw)] imask: bool, /// Enables the timer. - #[bits(0..=0, rw)] + #[bit(0, rw)] enable: bool, } diff --git a/cortex-ar/src/register/armv8r/cnthp_cval.rs b/cortex-ar/src/register/armv8r/cnthp_cval.rs index b8dc4dc..32a3820 100644 --- a/cortex-ar/src/register/armv8r/cnthp_cval.rs +++ b/cortex-ar/src/register/armv8r/cnthp_cval.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg64, SysRegRead64, SysRegWrite64}; /// CNTHP_CVAL (*Hyp Physical Counter-timer CompareValue Register*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct CnthpCval(pub u64); impl SysReg64 for CnthpCval { diff --git a/cortex-ar/src/register/armv8r/cnthp_tval.rs b/cortex-ar/src/register/armv8r/cnthp_tval.rs index cd4a9ab..09519a7 100644 --- a/cortex-ar/src/register/armv8r/cnthp_tval.rs +++ b/cortex-ar/src/register/armv8r/cnthp_tval.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// CNTHP_TVAL (*Hyp Physical Counter-timer TimerValue Register*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct CnthpTval(pub u32); impl SysReg for CnthpTval { diff --git a/cortex-ar/src/register/armv8r/cntkctl.rs b/cortex-ar/src/register/armv8r/cntkctl.rs index 54bfb70..92db33f 100644 --- a/cortex-ar/src/register/armv8r/cntkctl.rs +++ b/cortex-ar/src/register/armv8r/cntkctl.rs @@ -5,7 +5,8 @@ use arbitrary_int::u4; use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// CNTKCTL (*Counter-timer Kernel Control Register*) -#[bitbybit::bitfield(u32)] +#[bitbybit::bitfield(u32, defmt_bitfields(feature = "defmt"))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Cntkctl { /// Controls whether the physical timer registers are accessible from EL0 /// modes. diff --git a/cortex-ar/src/register/armv8r/cntp_ctl.rs b/cortex-ar/src/register/armv8r/cntp_ctl.rs index 6d49459..e902ec7 100644 --- a/cortex-ar/src/register/armv8r/cntp_ctl.rs +++ b/cortex-ar/src/register/armv8r/cntp_ctl.rs @@ -3,7 +3,8 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// CNTP_CTL (*Physical Counter-timer Control Register*) -#[bitbybit::bitfield(u32)] +#[bitbybit::bitfield(u32, defmt_bitfields(feature = "defmt"))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct CntpCtl { /// The status of the timer interrupt. #[bits(2..=2, r)] diff --git a/cortex-ar/src/register/armv8r/cntp_cval.rs b/cortex-ar/src/register/armv8r/cntp_cval.rs index 3aa5e1a..a71ba35 100644 --- a/cortex-ar/src/register/armv8r/cntp_cval.rs +++ b/cortex-ar/src/register/armv8r/cntp_cval.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg64, SysRegRead64, SysRegWrite64}; /// CNTP_CVAL (*Physical Counter-timer CompareValue Register*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct CntpCval(pub u64); impl SysReg64 for CntpCval { diff --git a/cortex-ar/src/register/armv8r/cntp_tval.rs b/cortex-ar/src/register/armv8r/cntp_tval.rs index ff3035e..56fa952 100644 --- a/cortex-ar/src/register/armv8r/cntp_tval.rs +++ b/cortex-ar/src/register/armv8r/cntp_tval.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// CNTP_TVAL (*Physical Counter-timer TimerValue Register*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct CntpTval(pub u32); impl SysReg for CntpTval { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/cntpct.rs b/cortex-ar/src/register/armv8r/cntpct.rs index 569cfdc..944c097 100644 --- a/cortex-ar/src/register/armv8r/cntpct.rs +++ b/cortex-ar/src/register/armv8r/cntpct.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg64, SysRegRead64}; /// CNTPCT (*Physical Counter-timer Count Register*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct CntPct(pub u64); impl SysReg64 for CntPct { diff --git a/cortex-ar/src/register/armv8r/cntv_ctl.rs b/cortex-ar/src/register/armv8r/cntv_ctl.rs index 39991e8..e7b4bc4 100644 --- a/cortex-ar/src/register/armv8r/cntv_ctl.rs +++ b/cortex-ar/src/register/armv8r/cntv_ctl.rs @@ -3,7 +3,8 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// CNTV_CTL (*Virtual Counter-timer Control Register*) -#[bitbybit::bitfield(u32)] +#[bitbybit::bitfield(u32, defmt_bitfields(feature = "defmt"))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct CntvCtl { /// The status of the timer interrupt. #[bits(2..=2, r)] diff --git a/cortex-ar/src/register/armv8r/cntv_cval.rs b/cortex-ar/src/register/armv8r/cntv_cval.rs index 9fb7ad5..ab60575 100644 --- a/cortex-ar/src/register/armv8r/cntv_cval.rs +++ b/cortex-ar/src/register/armv8r/cntv_cval.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg64, SysRegRead64, SysRegWrite64}; /// CNTV_CVAL (*Virtual Counter-timer CompareValue Register*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct CntvCval(pub u64); impl SysReg64 for CntvCval { diff --git a/cortex-ar/src/register/armv8r/cntv_tval.rs b/cortex-ar/src/register/armv8r/cntv_tval.rs index dc13ba8..8ca3a8d 100644 --- a/cortex-ar/src/register/armv8r/cntv_tval.rs +++ b/cortex-ar/src/register/armv8r/cntv_tval.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// CNTV_TVAL (*Virtual Counter-timer TimerValue Register*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct CntvTval(pub u32); impl SysReg for CntvTval { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/cntvct.rs b/cortex-ar/src/register/armv8r/cntvct.rs index f9b87cf..36ea87b 100644 --- a/cortex-ar/src/register/armv8r/cntvct.rs +++ b/cortex-ar/src/register/armv8r/cntvct.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg64, SysRegRead64}; /// CNTVCT (*Virtual Counter-timer Count Register*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct CntVct(pub u64); impl SysReg64 for CntVct { diff --git a/cortex-ar/src/register/armv8r/cntvoff.rs b/cortex-ar/src/register/armv8r/cntvoff.rs index 8f0d682..d019bb0 100644 --- a/cortex-ar/src/register/armv8r/cntvoff.rs +++ b/cortex-ar/src/register/armv8r/cntvoff.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg64, SysRegRead64, SysRegWrite64}; /// CNTVOFF (*Virtual Counter-timer Offset Register*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct CntVoff(pub u64); impl SysReg64 for CntVoff { diff --git a/cortex-ar/src/register/armv8r/hacr.rs b/cortex-ar/src/register/armv8r/hacr.rs index 5c22730..6fa36dd 100644 --- a/cortex-ar/src/register/armv8r/hacr.rs +++ b/cortex-ar/src/register/armv8r/hacr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HACR (*Hyp Auxiliary Configuration Register*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hacr(pub u32); impl SysReg for Hacr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/hactlr.rs b/cortex-ar/src/register/armv8r/hactlr.rs index 6caa2ae..8c88fb1 100644 --- a/cortex-ar/src/register/armv8r/hactlr.rs +++ b/cortex-ar/src/register/armv8r/hactlr.rs @@ -4,6 +4,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HACTRL (*Hyp Auxiliary Control Register*) #[bitbybit::bitfield(u32)] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hactlr { /// Controls access to IMP_TESTR1 at EL0 and EL1 #[bits(15..=15, rw)] diff --git a/cortex-ar/src/register/armv8r/hactlr2.rs b/cortex-ar/src/register/armv8r/hactlr2.rs index 9b35d56..f25b07e 100644 --- a/cortex-ar/src/register/armv8r/hactlr2.rs +++ b/cortex-ar/src/register/armv8r/hactlr2.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HACTLR2 (*Hyp Auxiliary Control Register 2*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hactlr2(pub u32); impl SysReg for Hactlr2 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/hadfsr.rs b/cortex-ar/src/register/armv8r/hadfsr.rs index 74d0580..16a8f98 100644 --- a/cortex-ar/src/register/armv8r/hadfsr.rs +++ b/cortex-ar/src/register/armv8r/hadfsr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HADFSR (*Hyp Auxiliary Data Fault Status Register*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hadfsr(pub u32); impl SysReg for Hadfsr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/haifsr.rs b/cortex-ar/src/register/armv8r/haifsr.rs index 0cea868..5799a16 100644 --- a/cortex-ar/src/register/armv8r/haifsr.rs +++ b/cortex-ar/src/register/armv8r/haifsr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HAIFSR (*Hyp Auxiliary Instruction Fault Status Register*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Haifsr(pub u32); impl SysReg for Haifsr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/hamair0.rs b/cortex-ar/src/register/armv8r/hamair0.rs index 1673f3c..0a91186 100644 --- a/cortex-ar/src/register/armv8r/hamair0.rs +++ b/cortex-ar/src/register/armv8r/hamair0.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HAMAIR0 (*Hyp Auxiliary Memory Attribute Indirection Register 0*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hamair0(pub u32); impl SysReg for Hamair0 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/hamair1.rs b/cortex-ar/src/register/armv8r/hamair1.rs index 316be2e..cdf56b3 100644 --- a/cortex-ar/src/register/armv8r/hamair1.rs +++ b/cortex-ar/src/register/armv8r/hamair1.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HAMAIR1 (*Hyp Auxiliary Memory Attribute Indirection Register 1*) +#[derive(Debug)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hamair1(pub u32); impl SysReg for Hamair1 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/hcptr.rs b/cortex-ar/src/register/armv8r/hcptr.rs index 9f5d034..fe2f4c1 100644 --- a/cortex-ar/src/register/armv8r/hcptr.rs +++ b/cortex-ar/src/register/armv8r/hcptr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HCPTR (*Hyp Architectural Feature Trap Register*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hcptr(pub u32); impl SysReg for Hcptr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/hcr.rs b/cortex-ar/src/register/armv8r/hcr.rs index 1cf7b2f..210d441 100644 --- a/cortex-ar/src/register/armv8r/hcr.rs +++ b/cortex-ar/src/register/armv8r/hcr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HCR (*Hyp Configuration Register*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hcr(pub u32); impl SysReg for Hcr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/hcr2.rs b/cortex-ar/src/register/armv8r/hcr2.rs index 0ddec55..e761483 100644 --- a/cortex-ar/src/register/armv8r/hcr2.rs +++ b/cortex-ar/src/register/armv8r/hcr2.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HCR2 (*Hyp Configuration Register 2*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hcr2(pub u32); impl SysReg for Hcr2 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/hdcr.rs b/cortex-ar/src/register/armv8r/hdcr.rs index 245d0fe..35ef3b2 100644 --- a/cortex-ar/src/register/armv8r/hdcr.rs +++ b/cortex-ar/src/register/armv8r/hdcr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HDCR (*Hyp Debug Control Register*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hdcr(pub u32); impl SysReg for Hdcr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/hdfar.rs b/cortex-ar/src/register/armv8r/hdfar.rs index 44068f6..fffbcdd 100644 --- a/cortex-ar/src/register/armv8r/hdfar.rs +++ b/cortex-ar/src/register/armv8r/hdfar.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HDFAR (*Hyp Data Fault Address Register*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hdfar(pub u32); impl SysReg for Hdfar { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/hifar.rs b/cortex-ar/src/register/armv8r/hifar.rs index 63e9f68..46dbaf9 100644 --- a/cortex-ar/src/register/armv8r/hifar.rs +++ b/cortex-ar/src/register/armv8r/hifar.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HIFAR (*Hyp Instruction Fault Address Register*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hifar(pub u32); impl SysReg for Hifar { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/hmair0.rs b/cortex-ar/src/register/armv8r/hmair0.rs index 3b5cd39..264fd5e 100644 --- a/cortex-ar/src/register/armv8r/hmair0.rs +++ b/cortex-ar/src/register/armv8r/hmair0.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HMAIR0 (*Hyp Memory Attribute Indirection Register 0*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hmair0(pub u32); impl SysReg for Hmair0 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/hmair1.rs b/cortex-ar/src/register/armv8r/hmair1.rs index 44268d2..473a53d 100644 --- a/cortex-ar/src/register/armv8r/hmair1.rs +++ b/cortex-ar/src/register/armv8r/hmair1.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HMAIR1 (*Hyp Memory Attribute Indirection Register 1*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hmair1(pub u32); impl SysReg for Hmair1 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/hmpuir.rs b/cortex-ar/src/register/armv8r/hmpuir.rs index 28abf96..fe4f345 100644 --- a/cortex-ar/src/register/armv8r/hmpuir.rs +++ b/cortex-ar/src/register/armv8r/hmpuir.rs @@ -3,7 +3,8 @@ use crate::register::{SysReg, SysRegRead}; /// HMPUIR (*Hyp MPU Type Register*) -#[bitbybit::bitfield(u32)] +#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hmpuir { /// The number of EL2 MPU regions implemented #[bits(0..=7, r)] diff --git a/cortex-ar/src/register/armv8r/hpfar.rs b/cortex-ar/src/register/armv8r/hpfar.rs index c6cc006..319ea7b 100644 --- a/cortex-ar/src/register/armv8r/hpfar.rs +++ b/cortex-ar/src/register/armv8r/hpfar.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HPFAR (*Hyp IPA Fault Address Register*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hpfar(pub u32); impl SysReg for Hpfar { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/hprbar.rs b/cortex-ar/src/register/armv8r/hprbar.rs index 4fd3b10..81face7 100644 --- a/cortex-ar/src/register/armv8r/hprbar.rs +++ b/cortex-ar/src/register/armv8r/hprbar.rs @@ -6,6 +6,8 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// Shareability for an MPU Region #[derive(Debug, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] #[bitbybit::bitenum(u2, exhaustive = true)] pub enum Shareability { /// Non-shareable @@ -20,6 +22,8 @@ pub enum Shareability { /// Access Permissions for an MPU Region #[derive(Debug, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] #[bitbybit::bitenum(u2, exhaustive = true)] pub enum AccessPerms { /// Read-Write at EL2, No access at EL1/0 @@ -33,7 +37,7 @@ pub enum AccessPerms { } /// HPRBAR (*Hyp Protection Region Base Address Register*) -#[bitbybit::bitfield(u32)] +#[bitbybit::bitfield(u32, debug, defmt_fields(feature = "defmt"))] pub struct Hprbar { /// Base Address #[bits(6..=31, rw)] diff --git a/cortex-ar/src/register/armv8r/hprbar0.rs b/cortex-ar/src/register/armv8r/hprbar0.rs index df2533f..6a6e99a 100644 --- a/cortex-ar/src/register/armv8r/hprbar0.rs +++ b/cortex-ar/src/register/armv8r/hprbar0.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HPRBAR0 (*Hyp Protection Region Base Address Register 0*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hprbar0(pub u32); impl SysReg for Hprbar0 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/hprbar1.rs b/cortex-ar/src/register/armv8r/hprbar1.rs index 4f3e59e..c0765f6 100644 --- a/cortex-ar/src/register/armv8r/hprbar1.rs +++ b/cortex-ar/src/register/armv8r/hprbar1.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HPRBAR1 (*Hyp Protection Region Base Address Register 1*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hprbar1(pub u32); impl SysReg for Hprbar1 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/hprbar10.rs b/cortex-ar/src/register/armv8r/hprbar10.rs index c50a192..f14de32 100644 --- a/cortex-ar/src/register/armv8r/hprbar10.rs +++ b/cortex-ar/src/register/armv8r/hprbar10.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HPRBAR10 (*Hyp Protection Region Base Address Register 10*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hprbar10(pub u32); impl SysReg for Hprbar10 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/hprbar11.rs b/cortex-ar/src/register/armv8r/hprbar11.rs index ff7ca6b..bc22da1 100644 --- a/cortex-ar/src/register/armv8r/hprbar11.rs +++ b/cortex-ar/src/register/armv8r/hprbar11.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HPRBAR11 (*Hyp Protection Region Base Address Register 11*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hprbar11(pub u32); impl SysReg for Hprbar11 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/hprbar12.rs b/cortex-ar/src/register/armv8r/hprbar12.rs index c613907..8f27213 100644 --- a/cortex-ar/src/register/armv8r/hprbar12.rs +++ b/cortex-ar/src/register/armv8r/hprbar12.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HPRBAR12 (*Hyp Protection Region Base Address Register 12*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hprbar12(pub u32); impl SysReg for Hprbar12 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/hprbar13.rs b/cortex-ar/src/register/armv8r/hprbar13.rs index ef50a29..db2cb81 100644 --- a/cortex-ar/src/register/armv8r/hprbar13.rs +++ b/cortex-ar/src/register/armv8r/hprbar13.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HPRBAR13 (*Hyp Protection Region Base Address Register 13*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hprbar13(pub u32); impl SysReg for Hprbar13 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/hprbar14.rs b/cortex-ar/src/register/armv8r/hprbar14.rs index 51c4c9d..2c256dd 100644 --- a/cortex-ar/src/register/armv8r/hprbar14.rs +++ b/cortex-ar/src/register/armv8r/hprbar14.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HPRBAR14 (*Hyp Protection Region Base Address Register 14*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hprbar14(pub u32); impl SysReg for Hprbar14 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/hprbar15.rs b/cortex-ar/src/register/armv8r/hprbar15.rs index 6a35e28..f3e05c4 100644 --- a/cortex-ar/src/register/armv8r/hprbar15.rs +++ b/cortex-ar/src/register/armv8r/hprbar15.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HPRBAR15 (*Hyp Protection Region Base Address Register 15*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hprbar15(pub u32); impl SysReg for Hprbar15 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/hprbar2.rs b/cortex-ar/src/register/armv8r/hprbar2.rs index 80c0efc..6141d36 100644 --- a/cortex-ar/src/register/armv8r/hprbar2.rs +++ b/cortex-ar/src/register/armv8r/hprbar2.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HPRBAR2 (*Hyp Protection Region Base Address Register 2*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hprbar2(pub u32); impl SysReg for Hprbar2 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/hprbar3.rs b/cortex-ar/src/register/armv8r/hprbar3.rs index dfa0daf..bcdb282 100644 --- a/cortex-ar/src/register/armv8r/hprbar3.rs +++ b/cortex-ar/src/register/armv8r/hprbar3.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HPRBAR3 (*Hyp Protection Region Base Address Register 3*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hprbar3(pub u32); impl SysReg for Hprbar3 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/hprbar4.rs b/cortex-ar/src/register/armv8r/hprbar4.rs index b678a57..3700ef7 100644 --- a/cortex-ar/src/register/armv8r/hprbar4.rs +++ b/cortex-ar/src/register/armv8r/hprbar4.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HPRBAR4 (*Hyp Protection Region Base Address Register 4*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hprbar4(pub u32); impl SysReg for Hprbar4 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/hprbar5.rs b/cortex-ar/src/register/armv8r/hprbar5.rs index 0553a46..d2cdbc6 100644 --- a/cortex-ar/src/register/armv8r/hprbar5.rs +++ b/cortex-ar/src/register/armv8r/hprbar5.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HPRBAR5 (*Hyp Protection Region Base Address Register 5*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hprbar5(pub u32); impl SysReg for Hprbar5 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/hprbar6.rs b/cortex-ar/src/register/armv8r/hprbar6.rs index c55b40d..5f17958 100644 --- a/cortex-ar/src/register/armv8r/hprbar6.rs +++ b/cortex-ar/src/register/armv8r/hprbar6.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HPRBAR6 (*Hyp Protection Region Base Address Register 6*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hprbar6(pub u32); impl SysReg for Hprbar6 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/hprbar7.rs b/cortex-ar/src/register/armv8r/hprbar7.rs index 01752d1..016406e 100644 --- a/cortex-ar/src/register/armv8r/hprbar7.rs +++ b/cortex-ar/src/register/armv8r/hprbar7.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HPRBAR7 (*Hyp Protection Region Base Address Register 7*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hprbar7(pub u32); impl SysReg for Hprbar7 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/hprbar8.rs b/cortex-ar/src/register/armv8r/hprbar8.rs index 5b9b8ac..1baef5b 100644 --- a/cortex-ar/src/register/armv8r/hprbar8.rs +++ b/cortex-ar/src/register/armv8r/hprbar8.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HPRBAR8 (*Hyp Protection Region Base Address Register 8*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hprbar8(pub u32); impl SysReg for Hprbar8 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/hprbar9.rs b/cortex-ar/src/register/armv8r/hprbar9.rs index bdce460..9d2472b 100644 --- a/cortex-ar/src/register/armv8r/hprbar9.rs +++ b/cortex-ar/src/register/armv8r/hprbar9.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HPRBAR9 (*Hyp Protection Region Base Address Register 9*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hprbar9(pub u32); impl SysReg for Hprbar9 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/hprenr.rs b/cortex-ar/src/register/armv8r/hprenr.rs index 183f830..551230c 100644 --- a/cortex-ar/src/register/armv8r/hprenr.rs +++ b/cortex-ar/src/register/armv8r/hprenr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HPRENR (*Hyp MPU Region Enable Register*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hprenr(pub u32); impl SysReg for Hprenr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/hprlar.rs b/cortex-ar/src/register/armv8r/hprlar.rs index adbbad7..ffeb0fb 100644 --- a/cortex-ar/src/register/armv8r/hprlar.rs +++ b/cortex-ar/src/register/armv8r/hprlar.rs @@ -5,7 +5,7 @@ use arbitrary_int::{u26, u3}; use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HPRLAR (*Hyp Protection Region Limit Address Register*) -#[bitbybit::bitfield(u32)] +#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))] pub struct Hprlar { /// Length of region #[bits(6..=31, rw)] diff --git a/cortex-ar/src/register/armv8r/hprlar0.rs b/cortex-ar/src/register/armv8r/hprlar0.rs index 6d03c1a..0fb241b 100644 --- a/cortex-ar/src/register/armv8r/hprlar0.rs +++ b/cortex-ar/src/register/armv8r/hprlar0.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HPRLAR0 (*Hyp Protection Region Limit Address Register 0*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hprlar0(pub u32); impl SysReg for Hprlar0 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/hprlar1.rs b/cortex-ar/src/register/armv8r/hprlar1.rs index 9a16602..e461a66 100644 --- a/cortex-ar/src/register/armv8r/hprlar1.rs +++ b/cortex-ar/src/register/armv8r/hprlar1.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HPRLAR1 (*Hyp Protection Region Limit Address Register 1*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hprlar1(pub u32); impl SysReg for Hprlar1 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/hprlar10.rs b/cortex-ar/src/register/armv8r/hprlar10.rs index 6584f79..9fd7f9a 100644 --- a/cortex-ar/src/register/armv8r/hprlar10.rs +++ b/cortex-ar/src/register/armv8r/hprlar10.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HPRLAR10 (*Hyp Protection Region Limit Address Register 10*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hprlar10(pub u32); impl SysReg for Hprlar10 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/hprlar11.rs b/cortex-ar/src/register/armv8r/hprlar11.rs index 4b51ebf..f1ed22b 100644 --- a/cortex-ar/src/register/armv8r/hprlar11.rs +++ b/cortex-ar/src/register/armv8r/hprlar11.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HPRLAR11 (*Hyp Protection Region Limit Address Register 11*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hprlar11(pub u32); impl SysReg for Hprlar11 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/hprlar12.rs b/cortex-ar/src/register/armv8r/hprlar12.rs index 5481abd..94bd70f 100644 --- a/cortex-ar/src/register/armv8r/hprlar12.rs +++ b/cortex-ar/src/register/armv8r/hprlar12.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HPRLAR12 (*Hyp Protection Region Limit Address Register 12*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hprlar12(pub u32); impl SysReg for Hprlar12 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/hprlar13.rs b/cortex-ar/src/register/armv8r/hprlar13.rs index a85e6d4..b9a6ccf 100644 --- a/cortex-ar/src/register/armv8r/hprlar13.rs +++ b/cortex-ar/src/register/armv8r/hprlar13.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HPRLAR13 (*Hyp Protection Region Limit Address Register 13*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hprlar13(pub u32); impl SysReg for Hprlar13 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/hprlar14.rs b/cortex-ar/src/register/armv8r/hprlar14.rs index 750dac3..fef31a9 100644 --- a/cortex-ar/src/register/armv8r/hprlar14.rs +++ b/cortex-ar/src/register/armv8r/hprlar14.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HPRLAR14 (*Hyp Protection Region Limit Address Register 14*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hprlar14(pub u32); impl SysReg for Hprlar14 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/hprlar15.rs b/cortex-ar/src/register/armv8r/hprlar15.rs index 0ab9f24..51ab73e 100644 --- a/cortex-ar/src/register/armv8r/hprlar15.rs +++ b/cortex-ar/src/register/armv8r/hprlar15.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HPRLAR15 (*Hyp Protection Region Limit Address Register 15*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hprlar15(pub u32); impl SysReg for Hprlar15 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/hprlar2.rs b/cortex-ar/src/register/armv8r/hprlar2.rs index b5318c8..922851a 100644 --- a/cortex-ar/src/register/armv8r/hprlar2.rs +++ b/cortex-ar/src/register/armv8r/hprlar2.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HPRLAR2 (*Hyp Protection Region Limit Address Register 2*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hprlar2(pub u32); impl SysReg for Hprlar2 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/hprlar3.rs b/cortex-ar/src/register/armv8r/hprlar3.rs index 89b5eda..3364250 100644 --- a/cortex-ar/src/register/armv8r/hprlar3.rs +++ b/cortex-ar/src/register/armv8r/hprlar3.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HPRLAR3 (*Hyp Protection Region Limit Address Register 3*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hprlar3(pub u32); impl SysReg for Hprlar3 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/hprlar4.rs b/cortex-ar/src/register/armv8r/hprlar4.rs index 88dc134..04e7cd4 100644 --- a/cortex-ar/src/register/armv8r/hprlar4.rs +++ b/cortex-ar/src/register/armv8r/hprlar4.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HPRLAR4 (*Hyp Protection Region Limit Address Register 4*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hprlar4(pub u32); impl SysReg for Hprlar4 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/hprlar5.rs b/cortex-ar/src/register/armv8r/hprlar5.rs index 08b6bb8..696f839 100644 --- a/cortex-ar/src/register/armv8r/hprlar5.rs +++ b/cortex-ar/src/register/armv8r/hprlar5.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HPRLAR5 (*Hyp Protection Region Limit Address Register 5*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hprlar5(pub u32); impl SysReg for Hprlar5 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/hprlar6.rs b/cortex-ar/src/register/armv8r/hprlar6.rs index b1fbbcd..f6e99af 100644 --- a/cortex-ar/src/register/armv8r/hprlar6.rs +++ b/cortex-ar/src/register/armv8r/hprlar6.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HPRLAR6 (*Hyp Protection Region Limit Address Register 6*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hprlar6(pub u32); impl SysReg for Hprlar6 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/hprlar7.rs b/cortex-ar/src/register/armv8r/hprlar7.rs index 8e6cc6f..e24dc28 100644 --- a/cortex-ar/src/register/armv8r/hprlar7.rs +++ b/cortex-ar/src/register/armv8r/hprlar7.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HPRLAR7 (*Hyp Protection Region Limit Address Register 7*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hprlar7(pub u32); impl SysReg for Hprlar7 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/hprlar8.rs b/cortex-ar/src/register/armv8r/hprlar8.rs index 5c4eef6..25b8b2b 100644 --- a/cortex-ar/src/register/armv8r/hprlar8.rs +++ b/cortex-ar/src/register/armv8r/hprlar8.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HPRLAR8 (*Hyp Protection Region Limit Address Register 8*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hprlar8(pub u32); impl SysReg for Hprlar8 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/hprlar9.rs b/cortex-ar/src/register/armv8r/hprlar9.rs index 1056991..c7e5c3a 100644 --- a/cortex-ar/src/register/armv8r/hprlar9.rs +++ b/cortex-ar/src/register/armv8r/hprlar9.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HPRLAR9 (*Hyp Protection Region Limit Address Register 9*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hprlar9(pub u32); impl SysReg for Hprlar9 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/hprselr.rs b/cortex-ar/src/register/armv8r/hprselr.rs index 89618f4..ebdb443 100644 --- a/cortex-ar/src/register/armv8r/hprselr.rs +++ b/cortex-ar/src/register/armv8r/hprselr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HPRSELR (*Hyp Protection Region Selection Register*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hprselr(pub u32); impl SysReg for Hprselr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/hsctlr.rs b/cortex-ar/src/register/armv8r/hsctlr.rs index 9abf5c4..f4e7210 100644 --- a/cortex-ar/src/register/armv8r/hsctlr.rs +++ b/cortex-ar/src/register/armv8r/hsctlr.rs @@ -3,7 +3,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HSCTLR (*Hyp System Control Register*) -#[bitbybit::bitfield(u32)] +#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))] pub struct Hsctlr { /// T32 Exception Enable. Controls whether exceptions to EL2 are taken to A32 or T32 state #[bits(30..=30, rw)] diff --git a/cortex-ar/src/register/armv8r/hsr.rs b/cortex-ar/src/register/armv8r/hsr.rs index 1156a57..1e5bbcb 100644 --- a/cortex-ar/src/register/armv8r/hsr.rs +++ b/cortex-ar/src/register/armv8r/hsr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HSR (*Hyp Syndrome Register*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hsr(pub u32); impl SysReg for Hsr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/hstr.rs b/cortex-ar/src/register/armv8r/hstr.rs index d0ada93..1d46ee5 100644 --- a/cortex-ar/src/register/armv8r/hstr.rs +++ b/cortex-ar/src/register/armv8r/hstr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HSTR (*Hyp System Trap Register*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Hstr(pub u32); impl SysReg for Hstr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/htpidr.rs b/cortex-ar/src/register/armv8r/htpidr.rs index f41838f..6491683 100644 --- a/cortex-ar/src/register/armv8r/htpidr.rs +++ b/cortex-ar/src/register/armv8r/htpidr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// HTPIDR (*Hyp Software Thread ID Register*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Htpidr(pub u32); impl SysReg for Htpidr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/prbar.rs b/cortex-ar/src/register/armv8r/prbar.rs index d0b1cdb..b9209d6 100644 --- a/cortex-ar/src/register/armv8r/prbar.rs +++ b/cortex-ar/src/register/armv8r/prbar.rs @@ -6,6 +6,8 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// Shareability for an MPU Region #[derive(Debug, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] #[bitbybit::bitenum(u2, exhaustive = true)] pub enum Shareability { /// Non-shareable @@ -20,6 +22,8 @@ pub enum Shareability { /// Access Permissions for an MPU Region #[derive(Debug, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] #[bitbybit::bitenum(u2, exhaustive = true)] pub enum AccessPerms { /// Read-Write at EL1, No access at EL0 @@ -33,7 +37,7 @@ pub enum AccessPerms { } /// PRBAR (*Protection Region Base Address Register*) -#[bitbybit::bitfield(u32)] +#[bitbybit::bitfield(u32, debug, defmt_fields(feature = "defmt"))] pub struct Prbar { /// Address #[bits(6..=31, rw)] diff --git a/cortex-ar/src/register/armv8r/prbar0.rs b/cortex-ar/src/register/armv8r/prbar0.rs index b386254..68f2e8e 100644 --- a/cortex-ar/src/register/armv8r/prbar0.rs +++ b/cortex-ar/src/register/armv8r/prbar0.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PRBAR0 (*Protection Region Base Address Register 0*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Prbar0(pub u32); impl SysReg for Prbar0 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/prbar1.rs b/cortex-ar/src/register/armv8r/prbar1.rs index cd6fb10..3449068 100644 --- a/cortex-ar/src/register/armv8r/prbar1.rs +++ b/cortex-ar/src/register/armv8r/prbar1.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PRBAR1 (*Protection Region Base Address Register 1*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Prbar1(pub u32); impl SysReg for Prbar1 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/prbar10.rs b/cortex-ar/src/register/armv8r/prbar10.rs index 4c50d01..92a8316 100644 --- a/cortex-ar/src/register/armv8r/prbar10.rs +++ b/cortex-ar/src/register/armv8r/prbar10.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PRBAR10 (*Protection Region Base Address Register 10*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Prbar10(pub u32); impl SysReg for Prbar10 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/prbar11.rs b/cortex-ar/src/register/armv8r/prbar11.rs index 2b13100..ed203fa 100644 --- a/cortex-ar/src/register/armv8r/prbar11.rs +++ b/cortex-ar/src/register/armv8r/prbar11.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PRBAR11 (*Protection Region Base Address Register 11*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Prbar11(pub u32); impl SysReg for Prbar11 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/prbar12.rs b/cortex-ar/src/register/armv8r/prbar12.rs index 72bd829..d1c7f64 100644 --- a/cortex-ar/src/register/armv8r/prbar12.rs +++ b/cortex-ar/src/register/armv8r/prbar12.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PRBAR12 (*Protection Region Base Address Register 12*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Prbar12(pub u32); impl SysReg for Prbar12 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/prbar13.rs b/cortex-ar/src/register/armv8r/prbar13.rs index edcc9db..e6b8ee5 100644 --- a/cortex-ar/src/register/armv8r/prbar13.rs +++ b/cortex-ar/src/register/armv8r/prbar13.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PRBAR13 (*Protection Region Base Address Register 13*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Prbar13(pub u32); impl SysReg for Prbar13 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/prbar14.rs b/cortex-ar/src/register/armv8r/prbar14.rs index fe6c097..bb94534 100644 --- a/cortex-ar/src/register/armv8r/prbar14.rs +++ b/cortex-ar/src/register/armv8r/prbar14.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PRBAR14 (*Protection Region Base Address Register 14*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Prbar14(pub u32); impl SysReg for Prbar14 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/prbar15.rs b/cortex-ar/src/register/armv8r/prbar15.rs index 7d82d4d..61c8d09 100644 --- a/cortex-ar/src/register/armv8r/prbar15.rs +++ b/cortex-ar/src/register/armv8r/prbar15.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PRBAR15 (*Protection Region Base Address Register 15*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Prbar15(pub u32); impl SysReg for Prbar15 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/prbar2.rs b/cortex-ar/src/register/armv8r/prbar2.rs index d565cc2..2e804fc 100644 --- a/cortex-ar/src/register/armv8r/prbar2.rs +++ b/cortex-ar/src/register/armv8r/prbar2.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PRBAR2 (*Protection Region Base Address Register 2*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Prbar2(pub u32); impl SysReg for Prbar2 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/prbar3.rs b/cortex-ar/src/register/armv8r/prbar3.rs index a3b3c5c..79dc96f 100644 --- a/cortex-ar/src/register/armv8r/prbar3.rs +++ b/cortex-ar/src/register/armv8r/prbar3.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PRBAR3 (*Protection Region Base Address Register 3*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Prbar3(pub u32); impl SysReg for Prbar3 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/prbar4.rs b/cortex-ar/src/register/armv8r/prbar4.rs index c1ee3d6..58e3574 100644 --- a/cortex-ar/src/register/armv8r/prbar4.rs +++ b/cortex-ar/src/register/armv8r/prbar4.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PRBAR4 (*Protection Region Base Address Register 4*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Prbar4(pub u32); impl SysReg for Prbar4 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/prbar5.rs b/cortex-ar/src/register/armv8r/prbar5.rs index 56223a4..6abb6f7 100644 --- a/cortex-ar/src/register/armv8r/prbar5.rs +++ b/cortex-ar/src/register/armv8r/prbar5.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PRBAR5 (*Protection Region Base Address Register 5*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Prbar5(pub u32); impl SysReg for Prbar5 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/prbar6.rs b/cortex-ar/src/register/armv8r/prbar6.rs index 11c2838..3e03d0b 100644 --- a/cortex-ar/src/register/armv8r/prbar6.rs +++ b/cortex-ar/src/register/armv8r/prbar6.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PRBAR6 (*Protection Region Base Address Register 6*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Prbar6(pub u32); impl SysReg for Prbar6 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/prbar7.rs b/cortex-ar/src/register/armv8r/prbar7.rs index 81dbd6b..e1791d7 100644 --- a/cortex-ar/src/register/armv8r/prbar7.rs +++ b/cortex-ar/src/register/armv8r/prbar7.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PRBAR7 (*Protection Region Base Address Register 7*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Prbar7(pub u32); impl SysReg for Prbar7 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/prbar8.rs b/cortex-ar/src/register/armv8r/prbar8.rs index 02659fc..bfcde93 100644 --- a/cortex-ar/src/register/armv8r/prbar8.rs +++ b/cortex-ar/src/register/armv8r/prbar8.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PRBAR8 (*Protection Region Base Address Register 8*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Prbar8(pub u32); impl SysReg for Prbar8 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/prbar9.rs b/cortex-ar/src/register/armv8r/prbar9.rs index 5eba086..19da2fa 100644 --- a/cortex-ar/src/register/armv8r/prbar9.rs +++ b/cortex-ar/src/register/armv8r/prbar9.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PRBAR9 (*Protection Region Base Address Register 9*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Prbar9(pub u32); impl SysReg for Prbar9 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/prlar.rs b/cortex-ar/src/register/armv8r/prlar.rs index 3602292..a4804ba 100644 --- a/cortex-ar/src/register/armv8r/prlar.rs +++ b/cortex-ar/src/register/armv8r/prlar.rs @@ -5,7 +5,7 @@ use arbitrary_int::{u26, u3}; use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PRLAR (*Protection Region Limit Address Register*) -#[bitbybit::bitfield(u32)] +#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))] pub struct Prlar { /// Length of region #[bits(6..=31, rw)] diff --git a/cortex-ar/src/register/armv8r/prlar0.rs b/cortex-ar/src/register/armv8r/prlar0.rs index b08ff61..9d1cbf0 100644 --- a/cortex-ar/src/register/armv8r/prlar0.rs +++ b/cortex-ar/src/register/armv8r/prlar0.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PRLAR0 (*Protection Region Limit Address Register 0*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Prlar0(pub u32); impl SysReg for Prlar0 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/prlar1.rs b/cortex-ar/src/register/armv8r/prlar1.rs index d24a1c8..e0680a9 100644 --- a/cortex-ar/src/register/armv8r/prlar1.rs +++ b/cortex-ar/src/register/armv8r/prlar1.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PRLAR1 (*Protection Region Limit Address Register 1*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Prlar1(pub u32); impl SysReg for Prlar1 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/prlar10.rs b/cortex-ar/src/register/armv8r/prlar10.rs index 7c48888..d2ca155 100644 --- a/cortex-ar/src/register/armv8r/prlar10.rs +++ b/cortex-ar/src/register/armv8r/prlar10.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PRLAR10 (*Protection Region Limit Address Register 10*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Prlar10(pub u32); impl SysReg for Prlar10 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/prlar11.rs b/cortex-ar/src/register/armv8r/prlar11.rs index ba3e314..d2dd657 100644 --- a/cortex-ar/src/register/armv8r/prlar11.rs +++ b/cortex-ar/src/register/armv8r/prlar11.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PRLAR11 (*Protection Region Limit Address Register 11*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Prlar11(pub u32); impl SysReg for Prlar11 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/prlar12.rs b/cortex-ar/src/register/armv8r/prlar12.rs index debf01c..4c777a2 100644 --- a/cortex-ar/src/register/armv8r/prlar12.rs +++ b/cortex-ar/src/register/armv8r/prlar12.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PRLAR12 (*Protection Region Limit Address Register 12*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Prlar12(pub u32); impl SysReg for Prlar12 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/prlar13.rs b/cortex-ar/src/register/armv8r/prlar13.rs index c6966eb..c8e414f 100644 --- a/cortex-ar/src/register/armv8r/prlar13.rs +++ b/cortex-ar/src/register/armv8r/prlar13.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PRLAR13 (*Protection Region Limit Address Register 13*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Prlar13(pub u32); impl SysReg for Prlar13 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/prlar14.rs b/cortex-ar/src/register/armv8r/prlar14.rs index c8b013a..7dde72e 100644 --- a/cortex-ar/src/register/armv8r/prlar14.rs +++ b/cortex-ar/src/register/armv8r/prlar14.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PRLAR14 (*Protection Region Limit Address Register 14*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Prlar14(pub u32); impl SysReg for Prlar14 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/prlar15.rs b/cortex-ar/src/register/armv8r/prlar15.rs index 923299a..9cc05b5 100644 --- a/cortex-ar/src/register/armv8r/prlar15.rs +++ b/cortex-ar/src/register/armv8r/prlar15.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PRLAR15 (*Protection Region Limit Address Register 15*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Prlar15(pub u32); impl SysReg for Prlar15 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/prlar2.rs b/cortex-ar/src/register/armv8r/prlar2.rs index 9ff67af..b918918 100644 --- a/cortex-ar/src/register/armv8r/prlar2.rs +++ b/cortex-ar/src/register/armv8r/prlar2.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PRLAR2 (*Protection Region Limit Address Register 2*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Prlar2(pub u32); impl SysReg for Prlar2 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/prlar3.rs b/cortex-ar/src/register/armv8r/prlar3.rs index 0d6d094..f7996d5 100644 --- a/cortex-ar/src/register/armv8r/prlar3.rs +++ b/cortex-ar/src/register/armv8r/prlar3.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PRLAR3 (*Protection Region Limit Address Register 3*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Prlar3(pub u32); impl SysReg for Prlar3 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/prlar4.rs b/cortex-ar/src/register/armv8r/prlar4.rs index 0284125..db4442d 100644 --- a/cortex-ar/src/register/armv8r/prlar4.rs +++ b/cortex-ar/src/register/armv8r/prlar4.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PRLAR4 (*Protection Region Limit Address Register 4*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Prlar4(pub u32); impl SysReg for Prlar4 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/prlar5.rs b/cortex-ar/src/register/armv8r/prlar5.rs index 4a94f81..b006807 100644 --- a/cortex-ar/src/register/armv8r/prlar5.rs +++ b/cortex-ar/src/register/armv8r/prlar5.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PRLAR5 (*Protection Region Limit Address Register 5*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Prlar5(pub u32); impl SysReg for Prlar5 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/prlar6.rs b/cortex-ar/src/register/armv8r/prlar6.rs index be39390..7fe777e 100644 --- a/cortex-ar/src/register/armv8r/prlar6.rs +++ b/cortex-ar/src/register/armv8r/prlar6.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PRLAR6 (*Protection Region Limit Address Register 6*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Prlar6(pub u32); impl SysReg for Prlar6 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/prlar7.rs b/cortex-ar/src/register/armv8r/prlar7.rs index 65d5c52..ab4e617 100644 --- a/cortex-ar/src/register/armv8r/prlar7.rs +++ b/cortex-ar/src/register/armv8r/prlar7.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PRLAR7 (*Protection Region Limit Address Register 7*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Prlar7(pub u32); impl SysReg for Prlar7 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/prlar8.rs b/cortex-ar/src/register/armv8r/prlar8.rs index 52f10e3..9b14e5f 100644 --- a/cortex-ar/src/register/armv8r/prlar8.rs +++ b/cortex-ar/src/register/armv8r/prlar8.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PRLAR8 (*Protection Region Limit Address Register 8*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Prlar8(pub u32); impl SysReg for Prlar8 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/prlar9.rs b/cortex-ar/src/register/armv8r/prlar9.rs index 1655f05..8149f2a 100644 --- a/cortex-ar/src/register/armv8r/prlar9.rs +++ b/cortex-ar/src/register/armv8r/prlar9.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PRLAR9 (*Protection Region Limit Address Register 9*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Prlar9(pub u32); impl SysReg for Prlar9 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/prselr.rs b/cortex-ar/src/register/armv8r/prselr.rs index a6e8974..267b275 100644 --- a/cortex-ar/src/register/armv8r/prselr.rs +++ b/cortex-ar/src/register/armv8r/prselr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PRSELR (*Protection Region Selection Register*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Prselr(pub u32); impl SysReg for Prselr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/armv8r/vbar.rs b/cortex-ar/src/register/armv8r/vbar.rs index dd3362c..97cf177 100644 --- a/cortex-ar/src/register/armv8r/vbar.rs +++ b/cortex-ar/src/register/armv8r/vbar.rs @@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// There is no `modify` method because this register holds a single 32-bit address. #[derive(Clone, Copy, PartialEq, Eq)] #[repr(transparent)] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Vbar(pub *mut u32); impl SysReg for Vbar { diff --git a/cortex-ar/src/register/ccsidr.rs b/cortex-ar/src/register/ccsidr.rs index 289a977..f995576 100644 --- a/cortex-ar/src/register/ccsidr.rs +++ b/cortex-ar/src/register/ccsidr.rs @@ -4,8 +4,8 @@ use crate::register::{SysReg, SysRegRead}; use arbitrary_int::{u10, u15, u3}; /// CCSIDR (*Current Cache Size ID Register*) -#[bitbybit::bitfield(u32)] -#[derive(Debug)] +#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Ccsidr { #[bit(31, rw)] write_through: bool, diff --git a/cortex-ar/src/register/clidr.rs b/cortex-ar/src/register/clidr.rs index eacb029..b77ba2a 100644 --- a/cortex-ar/src/register/clidr.rs +++ b/cortex-ar/src/register/clidr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead}; /// CLIDR (*Cache Level ID Register*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Clidr(pub u32); impl SysReg for Clidr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/contextidr.rs b/cortex-ar/src/register/contextidr.rs index 4a7e1e4..2a58179 100644 --- a/cortex-ar/src/register/contextidr.rs +++ b/cortex-ar/src/register/contextidr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// CONTEXTIDR (*Context ID Register*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Contextidr(pub u32); impl SysReg for Contextidr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/cpacr.rs b/cortex-ar/src/register/cpacr.rs index 3287310..aeca387 100644 --- a/cortex-ar/src/register/cpacr.rs +++ b/cortex-ar/src/register/cpacr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// CPACR (*Architectural Feature Access Control Register*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Cpacr(pub u32); impl SysReg for Cpacr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/cpsr.rs b/cortex-ar/src/register/cpsr.rs index 60bb41a..41b5b20 100644 --- a/cortex-ar/src/register/cpsr.rs +++ b/cortex-ar/src/register/cpsr.rs @@ -1,7 +1,9 @@ //! Code for managing CPSR (*Current Program Status Register*) /// The current Processor Mode -#[derive(Debug)] +#[derive(Debug, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] #[bitbybit::bitenum(u5, exhaustive = false)] pub enum ProcessorMode { /// User Mode @@ -26,6 +28,7 @@ pub enum ProcessorMode { /// CPSR (*Current Program Status Register*) #[bitbybit::bitfield(u32)] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Cpsr { /// Negative Result from ALU #[bits(31..=31, r)] diff --git a/cortex-ar/src/register/csselr.rs b/cortex-ar/src/register/csselr.rs index 794227d..7f5ad86 100644 --- a/cortex-ar/src/register/csselr.rs +++ b/cortex-ar/src/register/csselr.rs @@ -5,14 +5,17 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; #[bitbybit::bitenum(u1, exhaustive = true)] #[derive(Debug, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub enum CacheType { DataOrUnified = 0, Instruction = 1, } /// CSSELR (*Cache Size Selection Register*) -#[bitbybit::bitfield(u32)] -#[derive(Debug, PartialEq, Eq)] +#[bitbybit::bitfield(u32, debug, defmt_fields(feature = "defmt"))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] +#[derive(PartialEq, Eq)] pub struct Csselr { /// 0 for L1 cache, 1 for L2, etc. #[bits(1..=3, rw)] diff --git a/cortex-ar/src/register/ctr.rs b/cortex-ar/src/register/ctr.rs index dd25629..3a24459 100644 --- a/cortex-ar/src/register/ctr.rs +++ b/cortex-ar/src/register/ctr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead}; /// CTR (*Cache Type Register*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Ctr(pub u32); impl SysReg for Ctr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/dccimvac.rs b/cortex-ar/src/register/dccimvac.rs index 404f055..3fa015c 100644 --- a/cortex-ar/src/register/dccimvac.rs +++ b/cortex-ar/src/register/dccimvac.rs @@ -1,6 +1,9 @@ //! DCCIMVAC (*Clean And Invalidate Data Cache Or Unified Cache Line by MVA to Point of Coherence.*) use crate::register::{SysReg, SysRegWrite}; +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Dccimvac(pub u32); impl Dccimvac { diff --git a/cortex-ar/src/register/dccisw.rs b/cortex-ar/src/register/dccisw.rs index 3787f46..34bbb22 100644 --- a/cortex-ar/src/register/dccisw.rs +++ b/cortex-ar/src/register/dccisw.rs @@ -4,6 +4,9 @@ use arbitrary_int::u3; use crate::register::{SysReg, SysRegWrite}; +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Dccisw(pub u32); impl Dccisw { diff --git a/cortex-ar/src/register/dccmvac.rs b/cortex-ar/src/register/dccmvac.rs index 8090830..402c612 100644 --- a/cortex-ar/src/register/dccmvac.rs +++ b/cortex-ar/src/register/dccmvac.rs @@ -1,6 +1,9 @@ //! DCCMVAC (*Clean Data Cache Or Unified Cache Line by MVA to Point of Coherence.*) use crate::register::{SysReg, SysRegWrite}; +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Dccmvac(pub u32); impl Dccmvac { diff --git a/cortex-ar/src/register/dccmvau.rs b/cortex-ar/src/register/dccmvau.rs index 0132afa..8356f86 100644 --- a/cortex-ar/src/register/dccmvau.rs +++ b/cortex-ar/src/register/dccmvau.rs @@ -1,6 +1,9 @@ //! DCCMVAU (*Clean Data Cache Or Unified Cache Line by MVA to Point of Unification.*) use crate::register::{SysReg, SysRegWrite}; +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Dccmvau(pub u32); impl Dccmvau { diff --git a/cortex-ar/src/register/dccsw.rs b/cortex-ar/src/register/dccsw.rs index 1215c2e..ea17426 100644 --- a/cortex-ar/src/register/dccsw.rs +++ b/cortex-ar/src/register/dccsw.rs @@ -4,6 +4,9 @@ use arbitrary_int::u3; use crate::register::{SysReg, SysRegWrite}; +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Dccsw(pub u32); impl Dccsw { diff --git a/cortex-ar/src/register/dcimvac.rs b/cortex-ar/src/register/dcimvac.rs index 22f50f3..b2ed6a2 100644 --- a/cortex-ar/src/register/dcimvac.rs +++ b/cortex-ar/src/register/dcimvac.rs @@ -1,6 +1,9 @@ //! DCIMVAC (*Invalidate Data Cache Or Unified Cache Line by MVA to Point of Coherence.*) use crate::register::{SysReg, SysRegWrite}; +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Dcimvac(pub u32); impl Dcimvac { diff --git a/cortex-ar/src/register/dcisw.rs b/cortex-ar/src/register/dcisw.rs index 2c2fe38..fa1a260 100644 --- a/cortex-ar/src/register/dcisw.rs +++ b/cortex-ar/src/register/dcisw.rs @@ -4,6 +4,9 @@ use arbitrary_int::u3; use crate::register::{SysReg, SysRegWrite}; +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Dcisw(pub u32); impl Dcisw { diff --git a/cortex-ar/src/register/dfar.rs b/cortex-ar/src/register/dfar.rs index e07a1e4..0849c96 100644 --- a/cortex-ar/src/register/dfar.rs +++ b/cortex-ar/src/register/dfar.rs @@ -3,7 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// DFAR (*Data Fault Address Register*) -#[derive(Debug)] +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Dfar(pub u32); impl SysReg for Dfar { const CP: u32 = 15; diff --git a/cortex-ar/src/register/dfsr.rs b/cortex-ar/src/register/dfsr.rs index dbc6a3b..d9865ce 100644 --- a/cortex-ar/src/register/dfsr.rs +++ b/cortex-ar/src/register/dfsr.rs @@ -6,7 +6,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; use super::ifsr::FsrStatus; -#[derive(Debug)] +#[derive(Debug, Copy, Clone, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] #[repr(u8)] pub enum DfsrStatus { AlignmentFault = 0b00001, @@ -32,7 +34,7 @@ impl TryFrom for DfsrStatus { } /// DFSR (*Data Fault Status Register*) -#[bitbybit::bitfield(u32)] +#[bitbybit::bitfield(u32, defmt_bitfields(feature = "defmt"))] pub struct Dfsr { /// External abort qualifier #[bit(12, rw)] diff --git a/cortex-ar/src/register/dlr.rs b/cortex-ar/src/register/dlr.rs index d194b29..7155230 100644 --- a/cortex-ar/src/register/dlr.rs +++ b/cortex-ar/src/register/dlr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// DLR (*Debug Link Register*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Dlr(pub u32); impl SysReg for Dlr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/dracr.rs b/cortex-ar/src/register/dracr.rs index ff151ac..6e5aa98 100644 --- a/cortex-ar/src/register/dracr.rs +++ b/cortex-ar/src/register/dracr.rs @@ -5,7 +5,8 @@ use arbitrary_int::u3; use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// DRACR (*Data Region Access Control Register*) -#[bitbybit::bitfield(u32)] +#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Dracr { /// Execute Never #[bits(12..=12, rw)] diff --git a/cortex-ar/src/register/drbar.rs b/cortex-ar/src/register/drbar.rs index 38c9cfe..b513e13 100644 --- a/cortex-ar/src/register/drbar.rs +++ b/cortex-ar/src/register/drbar.rs @@ -3,6 +3,8 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// DRBAR (*Data Region Base Address Register*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] pub struct Drbar(pub *mut u8); impl SysReg for Drbar { diff --git a/cortex-ar/src/register/drsr.rs b/cortex-ar/src/register/drsr.rs index 6e1f3d4..b1fe4dc 100644 --- a/cortex-ar/src/register/drsr.rs +++ b/cortex-ar/src/register/drsr.rs @@ -6,6 +6,8 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// The size of a region #[derive(Debug, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] #[bitbybit::bitenum(u5, exhaustive = true)] pub enum RegionSize { /// A value of 0 is not permitted, this value is reserved and unpredictable. @@ -89,7 +91,7 @@ impl RegionSize { } /// DRSR (*Data Region Size and Enable Register*) -#[bitbybit::bitfield(u32)] +#[bitbybit::bitfield(u32, debug, defmt_fields(feature = "defmt"))] pub struct Drsr { /// Sub-region bitmask /// diff --git a/cortex-ar/src/register/dspsr.rs b/cortex-ar/src/register/dspsr.rs index e48bc93..c34b3ee 100644 --- a/cortex-ar/src/register/dspsr.rs +++ b/cortex-ar/src/register/dspsr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// DSPSR (*Debug Saved Program Status Register*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Dspsr(pub u32); impl SysReg for Dspsr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/fcseidr.rs b/cortex-ar/src/register/fcseidr.rs index 3b5e732..dccc125 100644 --- a/cortex-ar/src/register/fcseidr.rs +++ b/cortex-ar/src/register/fcseidr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// FCSEIDR (*FCSE Process ID Register*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Fcseidr(pub u32); impl SysReg for Fcseidr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/icc_pmr.rs b/cortex-ar/src/register/icc_pmr.rs index da084fa..94a138b 100644 --- a/cortex-ar/src/register/icc_pmr.rs +++ b/cortex-ar/src/register/icc_pmr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// ICC_PMR (*Interrupt Controller Interrupt Priority Mask Register*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct IccPmr(pub u32); impl SysReg for IccPmr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/id_afr0.rs b/cortex-ar/src/register/id_afr0.rs index d28b28c..ebcbdb2 100644 --- a/cortex-ar/src/register/id_afr0.rs +++ b/cortex-ar/src/register/id_afr0.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead}; /// ID_AFR0 (*Auxiliary Feature Register 0*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct IdAfr0(pub u32); impl SysReg for IdAfr0 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/id_dfr0.rs b/cortex-ar/src/register/id_dfr0.rs index 7a1aa3e..83da1bd 100644 --- a/cortex-ar/src/register/id_dfr0.rs +++ b/cortex-ar/src/register/id_dfr0.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead}; /// ID_DFR0 (*Debug Feature Register 0*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct IdDfr0(pub u32); impl SysReg for IdDfr0 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/id_isar0.rs b/cortex-ar/src/register/id_isar0.rs index 9afec70..666203b 100644 --- a/cortex-ar/src/register/id_isar0.rs +++ b/cortex-ar/src/register/id_isar0.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead}; /// ID_ISAR0 (*Instruction Set Attribute Register 0*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct IdIsar0(pub u32); impl SysReg for IdIsar0 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/id_isar1.rs b/cortex-ar/src/register/id_isar1.rs index 6b92690..eb7faa2 100644 --- a/cortex-ar/src/register/id_isar1.rs +++ b/cortex-ar/src/register/id_isar1.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead}; /// ID_ISAR1 (*Instruction Set Attribute Register 1*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct IdIsar1(pub u32); impl SysReg for IdIsar1 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/id_isar2.rs b/cortex-ar/src/register/id_isar2.rs index 069a308..1873b13 100644 --- a/cortex-ar/src/register/id_isar2.rs +++ b/cortex-ar/src/register/id_isar2.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead}; /// ID_ISAR2 (*Instruction Set Attribute Register 2*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct IdIsar2(pub u32); impl SysReg for IdIsar2 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/id_isar3.rs b/cortex-ar/src/register/id_isar3.rs index 7587500..3381b8b 100644 --- a/cortex-ar/src/register/id_isar3.rs +++ b/cortex-ar/src/register/id_isar3.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead}; /// ID_ISAR3 (*Instruction Set Attribute Register 3*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct IdIsar3(pub u32); impl SysReg for IdIsar3 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/id_isar4.rs b/cortex-ar/src/register/id_isar4.rs index 56542a7..54259f9 100644 --- a/cortex-ar/src/register/id_isar4.rs +++ b/cortex-ar/src/register/id_isar4.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead}; /// ID_ISAR4 (*Instruction Set Attribute Register 4*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct IdIsar4(pub u32); impl SysReg for IdIsar4 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/id_isar5.rs b/cortex-ar/src/register/id_isar5.rs index 547da58..6682f13 100644 --- a/cortex-ar/src/register/id_isar5.rs +++ b/cortex-ar/src/register/id_isar5.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead}; /// ID_ISAR5 (*Instruction Set Attribute Register 5*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct IdIsar5(pub u32); impl SysReg for IdIsar5 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/id_mmfr0.rs b/cortex-ar/src/register/id_mmfr0.rs index 48ff8fa..292a1d7 100644 --- a/cortex-ar/src/register/id_mmfr0.rs +++ b/cortex-ar/src/register/id_mmfr0.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead}; /// ID_MMFR0 (*Memory Model Feature Register 0*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct IdMmfr0(pub u32); impl SysReg for IdMmfr0 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/id_mmfr1.rs b/cortex-ar/src/register/id_mmfr1.rs index 42d1fe0..a05eb80 100644 --- a/cortex-ar/src/register/id_mmfr1.rs +++ b/cortex-ar/src/register/id_mmfr1.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead}; /// ID_MMFR1 (*Memory Model Feature Register 1*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct IdMmfr1(pub u32); impl SysReg for IdMmfr1 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/id_mmfr2.rs b/cortex-ar/src/register/id_mmfr2.rs index 1bc7da0..77a015d 100644 --- a/cortex-ar/src/register/id_mmfr2.rs +++ b/cortex-ar/src/register/id_mmfr2.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead}; /// ID_MMFR2 (*Memory Model Feature Register 2*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct IdMmfr2(pub u32); impl SysReg for IdMmfr2 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/id_mmfr3.rs b/cortex-ar/src/register/id_mmfr3.rs index 4ffbdc2..fed7e1a 100644 --- a/cortex-ar/src/register/id_mmfr3.rs +++ b/cortex-ar/src/register/id_mmfr3.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead}; /// ID_MMFR3 (*Memory Model Feature Register 3*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct IdMmfr3(pub u32); impl SysReg for IdMmfr3 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/id_mmfr4.rs b/cortex-ar/src/register/id_mmfr4.rs index b2cc680..dbc7ab4 100644 --- a/cortex-ar/src/register/id_mmfr4.rs +++ b/cortex-ar/src/register/id_mmfr4.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead}; /// ID_MMFR4 (*Memory Model Feature Register 4*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct IdMmfr4(pub u32); impl SysReg for IdMmfr4 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/id_pfr0.rs b/cortex-ar/src/register/id_pfr0.rs index 379f482..9898a5c 100644 --- a/cortex-ar/src/register/id_pfr0.rs +++ b/cortex-ar/src/register/id_pfr0.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead}; /// ID_PFR0 (*Processor Feature Register 0*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct IdPfr0(pub u32); impl SysReg for IdPfr0 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/id_pfr1.rs b/cortex-ar/src/register/id_pfr1.rs index 3a52485..b5103b0 100644 --- a/cortex-ar/src/register/id_pfr1.rs +++ b/cortex-ar/src/register/id_pfr1.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead}; /// ID_PFR1 (*Processor Feature Register 1*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct IdPfr1(pub u32); impl SysReg for IdPfr1 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/ifar.rs b/cortex-ar/src/register/ifar.rs index 66bc59e..4dd19be 100644 --- a/cortex-ar/src/register/ifar.rs +++ b/cortex-ar/src/register/ifar.rs @@ -3,7 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// IFAR (*Instruction Fault Address Register*) -#[derive(Debug)] +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Ifar(pub u32); impl SysReg for Ifar { const CP: u32 = 15; diff --git a/cortex-ar/src/register/ifsr.rs b/cortex-ar/src/register/ifsr.rs index 8cf5cb3..b8fd384 100644 --- a/cortex-ar/src/register/ifsr.rs +++ b/cortex-ar/src/register/ifsr.rs @@ -5,7 +5,8 @@ use arbitrary_int::{prelude::*, u4, u5}; use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// IFSR (*Instruction Fault Status Register*) -#[bitbybit::bitfield(u32)] +#[bitbybit::bitfield(u32, defmt_bitfields(feature = "defmt"))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Ifsr { /// External abort qualifier #[bit(12, rw)] @@ -18,7 +19,9 @@ pub struct Ifsr { } /// Fault status register enumeration for IFSR, which is also part of the DFSR -#[derive(Debug, num_enum::TryFromPrimitive)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, num_enum::TryFromPrimitive)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] #[repr(u8)] pub enum FsrStatus { SyncExtAbortOnTranslationTableWalkFirstLevel = 0b01100, diff --git a/cortex-ar/src/register/imp/imp_atcmregionr.rs b/cortex-ar/src/register/imp/imp_atcmregionr.rs index 618d0e9..dfaf7d7 100644 --- a/cortex-ar/src/register/imp/imp_atcmregionr.rs +++ b/cortex-ar/src/register/imp/imp_atcmregionr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// IMP_ATCMREGIONR (*TCM Region Registers A B and C*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct ImpAtcmregionr(pub u32); impl SysReg for ImpAtcmregionr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/imp/imp_bpctlr.rs b/cortex-ar/src/register/imp/imp_bpctlr.rs index 6b2fca5..070626a 100644 --- a/cortex-ar/src/register/imp/imp_bpctlr.rs +++ b/cortex-ar/src/register/imp/imp_bpctlr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// IMP_BPCTLR (*Branch Predictor Control Register*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct ImpBpctlr(pub u32); impl SysReg for ImpBpctlr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/imp/imp_btcmregionr.rs b/cortex-ar/src/register/imp/imp_btcmregionr.rs index dbb266b..25063ca 100644 --- a/cortex-ar/src/register/imp/imp_btcmregionr.rs +++ b/cortex-ar/src/register/imp/imp_btcmregionr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// IMP_BTCMREGIONR (*TCM Region Registers A B and C*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct ImpBtcmregionr(pub u32); impl SysReg for ImpBtcmregionr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/imp/imp_buildoptr.rs b/cortex-ar/src/register/imp/imp_buildoptr.rs index 6dc36cd..65d0b13 100644 --- a/cortex-ar/src/register/imp/imp_buildoptr.rs +++ b/cortex-ar/src/register/imp/imp_buildoptr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead}; /// IMP_BUILDOPTR (*Build Options Register*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct ImpBuildoptr(pub u32); impl SysReg for ImpBuildoptr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/imp/imp_bustimeoutr.rs b/cortex-ar/src/register/imp/imp_bustimeoutr.rs index f417a54..5e6b2ce 100644 --- a/cortex-ar/src/register/imp/imp_bustimeoutr.rs +++ b/cortex-ar/src/register/imp/imp_bustimeoutr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// IMP_BUSTIMEOUTR (*Bus Timeout Register*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct ImpBustimeoutr(pub u32); impl SysReg for ImpBustimeoutr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/imp/imp_cbar.rs b/cortex-ar/src/register/imp/imp_cbar.rs index c250988..0d0384f 100644 --- a/cortex-ar/src/register/imp/imp_cbar.rs +++ b/cortex-ar/src/register/imp/imp_cbar.rs @@ -3,8 +3,9 @@ use crate::register::{SysReg, SysRegRead}; /// IMP_CBAR (*Configuration Base Address Register*) -#[derive(Clone, Copy, PartialEq, Eq)] -pub struct ImpCbar(u32); +#[derive(Clone, Copy)] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] +pub struct ImpCbar(pub u32); impl SysReg for ImpCbar { const CP: u32 = 15; diff --git a/cortex-ar/src/register/imp/imp_cdbgdcd.rs b/cortex-ar/src/register/imp/imp_cdbgdcd.rs index 8cf6c10..14847ab 100644 --- a/cortex-ar/src/register/imp/imp_cdbgdcd.rs +++ b/cortex-ar/src/register/imp/imp_cdbgdcd.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegWrite}; /// IMP_CDBGDCD (*Data Cache Data Read Operation.*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct ImpCdbgdcd(pub u32); impl SysReg for ImpCdbgdcd { const CP: u32 = 15; diff --git a/cortex-ar/src/register/imp/imp_cdbgdci.rs b/cortex-ar/src/register/imp/imp_cdbgdci.rs index 1422f48..998ff88 100644 --- a/cortex-ar/src/register/imp/imp_cdbgdci.rs +++ b/cortex-ar/src/register/imp/imp_cdbgdci.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegWrite}; /// IMP_CDBGDCI (*Invalidate All Register*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct ImpCdbgdci(pub u32); impl SysReg for ImpCdbgdci { const CP: u32 = 15; diff --git a/cortex-ar/src/register/imp/imp_cdbgdct.rs b/cortex-ar/src/register/imp/imp_cdbgdct.rs index 837d87a..d3451a2 100644 --- a/cortex-ar/src/register/imp/imp_cdbgdct.rs +++ b/cortex-ar/src/register/imp/imp_cdbgdct.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegWrite}; /// IMP_CDBGDCT (*Data Cache Tag Read Operation.*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct ImpCdbgdct(pub u32); impl SysReg for ImpCdbgdct { const CP: u32 = 15; diff --git a/cortex-ar/src/register/imp/imp_cdbgdr0.rs b/cortex-ar/src/register/imp/imp_cdbgdr0.rs index 373c049..142a514 100644 --- a/cortex-ar/src/register/imp/imp_cdbgdr0.rs +++ b/cortex-ar/src/register/imp/imp_cdbgdr0.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead}; /// IMP_CDBGDR0 (*Cache Debug Data Register 0.*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct ImpCdbgdr0(pub u32); impl SysReg for ImpCdbgdr0 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/imp/imp_cdbgdr1.rs b/cortex-ar/src/register/imp/imp_cdbgdr1.rs index e35dbbf..e4864e7 100644 --- a/cortex-ar/src/register/imp/imp_cdbgdr1.rs +++ b/cortex-ar/src/register/imp/imp_cdbgdr1.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead}; /// IMP_CDBGDR1 (*Cache Debug Data Register 1.*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct ImpCdbgdr1(pub u32); impl SysReg for ImpCdbgdr1 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/imp/imp_cdbgdr2.rs b/cortex-ar/src/register/imp/imp_cdbgdr2.rs index 73e14d0..67046ce 100644 --- a/cortex-ar/src/register/imp/imp_cdbgdr2.rs +++ b/cortex-ar/src/register/imp/imp_cdbgdr2.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead}; /// IMP_CDBGDR2 (*Cache Debug Data Register 2.*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct ImpCdbgdr2(pub u32); impl SysReg for ImpCdbgdr2 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/imp/imp_cdbgicd.rs b/cortex-ar/src/register/imp/imp_cdbgicd.rs index d9e9e0b..1d0e2a6 100644 --- a/cortex-ar/src/register/imp/imp_cdbgicd.rs +++ b/cortex-ar/src/register/imp/imp_cdbgicd.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegWrite}; /// IMP_CDBGICD (*Instruction Cache Data Read Operation.*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct ImpCdbgicd(pub u32); impl SysReg for ImpCdbgicd { const CP: u32 = 15; diff --git a/cortex-ar/src/register/imp/imp_cdbgict.rs b/cortex-ar/src/register/imp/imp_cdbgict.rs index 489da43..f0a2220 100644 --- a/cortex-ar/src/register/imp/imp_cdbgict.rs +++ b/cortex-ar/src/register/imp/imp_cdbgict.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegWrite}; /// IMP_CDBGICT (*Instruction Cache Tag Read Operation.*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct ImpCdbgict(pub u32); impl SysReg for ImpCdbgict { const CP: u32 = 15; diff --git a/cortex-ar/src/register/imp/imp_csctlr.rs b/cortex-ar/src/register/imp/imp_csctlr.rs index f7b439e..792d28f 100644 --- a/cortex-ar/src/register/imp/imp_csctlr.rs +++ b/cortex-ar/src/register/imp/imp_csctlr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// IMP_CSCTLR (*Cache Segregation Control Register*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct ImpCsctlr(pub u32); impl SysReg for ImpCsctlr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/imp/imp_ctcmregionr.rs b/cortex-ar/src/register/imp/imp_ctcmregionr.rs index 78a36b6..09c4064 100644 --- a/cortex-ar/src/register/imp/imp_ctcmregionr.rs +++ b/cortex-ar/src/register/imp/imp_ctcmregionr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// IMP_CTCMREGIONR (*TCM Region Registers A B and C*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct ImpCtcmregionr(pub u32); impl SysReg for ImpCtcmregionr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/imp/imp_dcerr0.rs b/cortex-ar/src/register/imp/imp_dcerr0.rs index 455dc98..01ccb69 100644 --- a/cortex-ar/src/register/imp/imp_dcerr0.rs +++ b/cortex-ar/src/register/imp/imp_dcerr0.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// IMP_DCERR0 (*Data Cache Error Record Register 0*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct ImpDcerr0(pub u32); impl SysReg for ImpDcerr0 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/imp/imp_dcerr1.rs b/cortex-ar/src/register/imp/imp_dcerr1.rs index 3a384e2..1eb657c 100644 --- a/cortex-ar/src/register/imp/imp_dcerr1.rs +++ b/cortex-ar/src/register/imp/imp_dcerr1.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// DMP_ICERR1 (*Data Cache Error Record Register 1*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct ImpDcerr1(pub u32); impl SysReg for ImpDcerr1 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/imp/imp_flasherr0.rs b/cortex-ar/src/register/imp/imp_flasherr0.rs index 033c7c7..560cf81 100644 --- a/cortex-ar/src/register/imp/imp_flasherr0.rs +++ b/cortex-ar/src/register/imp/imp_flasherr0.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// IMP_FLASHERR0 (*Flash Error Record Register 0*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct ImpFlasherr0(pub u32); impl SysReg for ImpFlasherr0 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/imp/imp_flasherr1.rs b/cortex-ar/src/register/imp/imp_flasherr1.rs index 3c360dc..e9b7265 100644 --- a/cortex-ar/src/register/imp/imp_flasherr1.rs +++ b/cortex-ar/src/register/imp/imp_flasherr1.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// IMP_FLASHERR1 (*Flash Error Record Register 1*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct ImpFlasherr1(pub u32); impl SysReg for ImpFlasherr1 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/imp/imp_flashifregionr.rs b/cortex-ar/src/register/imp/imp_flashifregionr.rs index a7a0e0d..39c8606 100644 --- a/cortex-ar/src/register/imp/imp_flashifregionr.rs +++ b/cortex-ar/src/register/imp/imp_flashifregionr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// IMP_FLASHIFREGIONR (*Flash Interface Region Register*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct ImpFlashifregionr(pub u32); impl SysReg for ImpFlashifregionr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/imp/imp_icerr0.rs b/cortex-ar/src/register/imp/imp_icerr0.rs index 2d3eed3..6ddc426 100644 --- a/cortex-ar/src/register/imp/imp_icerr0.rs +++ b/cortex-ar/src/register/imp/imp_icerr0.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// IMP_ICERR0 (*Instruction Cache Error Record Register 0*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct ImpIcerr0(pub u32); impl SysReg for ImpIcerr0 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/imp/imp_icerr1.rs b/cortex-ar/src/register/imp/imp_icerr1.rs index c9d503b..60dca05 100644 --- a/cortex-ar/src/register/imp/imp_icerr1.rs +++ b/cortex-ar/src/register/imp/imp_icerr1.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// IMP_ICERR1 (*Instruction Cache Error Record Register 1*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct ImpIcerr1(pub u32); impl SysReg for ImpIcerr1 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/imp/imp_intmonr.rs b/cortex-ar/src/register/imp/imp_intmonr.rs index 83fbc77..5f69c55 100644 --- a/cortex-ar/src/register/imp/imp_intmonr.rs +++ b/cortex-ar/src/register/imp/imp_intmonr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// IMP_INTMONR (*Interrupt Monitoring Register*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct ImpIntmonr(pub u32); impl SysReg for ImpIntmonr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/imp/imp_memprotctlr.rs b/cortex-ar/src/register/imp/imp_memprotctlr.rs index 1132cd7..827b9da 100644 --- a/cortex-ar/src/register/imp/imp_memprotctlr.rs +++ b/cortex-ar/src/register/imp/imp_memprotctlr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// IMP_MEMPROTCTLR (*Memory Protection Control Register*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct ImpMemprotctlr(pub u32); impl SysReg for ImpMemprotctlr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/imp/imp_periphpregionr.rs b/cortex-ar/src/register/imp/imp_periphpregionr.rs index 6c53d57..06c20b3 100644 --- a/cortex-ar/src/register/imp/imp_periphpregionr.rs +++ b/cortex-ar/src/register/imp/imp_periphpregionr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// IMP_PERIPHPREGIONR (*Peripheral Port Region Register*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct ImpPeriphpregionr(pub u32); impl SysReg for ImpPeriphpregionr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/imp/imp_pinoptr.rs b/cortex-ar/src/register/imp/imp_pinoptr.rs index 1a40465..7801f88 100644 --- a/cortex-ar/src/register/imp/imp_pinoptr.rs +++ b/cortex-ar/src/register/imp/imp_pinoptr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead}; /// IMP_PINOPTR (*Pin Options Register*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct ImpPinoptr(pub u32); impl SysReg for ImpPinoptr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/imp/imp_qosr.rs b/cortex-ar/src/register/imp/imp_qosr.rs index 948aa1b..2d55a5d 100644 --- a/cortex-ar/src/register/imp/imp_qosr.rs +++ b/cortex-ar/src/register/imp/imp_qosr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// IMP_QOSR (*Quality Of Service Register*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct ImpQosr(pub u32); impl SysReg for ImpQosr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/imp/imp_slavepctlr.rs b/cortex-ar/src/register/imp/imp_slavepctlr.rs index 272d802..be815a7 100644 --- a/cortex-ar/src/register/imp/imp_slavepctlr.rs +++ b/cortex-ar/src/register/imp/imp_slavepctlr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// IMP_SLAVEPCTLR (*Slave Port Control Register*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct ImpSlavepctlr(pub u32); impl SysReg for ImpSlavepctlr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/imp/imp_tcmerr0.rs b/cortex-ar/src/register/imp/imp_tcmerr0.rs index fb8dff7..e299acf 100644 --- a/cortex-ar/src/register/imp/imp_tcmerr0.rs +++ b/cortex-ar/src/register/imp/imp_tcmerr0.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// IMP_TCMERR0 (*TCM Error Record Register 0*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct ImpTcmerr0(pub u32); impl SysReg for ImpTcmerr0 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/imp/imp_tcmerr1.rs b/cortex-ar/src/register/imp/imp_tcmerr1.rs index 3a90a74..9487100 100644 --- a/cortex-ar/src/register/imp/imp_tcmerr1.rs +++ b/cortex-ar/src/register/imp/imp_tcmerr1.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// IMP_TCMERR1 (*TCM Error Record Register 1*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct ImpTcmerr1(pub u32); impl SysReg for ImpTcmerr1 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/imp/imp_tcmsyndr0.rs b/cortex-ar/src/register/imp/imp_tcmsyndr0.rs index 894a5e1..6f72b8c 100644 --- a/cortex-ar/src/register/imp/imp_tcmsyndr0.rs +++ b/cortex-ar/src/register/imp/imp_tcmsyndr0.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead}; /// IMP_TCMSYNDR0 (*TCM Syndrome Register 0*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct ImpTcmsyndr0(pub u32); impl SysReg for ImpTcmsyndr0 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/imp/imp_tcmsyndr1.rs b/cortex-ar/src/register/imp/imp_tcmsyndr1.rs index df404df..7508792 100644 --- a/cortex-ar/src/register/imp/imp_tcmsyndr1.rs +++ b/cortex-ar/src/register/imp/imp_tcmsyndr1.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead}; /// IMP_TCMSYNDR1 (*TCM Syndrome Register 1*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct ImpTcmsyndr1(pub u32); impl SysReg for ImpTcmsyndr1 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/imp/imp_testr0.rs b/cortex-ar/src/register/imp/imp_testr0.rs index fa8aabd..1c90dcc 100644 --- a/cortex-ar/src/register/imp/imp_testr0.rs +++ b/cortex-ar/src/register/imp/imp_testr0.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead}; /// IMP_TESTR0 (*Test Register 0*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct ImpTestr0(pub u32); impl SysReg for ImpTestr0 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/iracr.rs b/cortex-ar/src/register/iracr.rs index c73d6ed..42afc96 100644 --- a/cortex-ar/src/register/iracr.rs +++ b/cortex-ar/src/register/iracr.rs @@ -5,7 +5,8 @@ use arbitrary_int::u3; use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// IRACR (*Instruction Region Access Control Register*) -#[bitbybit::bitfield(u32)] +#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Iracr { /// Execute Never #[bits(12..=12, rw)] diff --git a/cortex-ar/src/register/irbar.rs b/cortex-ar/src/register/irbar.rs index 2076055..0754cd2 100644 --- a/cortex-ar/src/register/irbar.rs +++ b/cortex-ar/src/register/irbar.rs @@ -3,6 +3,8 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// IRBAR (*Instruction Region Base Address Register*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] pub struct Irbar(pub *mut u8); impl SysReg for Irbar { const CP: u32 = 15; diff --git a/cortex-ar/src/register/irsr.rs b/cortex-ar/src/register/irsr.rs index d106f36..5e24992 100644 --- a/cortex-ar/src/register/irsr.rs +++ b/cortex-ar/src/register/irsr.rs @@ -5,7 +5,8 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; pub use super::drsr::RegionSize; /// IRSR (*Instruction Region Size and Enable Register*) -#[bitbybit::bitfield(u32)] +#[bitbybit::bitfield(u32, debug, defmt_fields(feature = "defmt"))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Irsr { /// Sub-region bitmask /// diff --git a/cortex-ar/src/register/mair0.rs b/cortex-ar/src/register/mair0.rs index a12afce..75bc30c 100644 --- a/cortex-ar/src/register/mair0.rs +++ b/cortex-ar/src/register/mair0.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// MAIR0 (*Memory Attribute Indirection Register 0*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Mair0(pub u32); impl SysReg for Mair0 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/mair1.rs b/cortex-ar/src/register/mair1.rs index 8883937..fc2158f 100644 --- a/cortex-ar/src/register/mair1.rs +++ b/cortex-ar/src/register/mair1.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// MAIR1 (*Memory Attribute Indirection Register 1*) +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Mair1(pub u32); impl SysReg for Mair1 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/mpidr.rs b/cortex-ar/src/register/mpidr.rs index bf2d976..bf3b87c 100644 --- a/cortex-ar/src/register/mpidr.rs +++ b/cortex-ar/src/register/mpidr.rs @@ -3,7 +3,9 @@ use crate::register::{SysReg, SysRegRead}; /// MPIDR (*Multiprocessor Affinity Register*) -#[derive(Debug)] +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Mpidr(pub u32); impl SysReg for Mpidr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/mpuir.rs b/cortex-ar/src/register/mpuir.rs index 79ed54b..8b64826 100644 --- a/cortex-ar/src/register/mpuir.rs +++ b/cortex-ar/src/register/mpuir.rs @@ -4,6 +4,7 @@ use crate::register::{SysReg, SysRegRead}; /// MPUIR (*MPU Type Register*) #[bitbybit::bitfield(u32)] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Mpuir { /// Specifies the number of Instruction regions implemented by the MPU. /// diff --git a/cortex-ar/src/register/nsacr.rs b/cortex-ar/src/register/nsacr.rs index 86625fa..b35e939 100644 --- a/cortex-ar/src/register/nsacr.rs +++ b/cortex-ar/src/register/nsacr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead}; /// NSACR (*Non-Secure Access Control Register*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Nsacr(pub u32); impl SysReg for Nsacr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/par.rs b/cortex-ar/src/register/par.rs index 2dd00d1..241021d 100644 --- a/cortex-ar/src/register/par.rs +++ b/cortex-ar/src/register/par.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PAR (*Physical Address Register*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Par(pub u32); impl SysReg for Par { const CP: u32 = 15; diff --git a/cortex-ar/src/register/pmccfiltr.rs b/cortex-ar/src/register/pmccfiltr.rs index 7c8385f..2a83e48 100644 --- a/cortex-ar/src/register/pmccfiltr.rs +++ b/cortex-ar/src/register/pmccfiltr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PMCCFILTR (*Performance Monitors Cycle Count Filter Register*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Pmccfiltr(pub u32); impl SysReg for Pmccfiltr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/pmccntr.rs b/cortex-ar/src/register/pmccntr.rs index 658dc2b..3a3c9ca 100644 --- a/cortex-ar/src/register/pmccntr.rs +++ b/cortex-ar/src/register/pmccntr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PMCCNTR (*Performance Monitors Cycle Count Register*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Pmccntr(pub u32); impl SysReg for Pmccntr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/pmceid0.rs b/cortex-ar/src/register/pmceid0.rs index 927883b..1e37a40 100644 --- a/cortex-ar/src/register/pmceid0.rs +++ b/cortex-ar/src/register/pmceid0.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead}; /// PMCEID0 (*Performance Monitors Common Event Identification Register 0*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Pmceid0(pub u32); impl SysReg for Pmceid0 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/pmceid1.rs b/cortex-ar/src/register/pmceid1.rs index ebd302e..4b329d7 100644 --- a/cortex-ar/src/register/pmceid1.rs +++ b/cortex-ar/src/register/pmceid1.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead}; /// PMCEID1 (*Performance Monitors Common Event Identification Register 1*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Pmceid1(pub u32); impl SysReg for Pmceid1 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/pmcntenclr.rs b/cortex-ar/src/register/pmcntenclr.rs index 1e146aa..fdc826a 100644 --- a/cortex-ar/src/register/pmcntenclr.rs +++ b/cortex-ar/src/register/pmcntenclr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PMCNTENCLR (*Performance Monitors Count Enable Clear Register*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Pmcntenclr(pub u32); impl SysReg for Pmcntenclr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/pmcntenset.rs b/cortex-ar/src/register/pmcntenset.rs index eaca30d..e5f5607 100644 --- a/cortex-ar/src/register/pmcntenset.rs +++ b/cortex-ar/src/register/pmcntenset.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PMCNTENSET (*Performance Monitors Count Enable Set Register*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Pmcntenset(pub u32); impl SysReg for Pmcntenset { const CP: u32 = 15; diff --git a/cortex-ar/src/register/pmcr.rs b/cortex-ar/src/register/pmcr.rs index 49424dc..ebc20eb 100644 --- a/cortex-ar/src/register/pmcr.rs +++ b/cortex-ar/src/register/pmcr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PMCR (*Performance Monitors Control Register*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Pmcr(pub u32); impl SysReg for Pmcr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/pmevcntr0.rs b/cortex-ar/src/register/pmevcntr0.rs index 40f7ed2..74e6dcd 100644 --- a/cortex-ar/src/register/pmevcntr0.rs +++ b/cortex-ar/src/register/pmevcntr0.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PMEVCNTR0 (*Performance Monitors Event Count Register 0*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Pmevcntr0(pub u32); impl SysReg for Pmevcntr0 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/pmevcntr1.rs b/cortex-ar/src/register/pmevcntr1.rs index 4fbdb9d..6104164 100644 --- a/cortex-ar/src/register/pmevcntr1.rs +++ b/cortex-ar/src/register/pmevcntr1.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PMEVCNTR1 (*Performance Monitors Event Count Register 1*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Pmevcntr1(pub u32); impl SysReg for Pmevcntr1 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/pmevcntr2.rs b/cortex-ar/src/register/pmevcntr2.rs index 1051b92..1493371 100644 --- a/cortex-ar/src/register/pmevcntr2.rs +++ b/cortex-ar/src/register/pmevcntr2.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PMEVCNTR2 (*Performance Monitors Event Count Register 2 *) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Pmevcntr2(pub u32); impl SysReg for Pmevcntr2 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/pmevcntr3.rs b/cortex-ar/src/register/pmevcntr3.rs index 7786277..e409255 100644 --- a/cortex-ar/src/register/pmevcntr3.rs +++ b/cortex-ar/src/register/pmevcntr3.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PMEVCNTR3 (*Performance Monitors Event Count Register 3*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Pmevcntr3(pub u32); impl SysReg for Pmevcntr3 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/pmevtyper0.rs b/cortex-ar/src/register/pmevtyper0.rs index a1798f4..7a0ee1b 100644 --- a/cortex-ar/src/register/pmevtyper0.rs +++ b/cortex-ar/src/register/pmevtyper0.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PMEVTYPER0 (*Performance Monitors Event Type Register 0*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Pmevtyper0(pub u32); impl SysReg for Pmevtyper0 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/pmevtyper1.rs b/cortex-ar/src/register/pmevtyper1.rs index 5dbe5c8..67e59a1 100644 --- a/cortex-ar/src/register/pmevtyper1.rs +++ b/cortex-ar/src/register/pmevtyper1.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PMEVTYPER1 (*Performance Monitors Event Type Register 1*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Pmevtyper1(pub u32); impl SysReg for Pmevtyper1 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/pmevtyper2.rs b/cortex-ar/src/register/pmevtyper2.rs index 5f6451c..70574b5 100644 --- a/cortex-ar/src/register/pmevtyper2.rs +++ b/cortex-ar/src/register/pmevtyper2.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PMEVTYPER2 (*Performance Monitors Event Type Register 2*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Pmevtyper2(pub u32); impl SysReg for Pmevtyper2 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/pmevtyper3.rs b/cortex-ar/src/register/pmevtyper3.rs index d3cbd5d..0d325fa 100644 --- a/cortex-ar/src/register/pmevtyper3.rs +++ b/cortex-ar/src/register/pmevtyper3.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PMEVTYPER3 (*Performance Monitors Event Type Register 3*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Pmevtyper3(pub u32); impl SysReg for Pmevtyper3 { const CP: u32 = 15; diff --git a/cortex-ar/src/register/pmintenclr.rs b/cortex-ar/src/register/pmintenclr.rs index 2227c6e..ec87ea5 100644 --- a/cortex-ar/src/register/pmintenclr.rs +++ b/cortex-ar/src/register/pmintenclr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PMINTENCLR (*Performance Monitors Interrupt Enable Clear Register*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Pmintenclr(pub u32); impl SysReg for Pmintenclr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/pmintenset.rs b/cortex-ar/src/register/pmintenset.rs index e3eb3a9..a1d6cbb 100644 --- a/cortex-ar/src/register/pmintenset.rs +++ b/cortex-ar/src/register/pmintenset.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PMINTENSET (*Performance Monitors Interrupt Enable Set Register*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Pmintenset(pub u32); impl SysReg for Pmintenset { const CP: u32 = 15; diff --git a/cortex-ar/src/register/pmovsr.rs b/cortex-ar/src/register/pmovsr.rs index 4214791..ed59d9b 100644 --- a/cortex-ar/src/register/pmovsr.rs +++ b/cortex-ar/src/register/pmovsr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PMOVSR (*Performance Monitor Overflow Flag Status Clear Register*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Pmovsr(pub u32); impl SysReg for Pmovsr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/pmovsset.rs b/cortex-ar/src/register/pmovsset.rs index 8c525e2..b1764aa 100644 --- a/cortex-ar/src/register/pmovsset.rs +++ b/cortex-ar/src/register/pmovsset.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PMOVSSET (*Performance Monitor Overflow Flag Status Set Register*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Pmovsset(pub u32); impl SysReg for Pmovsset { const CP: u32 = 15; diff --git a/cortex-ar/src/register/pmselr.rs b/cortex-ar/src/register/pmselr.rs index d7f8108..fa6fb56 100644 --- a/cortex-ar/src/register/pmselr.rs +++ b/cortex-ar/src/register/pmselr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PMSELR (*Performance Monitors Event Counter Selection Register*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Pmselr(pub u32); impl SysReg for Pmselr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/pmswinc.rs b/cortex-ar/src/register/pmswinc.rs index 74731a8..b24b330 100644 --- a/cortex-ar/src/register/pmswinc.rs +++ b/cortex-ar/src/register/pmswinc.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegWrite}; /// PMSWINC (*Performance Monitors Software Increment Register*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Pmswinc(pub u32); impl SysReg for Pmswinc { const CP: u32 = 15; diff --git a/cortex-ar/src/register/pmuserenr.rs b/cortex-ar/src/register/pmuserenr.rs index d5892c9..da10d3b 100644 --- a/cortex-ar/src/register/pmuserenr.rs +++ b/cortex-ar/src/register/pmuserenr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PMUSERENR (*Performance Monitors User Enable Register*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Pmuserenr(pub u32); impl SysReg for Pmuserenr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/pmxevcntr.rs b/cortex-ar/src/register/pmxevcntr.rs index 3c8c196..ddd35f2 100644 --- a/cortex-ar/src/register/pmxevcntr.rs +++ b/cortex-ar/src/register/pmxevcntr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PMXEVCNTR (*Performance Monitors Selected Event Count Register*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Pmxevcntr(pub u32); impl SysReg for Pmxevcntr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/pmxevtyper.rs b/cortex-ar/src/register/pmxevtyper.rs index de5daf0..5aaef51 100644 --- a/cortex-ar/src/register/pmxevtyper.rs +++ b/cortex-ar/src/register/pmxevtyper.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// PMXEVTYPER (*Performance Monitors Selected Event Type Register*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Pmxevtyper(pub u32); impl SysReg for Pmxevtyper { const CP: u32 = 15; diff --git a/cortex-ar/src/register/revidr.rs b/cortex-ar/src/register/revidr.rs index 9f2a6f7..fb2aae0 100644 --- a/cortex-ar/src/register/revidr.rs +++ b/cortex-ar/src/register/revidr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead}; /// REVIDR (*Revision ID Register*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Revidr(pub u32); impl SysReg for Revidr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/rgnr.rs b/cortex-ar/src/register/rgnr.rs index ab2e2b0..82cba4d 100644 --- a/cortex-ar/src/register/rgnr.rs +++ b/cortex-ar/src/register/rgnr.rs @@ -5,6 +5,9 @@ use crate::register::{SysReg, SysRegRead}; use super::SysRegWrite; /// RGNR (*MPU Region Number Register*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Rgnr(pub u32); impl SysReg for Rgnr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/rvbar.rs b/cortex-ar/src/register/rvbar.rs index 9d12e74..8c5a684 100644 --- a/cortex-ar/src/register/rvbar.rs +++ b/cortex-ar/src/register/rvbar.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead}; /// RVBAR (*Reset Vector Base Address Register*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Rvbar(pub u32); impl SysReg for Rvbar { const CP: u32 = 15; diff --git a/cortex-ar/src/register/sctlr.rs b/cortex-ar/src/register/sctlr.rs index 01b6976..5ff397b 100644 --- a/cortex-ar/src/register/sctlr.rs +++ b/cortex-ar/src/register/sctlr.rs @@ -4,6 +4,7 @@ use super::{SysReg, SysRegRead, SysRegWrite}; /// SCTLR (*System Control Register*) #[bitbybit::bitfield(u32)] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Sctlr { /// The bitmask for the Instruction Endianness bit #[bits(31..=31, rw)] diff --git a/cortex-ar/src/register/tcmtr.rs b/cortex-ar/src/register/tcmtr.rs index d05c6ac..145fbea 100644 --- a/cortex-ar/src/register/tcmtr.rs +++ b/cortex-ar/src/register/tcmtr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead}; /// TCMTR (*TCM Type Register*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Tcmtr(pub u32); impl SysReg for Tcmtr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/tlbtr.rs b/cortex-ar/src/register/tlbtr.rs index 15db631..4b64851 100644 --- a/cortex-ar/src/register/tlbtr.rs +++ b/cortex-ar/src/register/tlbtr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead}; /// TLBTR (*TLB Type Register*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Tlbtr(pub u32); impl SysReg for Tlbtr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/tpidrprw.rs b/cortex-ar/src/register/tpidrprw.rs index e3198d5..1332407 100644 --- a/cortex-ar/src/register/tpidrprw.rs +++ b/cortex-ar/src/register/tpidrprw.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// TPIDRPRW (*EL1 Software Thread ID Register*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Tpidrprw(pub u32); impl SysReg for Tpidrprw { const CP: u32 = 15; diff --git a/cortex-ar/src/register/tpidruro.rs b/cortex-ar/src/register/tpidruro.rs index aa573a8..87190c9 100644 --- a/cortex-ar/src/register/tpidruro.rs +++ b/cortex-ar/src/register/tpidruro.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// TPIDRURO (*EL0 Read-Only Software Thread ID Register*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Tpidruro(pub u32); impl SysReg for Tpidruro { const CP: u32 = 15; diff --git a/cortex-ar/src/register/tpidrurw.rs b/cortex-ar/src/register/tpidrurw.rs index 3e8052b..7a54f0f 100644 --- a/cortex-ar/src/register/tpidrurw.rs +++ b/cortex-ar/src/register/tpidrurw.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// TPIDRURW (*EL0 Read/Write Software Thread ID Register*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Tpidrurw(pub u32); impl SysReg for Tpidrurw { const CP: u32 = 15; diff --git a/cortex-ar/src/register/vmpidr.rs b/cortex-ar/src/register/vmpidr.rs index b83b651..d581769 100644 --- a/cortex-ar/src/register/vmpidr.rs +++ b/cortex-ar/src/register/vmpidr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// VMPIDR (*Virtualization Multiprocessor ID Register*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Vmpidr(pub u32); impl SysReg for Vmpidr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/vpidr.rs b/cortex-ar/src/register/vpidr.rs index ad10823..a67e305 100644 --- a/cortex-ar/src/register/vpidr.rs +++ b/cortex-ar/src/register/vpidr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// VPIDR (*Virtualization Processor ID Register*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Vpidr(pub u32); impl SysReg for Vpidr { const CP: u32 = 15; diff --git a/cortex-ar/src/register/vsctlr.rs b/cortex-ar/src/register/vsctlr.rs index 44f8295..4036ed2 100644 --- a/cortex-ar/src/register/vsctlr.rs +++ b/cortex-ar/src/register/vsctlr.rs @@ -3,6 +3,9 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite}; /// VSCTLR (*Virtualization System Control Register*) +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] pub struct Vsctlr(pub u32); impl SysReg for Vsctlr { const CP: u32 = 15;